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stm32/boards/stm32f746_af.csv: Fix typos in AF table.

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This commit is contained in:
Damien George 2017-11-20 14:19:12 +11:00
parent 12ad64bc55
commit bbac2df0cf
1 changed files with 7 additions and 8 deletions
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15
ports/stm32/boards/stm32f746_af.csv
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@ -5,7 +5,7 @@ PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,
PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,,,LCD_R1,EVENTOUT
PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT
PortA,PA4,,,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT
PortA,PA5,,TIM2_CH1/TIM2_ETR,TIM8_CH1N,SPI1_SCK/I2S1_CK,,,,,,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT
PortA,PA5,,TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT
PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCLK,LCD_G2,EVENTOUT
PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT
PortA,PA8,MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,LCD_R6,EVENTOUT
@ -13,16 +13,16 @@ PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,,EVENTO
PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT
PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT
PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT
PortA,PA13,JTMS,SWDIO,,,,,,,,,,,,,,EVENTOUT
PortA,PA14,JTCK,SWCLK,,,,,,,,,,,,,,EVENTOUT
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,HDMICE,CSPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT
PortB,PB0,,TIM1_CH2N,TIM3_CH3T,IM8_CH2N,,,,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT
PortB,PB1,,TIM1_CH3N,TIM3_CH4T,IM8_CH3N,,,,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT
PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT
PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT
PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT
PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT
PortB,PB2,,,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,,,,,,EVENTOUT
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT
PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,,,,,EVENTOUT
PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,,EVENTOUT
PortB,PB6,,,TIM4_CH1,HDMICEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,,FMC_SDNE1,DCMI_D5,,EVENTOUT
PortB,PB6,,,TIM4_CH1,HDMI_CEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,,FMC_SDNE1,DCMI_D5,,EVENTOUT
PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FMC_NL,DCMI_VSYNC,,EVENTOUT
PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,ETH_MII_TXD3,SDMMC1_D4,DCMI_D6,LCD_B6,EVENTOUT
PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDMMC1_D5,DCMI_D7,LCD_B7,EVENTOUT
@ -168,4 +168,3 @@ PortK,PK4,,,,,,,,,,,,,,,LCD_B5,EVENTOUT
PortK,PK5,,,,,,,,,,,,,,,LCD_B6,EVENTOUT
PortK,PK6,,,,,,,,,,,,,,,LCD_B7,EVENTOUT
PortK,PK7,,,,,,,,,,,,,,,LCD_DE,EVENTOUT

1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
5 PortA PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX SAI2_SCK_B ETH_MDIO LCD_R1 EVENTOUT
6 PortA PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_D0 ETH_MII_COL LCD_B5 EVENTOUT
7 PortA PA4 SPI1_NSS/I2S1_WS SPI3_NSS/I2S3_WS USART2_CK OTG_HS_SOF DCMI_HSYNC LCD_VSYNC EVENTOUT
8 PortA PA5 TIM2_CH1/TIM2_ETR TIM8_CH1N SPI1_SCK/I2S1_CK TIM8_CH1N SPI1_SCK/I2S1_CK OTG_HS_ULPI_CK LCD_R4 EVENTOUT
9 PortA PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCLK LCD_G2 EVENTOUT
10 PortA PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI/I2S1_SD TIM14_CH1 ETH_MII_RX_DV/ETH_RMII_CRS_DV FMC_SDNWE EVENTOUT
11 PortA PA8 MCO1 TIM1_CH1 TIM8_BKIN2 I2C3_SCL USART1_CK OTG_FS_SOF LCD_R6 EVENTOUT
13 PortA PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT
14 PortA PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM LCD_R4 EVENTOUT
15 PortA PA12 TIM1_ETR USART1_RTS SAI2_FS_B CAN1_TX OTG_FS_DP LCD_R5 EVENTOUT
16 PortA PA13 JTMS JTMS/SWDIO SWDIO EVENTOUT
17 PortA PA14 JTCK JTCK/SWCLK SWCLK EVENTOUT
18 PortA PA15 JTDI TIM2_CH1/TIM2_ETR HDMICE HDMI_CEC CSPI1_NSS/I2S1_WS SPI1_NSS/I2S1_WS SPI3_NSS/I2S3_WS UART4_RTS EVENTOUT
19 PortB PB0 TIM1_CH2N TIM3_CH3T TIM3_CH3 IM8_CH2N TIM8_CH2N UART4_CTS LCD_R3 OTG_HS_ULPI_D1 ETH_MII_RXD2 EVENTOUT
20 PortB PB1 TIM1_CH3N TIM3_CH4T TIM3_CH4 IM8_CH3N TIM8_CH3N LCD_R6 OTG_HS_ULPI_D2 ETH_MII_RXD3 EVENTOUT
21 PortB PB2 SAI1_SD_A SPI3_MOSI/I2S3_SD QUADSPI_CLK EVENTOUT
22 PortB PB3 JTDO/TRACESWO TIM2_CH2 SPI1_SCK/I2S1_CK SPI3_SCK/I2S3_CK EVENTOUT
23 PortB PB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO SPI2_NSS/I2S2_WS EVENTOUT
24 PortB PB5 TIM3_CH2 I2C1_SMBA SPI1_MOSI/I2S1_SD SPI3_MOSI/I2S3_SD CAN2_RX OTG_HS_ULPI_D7 ETH_PPS_OUT FMC_SDCKE1 DCMI_D10 EVENTOUT
25 PortB PB6 TIM4_CH1 HDMICEC HDMI_CEC I2C1_SCL USART1_TX CAN2_TX QUADSPI_BK1_NCS FMC_SDNE1 DCMI_D5 EVENTOUT
26 PortB PB7 TIM4_CH2 I2C1_SDA USART1_RX FMC_NL DCMI_VSYNC EVENTOUT
27 PortB PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX ETH_MII_TXD3 SDMMC1_D4 DCMI_D6 LCD_B6 EVENTOUT
28 PortB PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS/I2S2_WS CAN1_TX SDMMC1_D5 DCMI_D7 LCD_B7 EVENTOUT
168 PortK PK5 LCD_B6 EVENTOUT
169 PortK PK6 LCD_B7 EVENTOUT
170 PortK PK7 LCD_DE EVENTOUT