From b9741cd8f84a2f49e3ea00382bfa71d994bc83ff Mon Sep 17 00:00:00 2001 From: Rami Ali Date: Mon, 5 Dec 2016 17:04:56 +1100 Subject: [PATCH] stmhal/hal: Update ST32CubeF7 HAL files to V1.1.2. These files originate from the STM32Cube_FW_F7_V1.5.0 software package from ST. Newlines are unixified and trailing whitespace is removed. --- stmhal/hal/f7/inc/Legacy/stm32_hal_legacy.h | 859 +++- stmhal/hal/f7/inc/stm32f7xx_hal.h | 50 +- stmhal/hal/f7/inc/stm32f7xx_hal_adc.h | 301 +- stmhal/hal/f7/inc/stm32f7xx_hal_adc_ex.h | 123 +- stmhal/hal/f7/inc/stm32f7xx_hal_can.h | 149 +- stmhal/hal/f7/inc/stm32f7xx_hal_cortex.h | 214 +- stmhal/hal/f7/inc/stm32f7xx_hal_dac.h | 46 +- stmhal/hal/f7/inc/stm32f7xx_hal_dac_ex.h | 10 +- stmhal/hal/f7/inc/stm32f7xx_hal_def.h | 20 +- stmhal/hal/f7/inc/stm32f7xx_hal_dma.h | 174 +- stmhal/hal/f7/inc/stm32f7xx_hal_dma_ex.h | 84 +- stmhal/hal/f7/inc/stm32f7xx_hal_flash.h | 70 +- stmhal/hal/f7/inc/stm32f7xx_hal_flash_ex.h | 314 +- stmhal/hal/f7/inc/stm32f7xx_hal_gpio.h | 82 +- stmhal/hal/f7/inc/stm32f7xx_hal_gpio_ex.h | 293 +- stmhal/hal/f7/inc/stm32f7xx_hal_i2c.h | 454 +- stmhal/hal/f7/inc/stm32f7xx_hal_i2c_ex.h | 69 +- stmhal/hal/f7/inc/stm32f7xx_hal_i2s.h | 90 +- stmhal/hal/f7/inc/stm32f7xx_hal_pcd.h | 63 +- stmhal/hal/f7/inc/stm32f7xx_hal_pcd_ex.h | 10 +- stmhal/hal/f7/inc/stm32f7xx_hal_pwr.h | 34 +- stmhal/hal/f7/inc/stm32f7xx_hal_pwr_ex.h | 8 +- stmhal/hal/f7/inc/stm32f7xx_hal_rcc.h | 368 +- stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h | 856 +++- stmhal/hal/f7/inc/stm32f7xx_hal_rng.h | 16 +- stmhal/hal/f7/inc/stm32f7xx_hal_rtc.h | 143 +- stmhal/hal/f7/inc/stm32f7xx_hal_rtc_ex.h | 176 +- stmhal/hal/f7/inc/stm32f7xx_hal_sd.h | 176 +- stmhal/hal/f7/inc/stm32f7xx_hal_spi.h | 395 +- stmhal/hal/f7/inc/stm32f7xx_hal_tim.h | 200 +- stmhal/hal/f7/inc/stm32f7xx_hal_tim_ex.h | 124 +- stmhal/hal/f7/inc/stm32f7xx_hal_uart.h | 260 +- stmhal/hal/f7/inc/stm32f7xx_hal_uart_ex.h | 40 +- stmhal/hal/f7/inc/stm32f7xx_ll_sdmmc.h | 38 +- stmhal/hal/f7/inc/stm32f7xx_ll_usb.h | 118 +- stmhal/hal/f7/src/stm32f7xx_hal.c | 54 +- stmhal/hal/f7/src/stm32f7xx_hal_adc.c | 760 ++-- stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c | 585 ++- stmhal/hal/f7/src/stm32f7xx_hal_can.c | 443 +- stmhal/hal/f7/src/stm32f7xx_hal_cortex.c | 46 +- stmhal/hal/f7/src/stm32f7xx_hal_dac.c | 24 +- stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c | 18 +- stmhal/hal/f7/src/stm32f7xx_hal_dma.c | 1049 +++-- stmhal/hal/f7/src/stm32f7xx_hal_flash.c | 65 +- stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c | 477 ++- stmhal/hal/f7/src/stm32f7xx_hal_gpio.c | 25 +- stmhal/hal/f7/src/stm32f7xx_hal_i2c.c | 4218 +++++++++++-------- stmhal/hal/f7/src/stm32f7xx_hal_i2s.c | 31 +- stmhal/hal/f7/src/stm32f7xx_hal_pcd.c | 199 +- stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c | 24 +- stmhal/hal/f7/src/stm32f7xx_hal_pwr.c | 14 +- stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c | 14 +- stmhal/hal/f7/src/stm32f7xx_hal_rcc.c | 282 +- stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c | 253 +- stmhal/hal/f7/src/stm32f7xx_hal_rng.c | 18 +- stmhal/hal/f7/src/stm32f7xx_hal_rtc.c | 24 +- stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c | 46 +- stmhal/hal/f7/src/stm32f7xx_hal_sd.c | 254 +- stmhal/hal/f7/src/stm32f7xx_hal_spi.c | 3104 +++++++++----- stmhal/hal/f7/src/stm32f7xx_hal_tim.c | 100 +- stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c | 119 +- stmhal/hal/f7/src/stm32f7xx_hal_uart.c | 1074 +++-- stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c | 9 +- stmhal/hal/f7/src/stm32f7xx_ll_usb.c | 72 +- 64 files changed, 12638 insertions(+), 7190 deletions(-) diff --git a/stmhal/hal/f7/inc/Legacy/stm32_hal_legacy.h b/stmhal/hal/f7/inc/Legacy/stm32_hal_legacy.h index f01bc166f7..bd8104e2d7 100644 --- a/stmhal/hal/f7/inc/Legacy/stm32_hal_legacy.h +++ b/stmhal/hal/f7/inc/Legacy/stm32_hal_legacy.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,6 +103,15 @@ #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ @@ -120,12 +129,96 @@ /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig /** * @} */ @@ -148,7 +241,7 @@ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE ((uint32_t)0x00000000) +#define DAC_WAVE_NONE ((uint32_t)0x00000000U) #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE @@ -255,6 +348,14 @@ #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS #define OB_WDG_SW OB_IWDG_SW #define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 /** * @} @@ -264,14 +365,15 @@ * @{ */ -#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 - +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 /** * @} */ @@ -330,6 +432,27 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 /** * @} */ @@ -346,6 +469,15 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE /** * @} */ @@ -361,6 +493,14 @@ #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif /** * @} */ @@ -417,6 +557,11 @@ /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose * @{ */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + #define NAND_AddressTypedef NAND_AddressTypeDef #define __ARRAY_ADDRESS ARRAY_ADDRESS @@ -480,6 +625,9 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif /** * @} */ @@ -575,7 +723,7 @@ */ - /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE @@ -593,7 +741,7 @@ * @} */ - /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE @@ -706,6 +854,8 @@ #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 +#define __DIV_LPUART UART_DIV_LPUART + #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK @@ -746,9 +896,9 @@ #define CAN_IT_RQCP2 CAN_IT_TME #define INAK_TIMEOUT CAN_TIMEOUT_VALUE #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) -#define CAN_TXSTATUS_OK ((uint8_t)0x01) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) /** * @} @@ -767,22 +917,96 @@ #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK -#define ETH_MMCCR ((uint32_t)0x00000100) -#define ETH_MMCRIR ((uint32_t)0x00000104) -#define ETH_MMCTIR ((uint32_t)0x00000108) -#define ETH_MMCRIMR ((uint32_t)0x0000010C) -#define ETH_MMCTIMR ((uint32_t)0x00000110) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) -#define ETH_MMCTGFCR ((uint32_t)0x00000168) -#define ETH_MMCRFCECR ((uint32_t)0x00000194) -#define ETH_MMCRFAECR ((uint32_t)0x00000198) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) +#define ETH_MMCCR ((uint32_t)0x00000100U) +#define ETH_MMCRIR ((uint32_t)0x00000104U) +#define ETH_MMCTIR ((uint32_t)0x00000108U) +#define ETH_MMCRIMR ((uint32_t)0x0000010CU) +#define ETH_MMCTIMR ((uint32_t)0x00000110U) +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) +#define ETH_MMCTGFCR ((uint32_t)0x00000168U) +#define ETH_MMCRFCECR ((uint32_t)0x00000194U) +#define ETH_MMCRFAECR ((uint32_t)0x00000198U) +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) + +#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ /** * @} */ +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4xx || STM32F7*/ + /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ @@ -804,7 +1028,8 @@ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ - +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish @@ -838,7 +1063,10 @@ #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) /** @@ -863,8 +1091,10 @@ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) /** @@ -965,7 +1195,7 @@ */ - /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ @@ -1178,29 +1408,190 @@ /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose * @{ */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif /** * @} */ +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ @@ -1346,7 +1737,7 @@ #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -1355,8 +1746,8 @@ #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4() -#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4() +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2015,47 +2406,211 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE /* alias define maintained for legacy */ #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + #if defined(STM32F4) -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED #define Sdmmc1ClockSelection SdioClockSelection #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 @@ -2065,13 +2620,14 @@ #endif #if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG @@ -2079,35 +2635,100 @@ #endif #if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 #define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER #define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER - +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS @@ -2128,9 +2749,46 @@ #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE + /** * @} */ @@ -2227,8 +2885,8 @@ #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -2420,31 +3078,7 @@ #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) - -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) - -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) - -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) - -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTSTATE_ENABLE)) +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 /** * @} */ @@ -2490,8 +3124,9 @@ #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE - +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal.h b/stmhal/hal/f7/inc/stm32f7xx_hal.h index 7ec488d88a..47335ee8f1 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f7xx_hal.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -57,6 +57,23 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U) +#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT +/** + * @} + */ + +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ @@ -125,6 +142,29 @@ #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\ }while(0); +/** + * @brief Return the memory boot mapping as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg @ref SYSCFG_MEM_BOOT_ADD0 + * @arg @ref SYSCFG_MEM_BOOT_ADD1 + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief SYSCFG Break Cortex-M7 Lockup lock. + * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ @@ -168,6 +208,10 @@ void HAL_EnableCompensationCell(void); void HAL_DisableCompensationCell(void); void HAL_EnableFMCMemorySwapping(void); void HAL_DisableFMCMemorySwapping(void); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +void HAL_EnableMemorySwappingBank(void); +void HAL_DisableMemorySwappingBank(void); +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_adc.h b/stmhal/hal/f7/inc/stm32f7xx_hal_adc.h index 8c6e358b7f..83c0f5864b 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_adc.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_adc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -60,103 +60,96 @@ */ /** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ - HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ - HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ - HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ - HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ - HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ - HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ - HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ - HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ - HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ - HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */ - -}HAL_ADC_StateTypeDef; - -/** - * @brief ADC Init structure definition + * @brief Structure definition of ADC and regular group initialization + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. + * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. + * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. + * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). */ typedef struct { - uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for + uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for all the ADCs. This parameter can be a value of @ref ADC_ClockPrescaler */ - uint32_t Resolution; /*!< Configures the ADC resolution dual mode. + uint32_t Resolution; /*!< Configures the ADC resolution. This parameter can be a value of @ref ADC_Resolution */ - uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or - Single (one channel) mode. + uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) + or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). + This parameter can be a value of @ref ADC_Data_Align */ + uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). + Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). + Scan direction is upward: from rank1 to rank 'n'. This parameter can be set to ENABLE or DISABLE */ - uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set - at the end of single channel conversion or at the end of all conversions. - This parameter can be a value of @ref ADC_EOCSelection */ - uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. + uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. + This parameter can be a value of @ref ADC_EOCSelection. + Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. + Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) + or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. + Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). + If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ + uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, + after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ - uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for - regular channel group. + uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. + To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ - uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not - for regular channels. + uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. */ - uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done - using the sequencer for regular channel group. + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. + If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. - This parameter can be a value of @ref ADC_External_trigger_Source_Regular - Note: This parameter can be modified only if there is no conversion is ongoing. */ + If set to external trigger source, triggering is on event rising edge by default. + This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. - This parameter can be a value of @ref ADC_External_trigger_edge_Regular - Note: This parameter can be modified only if there is no conversion is ongoing. */ + This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ + uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). + This parameter can be set to ENABLE or DISABLE. */ }ADC_InitTypeDef; + + /** - * @brief ADC handle Structure definition + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { - ADC_TypeDef *Instance; /*!< Register base address */ - - ADC_InitTypeDef Init; /*!< ADC required parameters */ - - __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ - - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - - HAL_LockTypeDef Lock; /*!< ADC locking object */ - - __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ - - __IO uint32_t ErrorCode; /*!< ADC Error code */ -}ADC_HandleTypeDef; - -/** - * @brief ADC Configuration regular Channel structure definition - */ -typedef struct -{ - uint32_t Channel; /*!< The ADC channel to configure. - This parameter can be a value of @ref ADC_channels */ - uint32_t Rank; /*!< The rank in the regular group sequencer. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ - uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel. - This parameter can be a value of @ref ADC_sampling_times */ - uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ + uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels */ + uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ }ADC_ChannelConfTypeDef; /** - * @brief ADC Configuration multi-mode structure definition + * @brief ADC Configuration multi-mode structure definition */ typedef struct { @@ -174,33 +167,86 @@ typedef struct This parameter can be set to ENABLE or DISABLE */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ }ADC_AnalogWDGConfTypeDef; + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */ + + +/** + * @brief ADC handle Structure definition + */ +typedef struct +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC required parameters */ + + __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO uint32_t State; /*!< ADC communication state */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ +}ADC_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup ADC_Exported_Constants ADC Exported Constants * @{ */ - /** @defgroup ADC_Error_Code ADC Error Code * @{ */ - -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */ /** * @} */ -/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler +/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler * @{ */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000) +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U) #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) @@ -211,7 +257,7 @@ typedef struct /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases * @{ */ -#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000) +#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U) #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) @@ -234,7 +280,7 @@ typedef struct /** @defgroup ADC_Resolution ADC Resolution * @{ */ -#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) +#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) @@ -245,7 +291,7 @@ typedef struct /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) @@ -258,7 +304,9 @@ typedef struct */ /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ /* compatibility with other STM32 devices. */ -#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000) + + +#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) @@ -275,14 +323,15 @@ typedef struct #define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL) #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1) + /** * @} */ -/** @defgroup ADC_data_align ADC Data Align +/** @defgroup ADC_Data_Align ADC Data Align * @{ */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} @@ -291,7 +340,7 @@ typedef struct /** @defgroup ADC_channels ADC Common Channels * @{ */ -#define ADC_CHANNEL_0 ((uint32_t)0x00000000) +#define ADC_CHANNEL_0 ((uint32_t)0x00000000U) #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) @@ -320,7 +369,7 @@ typedef struct /** @defgroup ADC_sampling_times ADC Sampling Times * @{ */ -#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000) +#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U) #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) @@ -335,9 +384,9 @@ typedef struct /** @defgroup ADC_EOCSelection ADC EOC Selection * @{ */ -#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000) -#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001) -#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */ +#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U) +#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U) +#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */ /** * @} */ @@ -360,7 +409,7 @@ typedef struct #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) +#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U) /** * @} */ @@ -392,9 +441,9 @@ typedef struct /** @defgroup ADC_channels_type ADC Channels Type * @{ */ -#define ADC_ALL_CHANNELS ((uint32_t)0x00000001) -#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */ -#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */ +#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U) +#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */ +#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */ /** * @} */ @@ -533,8 +582,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * @{ */ /* Peripheral State functions ***************************************************/ -HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} */ @@ -552,11 +601,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ /* Unit: us */ -#define ADC_STAB_DELAY_US ((uint32_t) 3) +#define ADC_STAB_DELAY_US ((uint32_t) 3U) /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ -#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) +#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) /** * @} */ @@ -565,6 +614,52 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ +/* Macro reserved for internal HAL driver usage, not intended to be used in + code of final user */ + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +#define ADC_IS_ENABLE(__HANDLE__) \ + ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + +/** + * @brief Test if conversion trigger of injected group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) + +/** + * @brief Simultaneously clears and sets specific bits of the handle State + * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Clear ADC error code (set it to error code: "no error") + * @param __HANDLE__: ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ + ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_adc_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_adc_ex.h index a1b69cdf2c..9ffe390e7e 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_adc_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_adc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -60,33 +60,78 @@ */ /** - * @brief ADC Configuration injected Channel structure definition + * @brief ADC Configuration injected Channel structure definition + * @note Parameters of this structure are shared within 2 scopes: + * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset + * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, + * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. + * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. + * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. */ typedef struct { - uint32_t InjectedChannel; /*!< Configure the ADC injected channel. - This parameter can be a value of @ref ADC_channels */ - uint32_t InjectedRank; /*!< The rank in the injected group sequencer - This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ - uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel. - This parameter can be a value of @ref ADC_sampling_times */ - uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for - injected channel group. - This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ - uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group - conversion after regular one */ - uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels. - This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */ - uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels. - This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */ + uint32_t InjectedChannel; /*!< Selection of ADC channel to configure + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ + uint32_t InjectedRank; /*!< Rank in the injected group sequencer + This parameter must be a value of @ref ADCEx_injected_rank + Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), + this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. + To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 4. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one + This parameter can be set to ENABLE or DISABLE. + Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) + Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. + To maintain JAUTO always enabled, DMA must be configured in circular mode. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. + This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected + Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. + This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. + If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ }ADC_InjectionConfTypeDef; +/** + * @} + */ /** - * @brief ADC Configuration multi-mode structure definition + * @brief ADC Configuration multi-mode structure definition */ typedef struct { @@ -110,7 +155,7 @@ typedef struct /** @defgroup ADCEx_Common_mode ADC Common Mode * @{ */ -#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000) +#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U) #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) @@ -130,7 +175,7 @@ typedef struct /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode * @{ */ -#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */ +#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */ #define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ #define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ #define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ @@ -141,7 +186,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected * @{ */ -#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) @@ -152,7 +197,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0) #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1) #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) @@ -167,17 +212,18 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) +#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1) /** * @} */ -/** @defgroup ADCEx_injected_channel_selection ADC Injected Channel Selection +/** @defgroup ADCEx_injected_rank ADC Injected Rank * @{ */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) +#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U) +#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U) +#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U) +#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U) /** * @} */ @@ -185,7 +231,7 @@ typedef struct /** @defgroup ADCEx_channels ADC Specific Channels * @{ */ -#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000U) /** * @} */ @@ -217,11 +263,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); /* Peripheral Control functions *************************************************/ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); @@ -286,7 +332,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)) + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)) #define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) #define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4))) diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_can.h b/stmhal/hal/f7/inc/stm32f7xx_hal_can.h index 6f516dcccf..02c1bff3bd 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_can.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_can.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_can.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,14 +64,14 @@ */ typedef enum { - HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ }HAL_CAN_StateTypeDef; @@ -248,16 +248,16 @@ typedef struct /** @defgroup HAL_CAN_Error_Code HAL CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */ -#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */ -#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */ -#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */ -#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR 0x10 /*!< Form error */ -#define HAL_CAN_ERROR_ACK 0x20 /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR 0x40 /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD 0x80 /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */ +#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */ +#define HAL_CAN_ERROR_EWG 0x01U /*!< EWG error */ +#define HAL_CAN_ERROR_EPV 0x02U /*!< EPV error */ +#define HAL_CAN_ERROR_BOF 0x04U /*!< BOF error */ +#define HAL_CAN_ERROR_STF 0x08U /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR 0x10U /*!< Form error */ +#define HAL_CAN_ERROR_ACK 0x20U /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR 0x40U /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD 0x80U /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC 0x100U /*!< LEC transfer error */ /** * @} */ @@ -265,8 +265,8 @@ typedef struct /** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */ /** * @} */ @@ -274,7 +274,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -285,7 +285,7 @@ typedef struct /** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width * @{ */ -#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -296,7 +296,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 * @{ */ -#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -319,7 +319,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 * @{ */ -#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -334,8 +334,8 @@ typedef struct /** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ /** * @} */ @@ -343,8 +343,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ /** * @} */ @@ -352,8 +352,8 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ @@ -361,8 +361,8 @@ typedef struct /** @defgroup CAN_Identifier_Type CAN Identifier Type * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */ /** * @} */ @@ -370,8 +370,8 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */ /** * @} */ @@ -379,8 +379,8 @@ typedef struct /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ /** * @} */ @@ -394,34 +394,37 @@ typedef struct CAN_GetFlagStatus() function. */ /* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */ +#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */ + /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */ /** * @} */ @@ -456,9 +459,9 @@ typedef struct /** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition * @{ */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +#define CAN_TXMAILBOX_0 ((uint8_t)0x00U) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01U) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02U) /** * @} */ @@ -559,17 +562,13 @@ typedef struct * @arg CAN_FLAG_WKU: Wake up Flag * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK)))) +((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK)))) /** @brief Check if the specified CAN interrupt source is enabled or disabled. * @param __HANDLE__: CAN Handle @@ -600,7 +599,7 @@ typedef struct * @retval None */ #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) +((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) /** * @brief Cancel a transmit request. @@ -609,9 +608,9 @@ typedef struct * @retval None */ #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) /** * @brief Enable or disable the DBG Freeze for CAN. @@ -701,8 +700,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -#define CAN_FLAG_MASK ((uint32_t)0x000000FF) +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +#define CAN_FLAG_MASK ((uint32_t)0x000000FFU) /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_cortex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_cortex.h index 1588c0e7b2..1bf5d8ec45 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_cortex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_cortex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -105,15 +105,15 @@ typedef struct /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ /** * @} @@ -122,8 +122,8 @@ typedef struct /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source * @{ */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /** * @} @@ -133,10 +133,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) /** * @} */ @@ -144,8 +144,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) +#define MPU_REGION_ENABLE ((uint8_t)0x01U) +#define MPU_REGION_DISABLE ((uint8_t)0x00U) /** * @} */ @@ -153,8 +153,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) /** * @} */ @@ -162,8 +162,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) /** * @} */ @@ -171,8 +171,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) /** * @} */ @@ -180,8 +180,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) /** * @} */ @@ -189,9 +189,9 @@ typedef struct /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels * @{ */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +#define MPU_TEX_LEVEL0 ((uint8_t)0x00U) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01U) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02U) /** * @} */ @@ -199,34 +199,34 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /** * @} */ @@ -234,12 +234,12 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) /** * @} */ @@ -247,14 +247,14 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /** * @} */ @@ -266,29 +266,6 @@ typedef struct /* Exported Macros -----------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros - * @{ - */ - -/** @brief Configures the SysTick clock source. - * @param __CLKSRC__: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \ - do { \ - if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \ - { \ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \ - } \ - else \ - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \ - } while(0) -/** - * @} - */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions @@ -314,6 +291,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); */ /* Peripheral Control functions ***********************************************/ #if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); @@ -346,9 +325,9 @@ void HAL_SYSTICK_Callback(void); ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) @@ -420,52 +399,7 @@ void HAL_SYSTICK_Callback(void); ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Functions CORTEX Private Functions - * @brief CORTEX private functions - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** - * @brief Disables the MPU - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Disable(void) -{ - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** - * @brief Enables the MPU - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -} +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) #endif /* __MPU_PRESENT */ /** diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_dac.h b/stmhal/hal/f7/inc/stm32f7xx_hal_dac.h index ed885ce1f2..d604e9be33 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_dac.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_dac.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,11 +64,11 @@ */ typedef enum { - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ }HAL_DAC_StateTypeDef; /** @@ -113,10 +113,10 @@ typedef struct /** @defgroup DAC_Error_Code DAC Error Code * @{ */ -#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ /** * @} */ @@ -125,7 +125,7 @@ typedef struct * @{ */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ @@ -143,7 +143,7 @@ typedef struct /** @defgroup DAC_output_buffer DAC Output Buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U) #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) /** * @} @@ -152,8 +152,8 @@ typedef struct /** @defgroup DAC_Channel_selection DAC Channel Selection * @{ */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) +#define DAC_CHANNEL_1 ((uint32_t)0x00000000U) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010U) /** * @} */ @@ -161,9 +161,9 @@ typedef struct /** @defgroup DAC_data_alignment DAC Data Alignment * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) +#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U) +#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U) +#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U) /** * @} */ @@ -342,7 +342,7 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); /** @defgroup DAC_Private_Macros DAC Private Macros * @{ */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) @@ -365,19 +365,19 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__)) /** * @} diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_dac_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_dac_ex.h index cf9b76f650..fc1506eeb4 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_dac_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_dac_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,7 +63,7 @@ /** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ @@ -75,7 +75,7 @@ #define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */ #define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ #define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ #define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_def.h b/stmhal/hal/f7/inc/stm32f7xx_hal_def.h index a1372ae61b..66e0af0386 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_def.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_def.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f7xx_hal_def.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,10 +55,10 @@ */ typedef enum { - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, - HAL_TIMEOUT = 0x03 + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; /** @@ -71,7 +71,7 @@ typedef enum } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ -#define HAL_MAX_DELAY 0xFFFFFFFF +#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) @@ -99,11 +99,11 @@ typedef enum * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) #if (USE_RTOS == 1) /* Reserved for future use */ - #error USE_RTOS should be 0 in the current HAL release + #error "USE_RTOS should be 0 in the current HAL release" #else #define __HAL_LOCK(__HANDLE__) \ do{ \ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_dma.h b/stmhal/hal/f7/inc/stm32f7xx_hal_dma.h index fb213543f5..e9ecae8a21 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_dma.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_dma.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,7 +67,7 @@ typedef struct { uint32_t Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_Channel_selection */ + This parameter can be a value of @ref DMAEx_Channel_selection */ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. @@ -119,17 +119,12 @@ typedef struct */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ - HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ - HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ - HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ - HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ }HAL_DMA_StateTypeDef; /** @@ -137,10 +132,24 @@ typedef enum */ typedef enum { - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + /** * @brief DMA handle Structure definition */ @@ -162,9 +171,18 @@ typedef struct __DMA_HandleTypeDef void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - __IO uint32_t ErrorCode; /*!< DMA Error code */ + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + }DMA_HandleTypeDef; /** @@ -183,27 +201,14 @@ typedef struct __DMA_HandleTypeDef * @brief DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ -#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -/** - * @} - */ - -/** @defgroup DMA_Channel_selection DMA Channel selection - * @brief DMA channel selection - * @{ - */ -#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */ -#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */ -#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */ -#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */ -#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */ -#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */ -#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */ -#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */ +#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ /** * @} */ @@ -212,7 +217,7 @@ typedef struct __DMA_HandleTypeDef * @brief DMA data transfer direction * @{ */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ /** @@ -224,7 +229,7 @@ typedef struct __DMA_HandleTypeDef * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */ +#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ /** * @} */ @@ -234,29 +239,27 @@ typedef struct __DMA_HandleTypeDef * @{ */ #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ /** * @} */ - /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @brief DMA peripheral data size * @{ */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} */ - /** @defgroup DMA_Memory_data_size DMA Memory data size * @brief DMA memory data size * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ /** @@ -267,19 +270,18 @@ typedef struct __DMA_HandleTypeDef * @brief DMA mode * @{ */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ /** * @} */ - /** @defgroup DMA_Priority_level DMA Priority level * @brief DMA priority levels * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */ +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ @@ -287,12 +289,11 @@ typedef struct __DMA_HandleTypeDef * @} */ - /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode * @brief DMA FIFO direct mode * @{ */ -#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ +#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ /** * @} @@ -302,7 +303,7 @@ typedef struct __DMA_HandleTypeDef * @brief DMA FIFO level * @{ */ -#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ @@ -314,7 +315,7 @@ typedef struct __DMA_HandleTypeDef * @brief DMA memory burst * @{ */ -#define DMA_MBURST_SINGLE ((uint32_t)0x00000000) +#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) @@ -322,12 +323,11 @@ typedef struct __DMA_HandleTypeDef * @} */ - /** @defgroup DMA_Peripheral_burst DMA Peripheral burst * @brief DMA peripheral burst * @{ */ -#define DMA_PBURST_SINGLE ((uint32_t)0x00000000) +#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) @@ -343,7 +343,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) -#define DMA_IT_FE ((uint32_t)0x00000080) +#define DMA_IT_FE ((uint32_t)0x00000080U) /** * @} */ @@ -352,26 +352,26 @@ typedef struct __DMA_HandleTypeDef * @brief DMA flag definitions * @{ */ -#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001) -#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004) -#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008) -#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010) -#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020) -#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040) -#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100) -#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200) -#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400) -#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800) -#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000) -#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000) -#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000) -#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000) -#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000) -#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000) -#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000) -#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000) -#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000) -#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000) +#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U) +#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U) +#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) +#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) +#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) +#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) +#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) +#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) +#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) +#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) +#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) +#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) +#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) +#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) +#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) +#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) +#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) +#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) +#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) +#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) /** * @} */ @@ -558,7 +558,7 @@ typedef struct __DMA_HandleTypeDef * @brief Enable the specified DMA Stream interrupts. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: + * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. * @arg DMA_IT_TE: Transfer error interrupt mask. @@ -573,7 +573,7 @@ typedef struct __DMA_HandleTypeDef * @brief Disable the specified DMA Stream interrupts. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: + * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. * @arg DMA_IT_TE: Transfer error interrupt mask. @@ -655,8 +655,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + /** * @} */ @@ -687,20 +692,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); * @brief DMA private macros * @{ */ -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ - ((CHANNEL) == DMA_CHANNEL_1) || \ - ((CHANNEL) == DMA_CHANNEL_2) || \ - ((CHANNEL) == DMA_CHANNEL_3) || \ - ((CHANNEL) == DMA_CHANNEL_4) || \ - ((CHANNEL) == DMA_CHANNEL_5) || \ - ((CHANNEL) == DMA_CHANNEL_6) || \ - ((CHANNEL) == DMA_CHANNEL_7)) - #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_dma_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_dma_ex.h index 48800d0c3b..433d279c4c 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_dma_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_dma_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,11 +65,49 @@ */ typedef enum { - MEMORY0 = 0x00, /*!< Memory 0 */ - MEMORY1 = 0x01, /*!< Memory 1 */ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U, /*!< Memory 1 */ }HAL_DMA_MemoryTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMAEx_Channel_selection DMA Channel selection + * @brief DMAEx channel selection + * @{ + */ +#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/ +#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/ +#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/ +#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/ +#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/ +#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/ +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + /** * @} */ @@ -97,6 +135,42 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre * @} */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMA Private Macros + * @brief DMAEx private macros + * @{ + */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7) || \ + ((CHANNEL) == DMA_CHANNEL_8) || \ + ((CHANNEL) == DMA_CHANNEL_9) || \ + ((CHANNEL) == DMA_CHANNEL_10) || \ + ((CHANNEL) == DMA_CHANNEL_11) || \ + ((CHANNEL) == DMA_CHANNEL_12) || \ + ((CHANNEL) == DMA_CHANNEL_13) || \ + ((CHANNEL) == DMA_CHANNEL_14) || \ + ((CHANNEL) == DMA_CHANNEL_15)) +#else +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7)) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + /* Private functions ---------------------------------------------------------*/ /** @defgroup DMAEx_Private_Functions DMAEx Private Functions * @brief DMAEx Private functions diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_flash.h b/stmhal/hal/f7/inc/stm32f7xx_hal_flash.h index 59055a5afb..eaa215d0cc 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_flash.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_flash.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ */ typedef enum { - FLASH_PROC_NONE = 0, + FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE, FLASH_PROC_MASSERASE, FLASH_PROC_PROGRAM @@ -80,7 +80,7 @@ typedef struct __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ - __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ + __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ @@ -88,7 +88,7 @@ typedef struct HAL_LockTypeDef Lock; /* FLASH locking object */ - __IO uint32_t ErrorCode; /* FLASH error code */ + __IO uint32_t ErrorCode; /* FLASH error code */ }FLASH_ProcessTypeDef; @@ -105,12 +105,12 @@ typedef struct * @brief FLASH Error Code * @{ */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002) /*!< Programming Sequence error */ -#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004) /*!< Programming Parallelism error */ -#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) /*!< Programming Alignment error */ -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010) /*!< Write protection error */ -#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020) /*!< Operation Error */ +#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ /** * @} */ @@ -118,10 +118,10 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */ /** * @} */ @@ -137,6 +137,10 @@ typedef struct #define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ #define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + + +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) /** * @} */ @@ -146,7 +150,7 @@ typedef struct * @{ */ #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */ /** * @} */ @@ -154,11 +158,11 @@ typedef struct /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism * @{ */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) #define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0) #define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1) #define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) /** * @} */ @@ -166,10 +170,25 @@ typedef struct /** @defgroup FLASH_Keys FLASH Keys * @{ */ -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) +#define FLASH_KEY1 ((uint32_t)0x45670123U) +#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) +/** + * @} + */ + +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ /** * @} */ @@ -346,6 +365,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); * @{ */ +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ +#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) + /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_flash_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_flash_ex.h index 701eee4cc0..5ad4894754 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_flash_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_flash_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,6 +67,11 @@ typedef struct uint32_t TypeErase; /*!< Mass erase or sector Erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ +#if defined (FLASH_OPTCR_nDBANK) + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ +#endif /* FLASH_OPTCR_nDBANK */ + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of @ref FLASHEx_Sectors */ @@ -89,7 +94,7 @@ typedef struct uint32_t WRPState; /*!< Write protection activation or deactivation. This parameter can be a value of @ref FLASHEx_WRP_State */ - uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series */ uint32_t RDPLevel; /*!< Set the read protection level. @@ -99,7 +104,8 @@ typedef struct This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / - IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY. */ + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. + nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. This parameter can be a value of @ref FLASHEx_Boot_Address */ @@ -121,8 +127,8 @@ typedef struct /** @defgroup FLASHEx_Type_Erase FLASH Type Erase * @{ */ -#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */ -#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */ +#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ /** * @} */ @@ -130,10 +136,10 @@ typedef struct /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range * @{ */ -#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */ -#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */ -#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ /** * @} */ @@ -141,8 +147,8 @@ typedef struct /** @defgroup FLASHEx_WRP_State FLASH WRP State * @{ */ -#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */ -#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ /** * @} */ @@ -150,12 +156,12 @@ typedef struct /** @defgroup FLASHEx_Option_Type FLASH Option Type * @{ */ -#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ -#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ -#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ -#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */ -#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10) /*!< Boot 0 Address configuration */ -#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20) /*!< Boot 1 Address configuration */ +#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ +#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ +#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ /** * @} */ @@ -163,9 +169,9 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection * @{ */ -#define OB_RDP_LEVEL_0 ((uint8_t)0xAA) -#define OB_RDP_LEVEL_1 ((uint8_t)0x55) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 +#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55U) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0 */ /** * @} @@ -174,8 +180,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog * @{ */ -#define OB_WWDG_SW ((uint32_t)0x10) /*!< Software WWDG selected */ -#define OB_WWDG_HW ((uint32_t)0x00) /*!< Hardware WWDG selected */ +#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ +#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ /** * @} */ @@ -184,8 +190,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog * @{ */ -#define OB_IWDG_SW ((uint32_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint32_t)0x00) /*!< Hardware IWDG selected */ +#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ /** * @} */ @@ -193,8 +199,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP * @{ */ -#define OB_STOP_NO_RST ((uint32_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint32_t)0x00) /*!< Reset generated when entering in STOP */ +#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ /** * @} */ @@ -202,8 +208,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY * @{ */ -#define OB_STDBY_NO_RST ((uint32_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint32_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ /** * @} */ @@ -211,8 +217,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP * @{ */ -#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */ -#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STOP mode */ +#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */ /** * @} */ @@ -220,8 +226,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY * @{ */ -#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STANDBY mode */ -#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STANDBY mode */ +#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */ /** * @} */ @@ -229,26 +235,47 @@ typedef struct /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level * @{ */ -#define OB_BOR_LEVEL3 ((uint32_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint32_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint32_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint32_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ - +#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */ /** * @} */ +#if defined (FLASH_OPTCR_nDBOOT) +/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT + * @{ + */ +#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ +#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash + (Dual bank Boot mode), or RAM if Boot address option in RAM */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBOOT */ + +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank + * @{ + */ +#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */ +#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ + /** @defgroup FLASHEx_Boot_Address FLASH Boot Address * @{ */ -#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000) /*!< Boot from ITCM RAM (0x00000000) */ -#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040) /*!< Boot from System memory bootloader (0x00100000) */ -#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080) /*!< Boot from Flash on ITCM interface (0x00200000) */ -#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000) /*!< Boot from Flash on AXIM interface (0x08000000) */ -#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000) /*!< Boot from DTCM RAM (0x20000000) */ -#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004) /*!< Boot from SRAM1 (0x20010000) */ -#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013) /*!< Boot from SRAM2 (0x2004C000) */ - +#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ /** * @} */ @@ -276,10 +303,26 @@ typedef struct * @} */ +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */ +#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */ +#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ + /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit * @{ */ -#define FLASH_MER_BIT (FLASH_CR_MER) /*!< MER bit to clear */ +#if defined (FLASH_OPTCR_nDBANK) +#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */ +#else +#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */ +#endif /* FLASH_OPTCR_nDBANK */ /** * @} */ @@ -287,43 +330,121 @@ typedef struct /** @defgroup FLASHEx_Sectors FLASH Sectors * @{ */ -#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ -#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ -#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ -#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ -#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ -#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ -#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */ -#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */ - +#if (FLASH_SECTOR_TOTAL == 24) +#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ /** * @} */ +#if (FLASH_SECTOR_TOTAL == 24) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. + * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and + * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). + * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. + * @{ + */ +/* Single Bank Sectors */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */ +#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ +#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ +#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ +#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ + +/* Dual Bank Sectors */ +#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */ +#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */ +#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */ +#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */ +#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */ +#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */ +#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */ +#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */ +#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ +#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ +#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ +#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ +#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ +#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ +#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ +#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */ +#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */ +#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */ +#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */ +#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */ +#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */ +#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */ +#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */ +#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */ +#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if (FLASH_SECTOR_TOTAL == 8) /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @{ */ -#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000) /*!< Write protection of Sector0 */ -#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000) /*!< Write protection of Sector1 */ -#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000) /*!< Write protection of Sector2 */ -#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000) /*!< Write protection of Sector3 */ -#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000) /*!< Write protection of Sector4 */ -#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000) /*!< Write protection of Sector5 */ -#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000) /*!< Write protection of Sector6 */ -#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000) /*!< Write protection of Sector7 */ -#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */ - - - +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */ /** * @} */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) + * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. + * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @retval The FLASH Boot Base Adress + */ +#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) + /** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ @@ -348,14 +469,6 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Constants FLASH Private Constants - * @{ - */ -#define FLASH_SECTOR_TOTAL 8 -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASHEx_Private_Macros FLASH Private Macros * @{ @@ -379,13 +492,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) -#define IS_OB_BOOT_ADDRESS(ADDRESS) (((ADDRESS) == OB_BOOTADDR_ITCM_RAM) || \ - ((ADDRESS) == OB_BOOTADDR_SYSTEM) || \ - ((ADDRESS) == OB_BOOTADDR_ITCM_FLASH) || \ - ((ADDRESS) == OB_BOOTADDR_AXIM_FLASH) || \ - ((ADDRESS) == OB_BOOTADDR_DTCM_RAM) || \ - ((ADDRESS) == OB_BOOTADDR_SRAM1) || \ - ((ADDRESS) == OB_BOOTADDR_SRAM2)) +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ ((LEVEL) == OB_RDP_LEVEL_1) ||\ @@ -423,17 +530,50 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); ((LATENCY) == FLASH_LATENCY_14) || \ ((LATENCY) == FLASH_LATENCY_15)) +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) + +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) + +#if (FLASH_SECTOR_TOTAL == 8) #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 8 */ -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) +#if (FLASH_SECTOR_TOTAL == 24) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ + ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ + ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ + ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ + ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ + ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ + ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ + ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ + ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ + ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ + ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) -#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if defined (FLASH_OPTCR_nDBANK) +#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ + ((VALUE) == OB_NDBANK_DUAL_BANK)) + +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#endif /* FLASH_OPTCR_nDBANK */ + +#if defined (FLASH_OPTCR_nDBOOT) +#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \ + ((VALUE) == OB_DUAL_BOOT_ENABLE)) +#endif /* FLASH_OPTCR_nDBOOT */ -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000)) /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_gpio.h b/stmhal/hal/f7/inc/stm32f7xx_hal_gpio.h index ab45cbccf2..ae8d7eafef 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_gpio.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_gpio.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,25 +101,25 @@ typedef enum /** @defgroup GPIO_pins_define GPIO pins define * @{ */ -#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ /** * @} */ @@ -134,21 +134,21 @@ typedef enum * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -157,10 +157,10 @@ typedef enum * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */ -#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */ -#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */ -#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */ +#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */ /** * @} */ @@ -169,9 +169,9 @@ typedef enum * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ +#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ /** * @} */ @@ -280,7 +280,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)) #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_gpio_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_gpio_ex.h index 7e2cc48257..474c24ff71 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_gpio_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_gpio_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,135 +64,178 @@ /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection * @{ */ - +/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** * @brief AF 0 selection */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */ +#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 2 selection */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ /** * @brief AF 3 selection */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -#define GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ - - +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 4 selection */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 5 selection */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ -#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */ /** * @brief AF 6 selection */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 7 selection */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ -#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */ -#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */ +#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 8 selection */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPIDIF-RX Alternate Function mapping */ -#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 9 selection */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */ -#if defined(STM32F756xx) || defined(STM32F746xx) -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F756xx || STM32F746xx */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 10 selection */ -#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ -#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 11 selection */ -#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ +#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 12 selection */ -#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 13 selection */ -#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ -#if defined(STM32F756xx) || defined(STM32F746xx) /** * @brief AF 14 selection */ -#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F756xx || STM32F746xx */ +#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 15 selection */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/*----------------------------------------------------------------------------*/ /** * @} @@ -252,6 +295,8 @@ /** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index * @{ */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -262,6 +307,8 @@ ((__GPIOx__) == (GPIOH))? 7U :\ ((__GPIOx__) == (GPIOI))? 8U :\ ((__GPIOx__) == (GPIOJ))? 9U : 10U) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ @@ -313,9 +360,9 @@ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC)) #elif defined(STM32F745xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ @@ -340,8 +387,106 @@ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT)) +#elif defined(STM32F767xx) || defined(STM32F777xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F769xx) || defined(STM32F779xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI)) +#elif defined(STM32F765xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF10_OTG_FS)) #endif /* STM32F756xx || STM32F746xx */ /** * @} diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_i2c.h b/stmhal/hal/f7/inc/stm32f7xx_hal_i2c.h index d0998a89c6..11f56df00b 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_i2c.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_i2c.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -73,22 +73,22 @@ typedef struct This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_addressing_mode */ + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_dual_addressing_mode */ + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_own_address2_masks */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_general_call_addressing_mode */ + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_nostretch_mode */ + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ }I2C_InitTypeDef; @@ -98,24 +98,81 @@ typedef struct /** @defgroup HAL_state_structure_definition HAL state structure definition * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (IP in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) * @{ */ typedef enum { - HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ - HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */ - HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ - HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ - HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ - HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */ - HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + }HAL_I2C_StateTypeDef; +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 + * 0 : None + * 1 : Memory (HAL I2C communication is in Memory Mode) + * b5 + * 0 : None + * 1 : Slave (HAL I2C communication is in Slave Mode) + * b4 + * 0 : None + * 1 : Master (HAL I2C communication is in Master Mode) + * b3-b2-b1-b0 (not used) + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +}HAL_I2C_ModeTypeDef; + /** * @} */ @@ -124,14 +181,15 @@ typedef enum * @brief I2C Error Code definition * @{ */ -#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */ +#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_ABORT ((uint32_t)0x00000080U) /*!< Abort user request */ /** * @} */ @@ -140,28 +198,38 @@ typedef enum * @brief I2C handle Structure definition * @{ */ -typedef struct +typedef struct __I2C_HandleTypeDef { - I2C_TypeDef *Instance; /*!< I2C registers base address */ + I2C_TypeDef *Instance; /*!< I2C registers base address */ - I2C_InitTypeDef Init; /*!< I2C communication parameters */ + I2C_InitTypeDef Init; /*!< I2C communication parameters */ - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - uint16_t XferSize; /*!< I2C transfer size */ + uint16_t XferSize; /*!< I2C transfer size */ - __IO uint16_t XferCount; /*!< I2C transfer counter */ + __IO uint16_t XferCount; /*!< I2C transfer counter */ - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_LockTypeDef Lock; /*!< I2C locking object */ + HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - __IO uint32_t ErrorCode; /*!< I2C Error code */ + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ }I2C_HandleTypeDef; /** * @} @@ -176,80 +244,101 @@ typedef struct * @{ */ -/** @defgroup I2C_addressing_mode I2C addressing mode +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options * @{ */ -#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) -#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) /** * @} */ -/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode * @{ */ -#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U) #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} */ -/** @defgroup I2C_own_address2_masks I2C own address2 masks +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks * @{ */ -#define I2C_OA2_NOMASK ((uint8_t)0x00) -#define I2C_OA2_MASK01 ((uint8_t)0x01) -#define I2C_OA2_MASK02 ((uint8_t)0x02) -#define I2C_OA2_MASK03 ((uint8_t)0x03) -#define I2C_OA2_MASK04 ((uint8_t)0x04) -#define I2C_OA2_MASK05 ((uint8_t)0x05) -#define I2C_OA2_MASK06 ((uint8_t)0x06) -#define I2C_OA2_MASK07 ((uint8_t)0x07) +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) /** * @} */ -/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode * @{ */ -#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U) #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} */ -/** @defgroup I2C_nostretch_mode I2C nostretch mode +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode * @{ */ -#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U) #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ -/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size * @{ */ -#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) -#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002) +#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U) +#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U) /** * @} */ -/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition +/** @defgroup I2C_XferDirection I2C Transfer Direction + * @{ + */ +#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000000U) +#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode * @{ */ #define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE ((uint32_t)0x00000000) +#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U) /** * @} */ -/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode * @{ */ -#define I2C_NO_STARTSTOP ((uint32_t)0x00000000) +#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U) #define I2C_GENERATE_STOP I2C_CR2_STOP #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define I2C_GENERATE_START_WRITE I2C_CR2_START @@ -270,7 +359,6 @@ typedef struct #define I2C_IT_ADDRI I2C_CR1_ADDRIE #define I2C_IT_RXI I2C_CR1_RXIE #define I2C_IT_TXI I2C_CR1_TXIE - /** * @} */ @@ -308,122 +396,127 @@ typedef struct * @{ */ -/** @brief Reset I2C handle state - * @param __HANDLE__: specifies the I2C Handle. +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -/** @brief Enable the specified I2C interrupts. - * @param __HANDLE__: specifies the I2C Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable. +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: - * @arg I2C_IT_ERRI: Errors interrupt enable - * @arg I2C_IT_TCI: Transfer complete interrupt enable - * @arg I2C_IT_STOPI: STOP detection interrupt enable - * @arg I2C_IT_NACKI: NACK received interrupt enable - * @arg I2C_IT_ADDRI: Address match interrupt enable - * @arg I2C_IT_RXI: RX interrupt enable - * @arg I2C_IT_TXI: TX interrupt enable + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable * * @retval None */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupts. - * @param __HANDLE__: specifies the I2C Handle. - * @param __INTERRUPT__: specifies the interrupt source to disable. +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. * This parameter can be one of the following values: - * @arg I2C_IT_ERRI: Errors interrupt enable - * @arg I2C_IT_TCI: Transfer complete interrupt enable - * @arg I2C_IT_STOPI: STOP detection interrupt enable - * @arg I2C_IT_NACKI: NACK received interrupt enable - * @arg I2C_IT_ADDRI: Address match interrupt enable - * @arg I2C_IT_RXI: RX interrupt enable - * @arg I2C_IT_TXI: TX interrupt enable + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable * * @retval None */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) -/** @brief Checks if the specified I2C interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2C Handle. - * @param __INTERRUPT__: specifies the I2C interrupt source to check. +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. * This parameter can be one of the following values: - * @arg I2C_IT_ERRI: Errors interrupt enable - * @arg I2C_IT_TCI: Transfer complete interrupt enable - * @arg I2C_IT_STOPI: STOP detection interrupt enable - * @arg I2C_IT_NACKI: NACK received interrupt enable - * @arg I2C_IT_ADDRI: Address match interrupt enable - * @arg I2C_IT_RXI: RX interrupt enable - * @arg I2C_IT_TXI: TX interrupt enable + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable * - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** @brief Checks whether the specified I2C flag is set or not. - * @param __HANDLE__: specifies the I2C Handle. - * @param __FLAG__: specifies the flag to check. +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg I2C_FLAG_TXE: Transmit data register empty - * @arg I2C_FLAG_TXIS: Transmit interrupt status - * @arg I2C_FLAG_RXNE: Receive data register not empty - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_TC: Transfer complete (master mode) - * @arg I2C_FLAG_TCR: Transfer complete reload - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus alert - * @arg I2C_FLAG_BUSY: Bus busy - * @arg I2C_FLAG_DIR: Transfer direction (slave mode) + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) * - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @retval The new state of __FLAG__ (SET or RESET). */ -#define I2C_FLAG_MASK ((uint32_t)0x0001FFFF) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) -/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__: specifies the I2C Handle. - * @param __FLAG__: specifies the flag to clear. +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus alert + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert * * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK)) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__: specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} */ -/* Include I2C HAL Extension module */ +/* Include I2C HAL Extended module */ #include "stm32f7xx_hal_i2c_ex.h" /* Exported functions --------------------------------------------------------*/ @@ -464,6 +557,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); @@ -475,7 +576,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @} */ -/** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ @@ -485,18 +586,22 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); /** * @} */ -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions * @{ */ -/* Peripheral State and Errors functions *************************************/ +/* Peripheral State, Mode and Error functions *********************************/ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** @@ -522,49 +627,59 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); */ #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) + ((CALL) == I2C_GENERALCALL_ENABLE)) #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) #define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16) +#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) /** * @} @@ -595,4 +710,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* __STM32F7xx_HAL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_i2c_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_i2c_ex.h index b353058163..f1e1e7c165 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_i2c_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_i2c_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,12 +64,32 @@ /** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP + +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP + +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + /** * @} */ @@ -80,6 +100,10 @@ /* Peripheral Control methods ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants @@ -97,7 +121,42 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ ((FILTER) == I2C_ANALOGFILTER_DISABLE)) -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) +#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) +#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) +#elif defined(SYSCFG_PMC_I2C1_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) +#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ +/** + * @} + */ /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_i2s.h b/stmhal/hal/f7/inc/stm32f7xx_hal_i2s.h index d2ae5ce045..af492784d4 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_i2s.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_i2s.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -91,14 +91,14 @@ typedef struct */ typedef enum { - HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */ - HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ }HAL_I2S_StateTypeDef; @@ -152,12 +152,12 @@ typedef struct *@brief I2S Error Code * @{ */ -#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */ -#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */ -#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */ -#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */ +#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */ +#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004U) /*!< UDR error */ +#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ +#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010U) /*!< Unknow Error error */ /** * @} @@ -165,8 +165,8 @@ typedef struct /** @defgroup I2S_Clock_Source I2S Clock Source * @{ */ -#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001) -#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002) +#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U) +#define I2S_CLOCK_PLL ((uint32_t)0x00000002U) /** * @} */ @@ -174,10 +174,10 @@ typedef struct /** @defgroup I2S_Mode I2S Mode * @{ */ -#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000) -#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100) -#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200) -#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300) +#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) +#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U) +#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U) +#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U) /** * @} */ @@ -185,11 +185,11 @@ typedef struct /** @defgroup I2S_Standard I2S Standard * @{ */ -#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) -#define I2S_STANDARD_MSB ((uint32_t)0x00000010) -#define I2S_STANDARD_LSB ((uint32_t)0x00000020) -#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030) -#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0) +#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) +#define I2S_STANDARD_MSB ((uint32_t)0x00000010U) +#define I2S_STANDARD_LSB ((uint32_t)0x00000020U) +#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U) +#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U) /** * @} */ @@ -197,10 +197,10 @@ typedef struct /** @defgroup I2S_Data_Format I2S Data Format * @{ */ -#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000) -#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001) -#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003) -#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005) +#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) +#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U) +#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U) +#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U) /** * @} */ @@ -209,7 +209,7 @@ typedef struct * @{ */ #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) -#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) +#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -217,16 +217,16 @@ typedef struct /** @defgroup I2S_Audio_Frequency I2S Audio Frequency * @{ */ -#define I2S_AUDIOFREQ_192K ((uint32_t)192000) -#define I2S_AUDIOFREQ_96K ((uint32_t)96000) -#define I2S_AUDIOFREQ_48K ((uint32_t)48000) -#define I2S_AUDIOFREQ_44K ((uint32_t)44100) -#define I2S_AUDIOFREQ_32K ((uint32_t)32000) -#define I2S_AUDIOFREQ_22K ((uint32_t)22050) -#define I2S_AUDIOFREQ_16K ((uint32_t)16000) -#define I2S_AUDIOFREQ_11K ((uint32_t)11025) -#define I2S_AUDIOFREQ_8K ((uint32_t)8000) -#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) +#define I2S_AUDIOFREQ_192K ((uint32_t)192000U) +#define I2S_AUDIOFREQ_96K ((uint32_t)96000U) +#define I2S_AUDIOFREQ_48K ((uint32_t)48000U) +#define I2S_AUDIOFREQ_44K ((uint32_t)44100U) +#define I2S_AUDIOFREQ_32K ((uint32_t)32000U) +#define I2S_AUDIOFREQ_22K ((uint32_t)22050U) +#define I2S_AUDIOFREQ_16K ((uint32_t)16000U) +#define I2S_AUDIOFREQ_11K ((uint32_t)11025U) +#define I2S_AUDIOFREQ_8K ((uint32_t)8000U) +#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U) /** * @} */ @@ -235,7 +235,7 @@ typedef struct /** @defgroup I2S_Clock_Polarity I2S Clock Polarity * @{ */ -#define I2S_CPOL_LOW ((uint32_t)0x00000000) +#define I2S_CPOL_LOW ((uint32_t)0x00000000U) #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) /** * @} @@ -434,7 +434,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @{ */ #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \ - ((CLOCK) == I2S_CLOCK_SYSCLK)) + ((CLOCK) == I2S_CLOCK_PLL)) #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ ((MODE) == I2S_MODE_SLAVE_RX) || \ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_pcd.h b/stmhal/hal/f7/inc/stm32f7xx_hal_pcd.h index 67cdc39813..53861137de 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_pcd.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_pcd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,20 +64,20 @@ */ typedef enum { - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 + HAL_PCD_STATE_RESET = 0x00U, + HAL_PCD_STATE_READY = 0x01U, + HAL_PCD_STATE_ERROR = 0x02U, + HAL_PCD_STATE_BUSY = 0x03U, + HAL_PCD_STATE_TIMEOUT = 0x04U } PCD_StateTypeDef; /* Device LPM suspend state */ typedef enum { - LPM_L0 = 0x00, /* on */ - LPM_L1 = 0x01, /* LPM L1 sleep */ - LPM_L2 = 0x02, /* suspend */ - LPM_L3 = 0x03, /* off */ + LPM_L0 = 0x00U, /* on */ + LPM_L1 = 0x01U, /* LPM L1 sleep */ + LPM_L2 = 0x02U, /* suspend */ + LPM_L3 = 0x03U, /* off */ }PCD_LPM_StateTypeDef; typedef USB_OTG_GlobalTypeDef PCD_TypeDef; @@ -118,9 +118,9 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_HIGH 0 -#define PCD_SPEED_HIGH_IN_FULL 1 -#define PCD_SPEED_FULL 2 +#define PCD_SPEED_HIGH 0U +#define PCD_SPEED_HIGH_IN_FULL 1U +#define PCD_SPEED_FULL 2U /** * @} */ @@ -128,8 +128,8 @@ typedef struct /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ -#define PCD_PHY_ULPI 1 -#define PCD_PHY_EMBEDDED 2 +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U /** * @} */ @@ -138,10 +138,10 @@ typedef struct * @{ */ #ifndef USBD_HS_TRDT_VALUE - #define USBD_HS_TRDT_VALUE 9 + #define USBD_HS_TRDT_VALUE 9U #endif /* USBD_HS_TRDT_VALUE */ #ifndef USBD_FS_TRDT_VALUE - #define USBD_FS_TRDT_VALUE 5 + #define USBD_FS_TRDT_VALUE 5U #endif /* USBD_HS_TRDT_VALUE */ /** @@ -172,16 +172,16 @@ typedef struct #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) +#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) -#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) +#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) +#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) +#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) -#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */ -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */ +#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) @@ -219,6 +219,9 @@ typedef struct EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup PCD_Exported_Functions PCD Exported Functions @@ -239,7 +242,7 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); /* I/O operation functions ***************************************************/ /* Non-Blocking mode: Interrupt */ -/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions * @{ */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); @@ -295,6 +298,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @} */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ /** @defgroup PCD_Instance_definition PCD Instance definition * @{ */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_pcd_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_pcd_ex.h index 2239363071..bd0a24aa27 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_pcd_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_pcd_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -56,8 +56,8 @@ /* Exported types ------------------------------------------------------------*/ typedef enum { - PCD_LPM_L0_ACTIVE = 0x00, /* on */ - PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ + PCD_LPM_L0_ACTIVE = 0x00U, /* on */ + PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */ }PCD_LPM_MsgTypeDef; /* Exported constants --------------------------------------------------------*/ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_pwr.h b/stmhal/hal/f7/inc/stm32f7xx_hal_pwr.h index 47792a65a8..d04517d403 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_pwr.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_pwr.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,13 +101,13 @@ typedef struct /** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -115,7 +115,7 @@ typedef struct /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode * @{ */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS /** * @} @@ -124,8 +124,8 @@ typedef struct /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /** * @} */ @@ -133,8 +133,8 @@ typedef struct /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /** * @} */ @@ -364,7 +364,7 @@ void HAL_PWR_DisableSEVOnPend(void); /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line * @{ */ -#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ /** * @} */ @@ -380,8 +380,6 @@ void HAL_PWR_DisableSEVOnPend(void); /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters * @{ */ -#define IS_PWR_WAKEUP_POLARITY(POLARITY) (((POLARITY) == PWR_POLARITY_RISINGEDGE) || \ - ((POLARITY) == PWR_POLARITY_FALLINGEDGE)) #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_pwr_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_pwr_ex.h index 3f4ab57779..d6faa04a18 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_pwr_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_pwr_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -99,7 +99,7 @@ */ #define PWR_FLAG_ODRDY PWR_CSR1_ODRDY #define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY -#define PWR_FLAG_UDRDY PWR_CSR1_UDSWRDY +#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rcc.h index 53e4d1dc78..fe7153f8b1 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_rcc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -46,6 +46,10 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +/* Include RCC HAL Extended module */ +/* (include on top of file since RCC structures are defined in extended file) */ +#include "stm32f7xx_hal_rcc_ex.h" + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -60,31 +64,6 @@ * @{ */ -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ - - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ - - uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. - This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ - -}RCC_PLLInitTypeDef; - /** * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ @@ -102,7 +81,7 @@ typedef struct uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ - uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ uint32_t LSIState; /*!< The new state of the LSI. @@ -146,11 +125,11 @@ typedef struct /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) +#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) +#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) +#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) +#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) +#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /** * @} */ @@ -158,7 +137,7 @@ typedef struct /** @defgroup RCC_HSE_Config RCC HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_OFF ((uint32_t)0x00000000U) #define RCC_HSE_ON RCC_CR_HSEON #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /** @@ -168,7 +147,7 @@ typedef struct /** @defgroup RCC_LSE_Config RCC LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000) +#define RCC_LSE_OFF ((uint32_t)0x00000000U) #define RCC_LSE_ON RCC_BDCR_LSEON #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /** @@ -178,8 +157,10 @@ typedef struct /** @defgroup RCC_HSI_Config RCC HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000) +#define RCC_HSI_OFF ((uint32_t)0x00000000U) #define RCC_HSI_ON RCC_CR_HSION + +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ /** * @} */ @@ -187,7 +168,7 @@ typedef struct /** @defgroup RCC_LSI_Config RCC LSI Config * @{ */ -#define RCC_LSI_OFF ((uint32_t)0x00000000) +#define RCC_LSI_OFF ((uint32_t)0x00000000U) #define RCC_LSI_ON RCC_CSR_LSION /** * @} @@ -196,9 +177,9 @@ typedef struct /** @defgroup RCC_PLL_Config RCC PLL Config * @{ */ -#define RCC_PLL_NONE ((uint32_t)0x00000000) -#define RCC_PLL_OFF ((uint32_t)0x00000001) -#define RCC_PLL_ON ((uint32_t)0x00000002) +#define RCC_PLL_NONE ((uint32_t)0x00000000U) +#define RCC_PLL_OFF ((uint32_t)0x00000001U) +#define RCC_PLL_ON ((uint32_t)0x00000002U) /** * @} */ @@ -206,10 +187,10 @@ typedef struct /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider * @{ */ -#define RCC_PLLP_DIV2 ((uint32_t)0x00000002) -#define RCC_PLLP_DIV4 ((uint32_t)0x00000004) -#define RCC_PLLP_DIV6 ((uint32_t)0x00000006) -#define RCC_PLLP_DIV8 ((uint32_t)0x00000008) +#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) +#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) +#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) +#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /** * @} */ @@ -226,10 +207,10 @@ typedef struct /** @defgroup RCC_System_Clock_Type RCC System Clock Type * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) +#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /** * @} */ @@ -286,38 +267,38 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source * @{ */ -#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300) +#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) +#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) +#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) +#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) +#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) +#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) +#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) +#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) +#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) +#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) +#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) +#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) +#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) +#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) +#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) +#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) +#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) +#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) +#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) +#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) /** * @} */ @@ -327,8 +308,8 @@ typedef struct /** @defgroup RCC_MCO_Index RCC MCO Index * @{ */ -#define RCC_MCO1 ((uint32_t)0x00000000) -#define RCC_MCO2 ((uint32_t)0x00000001) +#define RCC_MCO1 ((uint32_t)0x00000000U) +#define RCC_MCO2 ((uint32_t)0x00000001U) /** * @} */ @@ -336,7 +317,7 @@ typedef struct /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source * @{ */ -#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000) +#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 @@ -347,7 +328,7 @@ typedef struct /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source * @{ */ -#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 @@ -358,7 +339,7 @@ typedef struct /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler * @{ */ -#define RCC_MCODIV_1 ((uint32_t)0x00000000) +#define RCC_MCODIV_1 ((uint32_t)0x00000000U) #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) @@ -370,14 +351,14 @@ typedef struct /** @defgroup RCC_Interrupt RCC Interrupt * @{ */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) -#define RCC_IT_CSS ((uint8_t)0x80) +#define RCC_IT_LSIRDY ((uint8_t)0x01U) +#define RCC_IT_LSERDY ((uint8_t)0x02U) +#define RCC_IT_HSIRDY ((uint8_t)0x04U) +#define RCC_IT_HSERDY ((uint8_t)0x08U) +#define RCC_IT_PLLRDY ((uint8_t)0x10U) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) +#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) +#define RCC_IT_CSS ((uint8_t)0x80U) /** * @} */ @@ -392,24 +373,24 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C) +#define RCC_FLAG_HSIRDY ((uint8_t)0x21U) +#define RCC_FLAG_HSERDY ((uint8_t)0x31U) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) +#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) /* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSERDY ((uint8_t)0x41U) /* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61U) +#define RCC_FLAG_BORRST ((uint8_t)0x79U) +#define RCC_FLAG_PINRST ((uint8_t)0x7AU) +#define RCC_FLAG_PORRST ((uint8_t)0x7BU) +#define RCC_FLAG_SFTRST ((uint8_t)0x7CU) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) /** * @} */ @@ -417,7 +398,7 @@ typedef struct /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations * @{ */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) +#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV @@ -563,11 +544,11 @@ typedef struct * @brief Force or release AHB peripheral reset. * @{ */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) -#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00) +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) /** @@ -578,11 +559,11 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) /** @@ -593,10 +574,10 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) /** @@ -714,7 +695,7 @@ typedef struct * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. + * (default is RCC_HSICALIBRATION_DEFAULT). */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM))) @@ -744,7 +725,10 @@ typedef struct * @{ */ /** - * @brief Macro to configure the External High Speed oscillator (__HSE__). + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. @@ -762,24 +746,27 @@ typedef struct * @arg RCC_HSE_ON: turn ON the HSE oscillator. * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - if((__STATE__) == RCC_HSE_ON) \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ } while(0) /** * @} @@ -791,7 +778,7 @@ typedef struct /** * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * User should request a transition to LSE Off first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using @@ -809,12 +796,15 @@ typedef struct */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ if((__STATE__) == RCC_LSE_ON) \ { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ else if((__STATE__) == RCC_LSE_BYPASS) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ @@ -822,8 +812,8 @@ typedef struct } \ else \ { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while(0) /** @@ -893,39 +883,6 @@ typedef struct #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between Min_Data = 192 and Max_Data = 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on - * the System clock frequency. - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\ - (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \ - ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) - /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. * @param __PLLSOURCE__: specifies the PLL entry clock source. @@ -963,8 +920,8 @@ typedef struct * used as I2S clock source. */ #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ - RCC->CFGR |= (__SOURCE__); \ - }while(0) + RCC->CFGR |= (__SOURCE__); \ + }while(0) /** @brief Macros to enable or disable the PLLI2S. * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. @@ -1025,6 +982,51 @@ typedef struct * @} */ +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); +/** + * @} + */ + /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ @@ -1054,7 +1056,7 @@ typedef struct * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. @@ -1171,9 +1173,9 @@ void HAL_RCC_CSSCallback(void); * @{ */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias @@ -1187,7 +1189,7 @@ void HAL_RCC_CSSCallback(void); #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) -#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /** * @} */ @@ -1225,7 +1227,7 @@ void HAL_RCC_CSSCallback(void); ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) -#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) @@ -1276,9 +1278,9 @@ void HAL_RCC_CSSCallback(void); #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ - ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((DRIVE) == RCC_LSEDRIVE_HIGH)) + ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((DRIVE) == RCC_LSEDRIVE_HIGH)) /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h index 1249282a4c..3af7f21567 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,13 +59,42 @@ * @{ */ +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +}RCC_PLLInitTypeDef; + /** * @brief PLLI2S Clock structure definition */ typedef struct { uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 49 and Max_Data = 432. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. @@ -76,9 +105,12 @@ typedef struct This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLI2S is selected as Clock Source SAI */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. - This parameter must be a number between 0 and 3 for respective values 2, 4, 6 and 8. - This parameter will be used only when PLLI2S is selected as Clock Source SPDDIF-RX */ + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ }RCC_PLLI2SInitTypeDef; /** @@ -87,19 +119,22 @@ typedef struct typedef struct { uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 49 and Max_Data = 432. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. - This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider This parameter will be used only when PLLSAI is disabled */ }RCC_PLLSAIInitTypeDef; @@ -191,6 +226,16 @@ typedef struct uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source + This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ + + uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ }RCC_PeriphCLKInitTypeDef; /** * @} @@ -204,45 +249,63 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection * @{ */ -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) -#if defined(STM32F756xx) || defined(STM32F746xx) -#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008) -#endif /* STM32F756xx || STM32F746xx */ -#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400) -#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800) -#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000) -#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000) -#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000) -#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000) -#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000) -#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000) -#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000) -#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000) - +#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) +#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) +#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) +#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) +#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) +#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) +#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) +#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) +#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider + * @{ + */ +#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) +/** + * @} + */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider * @{ */ -#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000) -#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001) -#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002) -#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003) +#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) /** * @} */ @@ -250,7 +313,7 @@ typedef struct /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR * @{ */ -#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000) +#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR @@ -261,7 +324,7 @@ typedef struct /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source * @{ */ -#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000) +#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC /** @@ -272,10 +335,12 @@ typedef struct /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source * @{ */ -#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 - +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -283,18 +348,12 @@ typedef struct /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source * @{ */ -#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source - * @{ - */ -#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000) -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -302,7 +361,7 @@ typedef struct /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source * @{ */ -#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000) +#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ /** * @} @@ -311,7 +370,7 @@ typedef struct /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source * @{ */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000) +#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL @@ -322,7 +381,7 @@ typedef struct /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source * @{ */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL @@ -333,7 +392,7 @@ typedef struct /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source * @{ */ -#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL @@ -344,7 +403,7 @@ typedef struct /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source * @{ */ -#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL @@ -355,7 +414,7 @@ typedef struct /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source * @{ */ -#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL @@ -366,7 +425,7 @@ typedef struct /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source * @{ */ -#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000) +#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL @@ -377,7 +436,7 @@ typedef struct /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source * @{ */ -#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL @@ -388,7 +447,7 @@ typedef struct /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source * @{ */ -#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL @@ -399,7 +458,7 @@ typedef struct /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source * @{ */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 /** @@ -409,7 +468,7 @@ typedef struct /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source * @{ */ -#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 @@ -420,7 +479,7 @@ typedef struct /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source * @{ */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 /** @@ -430,18 +489,17 @@ typedef struct /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source * @{ */ -#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 /** * @} */ - /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) +#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL @@ -453,7 +511,7 @@ typedef struct /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source * @{ */ -#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000) +#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL /** * @} @@ -462,14 +520,61 @@ typedef struct /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection * @{ */ -#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000) +#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE - - /** * @} */ +/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source + * @{ + */ +#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL +/** + * @} + */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source + * @{ + */ +#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) +/** + * @} + */ +#endif /* STM32F769xx || STM32F779xx */ + /** * @} */ @@ -710,6 +815,17 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ @@ -724,16 +840,14 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ UNUSED(tmpreg); \ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ } while(0) #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_DISABLE();\ - }while(0) -#if defined(STM32F756xx) +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -752,7 +866,8 @@ typedef struct #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F756x */ +#endif /* STM32F756x || STM32F777xx || STM32F779xx */ + /** @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before @@ -862,6 +977,24 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ @@ -1008,6 +1141,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) @@ -1063,6 +1200,16 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ @@ -1167,7 +1314,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ @@ -1175,16 +1322,47 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) @@ -1194,9 +1372,17 @@ typedef struct #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ @@ -1259,7 +1445,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) /** * @brief Disable ETHERNET clock. @@ -1270,7 +1456,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) /** @brief Get the enable or disable status of the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1281,17 +1467,21 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) - #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F756x */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1319,6 +1509,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) @@ -1347,6 +1541,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) @@ -1387,9 +1585,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) @@ -1407,9 +1613,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1455,31 +1669,35 @@ typedef struct /** @brief Force or release AHB2 peripheral reset. */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) - #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -#if defined(STM32F756xx) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) +#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Force or release AHB3 peripheral reset */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) @@ -1495,6 +1713,9 @@ typedef struct #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) @@ -1523,6 +1744,9 @@ typedef struct #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) @@ -1558,9 +1782,9 @@ typedef struct #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) @@ -1577,9 +1801,24 @@ typedef struct #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) + +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1656,19 +1895,24 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1698,6 +1942,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) @@ -1726,6 +1974,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) @@ -1741,8 +1993,8 @@ typedef struct #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1767,9 +2019,9 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) @@ -1788,9 +2040,22 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) + +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1871,19 +2136,24 @@ typedef struct #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) +#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1913,6 +2183,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) @@ -1941,6 +2215,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) @@ -1982,9 +2260,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) @@ -2003,13 +2289,92 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ +/*------------------------------- PLL Configuration --------------------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * @param __PLLR__: specifies the division factor for DSI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ + ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ + ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \ + ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR)))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ + ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ + ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*---------------------------------------------------------------------------------------------*/ /** @brief Macro to configure the Timers clocks prescalers @@ -2025,8 +2390,8 @@ typedef struct * to division by 8 or more. */ #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ - RCC->DCKCFGR1 |= (__PRESC__);\ - }while(0) + RCC->DCKCFGR1 |= (__PRESC__); \ + }while(0) /** @brief Macros to Enable or Disable the PLLISAI. * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. @@ -2039,36 +2404,44 @@ typedef struct * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. - * This parameter must be a number between Min_Data = 49 and Max_Data = 432. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 49 and Max_Data = 432 MHz. + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. * @param __PLLSAIQ__: specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLSAIR__: specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks - * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider . */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28)) +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\ + ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\ + ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\ + ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))) -/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API) * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. - * This parameter must be a number between Min_Data = 192 and Max_Data = 432. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock. + * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. * @param __PLLI2SQ__: specifies the division factor for SAI clock. * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLI2SR__: specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. - * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock. - * This parameter can be a number between 0 and 3 for respective values 2, 4, 6 and 8 */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28)) +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ + ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ + ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ + ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. @@ -2090,7 +2463,7 @@ typedef struct * * @note This function must be called before enabling the PLLSAI. * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . - * This parameter must be a number between Min_Data = 2 and Max_Data = 16. + * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ @@ -2107,6 +2480,9 @@ typedef struct * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) @@ -2119,6 +2495,9 @@ typedef struct * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) @@ -2134,6 +2513,9 @@ typedef struct * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) @@ -2147,6 +2529,9 @@ typedef struct * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) @@ -2450,7 +2835,7 @@ typedef struct * @param __CEC_CLKSOURCE__: specifies the CEC clock source. * This parameter can be one of the following values: * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock - * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock */ #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) @@ -2467,7 +2852,7 @@ typedef struct * @param __CLK48_SOURCE__: specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source - * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 selected as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source */ #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) @@ -2475,7 +2860,7 @@ typedef struct /** @brief macro to get the CLK48 source. * @retval The clock source can be one of the following values: * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source - * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 used as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source */ #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) @@ -2496,6 +2881,72 @@ typedef struct */ #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). + * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) + +/** @brief macro to get the SDMMC2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) + +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock + * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) + +/** @brief Macro to configure the DFSDM1 Audio clock + * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 Audio clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__: specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) +#endif /* STM32F769xx || STM32F779xx */ /** * @} */ @@ -2520,7 +2971,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); */ #if defined(STM32F756xx) || defined(STM32F746xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ @@ -2540,12 +2991,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32F745xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ @@ -2564,17 +3015,78 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#endif /* STM32F756xx || STM32F746xx */ -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8)) +#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F765xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F746xx || STM32F756xx */ +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ + ((VALUE) == RCC_PLLI2SP_DIV4) ||\ + ((VALUE) == RCC_PLLI2SP_DIV6) ||\ + ((VALUE) == RCC_PLLI2SP_DIV8)) #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8)) +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) @@ -2583,20 +3095,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ - ((VALUE) == RCC_PLLSAIDIVR_4) ||\ - ((VALUE) == RCC_PLLSAIDIVR_8) ||\ + ((VALUE) == RCC_PLLSAIDIVR_4) ||\ + ((VALUE) == RCC_PLLSAIDIVR_8) ||\ ((VALUE) == RCC_PLLSAIDIVR_16)) #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) -#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) -#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) + ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) -#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) +#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ ((SOURCE) == RCC_CECCLKSOURCE_LSE)) @@ -2674,6 +3180,44 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); #define IS_RCC_TIMPRES(VALUE) \ (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rng.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rng.h index b2bca21de1..385aacdcfd 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_rng.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_rng.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -66,11 +66,11 @@ */ typedef enum { - HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */ - HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */ - HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */ - HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */ - HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */ + HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */ + HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */ + HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */ + HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */ + HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */ }HAL_RNG_StateTypeDef; diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rtc.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rtc.h index 20356a4564..a508fce6be 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_rtc.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_rtc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,11 +64,11 @@ */ typedef enum { - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ }HAL_RTCStateTypeDef; @@ -111,8 +111,15 @@ typedef struct uint8_t Seconds; /*!< Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity */ + + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content + corresponding to Synchronous pre-scaler factor value (PREDIV_S) + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity. + This field will be used only by HAL_RTC_GetTime function */ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ @@ -195,8 +202,8 @@ typedef struct /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) +#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U) +#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U) /** * @} */ @@ -205,8 +212,8 @@ typedef struct /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) +#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U) +#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U) /** * @} */ @@ -214,7 +221,7 @@ typedef struct /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U) #define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */ /** * @} @@ -223,8 +230,8 @@ typedef struct /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) /** * @} */ @@ -232,9 +239,9 @@ typedef struct /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) +#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U) +#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U) +#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U) /** * @} */ @@ -242,8 +249,8 @@ typedef struct /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) +#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U) +#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U) /** * @} */ @@ -251,8 +258,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x000000000) -#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN ((uint32_t)0x00000000U) +#define RTC_FORMAT_BCD ((uint32_t)0x00000001U) /** * @} */ @@ -261,18 +268,18 @@ typedef struct * @{ */ /* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) /** * @} */ @@ -280,13 +287,13 @@ typedef struct /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /** * @} */ @@ -294,8 +301,8 @@ typedef struct /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) +#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U) /** * @} */ @@ -303,12 +310,12 @@ typedef struct /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions * @{ */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U) #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U) /** * @} */ @@ -325,38 +332,38 @@ typedef struct /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. +#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U) /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U) /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U) /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U) /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U) /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U) /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U) /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U) /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U) /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U) /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U) /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U) /*!< SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U) /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U) /*!< SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match +#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U) /*!< SS[14:0] are compared and must match to activate alarm. */ /** * @} @@ -690,14 +697,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) #define RTC_TIMEOUT_VALUE 1000 -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rtc_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rtc_ex.h index c5da404be9..7f22612184 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_rtc_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_rtc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -106,10 +106,10 @@ typedef struct /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output selection Definitions * @{ */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) -#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) -#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000) -#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) +#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U) +#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U) +#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U) +#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U) /** * @} */ @@ -117,38 +117,38 @@ typedef struct /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions * @{ */ -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define RTC_BKP_DR20 ((uint32_t)0x00000014) -#define RTC_BKP_DR21 ((uint32_t)0x00000015) -#define RTC_BKP_DR22 ((uint32_t)0x00000016) -#define RTC_BKP_DR23 ((uint32_t)0x00000017) -#define RTC_BKP_DR24 ((uint32_t)0x00000018) -#define RTC_BKP_DR25 ((uint32_t)0x00000019) -#define RTC_BKP_DR26 ((uint32_t)0x0000001A) -#define RTC_BKP_DR27 ((uint32_t)0x0000001B) -#define RTC_BKP_DR28 ((uint32_t)0x0000001C) -#define RTC_BKP_DR29 ((uint32_t)0x0000001D) -#define RTC_BKP_DR30 ((uint32_t)0x0000001E) -#define RTC_BKP_DR31 ((uint32_t)0x0000001F) +#define RTC_BKP_DR0 ((uint32_t)0x00000000U) +#define RTC_BKP_DR1 ((uint32_t)0x00000001U) +#define RTC_BKP_DR2 ((uint32_t)0x00000002U) +#define RTC_BKP_DR3 ((uint32_t)0x00000003U) +#define RTC_BKP_DR4 ((uint32_t)0x00000004U) +#define RTC_BKP_DR5 ((uint32_t)0x00000005U) +#define RTC_BKP_DR6 ((uint32_t)0x00000006U) +#define RTC_BKP_DR7 ((uint32_t)0x00000007U) +#define RTC_BKP_DR8 ((uint32_t)0x00000008U) +#define RTC_BKP_DR9 ((uint32_t)0x00000009U) +#define RTC_BKP_DR10 ((uint32_t)0x0000000AU) +#define RTC_BKP_DR11 ((uint32_t)0x0000000BU) +#define RTC_BKP_DR12 ((uint32_t)0x0000000CU) +#define RTC_BKP_DR13 ((uint32_t)0x0000000DU) +#define RTC_BKP_DR14 ((uint32_t)0x0000000EU) +#define RTC_BKP_DR15 ((uint32_t)0x0000000FU) +#define RTC_BKP_DR16 ((uint32_t)0x00000010U) +#define RTC_BKP_DR17 ((uint32_t)0x00000011U) +#define RTC_BKP_DR18 ((uint32_t)0x00000012U) +#define RTC_BKP_DR19 ((uint32_t)0x00000013U) +#define RTC_BKP_DR20 ((uint32_t)0x00000014U) +#define RTC_BKP_DR21 ((uint32_t)0x00000015U) +#define RTC_BKP_DR22 ((uint32_t)0x00000016U) +#define RTC_BKP_DR23 ((uint32_t)0x00000017U) +#define RTC_BKP_DR24 ((uint32_t)0x00000018U) +#define RTC_BKP_DR25 ((uint32_t)0x00000019U) +#define RTC_BKP_DR26 ((uint32_t)0x0000001AU) +#define RTC_BKP_DR27 ((uint32_t)0x0000001BU) +#define RTC_BKP_DR28 ((uint32_t)0x0000001CU) +#define RTC_BKP_DR29 ((uint32_t)0x0000001DU) +#define RTC_BKP_DR30 ((uint32_t)0x0000001EU) +#define RTC_BKP_DR31 ((uint32_t)0x0000001FU) /** * @} */ @@ -156,8 +156,8 @@ typedef struct /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definitions * @{ */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) -#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) +#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U) +#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U) /** * @} */ @@ -186,9 +186,9 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) -#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002) -#define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004) +#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U) +#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002U) +#define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004U) /** * @} */ @@ -196,8 +196,8 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) +#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U) +#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U) #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE /** @@ -207,8 +207,8 @@ typedef struct /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions * @{ */ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000) -#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U) +#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U) /** * @} */ @@ -216,8 +216,8 @@ typedef struct /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions * @{ */ -#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000) -#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000) +#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U) +#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U) /** * @} */ @@ -225,13 +225,13 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions * @{ */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled */ -#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 +#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800U) /*!< Tamper is activated after 2 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 +#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000U) /*!< Tamper is activated after 4 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 +#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800U) /*!< Tamper is activated after 8 consecutive samples at the active leve. */ /** * @} @@ -240,21 +240,21 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ /** * @} @@ -263,13 +263,13 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U) /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U) /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ /** * @} @@ -279,7 +279,7 @@ typedef struct * @{ */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */ /** * @} */ @@ -287,7 +287,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event saved */ #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ /** * @} @@ -296,12 +296,12 @@ typedef struct /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U) +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U) /** * @} */ @@ -309,11 +309,11 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration +#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration +#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration +#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds */ /** * @} @@ -322,10 +322,10 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added +#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000U) /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] */ /** * @} @@ -334,8 +334,8 @@ typedef struct /** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions * @{ */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) +#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U) +#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U) /** * @} */ @@ -343,8 +343,8 @@ typedef struct /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions * @{ */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) +#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U) +#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000U) /** * @} */ @@ -924,8 +924,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_IM21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ /** * @} */ @@ -936,7 +936,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t */ /* Masks Definition */ #define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E)) -#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT)) +#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT)) /** * @} */ @@ -956,9 +956,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER) #define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \ ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING)) -#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET)) +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET)) -#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET)) +#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET)) #define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \ ((__PIN__) == RTC_TIMESTAMPPIN_POS1) || \ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_sd.h b/stmhal/hal/f7/inc/stm32f7xx_hal_sd.h index e74c092344..50fe9379c1 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_sd.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_sd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -285,15 +285,15 @@ typedef enum */ typedef enum { - SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */ - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */ - SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */ - SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */ - SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */ - SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */ - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */ - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */ - SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */ + SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */ + SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */ + SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */ + SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */ + SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */ + SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */ + SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */ + SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */ + SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card is in error state */ }HAL_SD_CardStateTypedef; /** @@ -305,10 +305,10 @@ typedef enum */ typedef enum { - SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */ - SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */ - SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */ - SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */ + SD_READ_SINGLE_BLOCK = 0U, /*!< Read single block operation */ + SD_READ_MULTIPLE_BLOCK = 1U, /*!< Read multiple blocks operation */ + SD_WRITE_SINGLE_BLOCK = 2U, /*!< Write single block operation */ + SD_WRITE_MULTIPLE_BLOCK = 3U /*!< Write multiple blocks operation */ }HAL_SD_OperationTypedef; /** @@ -327,102 +327,102 @@ typedef enum /** * @brief SD Commands Index */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ -#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ -#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ -#define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ +#define SD_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SD_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SD_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ +#define SD_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ +#define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information +#define SD_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ -#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ -#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands +#define SD_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SD_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ +#define SD_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ +#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14U) +#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */ -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of +#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ +#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ -#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SD_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ +#define SD_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ +#define SD_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ +#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ +#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ +#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SD_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. +#define SD_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by +#define SD_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ +#define SD_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ +#define SD_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ +#define SD_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather +#define SD_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card +#define SD_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SD_CMD_NO_CMD ((uint8_t)64) +#define SD_CMD_NO_CMD ((uint8_t)64U) /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with +#define SD_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ -#define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ -#define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */ +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ +#define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ +#define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are SD Card Specific security commands. * SD_CMD_APP_CMD should be sent before sending these commands. */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43U) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_MID ((uint8_t)44U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) /*!< For SD card only */ +#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) /*!< For SD card only */ /** * @brief Supported SD Memory Cards */ -#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) +#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000U) +#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001U) +#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002U) +#define MULTIMEDIA_CARD ((uint32_t)0x00000003U) +#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004U) +#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005U) +#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006U) +#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007U) /** * @} */ @@ -643,9 +643,8 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); * @{ */ /* Blocking mode: Polling */ -// dpgeorge: read/write functions renamed to emphasise that address is given by block number -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks); +HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); +HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr); /* Non-Blocking mode: Interrupt */ @@ -660,9 +659,8 @@ void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd); void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd); /* Non-Blocking mode: DMA */ -// dpgeorge: read/write functions renamed to emphasise that address is given by block number -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks); +HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); +HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); /** diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_spi.h b/stmhal/hal/f7/inc/stm32f7xx_hal_spi.h index ef1f100344..abda07e7de 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_spi.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_spi.h @@ -1,14 +1,14 @@ - /** +/** ****************************************************************************** * @file stm32f7xx_hal_spi.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -40,7 +40,7 @@ #define __STM32F7xx_HAL_SPI_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -64,48 +64,48 @@ */ typedef struct { - uint32_t Mode; /*!< Specifies the SPI operating mode. + uint32_t Mode; /*!< Specifies the SPI operating mode. This parameter can be a value of @ref SPI_Mode */ - uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. This parameter can be a value of @ref SPI_Direction */ - uint32_t DataSize; /*!< Specifies the SPI data size. + uint32_t DataSize; /*!< Specifies the SPI data size. This parameter can be a value of @ref SPI_Data_Size */ - uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_Clock_Polarity */ - uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_Clock_Phase */ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of @ref SPI_Slave_Select_management */ - uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_BaudRate_Prescaler @note The communication clock is derived from the master clock. The slave clock does not need to be set. */ - uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not . + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. This parameter can be a value of @ref SPI_TI_mode */ - uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_CRC_Calculation */ - uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */ - uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of @ref SPI_CRC_length */ - uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . This parameter can be a value of @ref SPI_NSSP_Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI @@ -114,57 +114,58 @@ typedef struct } SPI_InitTypeDef; /** - * @brief HAL State structures definition + * @brief HAL SPI State structure definition */ typedef enum { - HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */ - HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing*/ - HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */ -}HAL_SPI_StateTypeDef; + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; /** * @brief SPI handle Structure definition */ typedef struct __SPI_HandleTypeDef { - SPI_TypeDef *Instance; /* SPI registers base address */ + SPI_TypeDef *Instance; /*!< SPI registers base address */ - SPI_InitTypeDef Init; /* SPI communication parameters */ + SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ - uint16_t TxXferSize; /* SPI Tx Transfer size */ + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ - uint16_t TxXferCount; /* SPI Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - uint16_t RxXferSize; /* SPI Rx Transfer size */ + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ - uint16_t RxXferCount; /* SPI Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ - uint32_t CRCSize; /* SPI CRC size used for the transfer */ + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ - void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */ + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ - void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */ + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ - DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - HAL_SPI_StateTypeDef State; /* SPI communication state */ + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ - uint32_t ErrorCode; /* SPI Error code */ + __IO uint32_t ErrorCode; /*!< SPI Error code */ -}SPI_HandleTypeDef; +} SPI_HandleTypeDef; /** * @} @@ -179,23 +180,22 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Error_Code SPI Error Code * @{ */ -#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */ -#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */ -#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */ -#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */ -#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */ -#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */ -#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknow Error error */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT ((uint32_t)0x00000040U) /*!< Error during SPI Abort procedure */ /** * @} */ - /** @defgroup SPI_Mode SPI Mode * @{ */ -#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_SLAVE ((uint32_t)0x00000000U) #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /** * @} @@ -204,7 +204,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Direction SPI Direction Mode * @{ */ -#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE /** @@ -214,19 +214,19 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Data_Size SPI Data Size * @{ */ -#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) -#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) -#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) -#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) -#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) -#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) -#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) -#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) -#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) -#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) -#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) -#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) -#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) +#define SPI_DATASIZE_4BIT ((uint32_t)0x00000300U) +#define SPI_DATASIZE_5BIT ((uint32_t)0x00000400U) +#define SPI_DATASIZE_6BIT ((uint32_t)0x00000500U) +#define SPI_DATASIZE_7BIT ((uint32_t)0x00000600U) +#define SPI_DATASIZE_8BIT ((uint32_t)0x00000700U) +#define SPI_DATASIZE_9BIT ((uint32_t)0x00000800U) +#define SPI_DATASIZE_10BIT ((uint32_t)0x00000900U) +#define SPI_DATASIZE_11BIT ((uint32_t)0x00000A00U) +#define SPI_DATASIZE_12BIT ((uint32_t)0x00000B00U) +#define SPI_DATASIZE_13BIT ((uint32_t)0x00000C00U) +#define SPI_DATASIZE_14BIT ((uint32_t)0x00000D00U) +#define SPI_DATASIZE_15BIT ((uint32_t)0x00000E00U) +#define SPI_DATASIZE_16BIT ((uint32_t)0x00000F00U) /** * @} */ @@ -234,7 +234,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Polarity SPI Clock Polarity * @{ */ -#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_LOW ((uint32_t)0x00000000U) #define SPI_POLARITY_HIGH SPI_CR1_CPOL /** * @} @@ -243,18 +243,18 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Phase SPI Clock Phase * @{ */ -#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U) #define SPI_PHASE_2EDGE SPI_CR1_CPHA /** * @} */ -/** @defgroup SPI_Slave_Select_management SPI Slave Select management +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management * @{ */ #define SPI_NSS_SOFT SPI_CR1_SSM -#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) -#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U) /** * @} */ @@ -263,7 +263,7 @@ typedef struct __SPI_HandleTypeDef * @{ */ #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP -#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000) +#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -271,31 +271,31 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler * @{ */ -#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) -#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008) -#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010) -#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018) -#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020) -#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028) -#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030) -#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038) +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U) /** * @} */ -/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission * @{ */ -#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST /** * @} */ -/** @defgroup SPI_TI_mode SPI TI mode +/** @defgroup SPI_TI_mode SPI TI Mode * @{ */ -#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) #define SPI_TIMODE_ENABLE SPI_CR2_FRF /** * @} @@ -304,7 +304,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_CRC_Calculation SPI CRC Calculation * @{ */ -#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN /** * @} @@ -317,9 +317,9 @@ typedef struct __SPI_HandleTypeDef * SPI_CRC_LENGTH_8BIT : CRC 8bit * SPI_CRC_LENGTH_16BIT : CRC 16bit */ -#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000) -#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001) -#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002) +#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000U) +#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001U) +#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002U) /** * @} */ @@ -334,16 +334,13 @@ typedef struct __SPI_HandleTypeDef * level is greater or equal to 1/4(8 bits). */ #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH -#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000) +#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000U) /** * @} */ -/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition - * @brief SPI Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition * @{ */ #define SPI_IT_TXE SPI_CR2_TXEIE @@ -353,23 +350,18 @@ typedef struct __SPI_HandleTypeDef * @} */ - -/** @defgroup SPI_Flag_definition SPI Flag definition - * @brief Flag definition - * Elements values convention: 0xXXXXYYYY - * - XXXX : Flag register Index - * - YYYY : Flag mask +/** @defgroup SPI_Flags_definition SPI Flags Definition * @{ */ -#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ -#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ -#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ -#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ -#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ -#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ -#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ -#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ +#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ +#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ /** * @} */ @@ -377,10 +369,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level * @{ */ -#define SPI_FTLVL_EMPTY ((uint32_t)0x0000) -#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800) -#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000) -#define SPI_FTLVL_FULL ((uint32_t)0x1800) +#define SPI_FTLVL_EMPTY ((uint32_t)0x00000000U) +#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x00000800U) +#define SPI_FTLVL_HALF_FULL ((uint32_t)0x00001000U) +#define SPI_FTLVL_FULL ((uint32_t)0x00001800U) /** * @} @@ -389,34 +381,31 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level * @{ */ -#define SPI_FRLVL_EMPTY ((uint32_t)0x0000) -#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200) -#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400) -#define SPI_FRLVL_FULL ((uint32_t)0x0600) +#define SPI_FRLVL_EMPTY ((uint32_t)0x00000000U) +#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x00000200U) +#define SPI_FRLVL_HALF_FULL ((uint32_t)0x00000400U) +#define SPI_FRLVL_FULL ((uint32_t)0x00000600U) /** * @} */ -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup SPI_Exported_Macros SPI Exported Macros * @{ */ -/** @brief Reset SPI handle state - * @param __HANDLE__: SPI handle. +/** @brief Reset SPI handle state. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -/** @brief Enables or disables the specified SPI interrupts. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Enable or disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__ : specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable * @arg SPI_IT_ERR: Error interrupt enable @@ -425,10 +414,10 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) -/** @brief Checks if the specified SPI interrupt source is enabled or disabled. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__ : specifies the SPI interrupt source to check. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -437,11 +426,11 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** @brief Checks whether the specified SPI flag is set or not. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__ : specifies the flag to check. - * This parameter can be one of the following values: + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag * @arg SPI_FLAG_CRCERR: CRC error flag @@ -455,63 +444,60 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/** @brief Clears the SPI CRCERR pending flag. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) -/** @brief Clears the SPI MODF pending flag. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * * @retval None */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0) -/** @brief Clears the SPI OVR pending flag. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * * @retval None */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0) -/** @brief Clears the SPI FRE pending flag. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * * @retval None */ -#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ + }while(0) -/** @brief Enables the SPI. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Enable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) -/** @brief Disables the SPI. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Disable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -521,27 +507,27 @@ typedef struct __SPI_HandleTypeDef * @} */ -/* Private macros --------------------------------------------------------*/ -/** @defgroup SPI_Private_Macros SPI Private Macros +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros * @{ */ -/** @brief Sets the SPI transmit-only mode. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) -/** @brief Sets the SPI receive-only mode. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) -/** @brief Resets the CRC calculation of the SPI. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -551,14 +537,14 @@ typedef struct __SPI_HandleTypeDef #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ ((MODE) == SPI_MODE_MASTER)) -#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\ +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ ((MODE) == SPI_DIRECTION_1LINE)) #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE)) +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_1LINE)) #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ ((DATASIZE) == SPI_DATASIZE_15BIT) || \ @@ -580,19 +566,19 @@ typedef struct __SPI_HandleTypeDef #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ ((CPHA) == SPI_PHASE_2EDGE)) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ ((NSS) == SPI_NSS_HARD_INPUT) || \ ((NSS) == SPI_NSS_HARD_OUTPUT)) #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ ((NSSP) == SPI_NSS_PULSE_DISABLE)) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) @@ -609,25 +595,23 @@ typedef struct __SPI_HandleTypeDef ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_16BIT)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) - +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0)) /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPI_Exported_Functions SPI Exported Functions +/** @addtogroup SPI_Exported_Functions * @{ */ /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ - -/* Initialization and de-initialization functions ****************************/ +/* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /** @@ -637,20 +621,25 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions * @{ */ - -/* IO operation functions *****************************************************/ +/* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); @@ -660,6 +649,7 @@ void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); /** * @} */ @@ -693,4 +683,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #endif /* __STM32F7xx_HAL_SPI_H */ +/** + * @} + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_tim.h b/stmhal/hal/f7/inc/stm32f7xx_hal_tim.h index 2f4a6f9b2b..7a6a69b3ba 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_tim.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_tim.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -77,7 +77,7 @@ typedef struct uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR down-counter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: @@ -264,11 +264,11 @@ typedef struct { */ typedef enum { - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ }HAL_TIM_StateTypeDef; /** @@ -276,11 +276,11 @@ typedef enum */ typedef enum { - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ }HAL_TIM_ActiveChannel; /** @@ -308,7 +308,7 @@ typedef struct /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity * @{ */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** @@ -319,7 +319,7 @@ typedef struct * @{ */ #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */ /** * @} */ @@ -327,7 +327,7 @@ typedef struct /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ @@ -338,7 +338,7 @@ typedef struct /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) +#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U) #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 @@ -350,7 +350,7 @@ typedef struct /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) +#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U) #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) /** @@ -360,7 +360,7 @@ typedef struct /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) /** @@ -370,7 +370,7 @@ typedef struct /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U) #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) /** * @} @@ -379,7 +379,7 @@ typedef struct /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U) #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) /** * @} @@ -388,7 +388,7 @@ typedef struct /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U) #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) /** * @} @@ -397,7 +397,7 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ -#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U) #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) /** * @} @@ -407,7 +407,7 @@ typedef struct * @{ */ #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U) /** * @} */ @@ -416,7 +416,7 @@ typedef struct * @{ */ #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U) /** * @} */ @@ -447,7 +447,7 @@ typedef struct /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ @@ -459,7 +459,7 @@ typedef struct * @{ */ #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) +#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U) /** * @} */ @@ -494,7 +494,7 @@ typedef struct * @{ */ #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) +#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U) /** * @} */ @@ -554,7 +554,7 @@ typedef struct */ #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U) #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) @@ -613,7 +613,7 @@ typedef struct * @{ */ #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) +#define TIM_OSSR_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -622,7 +622,7 @@ typedef struct * @{ */ #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) +#define TIM_OSSI_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -630,7 +630,7 @@ typedef struct /** @defgroup TIM_Lock_level TIM Lock level * @{ */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) +#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U) #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) @@ -641,7 +641,7 @@ typedef struct * @{ */ #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE ((uint32_t)0x0000) +#define TIM_BREAK_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -649,7 +649,7 @@ typedef struct /** @defgroup TIM_Break_Polarity TIM Break Polarity * @{ */ -#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) +#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U) #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) /** * @} @@ -659,7 +659,7 @@ typedef struct * @{ */ #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) +#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -667,7 +667,7 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_RESET ((uint32_t)0x0000U) #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) @@ -683,7 +683,7 @@ typedef struct * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -691,15 +691,15 @@ typedef struct /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) +#define TIM_TS_ITR0 ((uint32_t)0x0000U) +#define TIM_TS_ITR1 ((uint32_t)0x0010U) +#define TIM_TS_ITR2 ((uint32_t)0x0020U) +#define TIM_TS_ITR3 ((uint32_t)0x0030U) +#define TIM_TS_TI1F_ED ((uint32_t)0x0040U) +#define TIM_TS_TI1FP1 ((uint32_t)0x0050U) +#define TIM_TS_TI2FP2 ((uint32_t)0x0060U) +#define TIM_TS_ETRF ((uint32_t)0x0070U) +#define TIM_TS_NONE ((uint32_t)0xFFFFU) /** * @} */ @@ -731,7 +731,7 @@ typedef struct /** @defgroup TIM_TI1_Selection TIM TI1 Selection * @{ */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) +#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U) #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) /** * @} @@ -740,26 +740,26 @@ typedef struct /** @defgroup TIM_DMA_Base_address TIM DMA Base address * @{ */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_OR (0x00000013) +#define TIM_DMABASE_CR1 (0x00000000U) +#define TIM_DMABASE_CR2 (0x00000001U) +#define TIM_DMABASE_SMCR (0x00000002U) +#define TIM_DMABASE_DIER (0x00000003U) +#define TIM_DMABASE_SR (0x00000004U) +#define TIM_DMABASE_EGR (0x00000005U) +#define TIM_DMABASE_CCMR1 (0x00000006U) +#define TIM_DMABASE_CCMR2 (0x00000007U) +#define TIM_DMABASE_CCER (0x00000008U) +#define TIM_DMABASE_CNT (0x00000009U) +#define TIM_DMABASE_PSC (0x0000000AU) +#define TIM_DMABASE_ARR (0x0000000BU) +#define TIM_DMABASE_RCR (0x0000000CU) +#define TIM_DMABASE_CCR1 (0x0000000DU) +#define TIM_DMABASE_CCR2 (0x0000000EU) +#define TIM_DMABASE_CCR3 (0x0000000FU) +#define TIM_DMABASE_CCR4 (0x00000010U) +#define TIM_DMABASE_BDTR (0x00000011U) +#define TIM_DMABASE_DCR (0x00000012U) +#define TIM_DMABASE_OR (0x00000013U) /** * @} */ @@ -767,24 +767,24 @@ typedef struct /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) /** * @} */ @@ -792,13 +792,13 @@ typedef struct /** @defgroup DMA_Handle_index DMA Handle index * @{ */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ @@ -806,10 +806,10 @@ typedef struct /** @defgroup Channel_CC_State Channel CC State * @{ */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -#define TIM_CCxN_ENABLE ((uint32_t)0x0004) -#define TIM_CCxN_DISABLE ((uint32_t)0x0000) +#define TIM_CCx_ENABLE ((uint32_t)0x0001U) +#define TIM_CCx_DISABLE ((uint32_t)0x0000U) +#define TIM_CCxN_ENABLE ((uint32_t)0x0004U) +#define TIM_CCxN_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -1326,7 +1326,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); ((__MODE__) == TIM_ENCODERMODE_TI2) || \ ((__MODE__) == TIM_ENCODERMODE_TI12)) -#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000)) +#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U)) #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \ @@ -1338,9 +1338,9 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); ((__IT__) == TIM_IT_TRIGGER) || \ ((__IT__) == TIM_IT_BREAK)) -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \ ((__FLAG__) == TIM_FLAG_CC1) || \ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_tim_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_tim_ex.h index a0f66c3333..d8bdef6772 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_tim_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_tim_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -97,7 +97,7 @@ typedef struct { */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode. + uint32_t OffStateRunMode; /*!< TIM off state in run mode. This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode. This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ @@ -121,10 +121,20 @@ typedef struct This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct { + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ +} TIMEx_BreakInputConfigTypeDef; +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants * @{ @@ -134,13 +144,13 @@ typedef struct * @{ */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_5 ((uint32_t)0x0010) -#define TIM_CHANNEL_6 ((uint32_t)0x0014) -#define TIM_CHANNEL_ALL ((uint32_t)0x003C) +#define TIM_CHANNEL_1 ((uint32_t)0x0000U) +#define TIM_CHANNEL_2 ((uint32_t)0x0004U) +#define TIM_CHANNEL_3 ((uint32_t)0x0008U) +#define TIM_CHANNEL_4 ((uint32_t)0x000CU) +#define TIM_CHANNEL_5 ((uint32_t)0x0010U) +#define TIM_CHANNEL_6 ((uint32_t)0x0014U) +#define TIM_CHANNEL_ALL ((uint32_t)0x003CU) /** * @} @@ -149,7 +159,7 @@ typedef struct /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes * @{ */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_TIMING ((uint32_t)0x0000U) #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) @@ -171,18 +181,18 @@ typedef struct /** @defgroup TIMEx_Remap TIMEx Remap * @{ */ -#define TIM_TIM2_TIM8_TRGO (0x00000000) -#define TIM_TIM2_ETH_PTP (0x00000400) -#define TIM_TIM2_USBFS_SOF (0x00000800) -#define TIM_TIM2_USBHS_SOF (0x00000C00) -#define TIM_TIM5_GPIO (0x00000000) -#define TIM_TIM5_LSI (0x00000040) -#define TIM_TIM5_LSE (0x00000080) -#define TIM_TIM5_RTC (0x000000C0) -#define TIM_TIM11_GPIO (0x00000000) -#define TIM_TIM11_SPDIFRX (0x00000001) -#define TIM_TIM11_HSE (0x00000002) -#define TIM_TIM11_MCO1 (0x00000003) +#define TIM_TIM2_TIM8_TRGO (0x00000000U) +#define TIM_TIM2_ETH_PTP (0x00000400U) +#define TIM_TIM2_USBFS_SOF (0x00000800U) +#define TIM_TIM2_USBHS_SOF (0x00000C00U) +#define TIM_TIM5_GPIO (0x00000000U) +#define TIM_TIM5_LSI (0x00000040U) +#define TIM_TIM5_LSE (0x00000080U) +#define TIM_TIM5_RTC (0x000000C0U) +#define TIM_TIM11_GPIO (0x00000000U) +#define TIM_TIM11_SPDIFRX (0x00000001U) +#define TIM_TIM11_HSE (0x00000002U) +#define TIM_TIM11_MCO1 (0x00000003U) /** * @} */ @@ -190,9 +200,9 @@ typedef struct /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) +#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) +#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U) +#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) /** * @} */ @@ -200,7 +210,7 @@ typedef struct /** @defgroup TIMEx_Break2_Input_enable_disable TIMEx Break input 2 Enable * @{ */ -#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) +#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) /** * @} @@ -209,7 +219,7 @@ typedef struct /** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity * @{ */ -#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) +#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U) #define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P) /** * @} @@ -218,7 +228,7 @@ typedef struct /** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_NONE ((uint32_t)0x00000000U) /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ @@ -229,7 +239,7 @@ typedef struct /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2) * @{ */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) +#define TIM_TRGO2_RESET ((uint32_t)0x00000000U) #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) @@ -252,7 +262,7 @@ typedef struct /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode * @{ */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U) #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) @@ -261,6 +271,38 @@ typedef struct /** * @} */ +#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK ((uint32_t)0x00000001U) /* !< Timer break input */ +#define TIM_BREAKINPUT_BRK2 ((uint32_t)0x00000002U) /* !< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)0x00000000U) /* !< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)0x00000001U) /* !< Break input source is enabled */ +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -291,7 +333,7 @@ typedef struct ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__))) + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) /** * @brief Gets the TIM Capture Compare Register value on runtime @@ -407,6 +449,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, u HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef); /** @@ -522,6 +567,17 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim); ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \ ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_uart.h b/stmhal/hal/f7/inc/stm32f7xx_hal_uart.h index 06efecc2f7..96050a2b00 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_uart.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_uart.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -102,7 +102,7 @@ typedef struct }UART_InitTypeDef; /** - * @brief UART Advanced Features initalization structure definition + * @brief UART Advanced Features initialization structure definition */ typedef struct { @@ -144,17 +144,62 @@ typedef struct /** * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_UART_STATE_ERROR = 0x04 /*!< Error */ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_UART_StateTypeDef; /** @@ -162,12 +207,12 @@ typedef enum */ typedef enum { - UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }UART_ClockSourceTypeDef; /** @@ -185,13 +230,13 @@ typedef struct uint16_t TxXferSize; /*!< UART Tx Transfer size */ - uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ uint16_t RxXferSize; /*!< UART Rx Transfer size */ - uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ uint16_t Mask; /*!< UART Rx RDR register mask */ @@ -201,7 +246,12 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_UART_StateTypeDef State; /*!< UART communication state */ + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ @@ -218,19 +268,19 @@ typedef struct /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ /** * @} */ /** @defgroup UART_Stop_Bits UART Number of Stop Bits * @{ */ -#define UART_STOPBITS_1 ((uint32_t)0x0000) +#define UART_STOPBITS_1 ((uint32_t)0x00000000U) #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /** * @} @@ -239,7 +289,7 @@ typedef struct /** @defgroup UART_Parity UART Parity * @{ */ -#define UART_PARITY_NONE ((uint32_t)0x00000000) +#define UART_PARITY_NONE ((uint32_t)0x00000000U) #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /** @@ -249,7 +299,7 @@ typedef struct /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control * @{ */ -#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) +#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U) #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) @@ -270,7 +320,7 @@ typedef struct /** @defgroup UART_State UART State * @{ */ -#define UART_STATE_DISABLE ((uint32_t)0x00000000) +#define UART_STATE_DISABLE ((uint32_t)0x00000000U) #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /** * @} @@ -279,7 +329,7 @@ typedef struct /** @defgroup UART_Over_Sampling UART Over Sampling * @{ */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) +#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U) #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /** * @} @@ -288,7 +338,7 @@ typedef struct /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method * @{ */ -#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) #define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /** * @} @@ -297,7 +347,7 @@ typedef struct /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U) #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) @@ -308,7 +358,7 @@ typedef struct /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) +#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U) #define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /** * @} @@ -317,7 +367,7 @@ typedef struct /** @defgroup UART_LIN UART Local Interconnection Network mode * @{ */ -#define UART_LIN_DISABLE ((uint32_t)0x00000000) +#define UART_LIN_DISABLE ((uint32_t)0x00000000U) #define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /** * @} @@ -326,7 +376,7 @@ typedef struct /** @defgroup UART_LIN_Break_Detection UART LIN Break Detection * @{ */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) +#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U) #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /** * @} @@ -335,7 +385,7 @@ typedef struct /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ -#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) +#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U) #define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /** * @} @@ -344,7 +394,7 @@ typedef struct /** @defgroup UART_DMA_Rx UART DMA Rx * @{ */ -#define UART_DMA_RX_DISABLE ((uint32_t)0x0000) +#define UART_DMA_RX_DISABLE ((uint32_t)0x0000U) #define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /** * @} @@ -353,7 +403,7 @@ typedef struct /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ */ -#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000) +#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U) #define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /** * @} @@ -362,7 +412,7 @@ typedef struct /** @defgroup UART_WakeUp_Methods UART WakeUp Methods * @{ */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) +#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U) #define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /** * @} @@ -383,15 +433,15 @@ typedef struct /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type * @{ */ -#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) -#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) -#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) -#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) -#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) -#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) +#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) +#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) +#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) +#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) +#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U) +#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) /** * @} */ @@ -399,7 +449,7 @@ typedef struct /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /** * @} @@ -408,7 +458,7 @@ typedef struct /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /** * @} @@ -417,7 +467,7 @@ typedef struct /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion * @{ */ -#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /** * @} @@ -426,7 +476,7 @@ typedef struct /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap * @{ */ -#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /** * @} @@ -435,7 +485,7 @@ typedef struct /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /** * @} @@ -444,7 +494,7 @@ typedef struct /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /** * @} @@ -453,7 +503,7 @@ typedef struct /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) #define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /** * @} @@ -462,7 +512,7 @@ typedef struct /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /** * @} @@ -471,7 +521,7 @@ typedef struct /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable * @{ */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /** * @} @@ -480,7 +530,7 @@ typedef struct /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) +#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U) /** * @} */ @@ -488,7 +538,7 @@ typedef struct /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity * @{ */ -#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) +#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U) #define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /** * @} @@ -497,7 +547,7 @@ typedef struct /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) +#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U) /** * @} */ @@ -505,7 +555,7 @@ typedef struct /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) +#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U) /** * @} */ @@ -513,7 +563,7 @@ typedef struct /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask * @{ */ -#define UART_IT_MASK ((uint32_t)0x001F) +#define UART_IT_MASK ((uint32_t)0x001FU) /** * @} */ @@ -521,7 +571,7 @@ typedef struct /** @defgroup UART_TimeOut_Value UART polling-based communications time-out value * @{ */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /** * @} */ @@ -531,25 +581,25 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define UART_FLAG_TEACK ((uint32_t)0x00200000) -#define UART_FLAG_SBKF ((uint32_t)0x00040000) -#define UART_FLAG_CMF ((uint32_t)0x00020000) -#define UART_FLAG_BUSY ((uint32_t)0x00010000) -#define UART_FLAG_ABRF ((uint32_t)0x00008000) -#define UART_FLAG_ABRE ((uint32_t)0x00004000) -#define UART_FLAG_EOBF ((uint32_t)0x00001000) -#define UART_FLAG_RTOF ((uint32_t)0x00000800) -#define UART_FLAG_CTS ((uint32_t)0x00000400) -#define UART_FLAG_CTSIF ((uint32_t)0x00000200) -#define UART_FLAG_LBDF ((uint32_t)0x00000100) -#define UART_FLAG_TXE ((uint32_t)0x00000080) -#define UART_FLAG_TC ((uint32_t)0x00000040) -#define UART_FLAG_RXNE ((uint32_t)0x00000020) -#define UART_FLAG_IDLE ((uint32_t)0x00000010) -#define UART_FLAG_ORE ((uint32_t)0x00000008) -#define UART_FLAG_NE ((uint32_t)0x00000004) -#define UART_FLAG_FE ((uint32_t)0x00000002) -#define UART_FLAG_PE ((uint32_t)0x00000001) +#define UART_FLAG_TEACK ((uint32_t)0x00200000U) +#define UART_FLAG_SBKF ((uint32_t)0x00040000U) +#define UART_FLAG_CMF ((uint32_t)0x00020000U) +#define UART_FLAG_BUSY ((uint32_t)0x00010000U) +#define UART_FLAG_ABRF ((uint32_t)0x00008000U) +#define UART_FLAG_ABRE ((uint32_t)0x00004000U) +#define UART_FLAG_EOBF ((uint32_t)0x00001000U) +#define UART_FLAG_RTOF ((uint32_t)0x00000800U) +#define UART_FLAG_CTS ((uint32_t)0x00000400U) +#define UART_FLAG_CTSIF ((uint32_t)0x00000200U) +#define UART_FLAG_LBDF ((uint32_t)0x00000100U) +#define UART_FLAG_TXE ((uint32_t)0x00000080U) +#define UART_FLAG_TC ((uint32_t)0x00000040U) +#define UART_FLAG_RXNE ((uint32_t)0x00000020U) +#define UART_FLAG_IDLE ((uint32_t)0x00000010U) +#define UART_FLAG_ORE ((uint32_t)0x00000008U) +#define UART_FLAG_NE ((uint32_t)0x00000004U) +#define UART_FLAG_FE ((uint32_t)0x00000002U) +#define UART_FLAG_PE ((uint32_t)0x00000001U) /** * @} */ @@ -564,14 +614,14 @@ typedef struct * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define UART_IT_PE ((uint32_t)0x0028) -#define UART_IT_TXE ((uint32_t)0x0727) -#define UART_IT_TC ((uint32_t)0x0626) -#define UART_IT_RXNE ((uint32_t)0x0525) -#define UART_IT_IDLE ((uint32_t)0x0424) -#define UART_IT_LBD ((uint32_t)0x0846) -#define UART_IT_CTS ((uint32_t)0x096A) -#define UART_IT_CM ((uint32_t)0x112E) +#define UART_IT_PE ((uint32_t)0x0028U) +#define UART_IT_TXE ((uint32_t)0x0727U) +#define UART_IT_TC ((uint32_t)0x0626U) +#define UART_IT_RXNE ((uint32_t)0x0525U) +#define UART_IT_IDLE ((uint32_t)0x0424U) +#define UART_IT_LBD ((uint32_t)0x0846U) +#define UART_IT_CTS ((uint32_t)0x096AU) +#define UART_IT_CM ((uint32_t)0x112EU) /** Elements values convention: 000000000XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) @@ -580,14 +630,14 @@ typedef struct * - 10: CR2 register * - 11: CR3 register */ -#define UART_IT_ERR ((uint32_t)0x0060) +#define UART_IT_ERR ((uint32_t)0x0060U) /** Elements values convention: 0000ZZZZ00000000b * - ZZZZ : Flag position in the ISR register(4bits) */ -#define UART_IT_ORE ((uint32_t)0x0300) -#define UART_IT_NE ((uint32_t)0x0200) -#define UART_IT_FE ((uint32_t)0x0100) +#define UART_IT_ORE ((uint32_t)0x0300U) +#define UART_IT_NE ((uint32_t)0x0200U) +#define UART_IT_FE ((uint32_t)0x0100U) /** * @} */ @@ -624,7 +674,10 @@ typedef struct * @param __HANDLE__: UART handle. * @retval None */ -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0) /** @brief Flush the UART Data registers * @param __HANDLE__: specifies the UART Handle. @@ -653,7 +706,7 @@ typedef struct * @arg UART_CLEAR_CMF: Character Match Clear Flag * @retval None */ -#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__)) +#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__)) /** @brief Clear the UART PE pending flag. * @param __HANDLE__: specifies the UART Handle. @@ -918,21 +971,21 @@ typedef struct * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define UART_DIV_LPUART(_PCLK_, _BAUD_) (((_PCLK_)*256)/((_BAUD_))) +#define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_))) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode * @param _PCLK_: UART clock * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_))) +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_))) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode * @param _PCLK_: UART clock * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_))) +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_))) /** @brief Check UART Baud rate * @param BAUDRATE: Baudrate specified by the user @@ -1069,6 +1122,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); void HAL_UART_MspInit(UART_HandleTypeDef *huart); void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); @@ -1091,6 +1145,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); + void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); @@ -1108,6 +1163,7 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); @@ -1141,7 +1197,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); /** diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_uart_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_uart_ex.h index 3fb12b5a38..3d83232f44 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_uart_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_uart_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ * @{ */ #define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) -#define UART_WORDLENGTH_8B ((uint32_t)0x0000) +#define UART_WORDLENGTH_8B ((uint32_t)0x0000U) #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ ((__LENGTH__) == UART_WORDLENGTH_8B) || \ @@ -78,7 +78,7 @@ /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) +#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U) #define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) @@ -318,6 +318,36 @@ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +/** + * @} + */ + /** * @} */ diff --git a/stmhal/hal/f7/inc/stm32f7xx_ll_sdmmc.h b/stmhal/hal/f7/inc/stm32f7xx_ll_sdmmc.h index 88c7405686..5c33e87eaa 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_ll_sdmmc.h +++ b/stmhal/hal/f7/inc/stm32f7xx_ll_sdmmc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -149,7 +149,7 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Edge Clock Edge * @{ */ -#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000) +#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ @@ -161,7 +161,7 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass * @{ */ -#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) +#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ @@ -173,7 +173,7 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving * @{ */ -#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) +#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ @@ -185,7 +185,7 @@ typedef struct /** @defgroup SDMMC_LL_Bus_Wide Bus Width * @{ */ -#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000) +#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 @@ -199,7 +199,7 @@ typedef struct /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control * @{ */ -#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) +#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ @@ -227,7 +227,7 @@ typedef struct /** @defgroup SDMMC_LL_Response_Type Response Type * @{ */ -#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000) +#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP @@ -241,7 +241,7 @@ typedef struct /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt * @{ */ -#define SDMMC_WAIT_NO ((uint32_t)0x00000000) +#define SDMMC_WAIT_NO ((uint32_t)0x00000000U) #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND @@ -255,7 +255,7 @@ typedef struct /** @defgroup SDMMC_LL_CPSM_State CPSM State * @{ */ -#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000) +#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ @@ -267,9 +267,9 @@ typedef struct /** @defgroup SDMMC_LL_Response_Registers Response Register * @{ */ -#define SDMMC_RESP1 ((uint32_t)0x00000000) -#define SDMMC_RESP2 ((uint32_t)0x00000004) -#define SDMMC_RESP3 ((uint32_t)0x00000008) +#define SDMMC_RESP1 ((uint32_t)0x00000000U) +#define SDMMC_RESP2 ((uint32_t)0x00000004U) +#define SDMMC_RESP3 ((uint32_t)0x00000008U) #define SDMMC_RESP4 ((uint32_t)0x0000000C) #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ @@ -291,7 +291,7 @@ typedef struct /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size * @{ */ -#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) +#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) @@ -329,7 +329,7 @@ typedef struct /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction * @{ */ -#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) +#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ @@ -341,7 +341,7 @@ typedef struct /** @defgroup SDMMC_LL_Transfer_Type Transfer Type * @{ */ -#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) +#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ @@ -353,7 +353,7 @@ typedef struct /** @defgroup SDMMC_LL_DPSM_State DPSM State * @{ */ -#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000) +#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ @@ -365,7 +365,7 @@ typedef struct /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode * @{ */ -#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) +#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ diff --git a/stmhal/hal/f7/inc/stm32f7xx_ll_usb.h b/stmhal/hal/f7/inc/stm32f7xx_ll_usb.h index ecef6ca58a..63f37f15dd 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_ll_usb.h +++ b/stmhal/hal/f7/inc/stm32f7xx_ll_usb.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -61,9 +61,9 @@ */ typedef enum { - USB_OTG_DEVICE_MODE = 0, - USB_OTG_HOST_MODE = 1, - USB_OTG_DRD_MODE = 2 + USB_OTG_DEVICE_MODE = 0U, + USB_OTG_HOST_MODE = 1U, + USB_OTG_DRD_MODE = 2U }USB_OTG_ModeTypeDef; @@ -71,7 +71,7 @@ typedef enum * @brief URB States definition */ typedef enum { - URB_IDLE = 0, + URB_IDLE = 0U, URB_DONE, URB_NOTREADY, URB_NYET, @@ -84,7 +84,7 @@ typedef enum { * @brief Host channel States definition */ typedef enum { - HC_IDLE = 0, + HC_IDLE = 0U, HC_XFRC, HC_HALTED, HC_NAK, @@ -233,9 +233,9 @@ typedef struct /** @defgroup USB_Core_Mode_ USB Core Mode * @{ */ -#define USB_OTG_MODE_DEVICE 0 -#define USB_OTG_MODE_HOST 1 -#define USB_OTG_MODE_DRD 2 +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U /** * @} */ @@ -243,10 +243,10 @@ typedef struct /** @defgroup USB_Core_Speed_ USB Core Speed * @{ */ -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_LOW 2 -#define USB_OTG_SPEED_FULL 3 +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_LOW 2U +#define USB_OTG_SPEED_FULL 3U /** * @} */ @@ -254,8 +254,8 @@ typedef struct /** @defgroup USB_Core_PHY_ USB Core PHY * @{ */ -#define USB_OTG_ULPI_PHY 1 -#define USB_OTG_EMBEDDED_PHY 2 +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U /** * @} */ @@ -263,9 +263,9 @@ typedef struct /** @defgroup USB_Core_MPS_ USB Core MPS * @{ */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512 -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ @@ -284,10 +284,10 @@ typedef struct /** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval * @{ */ -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U /** * @} */ @@ -295,10 +295,10 @@ typedef struct /** @defgroup USB_EP0_MPS_ USB EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U /** * @} */ @@ -306,9 +306,9 @@ typedef struct /** @defgroup USB_EP_Speed_ USB EP Speed * @{ */ -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U /** * @} */ @@ -316,11 +316,11 @@ typedef struct /** @defgroup USB_EP_Type_ USB EP Type * @{ */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U /** * @} */ @@ -328,11 +328,11 @@ typedef struct /** @defgroup USB_STS_Defines_ USB STS Defines * @{ */ -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U /** * @} */ @@ -340,9 +340,9 @@ typedef struct /** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines * @{ */ -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U /** * @} */ @@ -350,27 +350,27 @@ typedef struct /** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines * @{ */ -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U /** * @} */ -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) diff --git a/stmhal/hal/f7/src/stm32f7xx_hal.c b/stmhal/hal/f7/src/stm32f7xx_hal.c index b92d22e6c4..a790e7a859 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -23,7 +23,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -68,11 +68,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.0.1 + * @brief STM32F7xx HAL Driver version number V1.1.2 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ @@ -242,7 +242,7 @@ __weak void HAL_MspDeInit(void) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + HAL_SYSTICK_Config(SystemCoreClock/1000); /*Configure the SysTick IRQ priority */ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); @@ -309,7 +309,7 @@ __weak uint32_t HAL_GetTick(void) * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. - * @note ThiS function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @param Delay: specifies the delay time length, in milliseconds. * @retval None @@ -327,7 +327,7 @@ __weak void HAL_Delay(__IO uint32_t Delay) * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment + * is called, the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -343,7 +343,7 @@ __weak void HAL_SuspendTick(void) * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment + * is called, the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -370,7 +370,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE) >> 16); + return((DBGMCU->IDCODE) >> 16U); } /** @@ -485,6 +485,38 @@ void HAL_DisableFMCMemorySwapping(void) SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC); } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** +* @brief Enable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_EnableMemorySwappingBank(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} + +/** +* @brief Disable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_DisableMemorySwappingBank(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_adc.c b/stmhal/hal/f7/src/stm32f7xx_hal_adc.c index 0c5f83b20c..b8da090f06 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_adc.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -164,7 +164,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -258,10 +258,12 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + /* Check ADC handle */ if(hadc == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ @@ -284,29 +286,45 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) if(hadc->State == HAL_ADC_STATE_RESET) { + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_ADC_MspInit(hadc); } - /* Initialize the ADC state */ - hadc->State = HAL_ADC_STATE_BUSY; + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); - /* Set ADC parameters */ - ADC_Init(hadc); + /* Set ADC parameters */ + ADC_Init(hadc); - /* Set ADC error code to none */ - hadc->ErrorCode = HAL_ADC_ERROR_NONE; + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); - /* Initialize the ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + tmp_hal_status = HAL_ERROR; + } /* Release Lock */ __HAL_UNLOCK(hadc); /* Return function status */ - return HAL_OK; + return tmp_hal_status; } /** @@ -317,29 +335,43 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) { + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + /* Check ADC handle */ if(hadc == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); - /* Set ADC error code to none */ - hadc->ErrorCode = HAL_ADC_ERROR_NONE; + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_RESET; + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); /* Return function status */ - return HAL_OK; + return tmp_hal_status; } /** @@ -350,6 +382,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_MspInit could be implemented in the user file */ @@ -363,6 +397,8 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_MspDeInit could be implemented in the user file */ @@ -409,18 +445,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Process locked */ __HAL_LOCK(hadc); - /* Check if an injected conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - } - + /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) @@ -437,26 +462,62 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) } } - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - } - else - { - /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { - /* Enable the selected ADC software conversion for regular group */ + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } } } @@ -476,11 +537,27 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { - /* Disable the Peripheral */ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; @@ -488,6 +565,14 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) /** * @brief Poll for regular conversion complete + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function. + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence. * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param Timeout: Timeout value in millisecond. @@ -507,7 +592,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -521,29 +606,46 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check End of conversion flag */ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) { - /* Check for the Timeout */ + /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { - hadc->State= HAL_ADC_STATE_TIMEOUT; + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* Process unlocked */ __HAL_UNLOCK(hadc); + return HAL_TIMEOUT; } } } - /* Check if an injected conversion is ready */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } /* Return ADC state */ @@ -566,6 +668,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy uint32_t tickstart = 0; /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get tick */ @@ -577,32 +680,38 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { - hadc->State= HAL_ADC_STATE_TIMEOUT; + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* Process unlocked */ __HAL_UNLOCK(hadc); + return HAL_TIMEOUT; } } } - /* Check analog watchdog flag */ + /* Analog watchdog (level out of window) event */ if(EventType == ADC_AWD_EVENT) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_AWD; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - /* Clear the ADCx's analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); } + /* Overrun event */ else { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_ERROR; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - /* Clear the ADCx's Overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } /* Return ADC state */ @@ -627,21 +736,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Process locked */ __HAL_LOCK(hadc); - /* Check if an injected conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - } - - /* Set ADC error code to none */ - hadc->ErrorCode = HAL_ADC_ERROR_NONE; - + /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) @@ -658,32 +753,65 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) } } - /* Enable the ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Enable the ADC end of conversion interrupt for regular group */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - } - else - { - /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { - /* Enable the selected ADC software conversion for regular group */ + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Enable end of conversion interrupt for regular group */ + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } } } @@ -702,17 +830,30 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { - /* Disable the ADC end of conversion interrupt for regular group */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Disable the ADC end of conversion interrupt for injected group */ - __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE); + /* Process locked */ + __HAL_LOCK(hadc); - /* Enable the Peripheral */ + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable ADC end of conversion interrupt for regular group */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; @@ -738,55 +879,44 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Check End of conversion flag for regular channels */ if(tmp1 && tmp2) { - /* Check if an injected conversion is ready */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) { - if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { - /* DISABLE the ADC end of conversion interrupt for regular group */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* DISABLE the ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - } - else - { - if (hadc->NbrOfCurrentConversionRank == 0) - { - hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion; - } - - /* Decrement the number of conversion when an interrupt occurs */ - hadc->NbrOfCurrentConversionRank--; - - /* Check if all conversions are finished */ - if(hadc->NbrOfCurrentConversionRank == 0) - { - /* DISABLE the ADC end of conversion interrupt for regular group */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* DISABLE the ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - } + SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ HAL_ADC_ConvCpltCallback(hadc); - /* Clear the ADCx flag for regular end of conversion */ - __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC); + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); @@ -794,31 +924,41 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Check End of conversion flag for injected channels */ if(tmp1 && tmp2) { - /* Check if a regular conversion is ready */ - if(hadc->State == HAL_ADC_STATE_EOC_REG) + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2) + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, scan sequence on going or by automatic injected */ + /* conversion from group regular (same conditions as group regular */ + /* interruption disabling above). */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) { - /* DISABLE the ADC end of conversion interrupt for injected group */ + /* Disable ADC end of single conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } /* Conversion complete callback */ HAL_ADCEx_InjectedConvCpltCallback(hadc); - /* Clear the ADCx flag for injected end of conversion */ - __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC); + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); @@ -826,14 +966,17 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Check Analog watchdog flag */ if(tmp1 && tmp2) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_AWD; + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - /* Clear the ADCx's Analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD); + /* Level out of window callback */ + HAL_ADC_LevelOutOfWindowCallback(hadc); - /* Level out of window callback */ - HAL_ADC_LevelOutOfWindowCallback(hadc); + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + } } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); @@ -841,17 +984,21 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Check Overrun flag */ if(tmp1 && tmp2) { - /* Change ADC state to overrun state */ - hadc->State = HAL_ADC_STATE_ERROR; + /* Note: On STM32F7, ADC overrun can be set through other parameters */ + /* refer to description of parameter "EOCSelection" for more */ + /* details. */ /* Set ADC error code to overrun */ - hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - /* Clear the Overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR); + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); /* Error callback */ HAL_ADC_ErrorCallback(hadc); + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } } @@ -874,30 +1021,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Process locked */ __HAL_LOCK(hadc); - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Enable ADC DMA mode */ - hadc->Instance->CR2 |= ADC_CR2_DMA; - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - + /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) @@ -914,11 +1038,85 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui } } - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= ADC_CR2_SWSTART; + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC DMA mode */ + hadc->Instance->CR2 |= ADC_CR2_DMA; + + /* Start the DMA channel */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } } /* Return function status */ @@ -933,23 +1131,42 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { - /* Disable the Peripheral */ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable the selected ADC DMA mode */ + hadc->Instance->CR2 &= ~ADC_CR2_DMA; - /* Disable the selected ADC DMA mode */ - hadc->Instance->CR2 &= ~ADC_CR2_DMA; + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - /* Disable the ADC DMA Stream */ - HAL_DMA_Abort(hadc->DMA_Handle); + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); /* Return function status */ - return HAL_OK; + return tmp_hal_status; } /** @@ -972,6 +1189,8 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_ConvCpltCallback could be implemented in the user file */ @@ -985,6 +1204,8 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file */ @@ -998,6 +1219,8 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file */ @@ -1005,12 +1228,20 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief Error ADC callback. + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_ErrorCallback could be implemented in the user file */ @@ -1057,14 +1288,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Process locked */ __HAL_LOCK(hadc); - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (sConfig->Channel > ADC_CHANNEL_9) - { - /* Clear the old sample time */ - hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (sConfig->Channel > ADC_CHANNEL_9) + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); + } + else + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); + } } else /* ADC_Channel include in ADC_Channel_[0..9] */ { @@ -1110,13 +1349,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf ADC->CCR |= ADC_CCR_VBATE; } - /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ + /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) { /* Enable the TSVREFE channel*/ ADC->CCR |= ADC_CCR_TSVREFE; - if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) + if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ @@ -1137,6 +1376,14 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /** * @brief Configures the analog watchdog. + * @note Analog watchdog thresholds can be modified while ADC conversion + * is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure @@ -1225,7 +1472,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * the configuration information for the specified ADC. * @retval HAL state */ -HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) { /* Return ADC state */ return hadc->State; @@ -1346,21 +1593,49 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { + /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Check if an injected conversion is ready */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); } else { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); } - - HAL_ADC_ConvCpltCallback(hadc); } /** @@ -1385,12 +1660,15 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) static void ADC_DMAError(DMA_HandleTypeDef *hdma) { ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR; + hadc->State= HAL_ADC_STATE_ERROR_DMA; /* Set ADC error code to DMA error */ hadc->ErrorCode |= HAL_ADC_ERROR_DMA; HAL_ADC_ErrorCallback(hadc); } +/** + * @} + */ /** * @} diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c index a5b4718cec..cee4e1c554 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions @@ -86,7 +86,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -131,10 +131,10 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ /** @addtogroup ADCEx_Private_Functions * @{ */ +/* Private function prototypes -----------------------------------------------*/ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); @@ -142,14 +142,14 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); * @} */ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * + * @brief Extended features functions + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -182,17 +182,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Process locked */ __HAL_LOCK(hadc); - /* Check if a regular conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_REG) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ; - } + /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ @@ -201,7 +191,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); - /* Delay for temperature sensor stabilization time */ + /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); while(counter != 0) @@ -210,30 +200,57 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) } } - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - else - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + else + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if((hadc->Instance == ADC1) && tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + } /* Return function status */ return HAL_OK; @@ -249,25 +266,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { __IO uint32_t counter = 0; - uint32_t tmp1 = 0, tmp2 =0; + uint32_t tmp1 = 0, tmp2 = 0; /* Process locked */ __HAL_LOCK(hadc); - /* Check if a regular conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_REG) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ; - } - - /* Set ADC error code to none */ - hadc->ErrorCode = HAL_ADC_ERROR_NONE; + /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ @@ -276,7 +280,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); - /* Delay for temperature sensor stabilization time */ + /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); while(counter != 0) @@ -285,60 +289,122 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) } } - /* Enable the ADC end of conversion interrupt for injected group */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - - /* Enable the ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Enable end of conversion interrupt for injected channels */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + else + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if((hadc->Instance == ADC1) && tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } } } - else - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; } /** - * @brief Disables ADC and stop conversion of injected channels. - * - * @note Caution: This function will stop also regular channels. - * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status. + * @brief Stop conversion of injected channels. Disable ADC peripheral if + * no regular conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @note In case of auto-injection mode, HAL_ADC_Stop must be used. + * @param hadc: ADC handle + * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) { - /* Disable the Peripheral */ - __HAL_ADC_DISABLE(hadc); + HAL_StatusTypeDef tmp_hal_status = HAL_OK; - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); /* Return function status */ - return HAL_OK; + return tmp_hal_status; } /** @@ -371,16 +437,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u } } - /* Check if a regular conversion is ready */ - if(hadc->State == HAL_ADC_STATE_EOC_REG) + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ; + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } /* Return ADC state */ @@ -388,30 +470,65 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u } /** - * @brief Disables the interrupt and stop ADC conversion of injected channels. - * - * @note Caution: This function will stop also regular channels. - * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status. + * @brief Stop conversion of injected channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no regular conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @param hadc: ADC handle + * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) { - /* Disable the ADC end of conversion interrupt for regular group */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + HAL_StatusTypeDef tmp_hal_status = HAL_OK; - /* Disable the ADC end of conversion interrupt for injected group */ - __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE); + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Enable the Peripheral */ - __HAL_ADC_DISABLE(hadc); + /* Process locked */ + __HAL_LOCK(hadc); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable ADC end of conversion interrupt for injected channels */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); /* Return function status */ - return HAL_OK; + return tmp_hal_status; } /** @@ -433,8 +550,9 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa /* Check the parameters */ assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - /* Clear the ADCx's flag for injected end of conversion */ - __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC); + /* Clear injected group conversion flag to have similar behaviour as */ + /* regular group: reading data register also clears end of conversion flag. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Return the selected ADC converted value */ switch(InjectedRank) @@ -488,35 +606,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Process locked */ __HAL_LOCK(hadc); - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - if (hadc->Init.DMAContinuousRequests != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADC->CCR &= ~ADC_CCR_DDS; - } - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) @@ -533,15 +622,80 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t } } - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + if (hadc->Init.DMAContinuousRequests != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADC->CCR |= ADC_CCR_DDS; + } + else + { + /* Disable the selected ADC EOC rising on each regular channel conversion */ + ADC->CCR &= ~ADC_CCR_DDS; + } + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); + + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } /* Return function status */ return HAL_OK; @@ -555,29 +709,42 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) { + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + /* Process locked */ __HAL_LOCK(hadc); - /* Enable the Peripheral */ + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable the selected ADC DMA mode for multimode */ + ADC->CCR &= ~ADC_CCR_DDS; - /* Disable the selected ADC DMA request after last transfer */ - ADC->CCR &= ~ADC_CCR_DDS; + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - /* Disable the ADC DMA Stream */ - HAL_DMA_Abort(hadc->DMA_Handle); + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return HAL_OK; + return tmp_hal_status; } /** @@ -601,6 +768,8 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file */ @@ -626,7 +795,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); @@ -636,6 +804,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); #endif /* USE_FULL_ASSERT */ + if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); + } + /* Process locked */ __HAL_LOCK(hadc); @@ -669,13 +842,27 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Set the SQx bits for the selected rank */ hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); - /* Select external trigger to start conversion */ - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); - hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; - /* Select external trigger polarity */ - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); - hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + } if (sConfigInjected->AutoInjectedConv != DISABLE) { @@ -793,21 +980,49 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ */ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Check if an injected conversion is ready */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); } else { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); } - - HAL_ADC_ConvCpltCallback(hadc); } /** @@ -832,7 +1047,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) { ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR; + hadc->State= HAL_ADC_STATE_ERROR_DMA; /* Set ADC error code to DMA error */ hadc->ErrorCode |= HAL_ADC_ERROR_DMA; HAL_ADC_ErrorCallback(hadc); diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_can.c b/stmhal/hal/f7/src/stm32f7xx_hal_can.c index 0f5d8a3135..100336e447 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_can.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_can.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: @@ -18,7 +18,8 @@ ============================================================================== [..] (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 + and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 -@- In case you are using CAN2 only, you have to enable the CAN1 clock. (#) CAN pins configuration @@ -31,8 +32,12 @@ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. + (#) Receive a CAN frame using HAL_CAN_Receive() function. + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + *** Polling mode IO operation *** ================================= [..] @@ -73,7 +78,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -165,7 +170,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { - uint32_t InitStatus = 3; + uint32_t InitStatus = CAN_INITSTATUS_FAILED; uint32_t tickstart = 0; /* Check CAN handle */ @@ -222,11 +227,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) } /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_INITSTATUS_FAILED; - } - else + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { /* Set the time triggered communication mode */ if (hcan->Init.TTCM == ENABLE) @@ -293,32 +294,28 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) ((uint32_t)hcan->Init.SJW) | \ ((uint32_t)hcan->Init.BS1) | \ ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1); + ((uint32_t)hcan->Init.Prescaler - 1); /* Request leave initialisation */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_INITSTATUS_FAILED; - } - else + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { InitStatus = CAN_INITSTATUS_SUCCESS; } @@ -357,6 +354,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) { uint32_t filternbrbitpos = 0; + CAN_TypeDef *can_ip; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); @@ -367,83 +365,100 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; +#if defined (CAN3) + /* Check the CAN instance */ + if(hcan->Instance == CAN3) + { + can_ip = CAN3; + } + else + { + can_ip = CAN1; + } +#else + can_ip = CAN1; +#endif /* Initialisation mode for the filter */ - CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; + can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; +#if defined (CAN2) /* Select the start slave bank */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); + can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); +#endif /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filternbrbitpos; + can_ip->FA1R &= ~(uint32_t)filternbrbitpos; /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filternbrbitpos; + can_ip->FS1R &= ~(uint32_t)filternbrbitpos; /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { /* 32-bit scale for the filter */ - CAN1->FS1R |= filternbrbitpos; + can_ip->FS1R |= filternbrbitpos; + /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filternbrbitpos; + can_ip->FM1R &= ~(uint32_t)filternbrbitpos; } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filternbrbitpos; + can_ip->FM1R |= (uint32_t)filternbrbitpos; } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) { /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filternbrbitpos; + can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; } if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) { /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filternbrbitpos; + can_ip->FFA1R |= (uint32_t)filternbrbitpos; } /* Filter activation */ if (sFilterConfig->FilterActivation == ENABLE) { - CAN1->FA1R |= filternbrbitpos; + can_ip->FA1R |= filternbrbitpos; } /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); + can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); /* Return function status */ return HAL_OK; @@ -490,6 +505,8 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) */ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file */ @@ -503,6 +520,8 @@ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) */ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file */ @@ -538,7 +557,7 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) */ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { - uint32_t transmitmailbox = 5; + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; uint32_t tickstart = 0; /* Check the parameters */ @@ -546,40 +565,38 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - /* Process locked */ - __HAL_LOCK(hcan); + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process locked */ + __HAL_LOCK(hcan); - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = 0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } - else - { - transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - } + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } - if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) - { /* Set up the Id */ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if (hcan->pTxMsg->IDE == CAN_ID_STD) @@ -597,8 +614,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) } /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ @@ -613,8 +630,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); /* Check End of transmission flag */ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) @@ -635,19 +652,16 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_RX; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } else { /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } + /* Process unlocked */ + __HAL_UNLOCK(hcan); + /* Return function status */ return HAL_OK; } @@ -656,9 +670,6 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_ERROR; } @@ -672,16 +683,16 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) */ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) { - uint32_t transmitmailbox = 5; - uint32_t tmp = 0; + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; /* Check the parameters */ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - tmp = hcan->State; - if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX)) + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) { /* Process Locked */ __HAL_LOCK(hcan); @@ -689,96 +700,84 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /* Select one empty transmit mailbox */ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) { - transmitmailbox = 0; + transmitmailbox = CAN_TXMAILBOX_0; } else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) { - transmitmailbox = 1; - } - else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; + transmitmailbox = CAN_TXMAILBOX_1; } else { - transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + transmitmailbox = CAN_TXMAILBOX_2; } - if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); - - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); - - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); - - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); - - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); - - /* Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Enable Error warning, Error passive, Bus-off, + Last error and Error Interrupts */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } else { - return HAL_BUSY; + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; } return HAL_OK; @@ -874,19 +873,16 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } else { /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } + /* Process unlocked */ + __HAL_UNLOCK(hcan); + /* Return function status */ return HAL_OK; } @@ -925,20 +921,13 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); - - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); - - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); - - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); - - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); + /* Enable Error warning, Error passive, Bus-off, + Last error and Error Interrupts */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -1120,8 +1109,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { /* Set CAN error code to EWG error */ hcan->ErrorCode |= HAL_CAN_ERROR_EWG; - /* Clear Error Warning Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG); } tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); @@ -1132,8 +1119,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { /* Set CAN error code to EPV error */ hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - /* Clear Error Passive Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV); } tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); @@ -1144,8 +1129,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { /* Set CAN error code to BOF error */ hcan->ErrorCode |= HAL_CAN_ERROR_BOF; - /* Clear Bus-Off Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF); } tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); @@ -1192,6 +1175,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Call the Error call Back in case of Errors */ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) { + /* Clear ERRI Flag */ + hcan->Instance->MSR = CAN_MSR_ERRI; /* Set the CAN state ready to be able to start again the process */ hcan->State = HAL_CAN_STATE_READY; /* Call Error callback function */ @@ -1207,6 +1192,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) */ __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxCpltCallback could be implemented in the user file */ @@ -1220,6 +1207,8 @@ __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) */ __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxCpltCallback could be implemented in the user file */ @@ -1233,6 +1222,8 @@ __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ @@ -1297,20 +1288,13 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) if(hcan->State == HAL_CAN_STATE_BUSY_TX) { - /* Disable Error warning Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); - - /* Disable Error passive Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); - - /* Disable Bus-off Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); - - /* Disable Last error code Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); - - /* Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); } if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) @@ -1385,20 +1369,13 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum if(hcan->State == HAL_CAN_STATE_BUSY_RX) { - /* Disable Error warning Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); - - /* Disable Error passive Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); - - /* Disable Bus-off Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); - - /* Disable Last error code Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); - - /* Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); } if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c b/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c index e8008351e1..b7dd19ad57 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -70,7 +70,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -269,6 +269,46 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) */ #if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enables the MPU + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + /** * @brief Initializes and configures the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dac.c b/stmhal/hal/f7/src/stm32f7xx_hal_dac.c index 77adc61201..a37465bcd8 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_dac.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -143,7 +143,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -302,6 +302,9 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_MspInit could be implemented in the user file */ @@ -315,6 +318,9 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_MspDeInit could be implemented in the user file */ @@ -682,6 +688,9 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_ConvCpltCallback could be implemented in the user file */ @@ -695,6 +704,9 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file */ @@ -708,6 +720,9 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file */ @@ -721,6 +736,9 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c index ca6d12b952..a7b803e9b6 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -25,7 +25,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -269,6 +269,9 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align */ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file */ @@ -282,6 +285,9 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) */ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file */ @@ -295,6 +301,9 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) */ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file */ @@ -308,6 +317,9 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dma.c b/stmhal/hal/f7/src/stm32f7xx_hal_dma.c index 1bb953aa30..92f0d975c8 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_dma.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -19,7 +19,7 @@ (#) Enable and configure the peripheral to be connected to the DMA Stream (except for internal SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between peripherals - and DMA requests . + and DMA requests. (#) For a given Stream, program the required configuration through the following parameters: Transfer Direction, Source and Destination data formats, @@ -27,13 +27,17 @@ Source and Destination Increment mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: + __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). + *** Polling mode IO operation *** ================================= [..] (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred + address and destination address and the Length of data to be transferred. (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_DMA_Abort() function to abort the current transfer. *** Interrupt mode IO operation *** =================================== @@ -51,7 +55,7 @@ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. - (#) Use HAL_DMA_Abort() function to abort the current transfer + (#) Use HAL_DMA_Abort_IT() function to abort the current transfer -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. @@ -72,11 +76,6 @@ (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. - (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. - (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags. - (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. [..] @@ -86,7 +85,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -128,12 +127,19 @@ #ifdef HAL_DMA_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @addtogroup DMA_Private_Constants * @{ */ - #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ + #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */ /** * @} */ @@ -143,42 +149,8 @@ * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear DBM bit */ - hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); - - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); /** * @} @@ -208,7 +180,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /** - * @brief Initializes the DMA according to the specified + * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. @@ -216,7 +188,9 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - uint32_t tmp = 0; + uint32_t tmp = 0U; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) @@ -244,9 +218,31 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + /* Get the CR register value */ tmp = hdma->Instance->CR; @@ -286,11 +282,29 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; + + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -308,6 +322,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { + DMA_Base_Registers *regs; + /* Check the DMA peripheral state */ if(hdma == NULL) { @@ -317,36 +333,39 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { - return HAL_ERROR; + /* Return error status */ + return HAL_BUSY; } + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + /* Disable the selected DMA Streamx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Streamx control register */ - hdma->Instance->CR = 0; + hdma->Instance->CR = 0U; /* Reset DMA Streamx number of data to transfer register */ - hdma->Instance->NDTR = 0; + hdma->Instance->NDTR = 0U; /* Reset DMA Streamx peripheral address register */ - hdma->Instance->PAR = 0; + hdma->Instance->PAR = 0U; /* Reset DMA Streamx memory 0 address register */ - hdma->Instance->M0AR = 0; + hdma->Instance->M0AR = 0U; /* Reset DMA Streamx memory 1 address register */ - hdma->Instance->M1AR = 0; + hdma->Instance->M1AR = 0U; /* Reset DMA Streamx FIFO control register */ - hdma->Instance->FCR = (uint32_t)0x00000021; + hdma->Instance->FCR = (uint32_t)0x00000021U; - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -393,25 +412,37 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + /* Process locked */ __HAL_LOCK(hdma); - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - - return HAL_OK; + /* Return error status */ + status = HAL_BUSY; + } + return status; } /** @@ -425,40 +456,53 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + /* Process locked */ __HAL_LOCK(hdma); - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; - /* Enable the transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; - /* Enable the Half transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + if(hdma->XferHalfCpltCallback != NULL) + { + hdma->Instance->CR |= DMA_IT_HT; + } - /* Enable the transfer Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); - /* Enable the FIFO Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE); + /* Return error status */ + status = HAL_BUSY; + } - /* Enable the direct mode Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - - return HAL_OK; + return status; } /** @@ -475,37 +519,86 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { - uint32_t tickstart = 0; + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); + uint32_t tickstart = HAL_GetTick(); - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the DMA Stream is effectively disabled */ - while((hdma->Instance->CR & DMA_SxCR_EN) != 0) + if(hdma->State != HAL_DMA_STATE_BUSY) { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + /* Process Unlocked */ + __HAL_UNLOCK(hdma); - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } + return HAL_ERROR; } - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + else + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + } + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } return HAL_OK; } @@ -515,155 +608,140 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CompleteLevel: Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout: Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { - uint32_t temp, tmp, tmp1, tmp2; - uint32_t tickstart = 0; + HAL_StatusTypeDef status = HAL_OK; + uint32_t mask_cpltlevel; + uint32_t tickstart = HAL_GetTick(); + uint32_t tmpisr; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode and double buffering mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ - temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; } else { /* Half Transfer Complete flag */ - temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; } - /* Get tick */ - tickstart = HAL_GetTick(); + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + tmpisr = regs->ISR; - while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) { - tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); - if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET)) - { - if(tmp != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - - /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - } - if(tmp1 != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Clear the FIFO error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - } - if(tmp2 != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Clear the Direct Mode error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); - } - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ + /* Check for the Timeout (Not applicable in circular mode)*/ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + return HAL_TIMEOUT; } } + + /* Get the ISR register value */ + tmpisr = regs->ISR; + + if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + } } + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + HAL_DMA_Abort(hdma); + + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + + /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { - /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) - { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_MEM0; - } - /* Current memory buffer used is Memory 1 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_MEM1; - } - } - else - { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - - /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers - are complete) */ - hdma->State = HAL_DMA_STATE_READY_MEM0; - } /* Process Unlocked */ __HAL_UNLOCK(hdma); + + hdma->State = HAL_DMA_STATE_READY; } else { - /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) - { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; - } - /* Current memory buffer used is Memory 1 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; - } - } - else - { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; - } + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; } - return HAL_OK; + + return status; } /** @@ -674,145 +752,140 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { + uint32_t tmpisr; + __IO uint32_t count = 0; + uint32_t timeout = SystemCoreClock / 9600; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr = regs->ISR; + /* Transfer Error Interrupt management ***************************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) { /* Disable the transfer error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); + hdma->Instance->CR &= ~(DMA_IT_TE); /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } } } /* FIFO Error Interrupt management ******************************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET) + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) { - /* Disable the FIFO Error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE); - /* Clear the FIFO error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } } } /* Direct Mode Error Interrupt management ***********************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET) + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) { - /* Disable the direct mode Error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME); - /* Clear the direct mode error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } } } /* Half Transfer Complete Interrupt management ******************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) { - /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) - { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } } /* Current memory buffer used is Memory 1 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + else { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) { /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + hdma->Instance->CR &= ~(DMA_IT_HT); } - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; - } - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } } } } /* Transfer Complete Interrupt management ***********************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) { - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) - { - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - /* Current memory buffer used is Memory 1 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) { if(hdma->XferM1CpltCallback != NULL) { @@ -820,8 +893,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->XferM1CpltCallback(hdma); } } - /* Current memory buffer used is Memory 0 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + /* Current memory buffer used is Memory 1 */ + else { if(hdma->XferCpltCallback != NULL) { @@ -833,22 +906,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) { /* Disable the transfer complete interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); + hdma->Instance->CR &= ~(DMA_IT_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; } - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_NONE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY_MEM0; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); if(hdma->XferCpltCallback != NULL) { @@ -858,6 +926,169 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifer + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback: pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; } /** @@ -905,6 +1136,172 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) * @} */ +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = hdma->Init.FIFOThreshold; + + /* Memory Data size equal to Byte */ + if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + break; + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + return status; +} + /** * @} */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_flash.c b/stmhal/hal/f7/src/stm32f7xx_hal_flash.c index b5ca6dcf46..b28b2768dd 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_flash.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -72,7 +72,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -118,8 +118,8 @@ /** @addtogroup FLASH_Private_Constants * @{ */ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ +#define SECTOR_MASK ((uint32_t)0xFFFFFF07U) +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */ /** * @} */ @@ -327,6 +327,9 @@ void HAL_FLASH_IRQHandler(void) /* Check FLASH End of Operation flag */ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + switch (pFlash.ProcedureOnGoing) { case FLASH_PROC_SECTERASE : @@ -341,9 +344,6 @@ void HAL_FLASH_IRQHandler(void) /* Indicate user which sector has been erased */ HAL_FLASH_EndOfOperationCallback(temp); - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - /* Increment sector number */ temp = ++pFlash.Sector; FLASH_Erase_Sector(temp, pFlash.VoltageForErase); @@ -352,13 +352,11 @@ void HAL_FLASH_IRQHandler(void) { /* No more sectors to Erase, user callback can be called.*/ /* Reset Sector and stop Erase sectors procedure */ - pFlash.Sector = temp = 0xFFFFFFFF; + pFlash.Sector = temp = 0xFFFFFFFFU; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(temp); /* Sector Erase procedure is completed */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } break; } @@ -370,8 +368,6 @@ void HAL_FLASH_IRQHandler(void) HAL_FLASH_EndOfOperationCallback(0); /* MAss Erase procedure is completed */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); break; } @@ -382,8 +378,6 @@ void HAL_FLASH_IRQHandler(void) HAL_FLASH_EndOfOperationCallback(pFlash.Address); /* Programming procedure is completed */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); break; } default : @@ -392,7 +386,7 @@ void HAL_FLASH_IRQHandler(void) } /* Check FLASH operation error flags */ - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) { switch (pFlash.ProcedureOnGoing) { @@ -400,7 +394,7 @@ void HAL_FLASH_IRQHandler(void) { /* return the faulty sector */ temp = pFlash.Sector; - pFlash.Sector = 0xFFFFFFFF; + pFlash.Sector = 0xFFFFFFFFU; break; } case FLASH_PROC_MASSERASE : @@ -415,16 +409,14 @@ void HAL_FLASH_IRQHandler(void) temp = pFlash.Address; break; } - default : - break; + default : + break; } /*Save the Error code*/ FLASH_SetErrorCode(); /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(temp); - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR ); /*Stop the procedure ongoing */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -455,9 +447,11 @@ void HAL_FLASH_IRQHandler(void) */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ } /** @@ -471,8 +465,10 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file + the HAL_FLASH_OperationErrorCallback could be implemented in the user file */ } @@ -637,14 +633,20 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) } } - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) { /*Save the error code*/ FLASH_SetErrorCode(); return HAL_ERROR; } + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + /* If there is an error flag set */ return HAL_OK; @@ -774,6 +776,11 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) */ static void FLASH_SetErrorCode(void) { + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; @@ -794,10 +801,8 @@ static void FLASH_SetErrorCode(void) pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; - } + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); } /** diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c index 359f09eedd..b6f2a3e3c5 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -14,13 +14,13 @@ ##### Flash Extension features ##### ============================================================================== - [..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and + [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx devices contains the following additional features (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write capability (RWW) (+) Dual bank memory organization - (+) PCROP protection for all banks + (+) Dual boot mode ##### How to use this driver ##### ============================================================================== @@ -39,18 +39,12 @@ (++) Set the Read protection Level (++) Set the BOR level (++) Program the user Option Bytes - (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : - (++) Extended space (bank 2) erase function - (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2) - (++) Dual Boot activation - (++) Write protection configuration for bank 2 - (++) PCROP protection configuration and control for both banks @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -96,8 +90,8 @@ /** @addtogroup FLASHEx_Private_Constants * @{ */ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ +#define SECTOR_MASK 0xFFFFFF07U +#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */ /** * @} */ @@ -117,11 +111,9 @@ extern FLASH_ProcessTypeDef pFlash; * @{ */ /* Option bytes control */ -static void FLASH_MassErase(uint8_t VoltageRange); static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector); static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector); -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address); static uint32_t FLASH_OB_GetUser(void); @@ -130,6 +122,15 @@ static uint8_t FLASH_OB_GetRDP(void); static uint32_t FLASH_OB_GetBOR(void); static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption); +#if defined (FLASH_OPTCR_nDBANK) +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot); +#else +static void FLASH_MassErase(uint8_t VoltageRange); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); +#endif /* FLASH_OPTCR_nDBANK */ + extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} @@ -182,12 +183,16 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t if(status == HAL_OK) { /*Initialization of SectorError variable*/ - *SectorError = 0xFFFFFFFF; + *SectorError = 0xFFFFFFFFU; if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); @@ -208,9 +213,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - /* If the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; + /* If the erase operation is completed, disable the SER Bit and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); if(status != HAL_OK) { @@ -259,7 +263,11 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { /*Mass erase to be done*/ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ } else { @@ -281,7 +289,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) } /** - * @brief Program option bytes + * @brief Program option bytes * @param pOBInit: pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * @@ -322,12 +330,23 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /* USER configuration */ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) { +#if defined (FLASH_OPTCR_nDBANK) + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST, + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE, + pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK, + pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE); +#else status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, pOBInit->USERConfig & OB_IWDG_SW, pOBInit->USERConfig & OB_STOP_NO_RST, pOBInit->USERConfig & OB_STDBY_NO_RST, pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); +#endif /* FLASH_OPTCR_nDBANK */ } /* BOR Level configuration */ @@ -355,7 +374,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) } /** - * @brief Get the Option byte configuration + * @brief Get the Option byte configuration * @param pOBInit: pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * @@ -364,7 +383,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ - OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; /*Get WRP*/ pOBInit->WRPSector = FLASH_OB_GetWRP(); @@ -378,17 +397,221 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /*Get BOR Level*/ pOBInit->BORLevel = FLASH_OB_GetBOR(); - /*Get Boot Address when Boot pin = 0 */ + /*Get Boot Address when Boot pin = 0 */ pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0); /*Get Boot Address when Boot pin = 1 */ pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); } - /** * @} */ +#if defined (FLASH_OPTCR_nDBANK) +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * @param Banks: Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + FLASH->CR |= FLASH_MER_BIT; + } + else if(Banks == FLASH_BANK_2) + { + /*Only bank2 will be erased*/ + FLASH->CR |= FLASH_CR_MER2; + } + else + { + /*Only bank1 will be erased*/ + FLASH->CR |= FLASH_CR_MER1; + } + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector: FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + if(Sector > FLASH_SECTOR_11) + { + Sector += 4; + } + + /* If the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); + FLASH->CR |= FLASH_CR_STRT; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg: Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @param NDBank: Flash Single Bank mode enabled. + * This parameter can be one of the following values: + * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) + * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) + * @param NDBoot: Flash Dual boot mode disable. + * This parameter can be one of the following values: + * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot + * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot + + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + assert_param(IS_OB_NDBANK(NDBank)); + assert_param(IS_OB_NDBOOT(NDBoot)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ + FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U)); +} +#else + /** * @brief Full erase of FLASH memory sectors * @param VoltageRange: The device voltage range which defines the erase parallelism. @@ -406,16 +629,13 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) */ static void FLASH_MassErase(uint8_t VoltageRange) { - uint32_t tmp_psize = 0; - /* Check the parameters */ assert_param(IS_VOLTAGERANGE(VoltageRange)); /* if the previous operation is completed, proceed to erase all sectors */ FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); /* Data synchronous Barrier (DSB) Just after the write operation This will force the CPU to respect the sequence of instruction (no optimization).*/ __DSB(); @@ -476,16 +696,100 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) } /** - * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg: Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; + +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U)); +} +#endif /* FLASH_OPTCR_nDBANK */ + +/** + * @brief Enable the write protection of the desired bank1 or bank2 sectors * * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 + * it is not possible to program or erase the flash sector i if CortexM7 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * * @param WRPSector: specifies the sector(s) to be write protected. * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) * @arg OB_WRP_SECTOR_All * * @retval HAL FLASH State @@ -518,7 +822,9 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) * * @param WRPSector: specifies the sector(s) to be write protected. * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) * @arg OB_WRP_Sector_All * * @@ -543,9 +849,6 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) return status; } - - - /** * @brief Set the read protection level. * @param Level: specifies the read protection level. @@ -558,7 +861,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) * * @retval HAL Status */ -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level) +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) { HAL_StatusTypeDef status = HAL_OK; @@ -570,73 +873,12 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level) if(status == HAL_OK) { - MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_RDP, Level); + *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; } return status; } -/** - * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_WWDG_SW: Software WWDG selected - * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg: Selects the WWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NO_RST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP - * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY - * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby ) -{ - uint32_t useroptionmask = 0x00; - uint32_t useroptionvalue = 0x00; - - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WWDG_SOURCE(Wwdg)); - assert_param(IS_OB_IWDG_SOURCE(Iwdg)); - assert_param(IS_OB_STOP_SOURCE(Stop)); - assert_param(IS_OB_STDBY_SOURCE(Stdby)); - assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); - assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ - FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); - - useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); - - /* Update User Option Byte */ - MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); - } - - return status; - -} - /** * @brief Set the BOR Level. * @param Level: specifies the Option Bytes BOR Reset Level. @@ -693,37 +935,16 @@ static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_ if(BootOption == OPTIONBYTE_BOOTADDR_0) { MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address); - } - else - { - MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16)); - } + } + else + { + MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16)); + } } return status; } -/** - * @brief Return the FLASH User Option Byte value. - * @retval uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -static uint32_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return ((uint32_t)(FLASH->OPTCR & 0xC00000F0)); -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval uint32_t FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); -} - /** * @brief Returns the FLASH Read Protection level. * @retval FlagStatus FLASH ReadOut Protection Status: @@ -736,11 +957,11 @@ static uint8_t FLASH_OB_GetRDP(void) { uint8_t readstatus = OB_RDP_LEVEL_0; - if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_0) + if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0) { readstatus = OB_RDP_LEVEL_0; } - else if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_2) + else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2) { readstatus = OB_RDP_LEVEL_2; } diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c b/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c index daec5d6258..1cba15df6b 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -95,7 +95,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -141,15 +141,15 @@ /** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE ((uint32_t)0x00000003) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define GPIO_MODE ((uint32_t)0x00000003U) +#define EXTI_MODE ((uint32_t)0x10000000U) +#define GPIO_MODE_IT ((uint32_t)0x00010000U) +#define GPIO_MODE_EVT ((uint32_t)0x00020000U) +#define RISING_EDGE ((uint32_t)0x00100000U) +#define FALLING_EDGE ((uint32_t)0x00200000U) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) -#define GPIO_NUMBER ((uint32_t)16) +#define GPIO_NUMBER ((uint32_t)16U) /** * @} */ @@ -514,6 +514,9 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c b/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c index 2c51ee21da..66a154edc3 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -21,7 +21,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -33,15 +33,16 @@ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Stream + (+++) Configure the DMA Tx or Rx stream (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream - (#) Configure the Communication Clock Timing, Own Address1, Master Addressing Mode, Dual Addressing mode, + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API. + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() @@ -65,70 +66,133 @@ *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode IO sequential operation *** + =================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit + (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] - (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using HAL_I2C_Mem_Write_IT() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using HAL_I2C_Mem_Read_IT() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] - (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode (DMA) using + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] - (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using HAL_I2C_Mem_Write_DMA() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using HAL_I2C_Mem_Read_DMA() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -138,8 +202,9 @@ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt @@ -150,7 +215,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -192,52 +257,104 @@ #ifdef HAL_I2C_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup I2C_Private_Constants I2C Private Constants +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define * @{ */ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*State) == HAL_I2C_STATE_BUSY_TX) ? \ + ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \ + ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR))) + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup I2C_Private_Functions I2C Private Functions + +/** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ +/* Private functions to handle DMA transfer */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout); +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); -static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c); +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c); +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private functions to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private functions to handle start, restart or stop a transfer */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} @@ -257,7 +374,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui ##### Initialization and de-initialization functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize and - de-initialize the I2Cx peripheral: + deinitialize the I2Cx peripheral: (+) User must Implement HAL_I2C_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). @@ -282,9 +399,9 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui /** * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and create the associated handle. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) @@ -309,6 +426,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); } @@ -323,18 +441,17 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Configure I2Cx: Own Address1 and ack own address1 mode */ + /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if(hi2c->Init.OwnAddress1 != 0) + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ @@ -347,6 +464,9 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); @@ -359,14 +479,16 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; return HAL_OK; } /** - * @brief DeInitializes the I2C peripheral. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief DeInitialize the I2C peripheral. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) @@ -389,8 +511,9 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) HAL_I2C_MspDeInit(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Release Lock */ __HAL_UNLOCK(hi2c); @@ -399,27 +522,33 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) } /** - * @brief I2C MSP Init. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Initialize the I2C MSP. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspInit could be implemented in the user file */ } /** - * @brief I2C MSP DeInit - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief DeInitialize the I2C MSP. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspDeInit could be implemented in the user file */ } @@ -489,9 +618,10 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address. The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -499,44 +629,47 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t sizetmp = 0; + uint32_t tickstart = 0; if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - do + while(hi2c->XferSize > 0) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -548,35 +681,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*pData++); - sizetmp--; - Size--; + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; - if((sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount!=0)) { - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(Size > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(Size > 0); + } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -595,6 +727,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -609,9 +742,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /** * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address. The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -619,78 +753,87 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t sizetmp = 0; + uint32_t tickstart = 0; if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - do + while(hi2c->XferSize > 0) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } - /* Write data to RXDR */ - (*pData++) =hi2c->Instance->RXDR; - sizetmp--; - Size--; + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; - if((sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(Size > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(Size > 0); + } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -709,6 +852,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -723,8 +867,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /** * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -732,24 +876,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -763,7 +917,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -775,17 +929,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - do + while(hi2c->XferCount > 0) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -800,22 +954,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } } - /* Read data from TXDR */ - hi2c->Instance->TXDR = (*pData++); - Size--; - }while(Size > 0); + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } else { @@ -827,7 +981,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -838,6 +992,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -852,8 +1007,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /** * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -861,24 +1016,34 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } - - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -889,20 +1054,29 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(Size > 0) + while(hi2c->XferCount > 0) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; + } + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; @@ -914,12 +1088,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Read data from RXDR */ - (*pData++) = hi2c->Instance->RXDR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -938,18 +1112,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -963,23 +1137,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /** - * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address. The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -988,30 +1160,30 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1020,11 +1192,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -1035,23 +1206,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D } /** - * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address. The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -1060,30 +1229,30 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1095,7 +1264,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; } @@ -1106,9 +1275,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De } /** - * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1117,23 +1286,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1145,7 +1313,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } @@ -1156,9 +1324,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** - * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1167,23 +1335,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1195,7 +1362,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } @@ -1206,23 +1373,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa } /** - * @brief Transmit in master mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address. The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -1231,18 +1396,25 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Set the I2C DMA transfer complete callback */ @@ -1251,43 +1423,32 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + return HAL_OK; } else @@ -1297,23 +1458,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t } /** - * @brief Receive in master mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address. The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -1322,53 +1481,69 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if(hi2c->XferSize > 0) { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); } - - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_OK; } else @@ -1378,9 +1553,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D } /** - * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1396,12 +1571,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; @@ -1409,52 +1588,28 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_OK; } else @@ -1464,9 +1619,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p } /** - * @brief Receive in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1482,12 +1637,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; @@ -1495,37 +1654,28 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size); + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* Wait until DIR flag is set Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_OK; } else @@ -1535,8 +1685,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1547,7 +1697,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t Sizetmp = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -1559,19 +1709,28 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1587,23 +1746,22 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - /* Set NBYTES to write and reload if size > 255 */ - /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } do { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1615,37 +1773,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - /* Write data to DR */ - hi2c->Instance->TXDR = (*pData++); - Sizetmp--; - Size--; + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; - if((Sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount!=0)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - - if(Size > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - }while(Size > 0); + }while(hi2c->XferCount > 0); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1664,6 +1821,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1678,8 +1836,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /** * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1690,7 +1848,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t Sizetmp = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -1702,19 +1860,28 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1731,59 +1898,55 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - Sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } do { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Read data from RXDR */ - (*pData++) = hi2c->Instance->RXDR; + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; - /* Decrement the Size counter */ - Sizetmp--; - Size--; - - if((Sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(Size > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(Size > 0); + }while(hi2c->XferCount > 0); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1802,6 +1965,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1814,9 +1978,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } } /** - * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1826,6 +1990,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0; + uint32_t xfermode = 0; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -1844,22 +2011,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1875,16 +2052,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } } - /* Set NBYTES to write and reload if size > 255 */ - /* Size > 255, need to set RELOAD bit */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1896,7 +2065,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -1907,9 +2076,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /** - * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1919,6 +2088,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0; + uint32_t xfermode = 0; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -1937,21 +2109,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1967,16 +2150,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } } - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - /* Size > 255, need to set RELOAD bit */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1988,7 +2163,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; } @@ -1998,9 +2173,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } } /** - * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -2010,6 +2185,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0; + uint32_t xfermode = 0; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2028,76 +2206,79 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } } /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt; + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + return HAL_OK; } else @@ -2107,9 +2288,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /** - * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -2119,6 +2300,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0; + uint32_t xfermode = 0; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2137,30 +2321,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -2176,27 +2362,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } } - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - return HAL_TIMEOUT; - } + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); return HAL_OK; } @@ -2209,8 +2404,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /** * @brief Checks if target device is ready for communication. * @note This function is used with Memory devices - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param Trials: Number of trials * @param Timeout: Timeout duration @@ -2262,7 +2457,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2281,7 +2476,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd else { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2300,7 +2495,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->Instance->CR2 |= I2C_CR2_STOP; /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2322,70 +2517,424 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_BUSY; } } + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address. The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode = 0; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If size > MAX_NBYTE_SIZE, use reload mode */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + xferrequest = I2C_NO_STARTSTOP; + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address. The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode = 0; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + xferrequest = I2C_NO_STARTSTOP; + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + /** * @} */ -/** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ */ /** * @brief This function handles I2C event interrupt request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) { - /* I2C in mode Transmitter ---------------------------------------------------*/ - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET)) - { - /* Slave mode selected */ - if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) - { - I2C_SlaveTransmit_ISR(hi2c); - } - } + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET)) + /* I2C events treatment -------------------------------------*/ + if(hi2c->XferISR != NULL) { - /* Master mode selected */ - if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)) - { - I2C_MasterTransmit_ISR(hi2c); - } - } - - /* I2C in mode Receiver ----------------------------------------------------*/ - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET)) - { - /* Slave mode selected */ - if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX) - { - I2C_SlaveReceive_ISR(hi2c); - } - } - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET)) - { - /* Master mode selected */ - if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)) - { - I2C_MasterReceive_ISR(hi2c); - } + hi2c->XferISR(hi2c, itflags, itsources); } } /** * @brief This function handles I2C error interrupt request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + /* I2C Bus error interrupt occurred ------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) + if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -2394,7 +2943,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) + if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -2403,7 +2952,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) + if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -2412,114 +2961,185 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* Call the Error Callback in case of Error detected */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_ErrorCallback(hi2c); + I2C_ITError(hi2c, hi2c->ErrorCode); } } /** - * @brief Master Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Master Tx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file */ } /** - * @brief Master Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Master Rx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } -/** @brief Slave Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. +/** @brief Slave Tx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file */ } /** - * @brief Slave Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Slave Rx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file */ } /** - * @brief Memory Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Slave Address Match callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS + * @param AddrMatchCode: Address Match Code * @retval None */ - __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file */ } /** - * @brief Memory Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Listen Complete callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file */ } /** - * @brief I2C error callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief I2C error callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback could be implemented in the user file */ } +/** + * @brief I2C abort callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + /** * @} */ -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions * @verbatim =============================================================================== - ##### Peripheral State and Errors functions ##### + ##### Peripheral State, Mode and Error functions ##### =============================================================================== [..] This subsection permit to get in run-time the status of the peripheral @@ -2530,19 +3150,31 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) */ /** - * @brief Returns the I2C state. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Return the I2C handle state. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL state */ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) { + /* Return I2C handle state */ return hi2c->State; } /** - * @brief Return the I2C error code - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** +* @brief Return the I2C error code. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval I2C Error Code */ @@ -2564,104 +3196,109 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) */ /** - * @brief Handle Interrupt Flags Master Transmit Mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags: Interrupt flags to handle. + * @param ITSources: Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t DevAddress; + uint16_t devaddress = 0; /* Process Locked */ __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferSize--; hi2c->XferCount--; } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) + else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) { - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - if(hi2c->XferCount > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); hi2c->XferSize = hi2c->XferCount; + if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } } } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); + /* Call TxCpltCallback() if no stop mode is set */ + if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER)) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) + else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { if(hi2c->XferCount == 0) { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; + if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER)) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + + if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { - /* Disable ERR, TC, STOP, NACK, TXI interrupt */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX) - { - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); } /* Process Unlocked */ @@ -2671,191 +3308,110 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) } /** - * @brief Handle Interrupt Flags Master Receive Mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags: Interrupt flags to handle. + * @param ITSources: Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) -{ - uint16_t DevAddress; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) - { - if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) - { - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > 255) - { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = 255; - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = hi2c->XferCount; - } - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) - { - if(hi2c->XferCount == 0) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Disable ERR, TC, STOP, NACK, TXI interrupt */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI ); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) - { - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - -} - -/** - * @brief Handle Interrupt Flags Slave Transmit Mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET) + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ - /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if(hi2c->XferCount == 0) { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } } else { - /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Error callback to prevent upper layer */ - HAL_I2C_ErrorCallback(hi2c); } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + if(hi2c->XferCount > 0) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + + if((hi2c->XferCount == 0) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } } - /* Check first if STOPF is set */ - /* to prevent a Write Data in TX buffer */ - /* which is stuck in TXDR until next */ - /* communication with Master */ - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { - /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI ); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_SlaveTxCpltCallback(hi2c); + I2C_ITAddrCplt(hi2c, ITFlags); } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) + else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Datas have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if(hi2c->XferCount > 0) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferCount--; + hi2c->XferSize--; } + else + { + if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + } + } + + /* Check if STOPF is set */ + if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); } /* Process Unlocked */ @@ -2865,56 +3421,137 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c) } /** - * @brief Handle Interrupt Flags Slave Receive Mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags: Interrupt flags to handle. + * @param ITSources: Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { + uint16_t devaddress = 0; + uint32_t xfermode = 0; + /* Process Locked */ __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET) + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - + /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if(hi2c->XferCount != 0) + { + /* Recover Slave address */ + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags: Interrupt flags to handle. + * @param ITSources: Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + /* Process locked */ + __HAL_LOCK(hi2c); + + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI ); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_SlaveRxCpltCallback(hi2c); + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); } /* Process Unlocked */ @@ -2925,20 +3562,21 @@ static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c) /** * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address * @param Timeout: Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -2963,7 +3601,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -2980,7 +3618,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2990,20 +3628,21 @@ return HAL_OK; /** * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address * @param Timeout: Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3028,7 +3667,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3045,7 +3684,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3053,6 +3692,532 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_OK; } +/** + * @brief I2C Address complete process callback. + * @param hi2c: I2C handle. + * @param ITFlags: Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection = 0; + uint16_t slaveaddrcode = 0; + uint16_t ownadd1code = 0; + uint16_t ownadd2code = 0; + + /* In case of Listen state, need to inform upper layer of address match code event */ + if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if(hi2c->AddrEventCount == 2) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c: I2C handle. + * @retval None + */ +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterRxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c: I2C handle. + * @retval None + */ +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c: I2C handle. + * @param ITFlags: Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if((ITFlags & I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c: I2C handle. + * @param ITFlags: Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + { + if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize) + { + hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c); + hi2c->XferCount += hi2c->XferSize; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Store Last receive data if any */ + if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if((hi2c->XferSize > 0)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Rx Complete callback */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Tx Complete callback */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c: I2C handle. + * @param ITFlags: Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if((hi2c->XferSize > 0)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); +} + +/** + * @brief I2C interrupts error process. + * @param hi2c: I2C handle. + * @param ErrorCode: Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + /* Abort DMA RX transfer if any */ + else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT) + { + hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c: I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00; + } + + /* Flush TX register if not empty */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + /** * @brief DMA I2C master transmit process complete callback. * @param hdma: DMA handle @@ -3060,152 +4225,38 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - uint16_t DevAddress; I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if(hi2c->XferCount == 0) { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) - { - hi2c->XferSize = 255; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); } + /* else prepare a new DMA transfer and enable TCReload interrupt */ else { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); + hi2c->XferSize = MAX_NBYTE_SIZE; } else { - HAL_I2C_MasterTxCpltCallback(hi2c); + hi2c->XferSize = hi2c->XferCount; } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } @@ -3216,586 +4267,68 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal Use case, a AF is generated by master */ - /* to inform slave the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_SlaveTxCpltCallback(hi2c); - } + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ } /** - * @brief DMA I2C master receive process complete callback + * @brief DMA I2C master receive process complete callback. * @param hdma: DMA handle * @retval None */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - uint16_t DevAddress; - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if(hi2c->XferCount == 0) { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) - { - hi2c->XferSize = 255; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - } + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); } + /* else prepare a new DMA transfer and enable TCReload interrupt */ else { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); + hi2c->XferSize = MAX_NBYTE_SIZE; } else { - HAL_I2C_MasterRxCpltCallback(hi2c); + hi2c->XferSize = hi2c->XferCount; } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } /** * @brief DMA I2C slave receive process complete callback. - * @param hdma: DMA handle + * @param hdma: DMA handle * @retval None */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOPF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_SlaveRxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C Memory Write process complete callback - * @param hdma : DMA handle - * @retval None - */ -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) -{ - uint16_t DevAddress; - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) - { - hi2c->XferSize = 255; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - } - else - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MemTxCpltCallback(hi2c); - } - } -} - -/** - * @brief DMA I2C Memory Read process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint16_t DevAddress; - - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) - { - hi2c->XferSize = 255; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - } - } - else - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MemRxCpltCallback(hi2c); - } - } + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ } /** * @brief DMA I2C communication error callback. - * @param hdma : DMA handle + * @param hdma: DMA handle * @retval None */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) @@ -3805,60 +4338,67 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - hi2c->XferCount = 0; + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} - hi2c->State = HAL_I2C_STATE_READY; +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma: DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - HAL_I2C_ErrorCallback(hi2c); + /* Reset AbortCpltCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT) + { + hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } } /** * @brief This function handles I2C Communication Timeout. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag: specifies the I2C flag to check. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag: Specifies the I2C flag to check. * @param Status: The new Flag status (SET or RESET). * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = HAL_GetTick(); + while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout)) + { + hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; } } } @@ -3867,19 +4407,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = HAL_GetTick(); - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -3887,10 +4426,11 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3904,29 +4444,28 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3939,18 +4478,22 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check if a STOPF is detected */ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { @@ -3962,6 +4505,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3970,7 +4514,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -3986,31 +4530,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /** * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - /* Generate stop if necessary only in case of I2C peripheral in MASTER mode */ - if((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX) - || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)) - { - /* No need to generate the STOP condition if AUTOEND mode is enabled */ - /* Generate the STOP condition only in case of SOFTEND mode is enabled */ - if((hi2c->Instance->CR2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - } - /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) @@ -4018,9 +4547,11 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; @@ -4034,11 +4565,15 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4051,20 +4586,13 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hi2c: I2C handle. - * @param DevAddress: specifies the slave address to be programmed. - * @param Size: specifies the number of bytes to be programmed. + * @param DevAddress: Specifies the slave address to be programmed. + * @param Size: Specifies the number of bytes to be programmed. * This parameter must be a value between 0 and 255. - * @param Mode: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_RELOAD_MODE: Enable Reload mode . - * @arg I2C_AUTOEND_MODE: Enable Automatic end mode. - * @arg I2C_SOFTEND_MODE: Enable Software end mode. - * @param Request: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition. - * @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0). - * @arg I2C_GENERATE_START_READ: Generate Restart for read request. - * @arg I2C_GENERATE_START_WRITE: Generate Restart for write request. + * @param Mode: New state of the I2C START condition generation. + * This parameter can be a value of @ref I2C_RELOAD_END_MODE. + * @param Request: New state of the I2C START condition generation. + * This parameter can be a value of I2C_START_STOP_MODE. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) @@ -4091,8 +4619,144 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui } /** - * @} + * @brief Manage the enabling of Interrupts. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0; + + if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0; + + if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} /** * @} diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c b/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c index f0fd09a07e..9d56dbf77e 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -109,7 +109,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -379,6 +379,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_MspInit could be implemented in the user file */ @@ -392,6 +395,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_MspDeInit could be implemented in the user file */ @@ -526,7 +532,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) { /* Wait until Busy flag is reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) { /* Set the error code and execute error callback*/ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT; @@ -1202,6 +1208,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, */ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_TxHalfCpltCallback could be implemented in the user file */ @@ -1215,6 +1224,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, */ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_TxCpltCallback could be implemented in the user file */ @@ -1228,6 +1240,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, */ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_RxCpltCallback could be implemented in the user file */ @@ -1241,6 +1256,9 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_RxCpltCallback could be implemented in the user file */ @@ -1254,6 +1272,9 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_ErrorCallback could be implemented in the user file */ @@ -1326,7 +1347,7 @@ static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s) /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */ switch(hi2s->Init.ClockSource) { - case I2S_CLOCK_SYSCLK : + case I2S_CLOCK_PLL : { /* Configure the PLLI2S division factor */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c b/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c index 1e132b9e82..09943a6a8e 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -24,12 +24,12 @@ (#) Fill parameters of Init structure in HCD handle - (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using - (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE(); - (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -38,14 +38,14 @@ (#)Associate the Upper USB device stack to the HAL PCD Driver: (##) hpcd.pData = pdev; - (#)Enable HCD transmission and reception: + (#)Enable PCD transmission and reception: (##) HAL_PCD_Start(); @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State= HAL_PCD_STATE_READY; /* Activate LPM */ - if (hpcd->Init.lpm_enable == 1) + if (hpcd->Init.lpm_enable ==1) { HAL_PCDEx_ActivateLPM(hpcd); } @@ -203,7 +203,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) } /** - * @brief DeInitializes the PCD peripheral + * @brief DeInitializes the PCD peripheral. * @param hpcd: PCD handle * @retval HAL status */ @@ -235,6 +235,9 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_MspInit could be implemented in the user file */ @@ -247,6 +250,9 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_MspDeInit could be implemented in the user file */ @@ -256,7 +262,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @} */ -/** @defgroup PCD_Exported_Functions_Group2 IO operation functions +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions * @brief Data transfers functions * @verbatim @@ -301,7 +307,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) } /** - * @brief This function handles PCD interrupt request. + * @brief Handle PCD interrupt request. * @param hpcd: PCD handle * @retval HAL status */ @@ -310,7 +316,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0; uint32_t fifoemptymsk = 0, temp = 0; - USB_OTG_EPTypeDef *ep; + USB_OTG_EPTypeDef *ep = NULL; + uint32_t hclk = 200000000; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) @@ -372,6 +379,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } + /* Clear Status Phase Received interrupt */ + if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } } epnum++; ep_intr >>= 1; @@ -462,7 +474,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Suspend Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) { - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { @@ -508,7 +519,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } else { - USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); + USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM); USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); } @@ -537,7 +548,74 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { hpcd->Init.speed = USB_OTG_SPEED_FULL; hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + if((hclk >= 14200000)&&(hclk < 15000000)) + { + /* hclk Clock Range between 14.2-15 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 15000000)&&(hclk < 16000000)) + { + /* hclk Clock Range between 15-16 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 16000000)&&(hclk < 17200000)) + { + /* hclk Clock Range between 16-17.2 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 17200000)&&(hclk < 18500000)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 18500000)&&(hclk < 20000000)) + { + /* hclk Clock Range between 18.5-20 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 20000000)&&(hclk < 21800000)) + { + /* hclk Clock Range between 20-21.8 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 21800000)&&(hclk < 24000000)) + { + /* hclk Clock Range between 21.8-24 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 24000000)&&(hclk < 27700000)) + { + /* hclk Clock Range between 24-27.7 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 27700000)&&(hclk < 32000000)) + { + /* hclk Clock Range between 27.7-32 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); + } } HAL_PCD_ResetCallback(hpcd); @@ -612,136 +690,168 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /** - * @brief Data out stage callbacks + * @brief Data OUT stage callback. * @param hpcd: PCD handle * @param epnum: endpoint number * @retval None */ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_DataOutStageCallback could be implemented in the user file */ } /** - * @brief Data IN stage callbacks + * @brief Data IN stage callback. * @param hpcd: PCD handle * @param epnum: endpoint number * @retval None */ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_DataInStageCallback could be implemented in the user file */ } /** - * @brief Setup stage callback + * @brief Setup stage callback. * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_SetupStageCallback could be implemented in the user file */ } /** - * @brief USB Start Of Frame callbacks + * @brief USB Start Of Frame callback. * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_SOFCallback could be implemented in the user file */ } /** - * @brief USB Reset callbacks + * @brief USB Reset callback. * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_ResetCallback could be implemented in the user file */ } - /** - * @brief Suspend event callbacks + * @brief Suspend event callback. * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_SuspendCallback could be implemented in the user file */ } /** - * @brief Resume event callbacks + * @brief Resume event callback. * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_ResumeCallback could be implemented in the user file */ } /** - * @brief Incomplete ISO OUT callbacks + * @brief Incomplete ISO OUT callback. * @param hpcd: PCD handle * @param epnum: endpoint number * @retval None */ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file */ } /** - * @brief Incomplete ISO IN callbacks + * @brief Incomplete ISO IN callback. * @param hpcd: PCD handle * @param epnum: endpoint number * @retval None */ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file */ } /** - * @brief Connection event callbacks + * @brief Connection event callback. * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_ConnectCallback could be implemented in the user file */ } /** - * @brief Disconnection event callbacks + * @brief Disconnection event callback. * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCD_DisconnectCallback could be implemented in the user file */ @@ -767,7 +877,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) */ /** - * @brief Connect the USB device + * @brief Connect the USB device. * @param hpcd: PCD handle * @retval HAL status */ @@ -780,7 +890,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) } /** - * @brief Disconnect the USB device + * @brief Disconnect the USB device. * @param hpcd: PCD handle * @retval HAL status */ @@ -793,7 +903,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) } /** - * @brief Set the USB Device address + * @brief Set the USB Device address. * @param hpcd: PCD handle * @param address: new device address * @retval HAL status @@ -806,7 +916,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) return HAL_OK; } /** - * @brief Open and configure an endpoint + * @brief Open and configure an endpoint. * @param hpcd: PCD handle * @param ep_addr: endpoint address * @param ep_mps: endpoint max packet size @@ -850,7 +960,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint /** - * @brief Deactivate an endpoint + * @brief Deactivate an endpoint. * @param hpcd: PCD handle * @param ep_addr: endpoint address * @retval HAL status @@ -879,7 +989,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** - * @brief Receive an amount of data + * @brief Receive an amount of data. * @param hpcd: PCD handle * @param ep_addr: endpoint address * @param pBuf: pointer to the reception buffer @@ -920,7 +1030,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u } /** - * @brief Get Received Data Size + * @brief Get Received Data Size. * @param hpcd: PCD handle * @param ep_addr: endpoint address * @retval Data Size @@ -930,7 +1040,7 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; } /** - * @brief Send an amount of data + * @brief Send an amount of data. * @param hpcd: PCD handle * @param ep_addr: endpoint address * @param pBuf: pointer to the transmission buffer @@ -972,7 +1082,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } /** - * @brief Set a STALL condition over an endpoint + * @brief Set a STALL condition over an endpoint. * @param hpcd: PCD handle * @param ep_addr: endpoint address * @retval HAL status @@ -1007,7 +1117,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief Clear a STALL condition over in an endpoint + * @brief Clear a STALL condition over in an endpoint. * @param hpcd: PCD handle * @param ep_addr: endpoint address * @retval HAL status @@ -1037,7 +1147,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief Flush an endpoint + * @brief Flush an endpoint. * @param hpcd: PCD handle * @param ep_addr: endpoint address * @retval HAL status @@ -1061,7 +1171,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling + * @brief Activate remote wakeup signalling. * @param hpcd: PCD handle * @retval HAL status */ @@ -1071,14 +1181,14 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { - /* Activate Remote wake-up signaling */ + /* Activate Remote wakeup signaling */ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; } return HAL_OK; } /** - * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling + * @brief De-activate remote wakeup signalling. * @param hpcd: PCD handle * @retval HAL status */ @@ -1086,7 +1196,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - /* De-activate Remote wake-up signaling */ + /* De-activate Remote wakeup signaling */ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); return HAL_OK; } @@ -1110,7 +1220,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ /** - * @brief Return the PCD state + * @brief Return the PCD handle state. * @param hpcd: PCD handle * @retval HAL state */ @@ -1132,8 +1242,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) */ /** - * @brief DCD_WriteEmptyTxFifo - * check FIFO for the next packet to be loaded + * @brief Check FIFO for the next packet to be loaded. * @param hpcd: PCD handle * @param epnum : endpoint number * @retval HAL status diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c index 69b0d5ad13..12fca17458 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin if(fifo == 0) { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); } else { @@ -114,8 +114,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin } /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; - + hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); } return HAL_OK; @@ -135,7 +134,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) } /** - * @brief HAL_PCDEx_ActivateLPM : active LPM Feature + * @brief Activate LPM Feature * @param hpcd: PCD handle * @retval HAL status */ @@ -152,7 +151,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) } /** - * @brief HAL_PCDEx_DeActivateLPM : de-active LPM feature + * @brief DeActivate LPM feature. * @param hpcd: PCD handle * @retval HAL status */ @@ -168,13 +167,20 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } /** - * @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer + * @brief Send LPM message to user layer callback. * @param hpcd: PCD handle * @param msg: LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ } /** diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c b/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c index 6d7d5660b4..e8258192fb 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,10 +63,10 @@ /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ */ -#define PVD_MODE_IT ((uint32_t)0x00010000) -#define PVD_MODE_EVT ((uint32_t)0x00020000) -#define PVD_RISING_EDGE ((uint32_t)0x00000001) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) +#define PVD_MODE_IT ((uint32_t)0x00010000U) +#define PVD_MODE_EVT ((uint32_t)0x00020000U) +#define PVD_RISING_EDGE ((uint32_t)0x00000001U) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) /** * @} */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c index 19ca4c8ce3..e77873b40d 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -157,6 +157,10 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) /* Enable Backup regulator */ PWR->CSR1 |= PWR_CSR1_BRE; + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; + /* Get tick */ tickstart = HAL_GetTick(); @@ -182,6 +186,10 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) /* Disable Backup regulator */ PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; + /* Get tick */ tickstart = HAL_GetTick(); diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c index e62c5e0511..f8f51d01f8 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -56,7 +56,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -119,7 +119,6 @@ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ -const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -227,7 +226,7 @@ void HAL_RCC_DeInit(void) /* Reset PLLCFGR register */ CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U)); /* Reset PLLI2SCFGR register */ CLEAR_REG(RCC->PLLI2SCFGR); @@ -238,6 +237,9 @@ void HAL_RCC_DeInit(void) /* Disable all interrupts */ CLEAR_REG(RCC->CIR); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; } /** @@ -246,6 +248,12 @@ void HAL_RCC_DeInit(void) * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) @@ -271,21 +279,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ - __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); @@ -450,21 +443,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } - /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ - __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ @@ -513,6 +491,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); @@ -530,11 +511,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined (RCC_PLLCFGR_PLLR) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); +#else __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLM, RCC_OscInitStruct->PLL.PLLN, RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ); +#endif + /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); @@ -611,8 +602,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui assert_param(IS_FLASH_LATENCY(FLatency)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) @@ -626,161 +617,87 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { return HAL_ERROR; } + } - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } } - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - return HAL_ERROR; + return HAL_TIMEOUT; } } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - return HAL_ERROR; + return HAL_TIMEOUT; } } - /* HSI is selected as System Clock Source */ - else + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - return HAL_ERROR; - } - } - - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } } } - /* Decreasing the CPU frequency */ - else + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) { - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration -------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); @@ -790,7 +707,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { return HAL_ERROR; } - } + } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) @@ -806,6 +723,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -981,12 +901,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) { /* HSE used as PLL clock source */ - //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); - // dpgeorge: Adjust the way the arithmetic is done so it retains - // precision for the case that pllm doesn't evenly divide HSE_VALUE. - // Must be sure not to overflow, so divide by 4 first. HSE_VALUE - // should be a multiple of 4 (being a multiple of 100 is enough). - pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4; + pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); } else { @@ -1011,14 +926,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void) * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; return SystemCoreClock; } @@ -1031,7 +943,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); } /** @@ -1043,7 +955,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); } /** diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c index e04960d33e..0cc2395f41 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Extension RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -109,17 +109,19 @@ @endverbatim * @{ */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals - * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source; in this case the Backup domain will be reset in * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. + * the backup registers) are set to their reset values. * * @retval HAL status */ @@ -200,27 +202,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { - /* Reset the Backup domain only if the RTC Clock source selection is modified */ - if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) { - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR1 |= PWR_CR1_DBP; - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait for Backup domain Write protection disable */ - while((PWR->CR1 & PWR_CR1_DBP) == RESET) + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); @@ -231,8 +238,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg0; - /* If LSE is selected as RTC clock source, wait for LSE reactivation */ - if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY)) + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) { /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -246,8 +253,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } /*------------------------------------ TIM configuration --------------------------------------*/ @@ -407,12 +414,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*-------------------------------------- LTDC Configuration -----------------------------------*/ -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) { pllsaiused = 1; } -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { @@ -423,7 +431,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } - /*------------------------------------- SDMMC Configuration ------------------------------------*/ + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) { /* Check the parameters */ @@ -433,6 +441,38 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) @@ -512,7 +552,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); @@ -564,7 +603,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) { /* check for PLLSAIQ Parameter */ @@ -600,7 +639,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); } -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /*---------------------------- LTDC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { @@ -619,7 +658,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); } -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); @@ -651,7 +690,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) uint32_t tempreg = 0; /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ @@ -660,8 +700,22 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ - RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ + RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; +#else + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ RCC_PERIPHCLK_CLK48; +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /* Get the PLLI2S Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); @@ -734,9 +788,20 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the CK48 clock configuration -----------------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - /* Get the SDMMC clock configuration -----------------------------------------------*/ + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the DFSDM clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + + /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); @@ -751,6 +816,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; } } +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief Return the peripheral clock frequency for a given peripheral(SAI..) @@ -764,16 +830,100 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { uint32_t tmpreg = 0; - /* This variable used to store the SAI clock frequency (value in Hz) */ + /* This variable is used to store the SAI clock frequency (value in Hz) */ uint32_t frequency = 0; - /* This variable used to store the VCO Input (value in Hz) */ + /* This variable is used to store the VCO Input (value in Hz) */ uint32_t vcoinput = 0; - /* This variable used to store the SAI clock source */ + /* This variable is used to store the SAI clock source */ uint32_t saiclocksource = 0; - if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2)) + + if (PeriphClk == RCC_PERIPHCLK_SAI1) { saiclocksource = RCC->DCKCFGR1; - saiclocksource &= (RCC_DCKCFGR1_SAI1SEL | RCC_DCKCFGR1_SAI2SEL); + saiclocksource &= RCC_DCKCFGR1_SAI1SEL; + switch (saiclocksource) + { + case 0: /* PLLSAI is the clock source for SAI1 */ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + default : + { + break; + } + } + } + + if (PeriphClk == RCC_PERIPHCLK_SAI2) + { + saiclocksource = RCC->DCKCFGR1; + saiclocksource &= RCC_DCKCFGR1_SAI2SEL; switch (saiclocksource) { case 0: /* PLLSAI is the clock source for SAI*/ @@ -800,8 +950,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = frequency/(tmpreg); break; } - case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI*/ - case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI*/ + case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ { /* Configure the PLLI2S division factor */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ @@ -826,18 +975,34 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = frequency/(tmpreg); break; } - case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI*/ - case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI*/ + case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ { frequency = EXTERNAL_CLOCK_VALUE; break; } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ default : { break; } } } + return frequency; } diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rng.c b/stmhal/hal/f7/src/stm32f7xx_hal_rng.c index e4b3d20380..a9c1169536 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_rng.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_rng.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -29,7 +29,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -187,6 +187,9 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) */ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_RNG_MspInit must be implemented in the user file. */ @@ -200,6 +203,9 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) */ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_RNG_MspDeInit must be implemented in the user file. */ @@ -441,6 +447,9 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) */ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_RNG_ReadyDataCallback must be implemented in the user file. */ @@ -454,6 +463,9 @@ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32 */ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_RNG_ErrorCallback must be implemented in the user file. */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c index 83bfcc6589..af604feb22 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -109,7 +109,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -384,6 +384,9 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_MspInit could be implemented in the user file */ @@ -397,6 +400,9 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) */ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_MspDeInit could be implemented in the user file */ @@ -509,7 +515,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Clear the bits to be configured */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); @@ -576,6 +582,9 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Get subseconds values from the correspondent registers*/ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); + /* Get the TR register */ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); @@ -620,9 +629,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); @@ -1345,6 +1354,9 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_AlarmAEventCallback could be implemented in the user file */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c index c541b7b29d..3289c24307 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: @@ -70,7 +70,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -243,6 +243,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL; hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); + /* Clear RTC Timestamp flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); /* Enable IT timestamp */ @@ -590,6 +593,22 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType hrtc->Instance->TAMPCR |= tmpreg; + if(sTamper->Tamper == RTC_TAMPER_1) + { + /* Clear RTC Tamper 1 flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + } + else if(sTamper->Tamper == RTC_TAMPER_2) + { + /* Clear RTC Tamper 2 flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + } + else + { + /* Clear RTC Tamper 3 flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + } + /* RTC Tamper Interrupt Configuration: EXTI configuration */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); @@ -728,6 +747,9 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_TimeStampEventCallback could be implemented in the user file */ @@ -741,6 +763,9 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_Tamper1EventCallback could be implemented in the user file */ @@ -754,6 +779,9 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_Tamper2EventCallback could be implemented in the user file */ @@ -766,6 +794,9 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file */ @@ -1073,6 +1104,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; + /* Clear RTC Wake Up timer Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + /* Configure the Interrupt in the RTC_CR register */ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); @@ -1193,6 +1227,9 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file */ @@ -1753,6 +1790,9 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) */ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_AlarmBEventCallback could be implemented in the user file */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_sd.c b/stmhal/hal/f7/src/stm32f7xx_hal_sd.c index 6157b029ed..8a0bffbe17 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_sd.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_sd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -149,7 +149,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -206,67 +206,67 @@ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ SDMMC_FLAG_DBCKEND)) -#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000) +#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000U) /** * @brief Mask for errors Card Status R1 (OCR Register) */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) +#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) +#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) +#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) +#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) +#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) +#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) +#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) +#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) +#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) +#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) +#define SD_OCR_CC_ERROR ((uint32_t)0x00100000U) +#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) +#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) +#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) +#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) +#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) +#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) +#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000U) +#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) +#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) /** * @brief Masks for R6 Response */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) +#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) +#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) +#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) +#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) +#define SD_HIGH_CAPACITY ((uint32_t)0x40000000U) +#define SD_STD_CAPACITY ((uint32_t)0x00000000U) +#define SD_CHECK_PATTERN ((uint32_t)0x000001AAU) -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) +#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) +#define SD_ALLZERO ((uint32_t)0x00000000U) -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) +#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) +#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) +#define SD_CARD_LOCKED ((uint32_t)0x02000000U) -#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF) -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) +#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#define SD_0TO7BITS ((uint32_t)0x000000FFU) +#define SD_8TO15BITS ((uint32_t)0x0000FF00U) +#define SD_16TO23BITS ((uint32_t)0x00FF0000U) +#define SD_24TO31BITS ((uint32_t)0xFF000000U) +#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) -#define SD_HALFFIFO ((uint32_t)0x00000008) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) +#define SD_HALFFIFO ((uint32_t)0x00000008U) +#define SD_HALFFIFOBYTES ((uint32_t)0x00000020U) /** * @brief Command Class Supported */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) -#define SD_CCCC_ERASE ((uint32_t)0x00000020) +#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080U) +#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040U) +#define SD_CCCC_ERASE ((uint32_t)0x00000020U) /** * @brief Following commands are SD Card Specific commands. @@ -413,6 +413,9 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_MspInit could be implemented in the user file */ @@ -425,6 +428,9 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_MspDeInit could be implemented in the user file */ @@ -453,14 +459,14 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * @brief Reads block(s) from a specified address in a card. The Data transfer * is managed by polling mode. * @param hsd: SD handle - * @param pReadBuffer: pointer to the buffer that will contain the received data - * @param BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize) + * @param pReadBuffer: pointer to the buffer that will contain the received data + * @param ReadAddr: Address from where data is to be read * @param BlockSize: SD card Data block size * @note BlockSize must be 512 bytes. * @param NumberOfBlocks: Number of SD blocks to read * @retval SD Card error state */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) { SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; SDMMC_DataInitTypeDef sdmmc_datainitstructure; @@ -470,16 +476,10 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_ /* Initialize data control register */ hsd->Instance->DCTRL = 0; - uint32_t ReadAddr; if (hsd->CardType == HIGH_CAPACITY_SD_CARD) { BlockSize = 512; - ReadAddr = BlockNumber; - } - else - { - // should not overflow for standard-capacity cards - ReadAddr = BlockNumber * BlockSize; + ReadAddr /= 512; } /* Set Block Size for Card */ @@ -518,7 +518,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; } - sdmmc_cmdinitstructure.Argument = ReadAddr; + sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr; SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); /* Read block(s) in polling mode */ @@ -636,13 +636,13 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_ * transfer is managed by polling mode. * @param hsd: SD handle * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize) + * @param WriteAddr: Address from where data is to be written * @param BlockSize: SD card Data block size * @note BlockSize must be 512 bytes. * @param NumberOfBlocks: Number of SD blocks to write * @retval SD Card error state */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) { SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; SDMMC_DataInitTypeDef sdmmc_datainitstructure; @@ -654,16 +654,10 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32 /* Initialize data control register */ hsd->Instance->DCTRL = 0; - uint32_t WriteAddr; if (hsd->CardType == HIGH_CAPACITY_SD_CARD) { BlockSize = 512; - WriteAddr = BlockNumber; - } - else - { - // should not overflow for standard-capacity cards - WriteAddr = BlockNumber * BlockSize; + WriteAddr /= 512; } /* Set Block Size for Card */ @@ -693,7 +687,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32 sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; } - sdmmc_cmdinitstructure.Argument = WriteAddr; + sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr; SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); /* Check for error conditions */ @@ -852,13 +846,13 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32 * to check the completion of the read process * @param hsd: SD handle * @param pReadBuffer: Pointer to the buffer that will contain the received data - * @param BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize) + * @param ReadAddr: Address from where data is to be read * @param BlockSize: SD card Data block size * @note BlockSize must be 512 bytes. * @param NumberOfBlocks: Number of blocks to read. * @retval SD Card error state */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) { SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; SDMMC_DataInitTypeDef sdmmc_datainitstructure; @@ -898,16 +892,10 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uin /* Enable the DMA Channel */ HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4); - uint32_t ReadAddr; if (hsd->CardType == HIGH_CAPACITY_SD_CARD) { BlockSize = 512; - ReadAddr = BlockNumber; - } - else - { - // should not overflow for standard-capacity cards - ReadAddr = BlockNumber * BlockSize; + ReadAddr /= 512; } /* Set Block Size for Card */ @@ -947,7 +935,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uin sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; } - sdmmc_cmdinitstructure.Argument = ReadAddr; + sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr; SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); /* Check for error conditions */ @@ -974,13 +962,13 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uin * to check the completion of the write process (by SD current status polling). * @param hsd: SD handle * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize) + * @param WriteAddr: Address from where data is to be read * @param BlockSize: the SD card Data block size * @note BlockSize must be 512 bytes. * @param NumberOfBlocks: Number of blocks to write * @retval SD Card error state */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) { SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; SDMMC_DataInitTypeDef sdmmc_datainitstructure; @@ -1020,16 +1008,10 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, ui /* Enable SDMMC DMA transfer */ __HAL_SD_SDMMC_DMA_ENABLE(hsd); - uint32_t WriteAddr; if (hsd->CardType == HIGH_CAPACITY_SD_CARD) { BlockSize = 512; - WriteAddr = BlockNumber; - } - else - { - // should not overflow for standard-capacity cards - WriteAddr = BlockNumber * BlockSize; + WriteAddr /= 512; } /* Set Block Size for Card */ @@ -1395,6 +1377,9 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_XferCpltCallback could be implemented in the user file */ @@ -1407,6 +1392,9 @@ __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_XferErrorCallback could be implemented in the user file */ @@ -1420,6 +1408,9 @@ __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_DMA_RxCpltCallback could be implemented in the user file */ @@ -1433,6 +1424,9 @@ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) */ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_DMA_RxErrorCallback could be implemented in the user file */ @@ -1446,6 +1440,9 @@ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) */ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_DMA_TxCpltCallback could be implemented in the user file */ @@ -1459,6 +1456,9 @@ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) */ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_DMA_TxErrorCallback could be implemented in the user file */ @@ -1499,7 +1499,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->RCA = (uint16_t)(hsd->RCA); /* Byte 0 */ - tmp = (hsd->CSD[0] & 0xFF000000) >> 24; + tmp = (hsd->CSD[0] & 0xFF000000U) >> 24; pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); pCardInfo->SD_csd.Reserved1 = tmp & 0x03; @@ -1517,16 +1517,16 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp; /* Byte 4 */ - tmp = (hsd->CSD[1] & 0xFF000000) >> 24; + tmp = (hsd->CSD[1] & 0xFF000000U) >> 24; pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4); /* Byte 5 */ - tmp = (hsd->CSD[1] & 0x00FF0000) >> 16; + tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16; pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F); /* Byte 6 */ - tmp = (hsd->CSD[1] & 0x0000FF00) >> 8; + tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8; pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); @@ -1538,23 +1538,23 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); + tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); pCardInfo->SD_csd.DeviceSize |= (tmp) << 2; /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); + tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); + tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ; @@ -1565,23 +1565,23 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy else if (hsd->CardType == HIGH_CAPACITY_SD_CARD) { /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); + tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); pCardInfo->SD_csd.DeviceSize |= (tmp << 8); /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); + tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); pCardInfo->SD_csd.DeviceSize |= (tmp); /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); + tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1ULL)) * 512 * 1024; + pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024); pCardInfo->CardBlockSize = 512; } else @@ -1599,7 +1599,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); /* Byte 12 */ - tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24); pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; @@ -1627,7 +1627,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_csd.Reserved4 = 1; /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24); pCardInfo->SD_cid.ManufacturerID = tmp; /* Byte 1 */ @@ -1643,7 +1643,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_cid.ProdName1 = tmp << 24; /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24); pCardInfo->SD_cid.ProdName1 |= tmp << 16; /* Byte 5 */ @@ -1659,7 +1659,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_cid.ProdName2 = tmp; /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24); pCardInfo->SD_cid.ProdRev = tmp; /* Byte 9 */ @@ -1675,7 +1675,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_cid.ProdSN |= tmp << 8; /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24); pCardInfo->SD_cid.ProdSN |= tmp; /* Byte 13 */ @@ -1840,7 +1840,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); /* Send CMD6 switch mode */ - sdmmc_cmdinitstructure.Argument = 0x80FFFF01; + sdmmc_cmdinitstructure.Argument = 0x80FFFF01U; sdmmc_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH; SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); @@ -2121,55 +2121,55 @@ HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatu pCardStatus->SECURED_MODE = (uint8_t)tmp; /* Byte 2 */ - tmp = (sd_status[2] & 0xFF); - pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8); + tmp = (sd_status[0] & 0x00FF0000) >> 16; + pCardStatus->SD_CARD_TYPE = (uint16_t)(tmp << 8); /* Byte 3 */ - tmp = (sd_status[3] & 0xFF); - pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp; + tmp = (sd_status[0] & 0xFF000000) >> 24; + pCardStatus->SD_CARD_TYPE |= (uint16_t)tmp; /* Byte 4 */ - tmp = (sd_status[4] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24); + tmp = (sd_status[1] & 0xFF); + pCardStatus->SIZE_OF_PROTECTED_AREA = (uint32_t)(tmp << 24); /* Byte 5 */ - tmp = (sd_status[5] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16); + tmp = (sd_status[1] & 0xFF00) >> 8; + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 16); /* Byte 6 */ - tmp = (sd_status[6] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8); + tmp = (sd_status[1] & 0xFF0000) >> 16; + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 8); /* Byte 7 */ - tmp = (sd_status[7] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp; + tmp = (sd_status[1] & 0xFF000000) >> 24; + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)tmp; /* Byte 8 */ - tmp = (sd_status[8] & 0xFF); + tmp = (sd_status[2] & 0xFF); pCardStatus->SPEED_CLASS = (uint8_t)tmp; /* Byte 9 */ - tmp = (sd_status[9] & 0xFF); + tmp = (sd_status[2] & 0xFF00) >> 8; pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp; /* Byte 10 */ - tmp = (sd_status[10] & 0xF0) >> 4; + tmp = (sd_status[2] & 0xF00000) >> 20; pCardStatus->AU_SIZE = (uint8_t)tmp; /* Byte 11 */ - tmp = (sd_status[11] & 0xFF); - pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8); + tmp = (sd_status[2] & 0xFF000000) >> 24; + pCardStatus->ERASE_SIZE = (uint16_t)(tmp << 8); /* Byte 12 */ - tmp = (sd_status[12] & 0xFF); - pCardStatus->ERASE_SIZE |= (uint8_t)tmp; + tmp = (sd_status[3] & 0xFF); + pCardStatus->ERASE_SIZE |= (uint16_t)tmp; /* Byte 13 */ - tmp = (sd_status[13] & 0xFC) >> 2; + tmp = (sd_status[3] & 0xFC00) >> 10; pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp; /* Byte 13 */ - tmp = (sd_status[13] & 0x3); + tmp = (sd_status[3] & 0x0300) >> 8; pCardStatus->ERASE_OFFSET = (uint8_t)tmp; return errorstate; diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_spi.c b/stmhal/hal/f7/src/stm32f7xx_hal_spi.c index 999877937f..4bb5a48472 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_spi.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spi.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -11,6 +11,7 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State functions + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -21,7 +22,7 @@ (#) Declare a SPI_HandleTypeDef handle structure, for example: SPI_HandleTypeDef hspi; - (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: (##) Enable the SPIx interface clock (##) SPI pins configuration (+++) Enable the clock for the SPI GPIOs @@ -30,19 +31,19 @@ (+++) Configure the SPIx interrupt priority (+++) Enable the NVIC SPI IRQ handle (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel (+++) Enable the DMAx clock (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel + (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customised HAL_SPI_MspInit() API. + by calling the customized HAL_SPI_MspInit() API. [..] Circular mode restriction: (#) The DMA circular mode cannot be used when the SPI is configured in these modes: @@ -51,12 +52,72 @@ (#) The CRC feature is not managed when the DMA circular mode is enabled (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,15 +162,15 @@ /** @defgroup SPI_Private_Constants SPI Private Constants * @{ */ -#define SPI_DEFAULT_TIMEOUT 50 +#define SPI_DEFAULT_TIMEOUT 100U /** * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SPI_Private_Functions +/** @defgroup SPI_Private_Functions SPI Private Functions * @{ */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -119,31 +180,39 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout); -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart); static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); -static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); /** * @} */ -/* Exported functions ---------------------------------------------------------*/ - +/* Exported functions --------------------------------------------------------*/ /** @defgroup SPI_Exported_Functions SPI Exported Functions * @{ */ @@ -184,8 +253,8 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ */ /** - * @brief Initializes the SPI according to the specified parameters - * in the SPI_InitTypeDef and create the associated handle. + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status @@ -195,7 +264,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) uint32_t frxth; /* Check the SPI handle allocation */ - if(hspi == NULL) + if (hspi == NULL) { return HAL_ERROR; } @@ -205,18 +274,28 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) assert_param(IS_SPI_MODE(hspi->Init.Mode)); assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); - assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); - assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); - assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ - if(hspi->State == HAL_SPI_STATE_RESET) + if (hspi->State == HAL_SPI_STATE_RESET) { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; @@ -231,7 +310,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Align by default the rs fifo threshold on the data size */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { frxth = SPI_RXFIFO_THRESHOLD_HF; } @@ -241,17 +320,17 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } /* CRC calculation is valid only for 16Bit and 8 Bit */ - if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT )) + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; } /* Align the CRC Length on the data size */ - if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) { /* CRC Length aligned on the data size : value set by default */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; } @@ -261,35 +340,46 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } } - /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/ + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, - Communication speed, First bit, CRC calculation state, CRC Length */ - hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); - - if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + Communication speed, First bit, CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); +#if (USE_SPI_CRC != 0U) + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - hspi->Instance->CR1|= SPI_CR1_CRCL; + hspi->Instance->CR1 |= SPI_CR1_CRCL; } +#endif /* USE_SPI_CRC */ - /* Configure : NSS management */ - /* Configure : Rx Fifo Threshold */ - hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | - hspi->Init.DataSize ) | frxth; + /* Configure : NSS management, TI Mode and Rx Fifo Threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | + hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); - /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ - hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State= HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; return HAL_OK; } /** - * @brief DeInitializes the SPI peripheral + * @brief De-Initialize the SPI peripheral. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status @@ -297,21 +387,16 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) { /* Check the SPI handle allocation */ - if(hspi == NULL) + if (hspi == NULL) { return HAL_ERROR; } - /* Check the parameters */ + /* Check SPI Instance parameter */ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); hspi->State = HAL_SPI_STATE_BUSY; - /* check flag before the SPI disable */ - SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT); - SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT); - SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT); - /* Disable the SPI Peripheral Clock */ __HAL_SPI_DISABLE(hspi); @@ -321,32 +406,39 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(hspi); return HAL_OK; } /** - * @brief SPI MSP Init + * @brief Initialize the SPI MSP. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) - { - /* NOTE : This function should not be modified, when the callback is needed, +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_MspInit should be implemented in the user file */ } /** - * @brief SPI MSP DeInit + * @brief De-Initialize the SPI MSP. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_MspDeInit should be implemented in the user file */ @@ -363,6 +455,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) ============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the SPI data transfers. @@ -373,13 +466,13 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) The HAL status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) exist for 1Line (simplex) and 2Lines (full duplex) modes. @@ -389,7 +482,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) */ /** - * @brief Transmit an amount of data in blocking mode + * @brief Transmit an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -399,142 +492,155 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); - if(hspi->State != HAL_SPI_STATE_READY) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) { - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_BUSY; + errorcode = HAL_BUSY; + goto error; } - if((pData == NULL ) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_ERROR; + errorcode = HAL_ERROR; + goto error; } /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; + hspi->pTxBuffPtr = (uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_TX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Transmit data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Transmit data in 16 Bit mode */ - while (hspi->TxXferCount > 0) + while (hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ - if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + hspi->Instance->DR = *((uint16_t *)pData); + pData += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; + } } - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; } } /* Transmit data in 8 Bit mode */ else { - while (hspi->TxXferCount > 0) + while (hspi->TxXferCount > 0U) { - if(hspi->TxXferCount != 0x1) + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + if (hspi->TxXferCount > 1U) { - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)pData); + pData += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++); + hspi->TxXferCount--; } - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; } else { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + /* Timeout management */ + if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) { - return HAL_TIMEOUT; + errorcode = HAL_TIMEOUT; + goto error; } - *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; } } } - +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1|= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } +error: + hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; - } - else - { - return HAL_OK; - } + return errorcode; } /** - * @brief Receive an amount of data in blocking mode + * @brief Receive an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -544,47 +650,63 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg; +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + uint32_t tickstart = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; - if(hspi->State != HAL_SPI_STATE_READY) + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { - return HAL_BUSY; - } - - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the transmitReceive process */ - return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } /* Process Locked */ __HAL_LOCK(hspi); + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; + hspi->pRxBuffPtr = (uint8_t *)pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); /* this is done to handle the CRCNEXT before the latest data */ hspi->RxXferCount--; } +#endif /* USE_SPI_CRC */ - /* Set the Rx Fido threshold */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + /* Set the Rx Fifo threshold */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -595,139 +717,160 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - /* Configure communication direction 1Line and enabled SPI if needed */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_RX(hspi); } /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) { - while(hspi->RxXferCount > 1) + /* Transfer loop */ + while (hspi->RxXferCount > 0U) { - /* Wait until the RXNE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { - return HAL_TIMEOUT; + /* read the received data */ + (*pData) = *(__IO uint8_t *)&hspi->Instance->DR; + pData += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; + } } - (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR; - hspi->RxXferCount--; } } - else /* Receive data in 16 Bit mode */ - { - while(hspi->RxXferCount > 1 ) - { - /* Wait until RXNE flag is reset to read data */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - } - } - - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; - } - - /* Wait until RXNE flag is set */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Receive last data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - } - /* Receive last data in 8 Bit mode */ else { - (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; - } - hspi->RxXferCount--; - - /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + /* Transfer loop */ + while (hspi->RxXferCount > 0U) { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + *((uint16_t *)pData) = hspi->Instance->DR; + pData += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } } - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + } + +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + + /* Read the latest data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* the latest data has not been received */ + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Receive last data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + *((uint16_t *)pData) = hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + (*pData) = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Read CRC to Flush DR and RXNE flag */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); - if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } +#endif /* USE_SPI_CRC */ /* Check the end of the transaction */ - if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK) + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - hspi->State = HAL_SPI_STATE_READY; - +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_ERROR; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; } - /* Process Unlocked */ +error : + hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; - } - else - { - return HAL_OK; - } + return errorcode; } /** - * @brief Transmit and Receive an amount of data in blocking mode + * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer @@ -736,44 +879,72 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout) { - __IO uint16_t tmpreg = 0; - uint32_t tickstart = HAL_GetTick(); + uint32_t tmp = 0U, tmp1 = 0U; +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + uint32_t tickstart = 0U; + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + HAL_StatusTypeDef errorcode = HAL_OK; + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - if(hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ __HAL_LOCK(hspi); - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + + if (!((tmp == HAL_SPI_STATE_READY) || \ + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pRxData; + hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = pTxData; + hspi->pTxBuffPtr = (uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ - /* Set the Rx Fido threshold */ - if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) { /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -785,85 +956,113 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Transmit and Receive data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ - if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) + if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ } /* Check RXNE flag */ - if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) + if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) { - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); + *((uint16_t *)pRxData) = hspi->Instance->DR; + pRxData += sizeof(uint16_t); hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; } - if(Timeout != HAL_MAX_DELAY) + if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hspi->State = HAL_SPI_STATE_READY; - __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; - } + errorcode = HAL_TIMEOUT; + goto error; } } } /* Transmit and Receive data in 8 Bit mode */ else { - while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*pTxData); + pTxData += sizeof(uint8_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* check TXE flag */ - if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) + if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { - if(hspi->TxXferCount > 1) + if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); hspi->TxXferCount--; } + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ } /* Wait until RXNE flag is reset */ - if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) + if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) { - if(hspi->RxXferCount > 1) + if (hspi->RxXferCount > 1U) { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2; - if(hspi->RxXferCount <= 1) + *((uint16_t *)pRxData) = hspi->Instance->DR; + pRxData += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount <= 1U) { /* set fiforxthreshold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -871,91 +1070,91 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } else { - (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; + (*pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR; hspi->RxXferCount--; } + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; } - if(Timeout != HAL_MAX_DELAY) + if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hspi->State = HAL_SPI_STATE_READY; - __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; - } + errorcode = HAL_TIMEOUT; + goto error; } } } +#if (USE_SPI_CRC != 0U) /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; } - - if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + /* Read CRC */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); - if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } - /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hspi->State = HAL_SPI_STATE_READY; - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + errorcode = HAL_ERROR; + } +#endif /* USE_SPI_CRC */ - return HAL_ERROR; + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - /* Process Unlocked */ + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error : + hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; - } - else - { - return HAL_OK; - } + return errorcode; } /** - * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -964,78 +1163,81 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - if(hspi->State == HAL_SPI_STATE_READY) + /* Process Locked */ + __HAL_LOCK(hspi); + + if ((pData == NULL) || (Size == 0U)) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } + errorcode = HAL_ERROR; + goto error; + } - /* Process Locked */ - __HAL_LOCK(hspi); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; - /* Set the function for IT treatement */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - hspi->RxISR = NULL; - hspi->TxISR = SPI_TxISR_16BIT; - } - else - { - hspi->RxISR = NULL; - hspi->TxISR = SPI_TxISR_8BIT; - } + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Note : The SPI must be enabled after unlocking current process - to avoid the risk of SPI interrupt handle execution before current - process unlock */ - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; } else { - return HAL_BUSY; + hspi->TxISR = SPI_TxISR_8BIT; } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Receive an amount of data in no-blocking mode with Interrupt + * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -1044,103 +1246,102 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - if(hspi->State == HAL_SPI_STATE_READY) + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } - /* Process Locked */ - __HAL_LOCK(hspi); + /* Process Locked */ + __HAL_LOCK(hspi); - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* the receive process is not supported in 2Lines direction master mode */ - /* in this we call the transmitReceive process */ - return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); - } + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1; - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2; - } - } - else - { - hspi->CRCSize = 0; - } + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; - /* check the data size to adapt Rx threshold and the set the function for IT treatment */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - /* set fiforxthreshold according the reception data length: 16 bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_RxISR_16BIT; - hspi->TxISR = NULL; - } - else - { - /* set fiforxthreshold according the reception data length: 8 bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_RxISR_8BIT; - hspi->TxISR = NULL; - } + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Note : The SPI must be enabled after unlocking current process - to avoid the risk of SPI interrupt handle execution before current - process unlock */ - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; + /* check the data size to adapt Rx threshold and the set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* set fiforxthreshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_16BIT; } else { - return HAL_BUSY; + /* set fiforxthreshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_8BIT; } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } + SPI_RESET_CRC(hspi); + } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer @@ -1150,95 +1351,105 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { + uint32_t tmp = 0U, tmp1 = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - if((hspi->State == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + /* Process locked */ + __HAL_LOCK(hspi); + + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + + if (!((tmp == HAL_SPI_STATE_READY) || \ + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } + errorcode = HAL_BUSY; + goto error; + } - /* Process locked */ - __HAL_LOCK(hspi); + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - hspi->CRCSize = 0; - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1; - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2; - } - } + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Set the function for IT treatement */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - hspi->RxISR = SPI_2linesRxISR_16BIT; - hspi->TxISR = SPI_2linesTxISR_16BIT; - } - else - { - hspi->RxISR = SPI_2linesRxISR_8BIT; - hspi->TxISR = SPI_2linesTxISR_8BIT; - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - /* check if packing mode is enabled and if there is more than 2 data to receive */ - if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) - { - /* set fiforxthreshold according the reception data length: 16 bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* set fiforxthreshold according the reception data length: 8 bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; } else { - return HAL_BUSY; + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } + SPI_RESET_CRC(hspi); + } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ + + /* check if packing mode is enabled and if there is more than 2 data to receive */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) + { + /* set fiforxthreshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* set fiforxthreshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit an amount of data in no-blocking mode with DMA + * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -1247,41 +1458,53 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - if(hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hspi); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; + hspi->pTxBuffPtr = (uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_TX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ /* Set the SPI TxDMA Half transfer complete callback */ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; @@ -1292,105 +1515,120 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Set the DMA error callback */ hspi->hdmatx->XferErrorCallback = SPI_DMAError; + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); /* packing mode is enabled only if the DMA setting is HALWORD */ - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Check the even/odd of the data size + crc if enabled */ - if((hspi->TxXferCount & 0x1) == 0) + if ((hspi->TxXferCount & 0x1U) == 0U) { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1); + hspi->TxXferCount = (hspi->TxXferCount >> 1U); } else { SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; } } - /* Enable the Tx DMA channel */ + /* Enable the Tx DMA Stream/Channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - /* Enable Tx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : /* Process Unlocked */ __HAL_UNLOCK(hspi); - - return HAL_OK; + return errorcode; } /** -* @brief Receive an amount of data in no-blocking mode with DMA -* @param hspi: SPI handle -* @param pData: pointer to data buffer -* @param Size: amount of data to be sent -* @retval HAL status -*/ + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size: amount of data to be sent + * @retval HAL status + */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - if(hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } + HAL_StatusTypeDef errorcode = HAL_OK; - if((pData == NULL) || (Size == 0)) + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { - return HAL_ERROR; + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); } /* Process Locked */ __HAL_LOCK(hspi); - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + if (hspi->State != HAL_SPI_STATE_READY) { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the transmitReceive process */ - return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size); + errorcode = HAL_BUSY; + goto error; } + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_RX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ /* packing mode management is enabled by the DMA settings */ - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { - /* Process Locked */ - __HAL_UNLOCK(hspi); /* Restriction the DMA data received is not allowed in this mode */ - return HAL_ERROR; + errorcode = HAL_ERROR; + goto error; } CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -1410,180 +1648,498 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; - /* Enable Rx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; - /* Enable the Rx DMA channel */ + /* Enable the Rx DMA Stream/Channel */ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - return HAL_OK; + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + +error: + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer * @param pRxData: pointer to reception data buffer - * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 * @param Size: amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { + uint32_t tmp = 0U, tmp1 = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - if((hspi->State == HAL_SPI_STATE_READY) || - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + /* Process locked */ + __HAL_LOCK(hspi); + + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + if (!((tmp == HAL_SPI_STATE_READY) || + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } + errorcode = HAL_BUSY; + goto error; + } - /* Process locked */ - __HAL_LOCK(hspi); + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /* check if the transmit Receive function is not called by a receive master */ - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; - /* Reset CRC Calculation + increase the rxsize */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; - /* Reset the threshold bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ - /* the packing mode management is enabled by the DMA settings according the spi data size */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* set fiforxthreshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + /* Reset the threshold bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); - if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - if((hspi->TxXferSize & 0x1) == 0x0 ) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = hspi->TxXferCount >> 1; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; - } - } - - if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - /* set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - /* Size must include the CRC length */ - if((hspi->RxXferCount & 0x1) == 0x0 ) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = hspi->RxXferCount >> 1; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; - } - } - } - - /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is - the reception request (RXNE) */ - if(hspi->State == HAL_SPI_STATE_BUSY_RX) - { - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - } - else - { - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; - } - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Enable Rx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; - - /* Enable the Rx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); - - /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing - is performed in DMA reception complete callback */ - hspi->hdmatx->XferHalfCpltCallback = NULL; - hspi->hdmatx->XferCpltCallback = NULL; - - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) - { - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - } - else - { - hspi->hdmatx->XferErrorCallback = NULL; - } - - /* Enable the Tx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Enable Tx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; - - return HAL_OK; + /* the packing mode management is enabled by the DMA settings according the spi data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - return HAL_BUSY; + /* set fiforxthreshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + if ((hspi->TxXferSize & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = hspi->TxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Pauses the DMA Transfer. + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + + /* Initialized local variable */ + errorcode = HAL_OK; + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + while (hspi->State != HAL_SPI_STATE_ABORT); + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + while (hspi->State != HAL_SPI_STATE_ABORT); + } + + /* Clear ERRIE interrupts in case of DMA Mode */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */ + if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + while (hspi->State != HAL_SPI_STATE_ABORT); + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + while (hspi->State != HAL_SPI_STATE_ABORT); + } + + /* Clear ERRIE interrupts in case of DMA Mode */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status @@ -1603,7 +2159,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) } /** - * @brief Resumes the DMA Transfer. + * @brief Resume the DMA Transfer. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status @@ -1623,7 +2179,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) } /** - * @brief Stops the DMA Transfer. + * @brief Stop the DMA Transfer. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status @@ -1636,13 +2192,13 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() */ - /* Abort the SPI DMA tx Stream */ - if(hspi->hdmatx != NULL) + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) { HAL_DMA_Abort(hspi->hdmatx); } - /* Abort the SPI DMA rx Stream */ - if(hspi->hdmarx != NULL) + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) { HAL_DMA_Abort(hspi->hdmarx); } @@ -1654,153 +2210,208 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) } /** - * @brief This function handles SPI interrupt request. + * @brief Handle SPI interrupt request. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + /* SPI in mode Receiver ----------------------------------------------------*/ - if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) && - (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET)) + if (((itflag & SPI_FLAG_OVR) == RESET) && + ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) { hspi->RxISR(hspi); return; } - /* SPI in mode Transmitter ---------------------------------------------------*/ - if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET)) + /* SPI in mode Transmitter -------------------------------------------------*/ + if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) { hspi->TxISR(hspi); return; } - /* SPI in ERROR Treatment ---------------------------------------------------*/ - if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) + /* SPI in Error Treatment --------------------------------------------------*/ + if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET)) { - /* SPI Overrun error interrupt occurred -------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if ((itflag & SPI_FLAG_OVR) != RESET) { - if(hspi->State != HAL_SPI_STATE_BUSY_TX) + if (hspi->State != HAL_SPI_STATE_BUSY_TX) { - hspi->ErrorCode |= HAL_SPI_ERROR_OVR; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); __HAL_SPI_CLEAR_OVRFLAG(hspi); } else { + __HAL_SPI_CLEAR_OVRFLAG(hspi); return; } } - /* SPI Mode Fault error interrupt occurred -------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((itflag & SPI_FLAG_MODF) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_MODF; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); __HAL_SPI_CLEAR_MODFFLAG(hspi); } - /* SPI Frame error interrupt occurred ----------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((itflag & SPI_FLAG_FRE) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_FRE; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); __HAL_SPI_CLEAR_FREFLAG(hspi); } - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_ErrorCallback(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + HAL_DMA_Abort_IT(hspi->hdmarx); + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + HAL_DMA_Abort_IT(hspi->hdmatx); + } + } + else + { + /* Call user error callback */ + HAL_SPI_ErrorCallback(hspi); + } + } return; } } /** - * @brief Tx Transfer completed callback + * @brief Tx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_TxCpltCallback should be implemented in the user file */ } /** - * @brief Rx Transfer completed callbacks + * @brief Rx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_RxCpltCallback should be implemented in the user file */ } /** - * @brief Tx and Rx Transfer completed callback + * @brief Tx and Rx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_TxRxCpltCallback should be implemented in the user file */ } /** - * @brief Tx Half Transfer completed callback + * @brief Tx Half Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_TxHalfCpltCallback should be implemented in the user file */ } /** - * @brief Rx Half Transfer completed callback + * @brief Rx Half Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file */ } /** - * @brief Tx and Rx Half Transfer callback + * @brief Tx and Rx Half Transfer callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file */ } /** - * @brief SPI error callback + * @brief SPI error callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_ErrorCallback should be implemented in the user file */ @@ -1810,15 +2421,26 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @} + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} /** * @} */ /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SPI control functions + * @brief SPI control functions * @verbatim =============================================================================== @@ -1833,24 +2455,26 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) */ /** - * @brief Return the SPI state + * @brief Return the SPI handle state. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) { + /* Return SPI handle state */ return hspi->State; } /** - * @brief Return the SPI error code + * @brief Return the SPI error code. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) { + /* Return SPI ErrorCode */ return hspi->ErrorCode; } @@ -1862,36 +2486,50 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) * @} */ -/** @defgroup SPI_Private_Functions SPI Private Functions +/** @addtogroup SPI_Private_Functions + * @brief Private functions * @{ */ /** - * @brief DMA SPI transmit process complete callback + * @brief DMA SPI transmit process complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t tickstart = 0U; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); /* DMA Normal Mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + /* Disable Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - hspi->TxXferCount = 0; + hspi->TxXferCount = 0U; hspi->State = HAL_SPI_STATE_READY; - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); return; @@ -1901,215 +2539,380 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI receive process complete callback + * @brief DMA SPI receive process complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - __IO uint16_t tmpreg; - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t tickstart = 0U; +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ - /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + /* Read CRC */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); - if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } +#endif /* USE_SPI_CRC */ - /* Disable Rx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); /* Check the end of the transaction */ - SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } - hspi->RxXferCount = 0; + hspi->RxXferCount = 0U; hspi->State = HAL_SPI_STATE_READY; +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_RxCpltCallback(hspi); } - else +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - HAL_SPI_RxCpltCallback(hspi); - } - else - { - HAL_SPI_ErrorCallback(hspi); - } + HAL_SPI_ErrorCallback(hspi); + return; } } - else - { - HAL_SPI_RxCpltCallback(hspi); - } + HAL_SPI_RxCpltCallback(hspi); } /** - * @brief DMA SPI transmit receive process complete callback - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - __IO int16_t tmpreg; - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t tickstart = 0U; +#if (USE_SPI_CRC != 0U) + __IO int16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) { - if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* To avoid GCC warning */ + UNUSED(tmpreg); } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - else - { - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) + else { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ + UNUSED(tmpreg); } - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ } - } +#endif /* USE_SPI_CRC */ - /* Check the end of the transaction */ - SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT); - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Disable Rx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode = HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_ErrorCallback(hspi); - } - else - { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { - HAL_SPI_TxRxCpltCallback(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } - else + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); + return; } } + HAL_SPI_TxRxCpltCallback(hspi); } /** - * @brief DMA SPI half transmit process complete callback - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI half transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; HAL_SPI_TxHalfCpltCallback(hspi); } /** - * @brief DMA SPI half receive process complete callback + * @brief DMA SPI half receive process complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; HAL_SPI_RxHalfCpltCallback(hspi); } /** - * @brief DMA SPI Half transmit receive process complete callback - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; HAL_SPI_TxRxHalfCpltCallback(hspi); } /** - * @brief DMA SPI communication error callback - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI communication error callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - hspi->ErrorCode|= HAL_SPI_ERROR_DMA; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); hspi->State = HAL_SPI_STATE_READY; HAL_SPI_ErrorCallback(hspi); } /** - * @brief Rx Handler for Transmit and Receive in Interrupt mode + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2117,12 +2920,12 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { /* Receive data in packing mode */ - if(hspi->RxXferCount > 1) + if (hspi->RxXferCount > 1U) { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2; - if(hspi->RxXferCount == 1) + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount == 1U) { /* set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -2136,55 +2939,62 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /* check end of the reception */ - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_2linesRxISR_8BITCRC; return; } +#endif /* USE_SPI_CRC */ - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } } } +#if (USE_SPI_CRC != 0U) /** - * @brief Rx Handler for Transmit and Receive in Interrupt mode + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg; + __IO uint8_t tmpreg = 0U; + /* Read data register to flush CRC */ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); - UNUSED(tmpreg); /* To avoid GCC warning */ + + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->CRCSize--; /* check end of the reception */ - if(hspi->CRCSize == 0) + if (hspi->CRCSize == 0U) { - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } } } +#endif /* USE_SPI_CRC */ /** - * @brief Tx Handler for Transmit and Receive in Interrupt mode + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2192,11 +3002,11 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in packing Bit mode */ - if(hspi->TxXferCount >= 2) + if (hspi->TxXferCount >= 2U) { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; + hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else @@ -2206,16 +3016,23 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /* check the end of the transmission */ - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; } +#endif /* USE_SPI_CRC */ + /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } @@ -2223,7 +3040,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2231,30 +3048,33 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Receive data in 16 Bit mode */ - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_2linesRxISR_16BITCRC; return; } +#endif /* USE_SPI_CRC */ /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } } } +#if (USE_SPI_CRC != 0U) /** - * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2262,17 +3082,23 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { /* Receive data in 16 Bit mode */ - __IO uint16_t tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + __IO uint16_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = hspi->Instance->DR; + + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); SPI_CloseRxTx_ISR(hspi); } +#endif /* USE_SPI_CRC */ /** - * @brief Tx Handler for Transmit and Receive in Interrupt mode + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2285,44 +3111,57 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) hspi->TxXferCount--; /* Enable CRC Transmission */ - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; } +#endif /* USE_SPI_CRC */ + /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } } } +#if (USE_SPI_CRC != 0U) /** - * @brief Manage the CRC receive in Interrupt context + * @brief Manage the CRC 8-bit receive in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg; - tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); - UNUSED(tmpreg); /* To avoid GCC warning */ + __IO uint8_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->CRCSize--; - if(hspi->CRCSize == 0) + if (hspi->CRCSize == 0U) { SPI_CloseRx_ISR(hspi); } } +#endif /* USE_SPI_CRC */ /** - * @brief Manage the receive in Interrupt context + * @brief Manage the receive 8-bit in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2332,44 +3171,53 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); hspi->RxXferCount--; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_RxISR_8BITCRC; return; } +#endif /* USE_SPI_CRC */ SPI_CloseRx_ISR(hspi); } } +#if (USE_SPI_CRC != 0U) /** - * @brief Manage the CRC 16bit receive in Interrupt context + * @brief Manage the CRC 16-bit receive in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint16_t tmpreg; + __IO uint16_t tmpreg = 0U; + /* Read data register to flush CRC */ tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ + + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); SPI_CloseRx_ISR(hspi); } +#endif /* USE_SPI_CRC */ /** - * @brief Manage the 16Bit receive in Interrupt context + * @brief Manage the 16-bit receive in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2380,25 +3228,29 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_RxISR_16BITCRC; return; } +#endif /* USE_SPI_CRC */ SPI_CloseRx_ISR(hspi); } } /** - * @brief Handle the data 8Bit transmit in Interrupt mode + * @brief Handle the data 8-bit transmit in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2408,19 +3260,21 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Enable CRC Transmission */ - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ SPI_CloseTx_ISR(hspi); } } /** - * @brief Handle the data 16Bit transmit in Interrupt mode + * @brief Handle the data 16-bit transmit in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2432,35 +3286,37 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Enable CRC Transmission */ - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ SPI_CloseTx_ISR(hspi); } } /** - * @brief This function handles SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Flag : SPI flag to check - * @param State : flag state to check - * @param Timeout : Timeout duration + * @brief Handle SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param State: flag state to check + * @param Timeout: Timeout duration + * @param Tickstart: tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout) +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = HAL_GetTick(); - - while((hspi->Instance->SR & Flag) != State) + while ((hspi->Instance->SR & Flag) != State) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -2469,72 +3325,15 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - hspi->State= HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @brief This function handles SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Fifo : Fifo to check - * @param State : Fifo state to check - * @param Timeout : Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout) -{ - __IO uint8_t tmpreg; - uint32_t tickstart = HAL_GetTick(); - - while((hspi->Instance->SR & Fifo) != State) - { - if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) - { - tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); - UNUSED(tmpreg); /* To avoid GCC warning */ - } - - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -2553,90 +3352,176 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, } /** - * @brief This function handles the check of the RX transaction complete. + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Fifo: Fifo to check + * @param State: Fifo state to check + * @param Timeout: Timeout duration + * @param Tickstart: tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint8_t tmpreg; + + while ((hspi->Instance->SR & Fifo) != State) + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + { + tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0) || ((HAL_GetTick() - Tickstart) >= Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle the check of the RX transaction complete. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout : Timeout duration - * @retval None + * @param Timeout: Timeout duration + * @param Tickstart: tick start value + * @retval None. */ -static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - return HAL_TIMEOUT; - } - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } return HAL_OK; } /** - * @brief This function handles the check of the RXTX or TX transaction complete. + * @brief Handle the check of the RXTX or TX transaction complete. * @param hspi: SPI handle - * @param Timeout : Timeout duration + * @param Timeout: Timeout duration + * @param Tickstart: tick start value */ -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { - /* Procedure to check the transaction complete */ - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK) + /* Control if the TX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } return HAL_OK; } /** - * @brief This function handles the close of the RXTX transaction. + * @brief Handle the end of the RXTX transaction. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { + uint32_t tickstart = 0U; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->State = HAL_SPI_STATE_READY; - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); HAL_SPI_ErrorCallback(hspi); } else { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) { - if(hspi->State == HAL_SPI_STATE_BUSY_RX) + if (hspi->State == HAL_SPI_STATE_BUSY_RX) { - hspi->State = HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; HAL_SPI_RxCpltCallback(hspi); } else { - hspi->State = HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; HAL_SPI_TxRxCpltCallback(hspi); } } @@ -2645,64 +3530,83 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_READY; HAL_SPI_ErrorCallback(hspi); } +#if (USE_SPI_CRC != 0U) } +#endif /* USE_SPI_CRC */ } /** - * @brief This function handles the close of the RX transaction. + * @brief Handle the end of the RX transaction. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) { - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Check the end of the transaction */ - SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + hspi->State = HAL_SPI_STATE_READY; - hspi->State = HAL_SPI_STATE_READY; - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_ErrorCallback(hspi); + HAL_SPI_RxCpltCallback(hspi); } else { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - HAL_SPI_RxCpltCallback(hspi); - } - else - { - HAL_SPI_ErrorCallback(hspi); - } + HAL_SPI_ErrorCallback(hspi); } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ } /** - * @brief This function handles the close of the TX transaction. + * @brief Handle the end of the TX transaction. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) { + uint32_t tickstart = 0U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Disable TXE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } hspi->State = HAL_SPI_STATE_READY; - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); } @@ -2712,11 +3616,73 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) } } +/** + * @brief Handle abort a Rx transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + hspi->State = HAL_SPI_STATE_ABORT; +} + /** * @} */ #endif /* HAL_SPI_MODULE_ENABLED */ + /** * @} */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_tim.c b/stmhal/hal/f7/src/stm32f7xx_hal_tim.c index 147cd670fb..3a6d7a9c98 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_tim.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -58,10 +58,10 @@ (++) Encoder mode output : HAL_TIM_Encoder_MspInit() (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); + __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the @@ -98,7 +98,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -265,6 +265,9 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ @@ -278,6 +281,9 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_Base_MspDeInit could be implemented in the user file */ @@ -544,6 +550,9 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ @@ -557,6 +566,9 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_OC_MspDeInit could be implemented in the user file */ @@ -1053,6 +1065,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ @@ -1066,6 +1081,9 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_PWM_MspDeInit could be implemented in the user file */ @@ -1144,7 +1162,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @brief Starts the PWM signal generation in interrupt mode. * @param htim: pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1565,6 +1583,9 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ @@ -1578,6 +1599,9 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_IC_MspDeInit could be implemented in the user file */ @@ -2050,6 +2074,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ @@ -2063,6 +2090,9 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file */ @@ -2366,6 +2396,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspInit could be implemented in the user file */ @@ -2379,6 +2412,9 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspDeInit could be implemented in the user file */ @@ -2948,9 +2984,6 @@ __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); /* Check input state */ __HAL_LOCK(htim); @@ -3120,9 +3153,6 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); htim->State = HAL_TIM_STATE_BUSY; @@ -3938,9 +3968,6 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; @@ -3961,6 +3988,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ETRMODE1: { assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -3980,6 +4010,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ETRMODE2: { assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -3993,6 +4027,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_TI1: { assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -4002,6 +4041,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_TI2: { assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + TIM_TI2_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -4011,6 +4055,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_TI1ED: { assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -4374,6 +4422,9 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ @@ -4387,6 +4438,9 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ @@ -4399,6 +4453,9 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_IC_CaptureCallback could be implemented in the user file */ @@ -4412,6 +4469,9 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ @@ -4425,6 +4485,9 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ @@ -4438,6 +4501,9 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ @@ -4793,8 +4859,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; @@ -4861,8 +4925,6 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c index 0252db920f..131d4a6fe2 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -42,10 +42,10 @@ (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); + __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the @@ -72,7 +72,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -266,6 +266,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file */ @@ -279,6 +282,9 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file */ @@ -1634,7 +1640,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) @@ -1643,9 +1648,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); /* Check input state */ __HAL_LOCK(htim); @@ -1738,7 +1740,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, @@ -1749,10 +1750,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); /* Check input state */ __HAL_LOCK(htim); @@ -1906,6 +1904,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { case TIM_CLEARINPUTSOURCE_NONE: { + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + /* Clear the OCREF clear selection bit */ tmpsmcr &= ~TIM_SMCR_OCCS; @@ -2162,6 +2163,92 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, return HAL_OK; } +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +/** + * @brief Configures the break input source. + * @param htim: TIM handle. + * @param BreakInput: Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig: Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + +{ + uint32_t tmporx = 0; + uint32_t bkin_enable_mask = 0; + uint32_t bkin_enable_bitpos = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + + /* Check input state */ + __HAL_LOCK(htim); + + switch(sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = 0; + } + break; + + case TIM_BREAKINPUTSOURCE_DFSDM1: + { + bkin_enable_mask = TIM1_AF1_BKDF1BKE; + bkin_enable_bitpos = 8; + } + break; + + default: + break; + } + + switch(BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + } + break; + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + } + break; + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. @@ -2265,6 +2352,9 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRe */ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_CommutationCallback could be implemented in the user file */ @@ -2278,6 +2368,9 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_uart.c b/stmhal/hal/f7/src/stm32f7xx_hal_uart.c index 3f3b06f539..060659414a 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_uart.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -126,7 +126,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -164,25 +164,41 @@ * @brief HAL UART module driver * @{ */ + #ifdef HAL_UART_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define HAL_UART_TXDMA_TIMEOUTVALUE 22000 +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); -/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions * @{ @@ -243,7 +259,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) assert_param(IS_UART_INSTANCE(huart->Instance)); } - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; @@ -252,7 +268,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -271,13 +287,13 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -295,15 +311,16 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) return HAL_ERROR; } - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -322,28 +339,28 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - huart->Instance->CR3 |= USART_CR3_HDSEL; + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } /** - * @brief Initializes the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: uart handle + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart: UART handle. * @param BreakDetectLength: specifies the LIN break detection length. * This parameter can be one of the following values: - * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection - * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) @@ -359,15 +376,16 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength)); - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -386,33 +404,32 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN); + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - huart->Instance->CR2 |= USART_CR2_LINEN; + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - /* Enable the Peripheral */ + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } - /** - * @brief Initializes the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle - * @param Address: UART node address (4-, 6-, 7- or 8-bit long) + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart: UART handle. + * @param Address: UART node address (4-, 6-, 7- or 8-bit long). * @param WakeUpMethod: specifies the UART wakeup method. * This parameter can be one of the following values: - * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection - * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark * @note If the user resorts to idle line detection wake up, the Address parameter * is useless and ignored by the initialization function. * @note If the user resorts to address mark wake up, the address length detection @@ -431,15 +448,16 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -458,8 +476,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) { @@ -473,12 +491,93 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart: UART handle. + * @param Polarity: select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime: Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime: Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +{ + uint32_t temp = 0x0; + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if(huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} /** * @brief DeInitializes the UART peripheral @@ -496,20 +595,21 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - huart->Instance->CR1 = 0x0; - huart->Instance->CR2 = 0x0; - huart->Instance->CR3 = 0x0; + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State = HAL_UART_STATE_RESET; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(huart); @@ -522,8 +622,11 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @param huart: uart handle * @retval None */ - __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspInit can be implemented in the user file */ @@ -534,8 +637,11 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @param huart: uart handle * @retval None */ - __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspDeInit can be implemented in the user file */ @@ -546,7 +652,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) */ /** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit/Receive functions + * @brief UART Transmit/Receive functions * @verbatim =============================================================================== @@ -557,9 +663,9 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) (#) There are two mode of transfer: (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) No-Blocking mode: The communication is performed using Interrupts + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts or DMA, These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when @@ -579,14 +685,14 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) (+) UART_Transmit_IT() (+) UART_Receive_IT() - (#) No-Blocking mode API's with DMA are : + (#) Non-Blocking mode API's with DMA are : (+) HAL_UART_Transmit_DMA() (+) HAL_UART_Receive_DMA() (+) HAL_UART_DMAPause() (+) HAL_UART_DMAResume() (+) HAL_UART_DMAStop() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: (+) HAL_UART_TxHalfCpltCallback() (+) HAL_UART_TxCpltCallback() (+) HAL_UART_RxHalfCpltCallback() @@ -602,20 +708,22 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) */ /** - * @brief Send an amount of data in blocking mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout : Timeout duration + * @brief Send an amount of data in blocking mode. + * @param huart: UART handle. + * @param pData: Pointer to data buffer. + * @param Size: Amount of data to be sent. + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t* tmp; + uint32_t tickstart = 0U; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -624,49 +732,38 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); huart->TxXferSize = Size; huart->TxXferCount = Size; - while(huart->TxXferCount > 0) + while(huart->TxXferCount > 0U) { huart->TxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); pData += 2; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); + huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } } - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - /* Check if a non-blocking receive Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -680,21 +777,23 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u } /** - * @brief Receive an amount of data in blocking mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout : Timeout duration + * @brief Receive an amount of data in blocking mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; uint16_t uhMask; + uint32_t tickstart = 0U; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -703,15 +802,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); huart->RxXferSize = Size; huart->RxXferCount = Size; @@ -721,18 +815,18 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui uhMask = huart->Mask; /* as long as data have to be received */ - while(huart->RxXferCount > 0) + while(huart->RxXferCount > 0U) { huart->RxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData ; *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2; + pData +=2U; } else { @@ -740,15 +834,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } } - /* Check if a non-blocking transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -761,17 +849,18 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } /** - * @brief Send an amount of data in interrupt mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in interrupt mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -784,24 +873,13 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + huart->gState = HAL_UART_STATE_BUSY_TX; /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Transmit Data Register Empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); return HAL_OK; } @@ -812,17 +890,18 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData } /** - * @brief Receive an amount of data in interrupt mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in interrupt mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -838,27 +917,16 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, UART_MASK_COMPUTATION(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + huart->RxState = HAL_UART_STATE_BUSY_RX; /* Process Unlocked */ __HAL_UNLOCK(huart); - /* Enable the UART Data Register not empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART Parity Error and Data Register not empty Interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); return HAL_OK; } @@ -869,19 +937,20 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, } /** - * @brief Send an amount of data in DMA mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in DMA mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -894,15 +963,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat huart->TxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; @@ -913,6 +974,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + /* Enable the UART transmit DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size); @@ -920,13 +984,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC); + /* Process Unlocked */ + __HAL_UNLOCK(huart); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAT; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -937,21 +1000,22 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat } /** - * @brief Receive an amount of data in DMA mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in DMA mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) + * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -963,15 +1027,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData huart->RxXferSize = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; @@ -982,16 +1038,25 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAR; + /* Process Unlocked */ + __HAL_UNLOCK(huart); - /* Process Unlocked */ - __HAL_UNLOCK(huart); + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -1002,31 +1067,30 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData } /** - * @brief Pauses the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Pause the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - if(huart->State == HAL_UART_STATE_BUSY_TX) + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } /* Process Unlocked */ @@ -1036,42 +1100,35 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) } /** - * @brief Resumes the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Resume the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { - /* Clear the Overrun flag before resuming the Rx transfer*/ + /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Enable the UART DMA Rx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; - } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - - /* Enable the UART DMA Rx request before the DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; - - /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } /* If the UART peripheral is still not enabled, enable it */ - if ((huart->Instance->CR1 & USART_CR1_UE) == 0) + if ((huart->Instance->CR1 & USART_CR1_UE) == 0U) { /* Enable UART peripheral */ __HAL_UART_ENABLE(huart); @@ -1081,9 +1138,9 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) } /** - * @brief Stops the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Stop the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { @@ -1094,22 +1151,35 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of the stream and the corresponding call back is executed. */ - /* Disable the UART Tx/Rx DMA requests */ - huart->Instance->CR3 &= ~USART_CR3_DMAT; - huart->Instance->CR3 &= ~USART_CR3_DMAR; + /* Stop UART DMA Tx request if ongoing */ + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - /* Abort the UART DMA tx channel */ - if(huart->hdmatx != NULL) - { - HAL_DMA_Abort(huart->hdmatx); - } - /* Abort the UART DMA rx channel */ - if(huart->hdmarx != NULL) - { - HAL_DMA_Abort(huart->hdmarx); + /* Abort the UART DMA Tx channel */ + if(huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + + UART_EndTxTransfer(huart); } - huart->State = HAL_UART_STATE_READY; + /* Stop UART DMA Rx request if ongoing */ + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if(huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + + UART_EndRxTransfer(huart); + } return HAL_OK; } @@ -1121,144 +1191,175 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { - /* UART parity error interrupt occurred -------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) - { - __HAL_UART_CLEAR_PEFLAG(huart); + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags; - huart->ErrorCode |= HAL_UART_ERROR_PE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == RESET) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } } - /* UART frame error interrupt occurred --------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + /* If some errors occur */ + if( (errorflags != RESET) + && ( ((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) { - __HAL_UART_CLEAR_FEFLAG(huart); - huart->ErrorCode |= HAL_UART_ERROR_FE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } + /* UART parity error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); - /* UART noise error interrupt occurred --------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { - __HAL_UART_CLEAR_NEFLAG(huart); + huart->ErrorCode |= HAL_UART_ERROR_PE; + } - huart->ErrorCode |= HAL_UART_ERROR_NE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } + /* UART frame error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); - /* UART Over-Run interrupt occurred -----------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { - __HAL_UART_CLEAR_OREFLAG(huart); + huart->ErrorCode |= HAL_UART_ERROR_FE; + } - huart->ErrorCode |= HAL_UART_ERROR_ORE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } + /* UART noise error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); - /* Call UART Error Call back function if need be --------------------------*/ - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - HAL_UART_ErrorCallback(huart); - } + huart->ErrorCode |= HAL_UART_ERROR_NE; + } - /* UART in mode Receiver ---------------------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET)) - { - UART_Receive_IT(huart); - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if(((isrflags & USART_ISR_ORE) != RESET) && + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if(huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_UART_ErrorCallback(huart); + } + } + else + { + /* Call user error callback */ + HAL_UART_ErrorCallback(huart); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_UART_ErrorCallback(huart); + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ /* UART in mode Transmitter ------------------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET)) + if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { UART_Transmit_IT(huart); + return; } /* UART in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) + if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { UART_EndTransmit_IT(huart); + return; } } - /** * @brief This function handles UART Communication Timeout. - * @param huart: UART handle - * @param Flag: specifies the UART flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param huart UART handle + * @param Flag specifies the UART flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) + while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) { - while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout)) { - if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - huart->State= HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_UART_GET_FLAG(huart, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(huart); + return HAL_TIMEOUT; } } } return HAL_OK; } - - /** * @brief DMA UART transmit process complete callback * @param hdma: DMA handle @@ -1269,16 +1370,16 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode*/ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { - huart->TxXferCount = 0; + huart->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else @@ -1309,23 +1410,20 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { - huart->RxXferCount = 0; + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; } HAL_UART_RxCpltCallback(huart); } @@ -1350,10 +1448,37 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; - huart->TxXferCount = 0; - huart->State= HAL_UART_STATE_READY; - huart->ErrorCode |= HAL_UART_ERROR_DMA; + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + /* Stop UART DMA Tx request if ongoing */ + if ( (huart->gState == HAL_UART_STATE_BUSY_TX) + &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) + { + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) + &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) + { + UART_EndRxTransfer(huart); + } + SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA); + HAL_UART_ErrorCallback(huart); +} + +/** + * @brief DMA UART communication abort callback, when call by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma: DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + HAL_UART_ErrorCallback(huart); } @@ -1364,6 +1489,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback can be implemented in the user file */ @@ -1376,6 +1504,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback can be implemented in the user file */ @@ -1388,6 +1519,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file */ @@ -1400,6 +1534,9 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file */ @@ -1412,6 +1549,9 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file */ @@ -1428,34 +1568,17 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if(huart->TxXferCount == 0) + if(huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - /* Check if a receive Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State = HAL_UART_STATE_READY; - } - - /* Wait on TC flag to be able to start a second transfer */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - HAL_UART_TxCpltCallback(huart); + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); return HAL_OK; } @@ -1464,12 +1587,12 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + huart->pTxBuffPtr += 2U; } else { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU); } huart->TxXferCount--; @@ -1492,20 +1615,10 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State = HAL_UART_STATE_READY; - } + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; HAL_UART_TxCpltCallback(huart); @@ -1524,7 +1637,8 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) uint16_t* tmp; uint16_t uhMask = huart->Mask; - if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) @@ -1540,23 +1654,14 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) if(--huart->RxXferCount == 0) { - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State = HAL_UART_STATE_READY; - } + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; HAL_UART_RxCpltCallback(huart); @@ -1567,10 +1672,43 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) } else { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + return HAL_BUSY; } } +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart: UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart: UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; +} + /** * @} */ @@ -1595,6 +1733,8 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver (+) HAL_LIN_SendBreak() API transmits the break characters + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. @endverbatim * @{ */ @@ -1610,12 +1750,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Enable USART mute mode by setting the MME bit in the CR1 register */ - huart->Instance->CR1 |= USART_CR1_MME; + SET_BIT(huart->Instance->CR1, USART_CR1_MME); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; return (UART_CheckIdleState(huart)); } @@ -1631,12 +1771,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - huart->Instance->CR1 &= ~(USART_CR1_MME); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; return (UART_CheckIdleState(huart)); } @@ -1661,7 +1801,11 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - return huart->State; + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); } /** @@ -1682,10 +1826,10 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000; + uint32_t tmpreg = 0x00000000U; UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint16_t brrtemp = 0x0000U; + uint16_t usartdiv = 0x0000U; HAL_StatusTypeDef ret = HAL_OK; /* Check the parameters */ @@ -1751,8 +1895,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) break; } - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); huart->Instance->BRR = brrtemp; } else @@ -1868,14 +2012,19 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { + uint32_t tickstart = 0U; + /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Check if the Transmitter is enabled */ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout Occurred */ return HAL_TIMEOUT; @@ -1885,7 +2034,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout Occurred */ return HAL_TIMEOUT; @@ -1893,7 +2042,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) } /* Initialize the UART State */ - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1911,14 +2061,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1934,14 +2084,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1962,12 +2112,12 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Send break characters */ - huart->Instance->RQR |= UART_SENDBREAK_REQUEST; + SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1975,6 +2125,44 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) return HAL_OK; } +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart: UART handle. + * @param AddressLength: this parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} /** * @} diff --git a/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c b/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c index b14445c686..2ce4013793 100644 --- a/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c +++ b/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -138,7 +138,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -239,7 +239,6 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) } - /** * @} */ @@ -485,7 +484,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode)); /* Set SDMMC read wait mode */ - SDMMCx->DCTRL |= SDMMC_ReadWaitMode; + MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); return HAL_OK; } diff --git a/stmhal/hal/f7/src/stm32f7xx_ll_usb.c b/stmhal/hal/f7/src/stm32f7xx_ll_usb.c index 8266b09a7a..51983557b4 100644 --- a/stmhal/hal/f7/src/stm32f7xx_ll_usb.c +++ b/stmhal/hal/f7/src/stm32f7xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -28,7 +28,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -72,7 +72,8 @@ /* Private functions ---------------------------------------------------------*/ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); -/** @defgroup PCD_Private_Functions +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions * @{ */ @@ -117,7 +118,6 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c } else /* FS interface (embedded Phy) */ { - /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; @@ -166,7 +166,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) * @brief USB_SetCurrentMode : Set functional mode * @param USBx : Selected device * @param mode : current core mode - * This parameter can be one of the these values: + * This parameter can be one of these values: * @arg USB_OTG_DEVICE_MODE: Peripheral mode * @arg USB_OTG_HOST_MODE: Host mode * @arg USB_OTG_DRD_MODE: Dual Role Device mode @@ -206,7 +206,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if (cfg.vbus_sensing_enable == 0) { - /*Desactivate VBUS Sensing B */ + /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; /* B-peripheral session valid override enable*/ @@ -243,7 +243,6 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ USB_FlushRxFifo(USBx); - /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0; USBx_DEVICE->DOEPMSK = 0; @@ -378,7 +377,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) * depending the PHY type and the enumeration speed of the device. * @param USBx : Selected device * @param speed : device speed - * This parameter can be one of the these values: + * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode @@ -395,7 +394,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) * @brief USB_GetDevSpeed :Return the Dev Speed * @param USBx : Selected device * @retval speed : device speed - * This parameter can be one of the these values: + * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode @@ -512,7 +511,6 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP } else { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; @@ -547,7 +545,7 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U * @param USBx : Selected device * @param ep: pointer to endpoint structure * @param dma: USB dma enabled or disabled - * This parameter can be one of the these values: + * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status @@ -669,7 +667,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * @param USBx : Selected device * @param ep: pointer to endpoint structure * @param dma: USB dma enabled or disabled - * This parameter can be one of the these values: + * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status @@ -705,6 +703,9 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD } + /* EP enable, IN data in FIFO */ + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + if (dma == 1) { USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); @@ -712,14 +713,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD else { /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) + if (ep->xfer_len > 0U) { - USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num); + USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num); } } - - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else /* OUT endpoint */ { @@ -758,7 +756,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD * @param ch_ep_num : endpoint or host channel number * @param len : Number of bytes to write * @param dma: USB dma enabled or disabled - * This parameter can be one of the these values: + * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status @@ -786,7 +784,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin * @param ch_ep_num : endpoint or host channel number * @param len : Number of bytes to read * @param dma: USB dma enabled or disabled - * This parameter can be one of the these values: + * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used * @retval pointer to destination buffer @@ -1017,7 +1015,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @brief Returns USB core mode * @param USBx : Selected device * @retval return core mode : Host or Device - * This parameter can be one of the these values: + * This parameter can be one of these values: * 0 : Host * 1 : Device */ @@ -1051,7 +1049,7 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) * @brief Prepare the EP0 to start the first control setup * @param USBx : Selected device * @param dma: USB dma enabled or disabled - * This parameter can be one of the these values: + * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used * @param psetup : pointer to setup packet @@ -1162,16 +1160,13 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef /* Clear any pending interrupts */ USBx->GINTSTS = 0xFFFFFFFF; - if(USBx == USB_OTG_FS) { /* set Rx FIFO size */ USBx->GRXFSIZ = (uint32_t )0x80; USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); - } - else { /* set Rx FIFO size */ @@ -1199,7 +1194,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef * HCFG register on the PHY type and set the right frame interval * @param USBx : Selected device * @param freq : clock frequency - * This parameter can be one of the these values: + * This parameter can be one of these values: * HCFG_48_MHZ : Full Speed 48 MHz Clock * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status @@ -1232,9 +1227,10 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) __IO uint32_t hprt0; hprt0 = USBx_HPRT0; + hprt0 |= USB_OTG_HPRT_PENA ; - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); + hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\ + USB_OTG_HPRT_POCCHNG ); USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); HAL_Delay (10); /* See Note #1 */ @@ -1245,7 +1241,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DriveVbus : activate or de-activate vbus * @param state : VBUS state - * This parameter can be one of the these values: + * This parameter can be one of these values: * 0 : VBUS Active * 1 : VBUS Inactive * @retval HAL status @@ -1255,8 +1251,10 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) __IO uint32_t hprt0; hprt0 = USBx_HPRT0; - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); + hprt0 |= USB_OTG_HPRT_PENA ; + + hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\ + USB_OTG_HPRT_POCCHNG ); if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) { @@ -1273,7 +1271,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) * @brief Return Host Core speed * @param USBx : Selected device * @retval speed : Host speed - * This parameter can be one of the these values: + * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode @@ -1306,12 +1304,12 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) * @param dev_address : Current device address * This parameter can be a value from 0 to 255 * @param speed : Current device speed - * This parameter can be one of the these values: + * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode * @param ep_type : Endpoint Type - * This parameter can be one of the these values: + * This parameter can be one of these values: * @arg EP_TYPE_CTRL: Control type * @arg EP_TYPE_ISOC: Isochronous type * @arg EP_TYPE_BULK: Bulk type @@ -1357,6 +1355,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, } } break; + case EP_TYPE_INTR: USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ @@ -1414,7 +1413,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, * @param USBx : Selected device * @param hc : pointer to host channel structure * @param dma: USB dma enabled or disabled - * This parameter can be one of the these values: + * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL state @@ -1466,8 +1465,6 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe hc->xfer_len = num_packets * hc->max_packet; } - - /* Initialize the HCTSIZn register */ USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ @@ -1659,7 +1656,6 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) /* Halt all channels to put them into a known state. */ for (i = 0; i <= 15; i++) { - value = USBx_HC(i)->HCCHAR ; value |= USB_OTG_HCCHAR_CHDIS;