esp8266: Allow for MOSI or MISO only SPI. Fixes #65
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@ -41,11 +41,36 @@ extern const mcu_pin_obj_t pin_MTDI;
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void common_hal_nativeio_spi_construct(nativeio_spi_obj_t *self,
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const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi,
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const mcu_pin_obj_t * miso) {
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if (clock != &pin_MTMS || mosi != &pin_MTCK || miso != &pin_MTDI) {
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if (clock != &pin_MTMS || !((mosi == &pin_MTCK && miso == MP_OBJ_TO_PTR(mp_const_none)) ||
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(mosi == MP_OBJ_TO_PTR(mp_const_none) && miso == &pin_MTDI))) {
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nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
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"Pins not valid for SPI"));
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}
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spi_init(HSPI);
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uint32_t clock_div_flag = 0;
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if (SPI_CLK_USE_DIV) {
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clock_div_flag = 0x0001;
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}
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// Set bit 9 if 80MHz sysclock required
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WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105 | (clock_div_flag<<9));
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// GPIO12 is HSPI MISO pin (Master Data In)
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if (miso == &pin_MTDI) {
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);
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}
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// GPIO13 is HSPI MOSI pin (Master Data Out)
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if (mosi == &pin_MTCK) {
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);
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}
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// GPIO14 is HSPI CLK pin (Clock)
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2);
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spi_clock(HSPI, SPI_CLK_PREDIV, SPI_CLK_CNTDIV);
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spi_tx_byte_order(HSPI, SPI_BYTE_ORDER_HIGH_TO_LOW);
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spi_rx_byte_order(HSPI, SPI_BYTE_ORDER_HIGH_TO_LOW);
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SET_PERI_REG_MASK(SPI_USER(HSPI), SPI_CS_SETUP|SPI_CS_HOLD);
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CLEAR_PERI_REG_MASK(SPI_USER(HSPI), SPI_FLASH_MODE);
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}
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void common_hal_nativeio_spi_deinit(nativeio_spi_obj_t *self) {
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