djsundog/circuitpython
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Replace asf4 tree with submodule repo adafruit/asf4, branch circuitpython.

Browse Source
This commit is contained in:
Dan Halbert 2017-10-11 18:30:01 -04:00 committed by Scott Shawcroft
parent 80654779e1
commit b7591cfd19
698 changed files with 5 additions and 441475 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.gitmodules vendored
View File

@ -20,3 +20,7 @@
[submodule "atmel-samd/frozen/Adafruit_CircuitPython_NeoPixel"]
path = frozen/Adafruit_CircuitPython_NeoPixel
url = https://github.com/adafruit/Adafruit_CircuitPython_NeoPixel
[submodule "atmel-samd/asf4"]
path = atmel-samd/asf4
url = https://github.com/adafruit/asf4.git
branch = circuitpython

1
atmel-samd/asf4 Submodule

@ -0,0 +1 @@
Subproject commit 8dc86ee7657c92553e70803fdcef681a257f7e32

20
atmel-samd/asf4/patches/samd21/assert_redefined.patch
View File

@ -1,20 +0,0 @@
--- samd21_vanilla/hal/utils/include/utils_assert.h 2017-09-28 12:05:22.000000000 -0700
+++ samd21/hal/utils/include/utils_assert.h 2017-09-19 13:07:29.000000000 -0700
@@ -72,7 +72,7 @@
if (!(condition)) \
__asm("BKPT #0");
#else
-#define ASSERT_IMPL(condition, file, line) assert((condition), file, line)
+#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line)
#endif
#else /* DEBUG */
@@ -95,7 +95,7 @@
* \param[in] file File name
* \param[in] line Line number
*/
-void assert(const bool condition, const char *const file, const int line);
+void asf_assert(const bool condition, const char *const file, const int line);
#ifdef __cplusplus
}

36
atmel-samd/asf4/patches/samd21/cast-align.patch
View File

@ -1,36 +0,0 @@
--- samd21_vanilla/hal/src/hal_timer.c 2017-09-28 12:05:22.000000000 -0700
+++ samd21/hal/src/hal_timer.c 2017-09-19 13:07:29.000000000 -0700
@@ -236,7 +236,10 @@
*/
static void timer_process_counted(struct _timer_device *device)
{
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wcast-align"
struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device);
+ #pragma GCC diagnostic pop
struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks);
uint32_t time = ++timer->time;
--- a/hal/src/hal_flash.c
+++ b/hal/src/hal_flash.c
@@ -304,7 +304,10 @@ static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const ui
*/
static void flash_ready(struct _flash_device *device)
{
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wcast-align"
struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev);
+ #pragma GCC diagnostic pop
if (descr->callbacks.cb_ready) {
descr->callbacks.cb_ready(descr);
}
@@ -317,7 +320,10 @@ static void flash_ready(struct _flash_device *device)
*/
static void flash_error(struct _flash_device *device)
{
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wcast-align"
struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev);
+ #pragma GCC diagnostic pop
if (descr->callbacks.cb_error) {
descr->callbacks.cb_error(descr);
}

20
atmel-samd/asf4/patches/samd21/cortex_sc.patch
View File

@ -1,20 +0,0 @@
--- samd21_vanilla/CMSIS/Include/core_cmInstr.h 2017-09-28 12:05:22.000000000 -0700
+++ samd21/CMSIS/Include/core_cmInstr.h 2017-09-19 13:07:29.000000000 -0700
@@ -171,7 +171,7 @@
#define __BKPT(value) __breakpoint(value)
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300)
/** \brief Reverse bit order of value
@@ -538,7 +538,7 @@
#define __BKPT(value) __ASM volatile ("bkpt "#value)
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300)
/** \brief Reverse bit order of value

61
atmel-samd/asf4/patches/samd21/flash-const.patch
View File

@ -1,61 +0,0 @@
--- a/hal/include/hal_flash.h
+++ b/hal/include/hal_flash.h
@@ -132,7 +132,7 @@ int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *
* \param[in] length Number of bytes to append
* \return Append status.
*/
-int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length);
+int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length);
/** \brief Reads a number of bytes to a page in the internal Flash
*
--- a/hal/include/hpl_flash.h
+++ b/hal/include/hpl_flash.h
@@ -125,7 +125,7 @@ void _flash_read(struct _flash_device *const device, const uint32_t src_addr, ui
* write is stored
* \param[in] length Number of bytes to write
*/
-void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length);
+void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length);
/**
* \brief Appends a number of bytes in the internal Flash.
@@ -135,7 +135,7 @@ void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, u
* \param[in] buffer Pointer to buffer with data to write to flash
* \param[in] length Number of bytes to write
*/
-void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length);
+void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length);
/** \brief Execute lock in the internal flash
* \param[in] device The pointer to FLASH device instance
--- a/hal/src/hal_flash.c
+++ b/hal/src/hal_flash.c
@@ -135,7 +135,7 @@ int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *
/**
* \brief Appends a number of bytes to a page in the internal Flash
*/
-int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length)
+int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length)
{
ASSERT(flash && buffer && length);
--- a/hpl/nvmctrl/hpl_nvmctrl.c
+++ b/hpl/nvmctrl/hpl_nvmctrl.c
@@ -175,7 +175,7 @@ void _flash_read(struct _flash_device *const device, const uint32_t src_addr, ui
/**
* \brief Writes a number of bytes to a page in the internal Flash.
*/
-void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length)
+void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length)
{
uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE];
uint32_t row_start_addr, row_end_addr;
@@ -219,7 +219,7 @@ void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, u
/**
* \brief Appends a number of bytes in the internal Flash.
*/
-void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length)
+void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length)
{
uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1);
uint32_t size;

11
atmel-samd/asf4/patches/samd21/gclk_defined.patch
View File

@ -1,11 +0,0 @@
--- samd21_vanilla/hpl/gclk/hpl_gclk.c 2017-09-28 12:05:22.000000000 -0700
+++ samd21/hpl/gclk/hpl_gclk.c 2017-09-19 13:07:29.000000000 -0700
@@ -147,7 +147,7 @@
| CONF_GCLK_GEN_7_SRC
| GCLK_GENCTRL_ID(7));
#endif
-#if CONF_GCLK_GEN_8_GENEN == 1
+#if defined(CONF_GCLK_GEN_8_GENEN) && CONF_GCLK_GEN_8_GENEN == 1
hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_8_DIV) | GCLK_GENDIV_ID(8));
hri_gclk_write_GENCTRL_reg(GCLK,
(CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)

22
atmel-samd/asf4/patches/samd21/little_endian_redefined.patch
View File

@ -1,22 +0,0 @@
--- samd21_vanilla/include/samd21e18a.h 2017-09-28 12:05:22.000000000 -0700
+++ samd21/include/samd21e18a.h 2017-09-19 13:07:30.000000000 -0700
@@ -210,7 +210,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+// #define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- samd21_vanilla/include/samd21g18a.h 2017-09-28 12:05:22.000000000 -0700
+++ samd21/include/samd21g18a.h 2017-09-19 13:07:30.000000000 -0700
@@ -214,7 +214,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

11
atmel-samd/asf4/patches/samd21/make_usb_cache_accessible.patch
View File

@ -1,11 +0,0 @@
--- samd21_vanilla/hpl/usb/hpl_usb.c 2017-09-28 12:05:22.000000000 -0700
+++ samd21/hpl/usb/hpl_usb.c 2017-09-19 13:07:29.000000000 -0700
@@ -300,7 +300,7 @@
/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
* transactions (control). */
#if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1
-static uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4];
+uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4];
#else
#define _usb_ep1_cache NULL
#endif

20
atmel-samd/asf4/patches/samd21/mark_used_no_c.patch
View File

@ -1,20 +0,0 @@
--- samd21_vanilla/gcc/gcc/startup_samd21.c 2017-09-20 22:33:52.000000000 -0700
+++ samd21/gcc/gcc/startup_samd21.c 2017-09-19 13:07:30.000000000 -0700
@@ -104,7 +105,7 @@
void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
/* Exception Table */
-__attribute__((section(".vectors"))) const DeviceVectors exception_table = {
+__attribute__((section(".vectors"), used)) const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void *)(&_estack),
@@ -234,7 +234,7 @@
NVMCTRL->CTRLB.bit.MANW = 1;
/* Initialize the C library */
- __libc_init_array();
+ //__libc_init_array();
/* Branch to main function */
main();

11
atmel-samd/asf4/patches/samd21/sysctrl_fix.patch
View File

@ -1,11 +0,0 @@
--- samd21_vanilla/hpl/sysctrl/hpl_sysctrl.c 2017-09-28 12:05:22.000000000 -0700
+++ samd21/hpl/sysctrl/hpl_sysctrl.c 2017-09-19 13:07:29.000000000 -0700
@@ -114,7 +114,7 @@
#if CONF_OSCULP32K_CONFIG == 1
hri_sysctrl_write_OSCULP32K_reg(hw,
-#if OSC32K_OVERWRITE_CALIBRATION == 1
+#if CONF_OSC32K_OVERWRITE_CALIBRATION == 1
SYSCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) |
#else
SYSCTRL_OSCULP32K_CALIB(calib) |

22
atmel-samd/asf4/patches/samd21/usb_undefined.patch
View File

@ -1,22 +0,0 @@
--- samd21_vanilla/usb/device/usbdc.c 2017-09-28 12:05:22.000000000 -0700
+++ samd21/usb/device/usbdc.c 2017-09-19 13:07:30.000000000 -0700
@@ -739,7 +737,7 @@
*/
int32_t usbdc_check_desces(struct usbdc_descriptors *desces)
{
-#if CONF_USBD_HS_SP
+#ifdef CONF_USBD_HS_SP
int32_t rc;
if (desces->hs == NULL && desces->ls_fs == NULL) {
return ERR_NOT_FOUND;
--- samd21_vanilla/usb/device/usbdc.h 2017-09-28 12:05:22.000000000 -0700
+++ samd21/usb/device/usbdc.h 2017-09-19 13:07:30.000000000 -0700
@@ -105,7 +105,7 @@
/** Describes the USB device core descriptors. */
struct usbdc_descriptors {
struct usbd_descriptors *ls_fs;
-#if CONF_USBD_HS_SP
+#ifdef CONF_USBD_HS_SP
struct usbd_descriptors *hs;
#endif
};

13
atmel-samd/asf4/patches/samd51/array-bounds.patch
View File

@ -1,13 +0,0 @@
--- a/CMSIS/Include/core_cm4.h
+++ b/CMSIS/Include/core_cm4.h
@@ -1493,8 +1493,12 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
+
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Warray-bounds"
/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+ #pragma GCC diagnostic pop
}

20
atmel-samd/asf4/patches/samd51/assert_redefined.patch
View File

@ -1,20 +0,0 @@
--- samd51_vanilla/hal/utils/include/utils_assert.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/hal/utils/include/utils_assert.h 2017-09-19 13:07:30.000000000 -0700
@@ -72,7 +72,7 @@
if (!(condition)) \
__asm("BKPT #0");
#else
-#define ASSERT_IMPL(condition, file, line) assert((condition), file, line)
+#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line)
#endif
#else /* DEBUG */
@@ -95,7 +95,7 @@
* \param[in] file File name
* \param[in] line Line number
*/
-void assert(const bool condition, const char *const file, const int line);
+void asf_assert(const bool condition, const char *const file, const int line);
#ifdef __cplusplus
}

49
atmel-samd/asf4/patches/samd51/cast-align.patch
View File

@ -1,49 +0,0 @@
--- samd51_vanilla/hal/src/hal_timer.c 2017-09-20 22:33:52.000000000 -0700
+++ samd51/hal/src/hal_timer.c 2017-09-19 13:07:30.000000000 -0700
@@ -236,7 +236,10 @@
*/
static void timer_process_counted(struct _timer_device *device)
{
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wcast-align"
struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device);
+ #pragma GCC diagnostic pop
struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks);
uint32_t time = ++timer->time;
--- a/hal/src/hal_flash.c
+++ b/hal/src/hal_flash.c
@@ -304,7 +304,10 @@ static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const ui
*/
static void flash_ready(struct _flash_device *device)
{
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wcast-align"
struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev);
+ #pragma GCC diagnostic pop
if (descr->callbacks.cb_ready) {
descr->callbacks.cb_ready(descr);
}
@@ -317,7 +320,10 @@ static void flash_ready(struct _flash_device *device)
*/
static void flash_error(struct _flash_device *device)
{
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wcast-align"
struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev);
+ #pragma GCC diagnostic pop
if (descr->callbacks.cb_error) {
descr->callbacks.cb_error(descr);
}
--- a/hpl/nvmctrl/hpl_nvmctrl.c
+++ b/hpl/nvmctrl/hpl_nvmctrl.c
@@ -386,7 +386,10 @@ static void _flash_erase_block(void *const hw, const uint32_t dst_addr)
*/
static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size)
{
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wcast-align"
uint32_t *ptr_read = (uint32_t *)buffer;
+ #pragma GCC diagnostic pop
uint32_t nvm_address = dst_addr / 4;
uint16_t i;

63
atmel-samd/asf4/patches/samd51/flash-const.patch
View File

@ -1,63 +0,0 @@
--- a/hal/include/hal_flash.h
+++ b/hal/include/hal_flash.h
@@ -132,7 +132,7 @@ int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *
* \param[in] length Number of bytes to append
* \return Append status.
*/
-int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length);
+int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length);
/** \brief Reads a number of bytes to a page in the internal Flash
*
--- a/hal/include/hpl_flash.h
+++ b/hal/include/hpl_flash.h
@@ -125,7 +125,7 @@ void _flash_read(struct _flash_device *const device, const uint32_t src_addr, ui
* write is stored
* \param[in] length Number of bytes to write
*/
-void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length);
+void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length);
/**
* \brief Appends a number of bytes in the internal Flash.
@@ -135,7 +135,7 @@ void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, u
* \param[in] buffer Pointer to buffer with data to write to flash
* \param[in] length Number of bytes to write
*/
-void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length);
+void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length);
/** \brief Execute lock in the internal flash
* \param[in] device The pointer to FLASH device instance
--- a/hal/src/hal_flash.c
+++ b/hal/src/hal_flash.c
@@ -135,7 +135,7 @@ int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *
/**
* \brief Appends a number of bytes to a page in the internal Flash
*/
-int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length)
+int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length)
{
ASSERT(flash && buffer && length);
--- a/hpl/nvmctrl/hpl_nvmctrl.c
+++ b/hpl/nvmctrl/hpl_nvmctrl.c
@@ -167,7 +167,7 @@ void _flash_read(struct _flash_device *const device, const uint32_t src_addr, ui
/**
* \brief Writes a number of bytes to a page in the internal Flash.
*/
-void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length)
+void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length)
{
uint8_t tmp_buffer[NVMCTRL_BLOCK_PAGES][NVMCTRL_PAGE_SIZE];
uint32_t block_start_addr, block_end_addr;
@@ -212,7 +212,7 @@ void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, u
/**
* \brief Appends a number of bytes in the internal Flash.
*/
-void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length)
+void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length)
{
uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1);
uint32_t size;

99
atmel-samd/asf4/patches/samd51/little_endian_redefined.patch
View File

@ -1,99 +0,0 @@
--- samd51_vanilla/include/samd51g18a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51g18a.h 2017-09-19 13:07:30.000000000 -0700
@@ -511,7 +512,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */
--- samd51_vanilla/include/samd51g19a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51g19a.h 2017-09-19 13:07:30.000000000 -0700
@@ -511,7 +512,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */
--- samd51_vanilla/include/samd51j18a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51j18a.h 2017-09-19 13:07:30.000000000 -0700
@@ -529,7 +530,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */
--- samd51_vanilla/include/samd51j19a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51j19a.h 2017-09-19 13:07:30.000000000 -0700
@@ -529,7 +530,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */
--- samd51_vanilla/include/samd51j20a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51j20a.h 2017-09-19 13:07:30.000000000 -0700
@@ -529,7 +530,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */
--- samd51_vanilla/include/samd51n19a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51n19a.h 2017-09-19 13:07:30.000000000 -0700
@@ -551,7 +552,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */
--- samd51_vanilla/include/samd51n20a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51n20a.h 2017-09-19 13:07:30.000000000 -0700
@@ -551,7 +552,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */
--- samd51_vanilla/include/samd51p19a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51p19a.h 2017-09-19 13:07:30.000000000 -0700
@@ -551,7 +552,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */
--- samd51_vanilla/include/samd51p20a.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/include/samd51p20a.h 2017-09-19 13:07:30.000000000 -0700
@@ -551,7 +552,7 @@
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+//#define LITTLE_ENDIAN 1
#define __CM4_REV 1 /*!< Core revision r0p1 */
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
#define __FPU_PRESENT 1 /*!< FPU present or not */

19
atmel-samd/asf4/patches/samd51/make_usb_cache_accessible.patch
View File

@ -1,19 +0,0 @@
--- samd51_vanilla/hpl/usb/hpl_usb.c 2017-09-20 22:33:52.000000000 -0700
+++ samd51/hpl/usb/hpl_usb.c 2017-09-19 13:07:30.000000000 -0700
@@ -299,14 +299,14 @@
/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
* transactions (control). */
#if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1
-static uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4];
+uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4];
#else
#define _usb_ep1_cache NULL
#endif
/** Endpoint cache buffer for IN transactions (none-control). */
#if CONF_USB_EP1_I_CACHE && CONF_USB_D_MAX_EP_N >= 1
-static uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4];
+uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4];
#else
#define _usb_ep1_i_cache NULL
#endif

20
atmel-samd/asf4/patches/samd51/mark_used_no_c.patch
View File

@ -1,20 +0,0 @@
--- samd51_vanilla/gcc/gcc/startup_samd51.c 2017-09-20 22:33:52.000000000 -0700
+++ samd51/gcc/gcc/startup_samd51.c 2017-09-19 13:07:30.000000000 -0700
@@ -314,7 +315,7 @@
#endif
/* Exception Table */
-__attribute__((section(".vectors"))) const DeviceVectors exception_table
+__attribute__((section(".vectors"), used)) const DeviceVectors exception_table
= {
/* Configure Initial Stack Pointer, using linker-generated symbols */
@@ -660,7 +661,7 @@
#endif
/* Initialize the C library */
- __libc_init_array();
+ //__libc_init_array();
/* Branch to main function */
main();

22
atmel-samd/asf4/patches/samd51/usb_undefined.patch
View File

@ -1,22 +0,0 @@
--- samd51_vanilla/usb/device/usbdc.c 2017-09-20 22:33:52.000000000 -0700
+++ samd51/usb/device/usbdc.c 2017-09-19 13:07:30.000000000 -0700
@@ -739,7 +741,7 @@
*/
int32_t usbdc_check_desces(struct usbdc_descriptors *desces)
{
-#if CONF_USBD_HS_SP
+#ifdef CONF_USBD_HS_SP
int32_t rc;
if (desces->hs == NULL && desces->ls_fs == NULL) {
return ERR_NOT_FOUND;
--- samd51_vanilla/usb/device/usbdc.h 2017-09-20 22:33:52.000000000 -0700
+++ samd51/usb/device/usbdc.h 2017-09-19 13:07:30.000000000 -0700
@@ -105,7 +105,7 @@
/** Describes the USB device core descriptors. */
struct usbdc_descriptors {
struct usbd_descriptors *ls_fs;
-#if CONF_USBD_HS_SP
+#ifdef CONF_USBD_HS_SP
struct usbd_descriptors *hs;
#endif
};

241
atmel-samd/asf4/samd21/CMSIS/Documentation/Core/html/index.html
View File

@ -1,241 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<title>CMSIS-CORE: Overview</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<link href="cmsis.css" rel="stylesheet" type="text/css" />
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
$(document).ready(initResizable);
</script>
<link href="search/search.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="search/search.js"></script>
<script type="text/javascript">
$(document).ready(function() { searchBox.OnSelectItem(0); });
</script>
<link href="stylsheetf" rel="stylesheet" type="text/css" />
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
<tbody>
<tr style="height: 46px;">
<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
<td style="padding-left: 0.5em;">
<div id="projectname">CMSIS-CORE
&#160;<span id="projectnumber">Version 4.00</span>
</div>
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
</td>
</tr>
</tbody>
</table>
</div>
<!-- end header part -->
<div id="CMSISnav" class="tabs1">
<ul class="tablist">
<li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
<li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
<li><a href="../../Driver/html/index.html"><span>Driver</span></a></li>
<li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
<li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
<li><a href="../../Pack/html/index.html"><span>Pack</span></a></li>
<li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
</ul>
</div>
<!-- Generated by Doxygen 1.8.2 -->
<script type="text/javascript">
var searchBox = new SearchBox("searchBox", "search",false,'Search');
</script>
<div id="navrow1" class="tabs">
<ul class="tablist">
<li class="current"><a href="index.html"><span>Main&#160;Page</span></a></li>
<li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
<li><a href="modules.html"><span>Reference</span></a></li>
<li>
<div id="MSearchBox" class="MSearchBoxInactive">
<span class="left">
<img id="MSearchSelect" src="search/mag_sel.png"
onmouseover="return searchBox.OnSearchSelectShow()"
onmouseout="return searchBox.OnSearchSelectHide()"
alt=""/>
<input type="text" id="MSearchField" value="Search" accesskey="S"
onfocus="searchBox.OnSearchFieldFocus(true)"
onblur="searchBox.OnSearchFieldFocus(false)"
onkeyup="searchBox.OnSearchFieldChange(event)"/>
</span><span class="right">
<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
</span>
</div>
</li>
</ul>
</div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
<div id="nav-tree">
<div id="nav-tree-contents">
<div id="nav-sync" class="sync"></div>
</div>
</div>
<div id="splitbar" style="-moz-user-select:none;"
class="ui-resizable-handle">
</div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('index.html','');});
</script>
<div id="doc-content">
<!-- window showing the filter options -->
<div id="MSearchSelectWindow"
onmouseover="return searchBox.OnSearchSelectShow()"
onmouseout="return searchBox.OnSearchSelectHide()"
onkeydown="return searchBox.OnSearchSelectKey(event)">
<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
<!-- iframe showing the search results (closed by default) -->
<div id="MSearchResultsWindow">
<iframe src="javascript:void(0)" frameborder="0"
name="MSearchResults" id="MSearchResults">
</iframe>
</div>
<div class="header">
<div class="headertitle">
<div class="title">Overview </div> </div>
</div><!--header-->
<div class="contents">
<div class="textblock"><p>CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
<ul>
<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system.">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
</ul>
<hr/>
<p>This chapter provides details about the CMSIS-CORE and contains the following sections:</p>
<ul>
<li><a class="el" href="_using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
<li><a class="el" href="_templates_pg.html">Template Files</a> describes the files of the CMSIS-CORE in detail and explains how to adapt template files provided by ARM to silicon vendor devices.</li>
<li><a class="el" href="_c_o_r_e__m_i_s_r_a__exceptions_pg.html">MISRA-C:2004 Compliance Exceptions</a> describes the violations to the MISRA standard.</li>
<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
</ul>
<hr/>
<h2>CMSIS-CORE in ARM::CMSIS Pack</h2>
<p>Files relevant to CMSIS-CORE are present in the following <b>ARM::CMSIS</b> directories: </p>
<table class="doxtable">
<tr>
<th>File/Folder </th><th>Content </th></tr>
<tr>
<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
<tr>
<td><b>CMSIS\Include</b> </td><td>CMSIS-CORE header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
<tr>
<td><b>Device</b> </td><td><a class="el" href="_using__a_r_m_pg.html">ARM reference implementations</a> of Cortex-M devices </td></tr>
<tr>
<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="_templates_pg.html">Template Files</a> for extension by silicon vendors </td></tr>
</table>
<hr/>
<h1><a class="anchor" id="ref_man_sec"></a>
Cortex-M Reference Manuals</h1>
<p>The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.</p>
<ul>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a></li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a></li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a></li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a></li>
</ul>
<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000001">Todo:</a></b></dt><dd><ul>
<li><a href="" target="_blank"><b>Link to Cortex-M7 Devices Generic User Guide</b></a></li>
</ul>
</dd></dl>
<hr/>
<h1><a class="anchor" id="tested_tools_sec"></a>
Tested and Verified Toolchains</h1>
<p>The CMSIS-CORE <a class="el" href="_templates_pg.html">Template Files</a> supplied by ARM have been tested and verified with the following toolchains:</p>
<ul>
<li>ARM: MDK-ARM Version 5.12</li>
<li>GNU: GNU Tools ARM Embedded 4.8 2014.q3</li>
<li>IAR: IAR Embedded Workbench Kickstart Edition V6.10</li>
</ul>
<hr/>
<h2><a class="anchor" id="core_revisionHistory"></a>Revision History of CMSIS-CORE</h2>
<table class="cmtable" summary="Core Exception Name">
<tr>
<th>Version </th><th>Description </th></tr>
<tr>
<td>V4.00 </td><td>Added: Cortex-M7 support.<br/>
Added: intrinsic functions for <a class="el" href="group__intrinsic___c_p_u__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a>, and <a class="el" href="group__intrinsic___c_p_u__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> <br/>
</td></tr>
<tr>
<td>V3.40 </td><td>Corrected: C++ include guard settings.<br/>
</td></tr>
<tr>
<td>V3.30 </td><td>Added: COSMIC tool chain support.<br/>
Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.<br/>
Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.<br/>
Corrected: GCC/CLang warnings.<br/>
</td></tr>
<tr>
<td>V3.20 </td><td>Added: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> instruction intrinsic.<br/>
Added: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> instruction intrinsic for Cortex-M4.<br/>
Corrected: <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a>.<br/>
Corrected: <a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>, <a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> and inline assembly for GCC Compiler.<br/>
Corrected: <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.<br/>
</td></tr>
<tr>
<td>V3.01 </td><td>Added support for Cortex-M0+ processor. <br/>
</td></tr>
<tr>
<td>V3.00 </td><td>Added support for GNU GCC ARM Embedded Compiler. <br/>
Added function <a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a>.<br/>
Added <a class="el" href="_reg_map_pg.html">Register Mapping</a> for TPIU, DWT. <br/>
Added support for <a class="el" href="device_h_pg.html#core_config_sect">SC000 and SC300 processors</a>.<br/>
Corrected <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function. <br/>
Corrected the functions <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> for the GNU GCC compiler section. <br/>
Documentation restructured. </td></tr>
<tr>
<td>V2.10 </td><td>Updated documentation.<br/>
Updated CMSIS core include files.<br/>
Changed CMSIS/Device folder structure.<br/>
Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.<br/>
Reworked CMSIS DSP library examples. </td></tr>
<tr>
<td>V2.00 </td><td>Added support for Cortex-M4 processor. </td></tr>
<tr>
<td>V1.30 </td><td>Reworked Startup Concept.<br/>
Added additional Debug Functionality.<br/>
Changed folder structure.<br/>
Added doxygen comments.<br/>
Added definitions for bit. </td></tr>
<tr>
<td>V1.01 </td><td>Added support for Cortex-M0 processor. </td></tr>
<tr>
<td>V1.01 </td><td>Added intrinsic functions for <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a>, and <a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> </td></tr>
<tr>
<td>V1.00 </td><td>Initial Release for Cortex-M3 processor. </td></tr>
</table>
</div></div><!-- contents -->
</div><!-- doc-content -->
<!-- start footer part -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
<ul>
<li class="footer">Generated on Wed Sep 24 2014 12:16:08 for CMSIS-CORE by ARM Ltd. All rights reserved.
<!--
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2
-->
</li>
</ul>
</div>
</body>
</html>

136
atmel-samd/asf4/samd21/CMSIS/Include/arm_common_tables.h
View File

@ -1,136 +0,0 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 31. July 2014
* $Revision: V1.4.4
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
//extern const q31_t realCoefAQ31[1024];
//extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

79
atmel-samd/asf4/samd21/CMSIS/Include/arm_const_structs.h
View File

@ -1,79 +0,0 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 31. July 2014
* $Revision: V1.4.4
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

7544
atmel-samd/asf4/samd21/CMSIS/Include/arm_math.h
View File

File diff suppressed because it is too large Load Diff

711
atmel-samd/asf4/samd21/CMSIS/Include/core_cm0.h
View File

@ -1,711 +0,0 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#ifdef __cplusplus
extern "C" {
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

822
atmel-samd/asf4/samd21/CMSIS/Include/core_cm0plus.h
View File

@ -1,822 +0,0 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#ifdef __cplusplus
extern "C" {
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

1650
atmel-samd/asf4/samd21/CMSIS/Include/core_cm3.h
View File

File diff suppressed because it is too large Load Diff

1802
atmel-samd/asf4/samd21/CMSIS/Include/core_cm4.h
View File

File diff suppressed because it is too large Load Diff

2221
atmel-samd/asf4/samd21/CMSIS/Include/core_cm7.h
View File

File diff suppressed because it is too large Load Diff

637
atmel-samd/asf4/samd21/CMSIS/Include/core_cmFunc.h
View File

@ -1,637 +0,0 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.00
* @date 28. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

880
atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h
View File

@ -1,880 +0,0 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.00
* @date 28. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
}
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
}
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

697
atmel-samd/asf4/samd21/CMSIS/Include/core_cmSimd.h
View File

@ -1,697 +0,0 @@
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/* not yet supported */
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

842
atmel-samd/asf4/samd21/CMSIS/Include/core_sc000.h
View File

@ -1,842 +0,0 @@
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC
#ifdef __cplusplus
extern "C" {
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup SC000
@{
*/
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (000) /*!< Cortex secure core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000
#warning "__SC000_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED0[1];
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154];
__IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/* SCB Security Features Register Definitions */
#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/** \brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2];
__IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of SC000 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

1630
atmel-samd/asf4/samd21/CMSIS/Include/core_sc300.h
View File

File diff suppressed because it is too large Load Diff

273
atmel-samd/asf4/samd21/armcc/Makefile
View File

@ -1,273 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
ifdef SystemRoot
SHELL = cmd.exe
MK_DIR = mkdir
else
ifeq ($(shell uname), Linux)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
MK_DIR = mkdir -p
endif
endif
# List the subdirectories for creating object files
SUB_DIRS += \
\
hpl/adc \
hal/src \
samd21a/armcc/Device/SAMD21/Source/ARM \
examples \
hpl/systick \
hpl/tc \
usb \
hpl/dmac \
usb/class/cdc/device \
hal/utils/src \
hpl/rtc \
usb/class/hid/device \
hpl/usb \
hpl/pm \
hpl/sysctrl \
hpl/gclk \
usb/device \
hpl/dac \
samd21a/armcc/Device/SAMD21/Source \
hpl/sercom \
hpl/nvmctrl \
hpl/core \
usb/class/msc/device
# List the object files
OBJS += \
hal/src/hal_io.o \
hpl/systick/hpl_systick.o \
usb/usb_protocol.o \
usb/class/hid/device/hiddf_generic.o \
usb/class/cdc/device/cdcdf_acm.o \
hpl/nvmctrl/hpl_nvmctrl.o \
usb/class/msc/device/mscdf.o \
hal/src/hal_spi_m_sync.o \
hal/src/hal_timer.o \
hal/src/hal_pwm.o \
hpl/usb/hpl_usb.o \
hal/src/hal_i2c_m_sync.o \
hal/src/hal_delay.o \
hpl/sysctrl/hpl_sysctrl.o \
hpl/core/hpl_init.o \
hal/utils/src/utils_list.o \
hpl/core/hpl_core_m0plus_base.o \
hal/utils/src/utils_assert.o \
hpl/dmac/hpl_dmac.o \
hpl/pm/hpl_pm.o \
usb/class/hid/device/hiddf_keyboard.o \
hal/src/hal_usart_sync.o \
hpl/dac/hpl_dac.o \
hpl/gclk/hpl_gclk.o \
hal/src/hal_flash.o \
hal/src/hal_init.o \
samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.o \
hal/src/hal_usb_device.o \
main.o \
hpl/rtc/hpl_rtc.o \
examples/driver_examples.o \
driver_init.o \
samd21a/armcc/Device/SAMD21/Source/system_samd21.o \
hal/src/hal_adc_sync.o \
hal/src/hal_dac_sync.o \
hpl/sercom/hpl_sercom.o \
hal/src/hal_gpio.o \
usb/class/hid/device/hiddf_mouse.o \
hal/utils/src/utils_event.o \
hal/src/hal_sleep.o \
usb_start.o \
atmel_start.o \
usb/device/usbdc.o \
hpl/tc/hpl_tc.o \
hal/src/hal_atomic.o \
hpl/adc/hpl_adc.o
OBJS_AS_ARGS += \
"hal/src/hal_io.o" \
"hpl/systick/hpl_systick.o" \
"usb/usb_protocol.o" \
"usb/class/hid/device/hiddf_generic.o" \
"usb/class/cdc/device/cdcdf_acm.o" \
"hpl/nvmctrl/hpl_nvmctrl.o" \
"usb/class/msc/device/mscdf.o" \
"hal/src/hal_spi_m_sync.o" \
"hal/src/hal_timer.o" \
"hal/src/hal_pwm.o" \
"hpl/usb/hpl_usb.o" \
"hal/src/hal_i2c_m_sync.o" \
"hal/src/hal_delay.o" \
"hpl/sysctrl/hpl_sysctrl.o" \
"hpl/core/hpl_init.o" \
"hal/utils/src/utils_list.o" \
"hpl/core/hpl_core_m0plus_base.o" \
"hal/utils/src/utils_assert.o" \
"hpl/dmac/hpl_dmac.o" \
"hpl/pm/hpl_pm.o" \
"usb/class/hid/device/hiddf_keyboard.o" \
"hal/src/hal_usart_sync.o" \
"hpl/dac/hpl_dac.o" \
"hpl/gclk/hpl_gclk.o" \
"hal/src/hal_flash.o" \
"hal/src/hal_init.o" \
"samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.o" \
"hal/src/hal_usb_device.o" \
"main.o" \
"hpl/rtc/hpl_rtc.o" \
"examples/driver_examples.o" \
"driver_init.o" \
"samd21a/armcc/Device/SAMD21/Source/system_samd21.o" \
"hal/src/hal_adc_sync.o" \
"hal/src/hal_dac_sync.o" \
"hpl/sercom/hpl_sercom.o" \
"hal/src/hal_gpio.o" \
"usb/class/hid/device/hiddf_mouse.o" \
"hal/utils/src/utils_event.o" \
"hal/src/hal_sleep.o" \
"usb_start.o" \
"atmel_start.o" \
"usb/device/usbdc.o" \
"hpl/tc/hpl_tc.o" \
"hal/src/hal_atomic.o" \
"hpl/adc/hpl_adc.o"
# List the dependency files
DEPS := $(OBJS:%.o=%.d)
DEPS_AS_ARGS += \
"usb/usb_protocol.d" \
"hal/utils/src/utils_event.d" \
"hal/src/hal_io.d" \
"hpl/systick/hpl_systick.d" \
"usb/class/hid/device/hiddf_generic.d" \
"usb/class/cdc/device/cdcdf_acm.d" \
"usb/class/hid/device/hiddf_mouse.d" \
"samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.d" \
"hal/src/hal_i2c_m_sync.d" \
"hpl/usb/hpl_usb.d" \
"samd21a/armcc/Device/SAMD21/Source/system_samd21.d" \
"usb/class/msc/device/mscdf.d" \
"hpl/nvmctrl/hpl_nvmctrl.d" \
"hal/src/hal_pwm.d" \
"hal/src/hal_timer.d" \
"hal/src/hal_spi_m_sync.d" \
"hpl/core/hpl_core_m0plus_base.d" \
"hal/utils/src/utils_list.d" \
"hpl/dmac/hpl_dmac.d" \
"hal/utils/src/utils_assert.d" \
"hal/src/hal_delay.d" \
"hpl/core/hpl_init.d" \
"hpl/sysctrl/hpl_sysctrl.d" \
"hal/src/hal_flash.d" \
"hpl/gclk/hpl_gclk.d" \
"hal/src/hal_usb_device.d" \
"usb_start.d" \
"hal/src/hal_init.d" \
"hal/src/hal_usart_sync.d" \
"usb/class/hid/device/hiddf_keyboard.d" \
"hpl/dac/hpl_dac.d" \
"driver_init.d" \
"hal/src/hal_adc_sync.d" \
"main.d" \
"examples/driver_examples.d" \
"hpl/rtc/hpl_rtc.d" \
"hal/src/hal_sleep.d" \
"hpl/sercom/hpl_sercom.d" \
"hal/src/hal_dac_sync.d" \
"hal/src/hal_gpio.d" \
"hal/src/hal_atomic.d" \
"hpl/tc/hpl_tc.d" \
"usb/device/usbdc.d" \
"hpl/pm/hpl_pm.d" \
"hpl/adc/hpl_adc.d" \
"atmel_start.d"
OUTPUT_FILE_NAME :=AtmelStart
QUOTE := "
OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
vpath %.c ../
vpath %.s ../
vpath %.S ../
# All Target
all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
# Linker target
$(OUTPUT_FILE_PATH): $(OBJS)
@echo Building target: $@
@echo Invoking: ARMCC Linker
$(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \
--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \
--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \
-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M0+ \
$(OBJS_AS_ARGS)
@echo Finished building target: $@
# Compiler target(s)
%.o: %.c
@echo Building file: $<
@echo ARMCC Compiler
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD21G18A__ \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \
--depend "$@" -o "$@" "$<"
@echo Finished building: $<
%.o: %.s
@echo Building file: $<
@echo ARMCC Assembler
$(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M0+ --pd "D__SAMD21G18A__ SETA 1" \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \
--depend "$(@:%.o=%.d)" -o "$@" "$<"
@echo Finished building: $<
%.o: %.S
@echo Building file: $<
@echo ARMCC Preprocessing Assembler
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD21G18A__ \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \
--depend "$@" -o "$@" "$<"
@echo Finished building: $<
# Detect changes in the dependent files and recompile the respective object files.
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(DEPS)),)
-include $(DEPS)
endif
endif
$(SUB_DIRS):
$(MK_DIR) "$@"
clean:
rm -f $(OBJS_AS_ARGS)
rm -f $(OUTPUT_FILE_PATH)
rm -f $(DEPS_AS_ARGS)
rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf

10
atmel-samd/asf4/samd21/atmel_start.c
View File

@ -1,10 +0,0 @@
#include <atmel_start.h>
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
usb_init();
}

19
atmel-samd/asf4/samd21/atmel_start.h
View File

@ -1,19 +0,0 @@
#ifndef ATMEL_START_H_INCLUDED
#define ATMEL_START_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "driver_init.h"
#include "usb_start.h"
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void);
#ifdef __cplusplus
}
#endif
#endif

1114
atmel-samd/asf4/samd21/atmel_start_config.atstart
View File

File diff suppressed because it is too large Load Diff

63
atmel-samd/asf4/samd21/atmel_start_pins.h
View File

@ -1,63 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#include <hal_gpio.h>
// SAMD21 has 8 pin functions
#define GPIO_PIN_FUNCTION_A 0
#define GPIO_PIN_FUNCTION_B 1
#define GPIO_PIN_FUNCTION_C 2
#define GPIO_PIN_FUNCTION_D 3
#define GPIO_PIN_FUNCTION_E 4
#define GPIO_PIN_FUNCTION_F 5
#define GPIO_PIN_FUNCTION_G 6
#define GPIO_PIN_FUNCTION_H 7
#define PA00 GPIO(GPIO_PORTA, 0)
#define PA01 GPIO(GPIO_PORTA, 1)
#define PA02 GPIO(GPIO_PORTA, 2)
#define PA03 GPIO(GPIO_PORTA, 3)
#define PA04 GPIO(GPIO_PORTA, 4)
#define PA05 GPIO(GPIO_PORTA, 5)
#define PA06 GPIO(GPIO_PORTA, 6)
#define PA07 GPIO(GPIO_PORTA, 7)
#define PA08 GPIO(GPIO_PORTA, 8)
#define PA09 GPIO(GPIO_PORTA, 9)
#define PA10 GPIO(GPIO_PORTA, 10)
#define PA11 GPIO(GPIO_PORTA, 11)
#define PA12 GPIO(GPIO_PORTA, 12)
#define PA13 GPIO(GPIO_PORTA, 13)
#define PA14 GPIO(GPIO_PORTA, 14)
#define PA15 GPIO(GPIO_PORTA, 15)
#define PA16 GPIO(GPIO_PORTA, 16)
#define PA17 GPIO(GPIO_PORTA, 17)
#define PA18 GPIO(GPIO_PORTA, 18)
#define PA19 GPIO(GPIO_PORTA, 19)
#define PA20 GPIO(GPIO_PORTA, 20)
#define PA21 GPIO(GPIO_PORTA, 21)
#define PA22 GPIO(GPIO_PORTA, 22)
#define PA23 GPIO(GPIO_PORTA, 23)
#define PA24 GPIO(GPIO_PORTA, 24)
#define PA25 GPIO(GPIO_PORTA, 25)
#define PA27 GPIO(GPIO_PORTA, 27)
#define PA28 GPIO(GPIO_PORTA, 28)
#define PA30 GPIO(GPIO_PORTA, 30)
#define PA31 GPIO(GPIO_PORTA, 31)
#define PB02 GPIO(GPIO_PORTB, 2)
#define PB03 GPIO(GPIO_PORTB, 3)
#define PB08 GPIO(GPIO_PORTB, 8)
#define PB09 GPIO(GPIO_PORTB, 9)
#define PB10 GPIO(GPIO_PORTB, 10)
#define PB11 GPIO(GPIO_PORTB, 11)
#define PB22 GPIO(GPIO_PORTB, 22)
#define PB23 GPIO(GPIO_PORTB, 23)
#endif // ATMEL_START_PINS_H_INCLUDED

296
atmel-samd/asf4/samd21/config/hpl_adc_config.h
View File

@ -1,296 +0,0 @@
/* Auto-generated config file hpl_adc_config.h */
#ifndef HPL_ADC_CONFIG_H
#define HPL_ADC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_ADC_0_ENABLE
#define CONF_ADC_0_ENABLE 1
#endif
// <h> Basic Configuration
// <o> Conversion resolution
// <0x0=>12-bit
// <0x1=>16-bit (averaging must be enabled)
// <0x2=>10-bit
// <0x3=>8-bit
// <i> Defines the bit resolution for the ADC sample values (RESSEL)
// <id> adc_resolution
#ifndef CONF_ADC_0_RESSEL
#define CONF_ADC_0_RESSEL 0x0
#endif
// <o> Reference Selection
// <0x0=>1.0V voltage reference
// <0x1=>1/1.48 VDDANA
// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
// <0x3=>External reference A
// <0x4=>External reference B
// <i> Select the reference for the ADC (REFSEL)
// <id> adc_reference
#ifndef CONF_ADC_0_REFSEL
#define CONF_ADC_0_REFSEL 0x0
#endif
// <o> Prescaler configuration
// <0x0=>Peripheral clock divided by 4
// <0x1=>Peripheral clock divided by 8
// <0x2=>Peripheral clock divided by 16
// <0x3=>Peripheral clock divided by 32
// <0x4=>Peripheral clock divided by 64
// <0x5=>Peripheral clock divided by 128
// <0x6=>Peripheral clock divided by 256
// <0x7=>Peripheral clock divided by 512
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
// <id> adc_prescaler
#ifndef CONF_ADC_0_PRESCALER
#define CONF_ADC_0_PRESCALER 0x0
#endif
// <q> Free Running Mode
// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
// <id> adc_freerunning_mode
#ifndef CONF_ADC_0_FREERUN
#define CONF_ADC_0_FREERUN 0
#endif
// <q> Differential Mode
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
// <id> adc_differential_mode
#ifndef CONF_ADC_0_DIFFMODE
#define CONF_ADC_0_DIFFMODE 0
#endif
// <o> Positive Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x08=>ADC AIN8 pin
// <0x09=>ADC AIN9 pin
// <0x0A=>ADC AIN10 pin
// <0x0B=>ADC AIN11 pin
// <0x0C=>ADC AIN12 pin
// <0x0D=>ADC AIN13 pin
// <0x0E=>ADC AIN14 pin
// <0x0F=>ADC AIN15 pin
// <0x10=>ADC AIN16 pin
// <0x11=>ADC AIN17 pin
// <0x12=>ADC AIN18 pin
// <0x13=>ADC AIN19 pin
// <0x18=>Temperature reference
// <0x19=>Bandgap voltage
// <0x1A=>1/4 scaled core supply
// <0x1B=>1/4 scaled I/O supply
// <0x1C=>DAC output
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
// <id> adc_pinmux_positive
#ifndef CONF_ADC_0_MUXPOS
#define CONF_ADC_0_MUXPOS 0x0
#endif
// <o> Negative Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x18=>Internal ground
// <0x19=>I/O ground
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
// <id> adc_pinmux_negative
#ifndef CONF_ADC_0_MUXNEG
#define CONF_ADC_0_MUXNEG 0x0
#endif
// </h>
// <e> Advanced Configuration
// <id> adc_advanced_settings
#ifndef CONF_ADC_0_ADVANCED_CONFIG
#define CONF_ADC_0_ADVANCED_CONFIG 0
#endif
// <q> Run in standby
// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
// <id> adc_arch_runstdby
#ifndef CONF_ADC_0_RUNSTDBY
#define CONF_ADC_0_RUNSTDBY 0
#endif
// <q>Debug Run
// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
// <id> adc_arch_dbgrun
#ifndef CONF_ADC_0_DBGRUN
#define CONF_ADC_0_DBGRUN 0
#endif
// <q> Left-Adjusted Result
// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
// <id> adc_arch_leftadj
#ifndef CONF_ADC_0_LEFTADJ
#define CONF_ADC_0_LEFTADJ 0
#endif
// <q> Reference Buffer Offset Compensation Enable
// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
// <id> adc_arch_refcomp
#ifndef CONF_ADC_0_REFCOMP
#define CONF_ADC_0_REFCOMP 0
#endif
// <q> Digital Correction Logic Enabled
// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
// <id> adc_arch_corren
#ifndef CONF_ADC_0_CORREN
#define CONF_ADC_0_CORREN 0
#endif
// <o> Offset Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
// <id> adc_arch_offsetcorr
#ifndef CONF_ADC_0_OFFSETCORR
#define CONF_ADC_0_OFFSETCORR 0
#endif
// <o> Gain Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
// <id> adc_arch_gaincorr
#ifndef CONF_ADC_0_GAINCORR
#define CONF_ADC_0_GAINCORR 0
#endif
// <o> Gain Factor Selection
// <0x0=>1x
// <0x1=>2x
// <0x2=>4x
// <0x3=>8x
// <0x4=>16x
// <0xF=>1/2x
// <i> These bits set the gain factor of the ADC gain stage. (GAIN)
// <id> adc_arch_gain
#ifndef CONF_ADC_0_GAIN
#define CONF_ADC_0_GAIN 0x0
#endif
// <o> Adjusting Result / Division Coefficient <0-7>
// <i> These bits define the division coefficient in 2n steps. (ADJRES)
// <id> adc_arch_adjres
#ifndef CONF_ADC_0_ADJRES
#define CONF_ADC_0_ADJRES 0x0
#endif
// <o.0..10> Number of Samples to be Collected
// <0x0=>1 sample
// <0x1=>2 samples
// <0x2=>4 samples
// <0x3=>8 samples
// <0x4=>16 samples
// <0x5=>32 samples
// <0x6=>64 samples
// <0x7=>128 samples
// <0x8=>256 samples
// <0x9=>512 samples
// <0xA=>1024 samples
// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
// <id> adc_arch_samplenum
#ifndef CONF_ADC_0_SAMPLENUM
#define CONF_ADC_0_SAMPLENUM 0x0
#endif
// <o> Sampling Time Length <0-63>
// <i> These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
// <id> adc_arch_samplen
#ifndef CONF_ADC_0_SAMPLEN
#define CONF_ADC_0_SAMPLEN 0
#endif
// <o> Window Monitor Mode
// <0x0=>No window mode
// <0x1=>Mode 1: RESULT above lower threshold
// <0x2=>Mode 2: RESULT beneath upper threshold
// <0x3=>Mode 3: RESULT inside lower and upper threshold
// <0x4=>Mode 4: RESULT outside lower and upper threshold
// <i> These bits enable and define the window monitor mode. (WINMODE)
// <id> adc_arch_winmode
#ifndef CONF_ADC_0_WINMODE
#define CONF_ADC_0_WINMODE 0x0
#endif
// <o> Window Monitor Lower Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
// <id> adc_arch_winlt
#ifndef CONF_ADC_0_WINLT
#define CONF_ADC_0_WINLT 0
#endif
// <o> Window Monitor Upper Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
// <id> adc_arch_winut
#ifndef CONF_ADC_0_WINUT
#define CONF_ADC_0_WINUT 0
#endif
// <o> Number of Input Channels Included in Scan <0-15>
// <i>This register gives the number of input sources included in pin scan. The number of input sources included is INPUTSCAN + 1. 0 disables the input scan feature. (INPUTSCAN)
// <id> adc_arch_inputscan
#ifndef CONF_ADC_0_INPUTSCAN
#define CONF_ADC_0_INPUTSCAN 0
#endif
// <o> Positive Mux Setting Offset <0-15>
// <i>When inputscan is enabled this value define the pin offset, which means that the actual input pin sampled is the muxpos pin + input offset. (INPUTOFFSET)
// <id> adc_arch_inputoffset
#ifndef CONF_ADC_0_INPUTOFFSET
#define CONF_ADC_0_INPUTOFFSET 0
#endif
// </e>
// <e> Event Control
// <id> adc_arch_event_settings
#ifndef CONF_ADC_0_EVENT_CONFIG
#define CONF_ADC_0_EVENT_CONFIG 0
#endif
// <q> Window Monitor Event Out
// <i> Enables event output on window event (WINMONEO)
// <id> adc_arch_winmoneo
#ifndef CONF_ADC_0_WINMONEO
#define CONF_ADC_0_WINMONEO 0
#endif
// <q> Result Ready Event Out
// <i> Enables event output on result ready event (RESRDEO)
// <id> adc_arch_resrdyeo
#ifndef CONF_ADC_0_RESRDYEO
#define CONF_ADC_0_RESRDYEO 0
#endif
// <q> Trigger Synchronization On Event
// <i> Trigger a flush operation and a new conversion on event in (SYNCEI)
// <id> adc_arch_syncei
#ifndef CONF_ADC_0_SYNCEI
#define CONF_ADC_0_SYNCEI 0
#endif
// <q> Trigger Conversion On Event
// <i> Trigger a conversion on event. (STARTEI)
// <id> adc_arch_startei
#ifndef CONF_ADC_0_STARTEI
#define CONF_ADC_0_STARTEI 0
#endif
// </e>
// <<< end of configuration section >>>
#endif // HPL_ADC_CONFIG_H

86
atmel-samd/asf4/samd21/config/hpl_dac_config.h
View File

@ -1,86 +0,0 @@
/* Auto-generated config file hpl_dac_config.h */
#ifndef HPL_DAC_CONFIG_H
#define HPL_DAC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic configuration
// <o> Reference Selection
// <0x00=> Internal 1.0v reference
// <0x01=> AVCC
// <0x02=> External reference
// <id> dac_arch_refsel
#ifndef CONF_DAC_REFSEL
#define CONF_DAC_REFSEL 0
#endif
// </h>
// <e> Advanced Configuration
// <id> dac_advanced_settings
#ifndef CONF_DAC_ADVANCED_CONFIG
#define CONF_DAC_ADVANCED_CONFIG 0
#endif
// <q> Run in standby
// <i> Indicates whether the DAC will continue running in standby sleep mode or not
// <id> dac_arch_runstdby
#ifndef CONF_DAC_RUNSTDBY
#define CONF_DAC_RUNSTDBY 0
#endif
// <q> Bypass DATABUF Write Protection
// <i> Indicate whether DATABUF write protection is bypass
// <id> dac_arch_bdwp
#ifndef CONF_DAC_BDWP
#define CONF_DAC_BDWP 0
#endif
// <q> Voltage Pump Disable
// <i> Indicate whether voltage pump is disable or not
// <id> dac_arch_vpd
#ifndef CONF_DAC_VPD
#define CONF_DAC_VPD 0
#endif
// <q> Left Adjusted Data
// <i> Indicate how the data is adjusted in the Data and Data Buffer register
// <id> dac_arch_leftadj
#ifndef CONF_DAC_LEFTADJ
#define CONF_DAC_LEFTADJ 0
#endif
// <q> Internal Output Enable
// <i> Indicate whether internal output is enable or not
// <id> dac_arch_ioen
#ifndef CONF_DAC_IOEN
#define CONF_DAC_IOEN 0
#endif
// <q> External Output Enable
// <i> Indicate whether external output is enable or not
// <id> dac_arch_eoen
#ifndef CONF_DAC_EOEN
#define CONF_DAC_EOEN 1
#endif
// </e>
// <h> Event configuration
// <q> Data Buffer Empty Event Output
// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not
// <id> dac_arch_emptyeo
#ifndef CONF_DAC_EMPTYEO
#define CONF_DAC_EMPTYEO 0
#endif
// <q> Start Conversion on Event Input
// <i> Indicate whether Start Conversion is enabled and data are loaded from the Data Buffer register to the Data register upon event reception or not
// <id> dac_arch_startei
#ifndef CONF_DAC_STARTEI
#define CONF_DAC_STARTEI 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_DAC_CONFIG_H

3057
atmel-samd/asf4/samd21/config/hpl_dmac_config.h
View File

File diff suppressed because it is too large Load Diff

618
atmel-samd/asf4/samd21/config/hpl_gclk_config.h
View File

@ -1,618 +0,0 @@
/* Auto-generated config file hpl_gclk_config.h */
#ifndef HPL_GCLK_CONFIG_H
#define HPL_GCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> Generic clock generator 0 configuration
// <i> Indicates whether generic clock 0 configuration is enabled or not
// <id> enable_gclk_gen_0
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
#define CONF_GCLK_GENERATOR_0_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_0_RUNSTDBY
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
#define CONF_GCLK_GEN_0_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
// <id> gclk_gen_0_div_sel
#ifndef CONF_GCLK_GEN_0_DIVSEL
#define CONF_GCLK_GEN_0_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_0_oe
#ifndef CONF_GCLK_GEN_0_OE
#define CONF_GCLK_GEN_0_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_0_oov
#ifndef CONF_GCLK_GEN_0_OOV
#define CONF_GCLK_GEN_0_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_0_idc
#ifndef CONF_GCLK_GEN_0_IDC
#define CONF_GCLK_GEN_0_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_0_enable
#ifndef CONF_GCLK_GEN_0_GENEN
#define CONF_GCLK_GEN_0_GENEN 1
#endif
// <y> Generic clock generator 0 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 0
// <id> gclk_gen_0_oscillator
#ifndef CONF_GCLK_GEN_0_SRC
#define CONF_GCLK_GEN_0_SRC GCLK_GENCTRL_SRC_OSC8M
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
// <i>
// <id> gclk_gen_0_div
#ifndef CONF_GCLK_GEN_0_DIV
#define CONF_GCLK_GEN_0_DIV 1
#endif
// </h>
// </e>// <e> Generic clock generator 1 configuration
// <i> Indicates whether generic clock 1 configuration is enabled or not
// <id> enable_gclk_gen_1
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
#define CONF_GCLK_GENERATOR_1_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_1_RUNSTDBY
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
#define CONF_GCLK_GEN_1_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
// <id> gclk_gen_1_div_sel
#ifndef CONF_GCLK_GEN_1_DIVSEL
#define CONF_GCLK_GEN_1_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_1_oe
#ifndef CONF_GCLK_GEN_1_OE
#define CONF_GCLK_GEN_1_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_1_oov
#ifndef CONF_GCLK_GEN_1_OOV
#define CONF_GCLK_GEN_1_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_1_idc
#ifndef CONF_GCLK_GEN_1_IDC
#define CONF_GCLK_GEN_1_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_1_enable
#ifndef CONF_GCLK_GEN_1_GENEN
#define CONF_GCLK_GEN_1_GENEN 0
#endif
// <y> Generic clock generator 1 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SRC
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
// <i>
// <id> gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 1
#endif
// </h>
// </e>// <e> Generic clock generator 2 configuration
// <i> Indicates whether generic clock 2 configuration is enabled or not
// <id> enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
#define CONF_GCLK_GENERATOR_2_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_2_RUNSTDBY
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
#define CONF_GCLK_GEN_2_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
// <id> gclk_gen_2_div_sel
#ifndef CONF_GCLK_GEN_2_DIVSEL
#define CONF_GCLK_GEN_2_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_2_oe
#ifndef CONF_GCLK_GEN_2_OE
#define CONF_GCLK_GEN_2_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_2_oov
#ifndef CONF_GCLK_GEN_2_OOV
#define CONF_GCLK_GEN_2_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_2_idc
#ifndef CONF_GCLK_GEN_2_IDC
#define CONF_GCLK_GEN_2_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
#define CONF_GCLK_GEN_2_GENEN 0
#endif
// <y> Generic clock generator 2 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 2
// <id> gclk_gen_2_oscillator
#ifndef CONF_GCLK_GEN_2_SRC
#define CONF_GCLK_GEN_2_SRC GCLK_GENCTRL_SRC_XOSC
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
// <i>
// <id> gclk_gen_2_div
#ifndef CONF_GCLK_GEN_2_DIV
#define CONF_GCLK_GEN_2_DIV 1
#endif
// </h>
// </e>// <e> Generic clock generator 3 configuration
// <i> Indicates whether generic clock 3 configuration is enabled or not
// <id> enable_gclk_gen_3
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
#define CONF_GCLK_GENERATOR_3_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_3_RUNSTDBY
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
#define CONF_GCLK_GEN_3_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
// <id> gclk_gen_3_div_sel
#ifndef CONF_GCLK_GEN_3_DIVSEL
#define CONF_GCLK_GEN_3_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_3_oe
#ifndef CONF_GCLK_GEN_3_OE
#define CONF_GCLK_GEN_3_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_3_oov
#ifndef CONF_GCLK_GEN_3_OOV
#define CONF_GCLK_GEN_3_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_3_idc
#ifndef CONF_GCLK_GEN_3_IDC
#define CONF_GCLK_GEN_3_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_3_enable
#ifndef CONF_GCLK_GEN_3_GENEN
#define CONF_GCLK_GEN_3_GENEN 0
#endif
// <y> Generic clock generator 3 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 3
// <id> gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SRC
#define CONF_GCLK_GEN_3_SRC GCLK_GENCTRL_SRC_XOSC
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
// <i>
// <id> gclk_gen_3_div
#ifndef CONF_GCLK_GEN_3_DIV
#define CONF_GCLK_GEN_3_DIV 1
#endif
// </h>
// </e>// <e> Generic clock generator 4 configuration
// <i> Indicates whether generic clock 4 configuration is enabled or not
// <id> enable_gclk_gen_4
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
#define CONF_GCLK_GENERATOR_4_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_4_RUNSTDBY
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
#define CONF_GCLK_GEN_4_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
// <id> gclk_gen_4_div_sel
#ifndef CONF_GCLK_GEN_4_DIVSEL
#define CONF_GCLK_GEN_4_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_4_oe
#ifndef CONF_GCLK_GEN_4_OE
#define CONF_GCLK_GEN_4_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_4_oov
#ifndef CONF_GCLK_GEN_4_OOV
#define CONF_GCLK_GEN_4_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_4_idc
#ifndef CONF_GCLK_GEN_4_IDC
#define CONF_GCLK_GEN_4_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_4_enable
#ifndef CONF_GCLK_GEN_4_GENEN
#define CONF_GCLK_GEN_4_GENEN 0
#endif
// <y> Generic clock generator 4 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 4
// <id> gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SRC
#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_XOSC
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
// <i>
// <id> gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
#define CONF_GCLK_GEN_4_DIV 1
#endif
// </h>
// </e>// <e> Generic clock generator 5 configuration
// <i> Indicates whether generic clock 5 configuration is enabled or not
// <id> enable_gclk_gen_5
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
#define CONF_GCLK_GENERATOR_5_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_5_RUNSTDBY
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
#define CONF_GCLK_GEN_5_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
// <id> gclk_gen_5_div_sel
#ifndef CONF_GCLK_GEN_5_DIVSEL
#define CONF_GCLK_GEN_5_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_5_oe
#ifndef CONF_GCLK_GEN_5_OE
#define CONF_GCLK_GEN_5_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_5_oov
#ifndef CONF_GCLK_GEN_5_OOV
#define CONF_GCLK_GEN_5_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_5_idc
#ifndef CONF_GCLK_GEN_5_IDC
#define CONF_GCLK_GEN_5_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_5_enable
#ifndef CONF_GCLK_GEN_5_GENEN
#define CONF_GCLK_GEN_5_GENEN 0
#endif
// <y> Generic clock generator 5 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 5
// <id> gclk_gen_5_oscillator
#ifndef CONF_GCLK_GEN_5_SRC
#define CONF_GCLK_GEN_5_SRC GCLK_GENCTRL_SRC_XOSC
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
// <i>
// <id> gclk_gen_5_div
#ifndef CONF_GCLK_GEN_5_DIV
#define CONF_GCLK_GEN_5_DIV 1
#endif
// </h>
// </e>// <e> Generic clock generator 6 configuration
// <i> Indicates whether generic clock 6 configuration is enabled or not
// <id> enable_gclk_gen_6
#ifndef CONF_GCLK_GENERATOR_6_CONFIG
#define CONF_GCLK_GENERATOR_6_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_6_RUNSTDBY
#ifndef CONF_GCLK_GEN_6_RUNSTDBY
#define CONF_GCLK_GEN_6_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
// <id> gclk_gen_6_div_sel
#ifndef CONF_GCLK_GEN_6_DIVSEL
#define CONF_GCLK_GEN_6_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_6_oe
#ifndef CONF_GCLK_GEN_6_OE
#define CONF_GCLK_GEN_6_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_6_oov
#ifndef CONF_GCLK_GEN_6_OOV
#define CONF_GCLK_GEN_6_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_6_idc
#ifndef CONF_GCLK_GEN_6_IDC
#define CONF_GCLK_GEN_6_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_6_enable
#ifndef CONF_GCLK_GEN_6_GENEN
#define CONF_GCLK_GEN_6_GENEN 0
#endif
// <y> Generic clock generator 6 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 6
// <id> gclk_gen_6_oscillator
#ifndef CONF_GCLK_GEN_6_SRC
#define CONF_GCLK_GEN_6_SRC GCLK_GENCTRL_SRC_XOSC
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 6 division <0x0000-0xFFFF>
// <i>
// <id> gclk_gen_6_div
#ifndef CONF_GCLK_GEN_6_DIV
#define CONF_GCLK_GEN_6_DIV 1
#endif
// </h>
// </e>// <e> Generic clock generator 7 configuration
// <i> Indicates whether generic clock 7 configuration is enabled or not
// <id> enable_gclk_gen_7
#ifndef CONF_GCLK_GENERATOR_7_CONFIG
#define CONF_GCLK_GENERATOR_7_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_7_RUNSTDBY
#ifndef CONF_GCLK_GEN_7_RUNSTDBY
#define CONF_GCLK_GEN_7_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
// <id> gclk_gen_7_div_sel
#ifndef CONF_GCLK_GEN_7_DIVSEL
#define CONF_GCLK_GEN_7_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_7_oe
#ifndef CONF_GCLK_GEN_7_OE
#define CONF_GCLK_GEN_7_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_7_oov
#ifndef CONF_GCLK_GEN_7_OOV
#define CONF_GCLK_GEN_7_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_7_idc
#ifndef CONF_GCLK_GEN_7_IDC
#define CONF_GCLK_GEN_7_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_7_enable
#ifndef CONF_GCLK_GEN_7_GENEN
#define CONF_GCLK_GEN_7_GENEN 0
#endif
// <y> Generic clock generator 7 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 7
// <id> gclk_gen_7_oscillator
#ifndef CONF_GCLK_GEN_7_SRC
#define CONF_GCLK_GEN_7_SRC GCLK_GENCTRL_SRC_XOSC
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
// <i>
// <id> gclk_gen_7_div
#ifndef CONF_GCLK_GEN_7_DIV
#define CONF_GCLK_GEN_7_DIV 1
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_GCLK_CONFIG_H

38
atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h
View File

@ -1,38 +0,0 @@
/* Auto-generated config file hpl_nvmctrl_config.h */
#ifndef HPL_NVMCTRL_CONFIG_H
#define HPL_NVMCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Settings
// <o> Read Mode Selection
// <0x00=> No Miss Penalty
// <0x01=> Low Power
// <0x02=> Deterministic
// <id> nvm_arch_read_mode
#ifndef CONF_NVM_READ_MODE
#define CONF_NVM_READ_MODE 0
#endif
// <o> Power Reduction Mode During Sleep
// <0x00=> Wake On Access
// <0x01=> Wake Up Instant
// <0x03=> Disabled
// <id> nvm_arch_sleepprm
#ifndef CONF_NVM_SLEEPPRM
#define CONF_NVM_SLEEPPRM 0
#endif
// <q> Cache Disable
// <i> Indicate whether cache is disable or not
// <id> nvm_arch_cache
#ifndef CONF_NVM_CACHE
#define CONF_NVM_CACHE 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_NVMCTRL_CONFIG_H

134
atmel-samd/asf4/samd21/config/hpl_pm_config.h
View File

@ -1,134 +0,0 @@
/* Auto-generated config file hpl_pm_config.h */
#ifndef HPL_PM_CONFIG_H
#define HPL_PM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> CPU Clock Settings
// <y> CPU Clock source
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
// <y> CPU clock Prescalar
// <PM_CPUSEL_CPUDIV_DIV1_Val"> 1
// <PM_CPUSEL_CPUDIV_DIV2_Val"> 2
// <PM_CPUSEL_CPUDIV_DIV4_Val"> 4
// <PM_CPUSEL_CPUDIV_DIV8_Val"> 8
// <PM_CPUSEL_CPUDIV_DIV16_Val"> 16
// <PM_CPUSEL_CPUDIV_DIV32_Val"> 32
// <PM_CPUSEL_CPUDIV_DIV64_Val"> 64
// <PM_CPUSEL_CPUDIV_DIV128_Val"> 128
// <i> Prescalar for Main CPU clock
// <id> cpu_div
#ifndef CONF_CPU_DIV
#define CONF_CPU_DIV PM_CPUSEL_CPUDIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 0
#endif
// </h>
// <h> APBA Clock Select
// <y> APBA clock prescalar
// <PM_APBASEL_APBADIV_DIV1"> 1
// <PM_APBASEL_APBADIV_DIV2"> 2
// <PM_APBASEL_APBADIV_DIV4"> 4
// <PM_APBASEL_APBADIV_DIV8"> 8
// <PM_APBASEL_APBADIV_DIV16"> 16
// <PM_APBASEL_APBADIV_DIV32"> 32
// <PM_APBASEL_APBADIV_DIV64"> 64
// <PM_APBASEL_APBADIV_DIV128"> 128
// <i> APBA clock prescalar
// <id> apba_div
#ifndef CONF_APBA_DIV
#define CONF_APBA_DIV PM_APBASEL_APBADIV_DIV1
#endif
// </h>
#if CONF_APBA_DIV < CONF_CPU_DIV
#warning APBA DIV cannot less than CPU DIV
#endif
// <h> APBB Clock Select
// <y> APBB clock prescalar
// <PM_APBBSEL_APBBDIV_DIV1"> 1
// <PM_APBBSEL_APBBDIV_DIV2"> 2
// <PM_APBBSEL_APBBDIV_DIV4"> 4
// <PM_APBBSEL_APBBDIV_DIV8"> 8
// <PM_APBBSEL_APBBDIV_DIV16"> 16
// <PM_APBBSEL_APBBDIV_DIV32"> 32
// <PM_APBBSEL_APBBDIV_DIV64"> 64
// <PM_APBBSEL_APBBDIV_DIV128"> 128
// <i> APBB clock prescalar
// <id> apbb_div
#ifndef CONF_APBB_DIV
#define CONF_APBB_DIV PM_APBBSEL_APBBDIV_DIV1
#endif
// </h>
#if CONF_APBB_DIV < CONF_CPU_DIV
#warning APBB DIV cannot less than CPU DIV
#endif
// <h> APBC Clock Select
// <y> APBC clock prescalar
// <PM_APBCSEL_APBCDIV_DIV1"> 1
// <PM_APBCSEL_APBCDIV_DIV2"> 2
// <PM_APBCSEL_APBCDIV_DIV4"> 4
// <PM_APBCSEL_APBCDIV_DIV8"> 8
// <PM_APBCSEL_APBCDIV_DIV16"> 16
// <PM_APBCSEL_APBCDIV_DIV32"> 32
// <PM_APBCSEL_APBCDIV_DIV64"> 64
// <PM_APBCSEL_APBCDIV_DIV128"> 128
// <i> APBC clock prescalar
// <id> apbc_div
#ifndef CONF_APBC_DIV
#define CONF_APBC_DIV PM_APBCSEL_APBCDIV_DIV1
#endif
// </h>
#if CONF_APBC_DIV < CONF_CPU_DIV
#warning APBC DIV cannot less than CPU DIV
#endif
// </e>
// <<< end of configuration section >>>
#endif // HPL_PM_CONFIG_H

117
atmel-samd/asf4/samd21/config/hpl_rtc_config.h
View File

@ -1,117 +0,0 @@
/* Auto-generated config file hpl_rtc_config.h */
#ifndef HPL_RTC_CONFIG_H
#define HPL_RTC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic settings
#ifndef CONF_RTC_ENABLE
#define CONF_RTC_ENABLE 1
#endif
// <o> Prescaler configuration
// <0x0=>Peripheral clock divided by 1
// <0x1=>Peripheral clock divided by 2
// <0x2=>Peripheral clock divided by 4
// <0x3=>Peripheral clock divided by 8
// <0x4=>Peripheral clock divided by 16
// <0x5=>Peripheral clock divided by 32
// <0x6=>Peripheral clock divided by 64
// <0x7=>Peripheral clock divided by 128
// <0x8=>Peripheral clock divided by 256
// <0x9=>Peripheral clock divided by 512
// <0xA=>Peripheral clock divided by 1024
// <i> These bits define the RTC clock relative to the peripheral clock
// <id> rtc_arch_prescaler
#ifndef CONF_RTC_PRESCALER
#define CONF_RTC_PRESCALER 0x0
#endif
// <o> Compare Value <1-4294967295>
// <i> These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value),
// <i> by default 1M clock input, 1 prescaler, 1024 compare value, the ticks period equals to 1ms.
// <id> rtc_arch_comp_val
#ifndef CONF_RTC_COMP_VAL
#define CONF_RTC_COMP_VAL 1024
#endif
// <e> Event control
// <id> rtc_event_control
#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
#define CONF_RTC_EVENT_CONTROL_ENABLE 0
#endif
// <q> Periodic Interval 0 Event Output
// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
// <id> rtc_pereo0
#ifndef CONF_RTC_PEREO0
#define CONF_RTC_PEREO0 0
#endif
// <q> Periodic Interval 1 Event Output
// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
// <id> rtc_pereo1
#ifndef CONF_RTC_PEREO1
#define CONF_RTC_PEREO1 0
#endif
// <q> Periodic Interval 2 Event Output
// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
// <id> rtc_pereo2
#ifndef CONF_RTC_PEREO2
#define CONF_RTC_PEREO2 0
#endif
// <q> Periodic Interval 3 Event Output
// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
// <id> rtc_pereo3
#ifndef CONF_RTC_PEREO3
#define CONF_RTC_PEREO3 0
#endif
// <q> Periodic Interval 4 Event Output
// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
// <id> rtc_pereo4
#ifndef CONF_RTC_PEREO4
#define CONF_RTC_PEREO4 0
#endif
// <q> Periodic Interval 5 Event Output
// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
// <id> rtc_pereo5
#ifndef CONF_RTC_PEREO5
#define CONF_RTC_PEREO5 0
#endif
// <q> Periodic Interval 6 Event Output
// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
// <id> rtc_pereo6
#ifndef CONF_RTC_PEREO6
#define CONF_RTC_PEREO6 0
#endif
// <q> Periodic Interval 7 Event Output
// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
// <id> rtc_pereo7
#ifndef CONF_RTC_PEREO7
#define CONF_RTC_PEREO7 0
#endif
// <q> Compare 0 Event Output
// <i> This bit indicates whether Compare O event is enabled and will be generated
// <id> rtc_cmpeo0
#ifndef CONF_RTC_COMPE0
#define CONF_RTC_COMPE0 0
#endif
// <q> Overflow Event Output
// <i> This bit indicates whether Overflow event is enabled and will be generated
// <id> rtc_ovfeo
#ifndef CONF_RTC_OVFEO
#define CONF_RTC_OVFEO 0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_RTC_CONFIG_H

534
atmel-samd/asf4/samd21/config/hpl_sercom_config.h
View File

@ -1,534 +0,0 @@
/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// Enable configuration of module
#ifndef CONF_SERCOM_0_SPI_ENABLE
#define CONF_SERCOM_0_SPI_ENABLE 1
#endif
// Set module in SPI Master mode
#ifndef CONF_SERCOM_0_SPI_MODE
#define CONF_SERCOM_0_SPI_MODE 0x03
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable receive buffer to receive data from slave (RXEN)
// <id> spi_master_rx_enable
#ifndef CONF_SERCOM_0_SPI_RXEN
#define CONF_SERCOM_0_SPI_RXEN 0x1
#endif
// <o> Character Size
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
// <0x0=>8 bits
// <0x1=>9 bits
// <id> spi_master_character_size
#ifndef CONF_SERCOM_0_SPI_CHSIZE
#define CONF_SERCOM_0_SPI_CHSIZE 0x0
#endif
// <o> Baud rate <1-12000000>
// <i> The SPI data transfer rate
// <id> spi_master_baud_rate
#ifndef CONF_SERCOM_0_SPI_BAUD
#define CONF_SERCOM_0_SPI_BAUD 50000
#endif
// </h>
// <e> Advanced Configuration
// <id> spi_master_advanced
#ifndef CONF_SERCOM_0_SPI_ADVANCED
#define CONF_SERCOM_0_SPI_ADVANCED 0
#endif
// <o> Dummy byte <0x00-0x1ff>
// <id> spi_master_dummybyte
// <i> Dummy byte used when reading data from the slave without sending any data
#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE
#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff
#endif
// <o> Data Order
// <0=>MSB first
// <1=>LSB first
// <i> I least significant or most significant bit is shifted out first (DORD)
// <id> spi_master_arch_dord
#ifndef CONF_SERCOM_0_SPI_DORD
#define CONF_SERCOM_0_SPI_DORD 0x0
#endif
// <o> Clock Polarity
// <0=>SCK is low when idle
// <1=>SCK is high when idle
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
// <id> spi_master_arch_cpol
#ifndef CONF_SERCOM_0_SPI_CPOL
#define CONF_SERCOM_0_SPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Sample input on leading edge
// <0x1=>Sample input on trailing edge
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
// <id> spi_master_arch_cpha
#ifndef CONF_SERCOM_0_SPI_CPHA
#define CONF_SERCOM_0_SPI_CPHA 0x0
#endif
// <o> Immediate Buffer Overflow Notification
// <i> Controls when OVF is asserted (IBON)
// <0x0=>In data stream
// <0x1=>On buffer overflow
// <id> spi_master_arch_ibon
#ifndef CONF_SERCOM_0_SPI_IBON
#define CONF_SERCOM_0_SPI_IBON 0x0
#endif
// <q> Run in stand-by
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
// <id> spi_master_arch_runstdby
#ifndef CONF_SERCOM_0_SPI_RUNSTDBY
#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
// <0=>Keep running
// <1=>Halt
// <id> spi_master_arch_dbgstop
#ifndef CONF_SERCOM_0_SPI_DBGSTOP
#define CONF_SERCOM_0_SPI_DBGSTOP 0
#endif
// </e>
// Address mode disabled in master mode
#ifndef CONF_SERCOM_0_SPI_AMODE_EN
#define CONF_SERCOM_0_SPI_AMODE_EN 0
#endif
#ifndef CONF_SERCOM_0_SPI_AMODE
#define CONF_SERCOM_0_SPI_AMODE 0
#endif
#ifndef CONF_SERCOM_0_SPI_ADDR
#define CONF_SERCOM_0_SPI_ADDR 0
#endif
#ifndef CONF_SERCOM_0_SPI_ADDRMASK
#define CONF_SERCOM_0_SPI_ADDRMASK 0
#endif
#ifndef CONF_SERCOM_0_SPI_SSDE
#define CONF_SERCOM_0_SPI_SSDE 0
#endif
#ifndef CONF_SERCOM_0_SPI_MSSEN
#define CONF_SERCOM_0_SPI_MSSEN 0x0
#endif
#ifndef CONF_SERCOM_0_SPI_PLOADEN
#define CONF_SERCOM_0_SPI_PLOADEN 0
#endif
// <o> Receive Data Pinout
// <0x0=>PAD[0]
// <0x1=>PAD[1]
// <0x2=>PAD[2]
// <0x3=>PAD[3]
// <id> spi_master_rxpo
#ifndef CONF_SERCOM_0_SPI_RXPO
#define CONF_SERCOM_0_SPI_RXPO 2
#endif
// <o> Transmit Data Pinout
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK
// <id> spi_master_txpo
#ifndef CONF_SERCOM_0_SPI_TXPO
#define CONF_SERCOM_0_SPI_TXPO 0
#endif
// Calculate baud register value from requested baudrate value
#ifndef CONF_SERCOM_0_SPI_BAUD_RATE
#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1
#endif
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_1_I2CM_ENABLE
#define CONF_SERCOM_1_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_1_I2CM_BAUD
#define CONF_SERCOM_1_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_1_I2CM_TRISE
#define CONF_SERCOM_1_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
#define CONF_SERCOM_1_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_1_I2CM_INACTOUT
#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_1_I2CM_SPEED
#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_1_I2CM_TRISE
#define CONF_SERCOM_1_I2CM_TRISE 215
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \
- (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \
/ 1000)) \
* 10 \
+ 5) \
/ (CONF_SERCOM_1_I2CM_BAUD * 10))
#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_1_I2CM_BAUD_RATE \
((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
#include <peripheral_clk_config.h>
#ifndef CONF_SERCOM_2_USART_ENABLE
#define CONF_SERCOM_2_USART_ENABLE 1
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable input buffer in SERCOM module
// <id> usart_rx_enable
#ifndef CONF_SERCOM_2_USART_RXEN
#define CONF_SERCOM_2_USART_RXEN 1
#endif
// <q> Transmitt buffer enable
// <i> Enable output buffer in SERCOM module
// <id> usart_tx_enable
#ifndef CONF_SERCOM_2_USART_TXEN
#define CONF_SERCOM_2_USART_TXEN 1
#endif
// <o> Frame parity
// <0x0=>No parity
// <0x1=>Even parity
// <0x2=>Odd parity
// <i> Parity bit mode for USART frame
// <id> usart_parity
#ifndef CONF_SERCOM_2_USART_PARITY
#define CONF_SERCOM_2_USART_PARITY 0x0
#endif
// <o> Character Size
// <0x0=>8 bits
// <0x1=>9 bits
// <0x5=>5 bits
// <0x6=>6 bits
// <0x7=>7 bits
// <i> Data character size in USART frame
// <id> usart_character_size
#ifndef CONF_SERCOM_2_USART_CHSIZE
#define CONF_SERCOM_2_USART_CHSIZE 0x0
#endif
// <o> Stop Bit
// <0=>One stop bit
// <1=>Two stop bits
// <i> Number of stop bits in USART frame
// <id> usart_stop_bit
#ifndef CONF_SERCOM_2_USART_SBMODE
#define CONF_SERCOM_2_USART_SBMODE 0
#endif
// <o> Baud rate <1-3000000>
// <i> USART baud rate setting
// <id> usart_baud_rate
#ifndef CONF_SERCOM_2_USART_BAUD
#define CONF_SERCOM_2_USART_BAUD 9600
#endif
// </h>
// <e> Advanced configuration
// <id> usart_advanced
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
#endif
// <q> Run in stand-by
// <i> Keep the module running in standby sleep mode
// <id> usart_arch_runstdby
#ifndef CONF_SERCOM_2_USART_RUNSTDBY
#define CONF_SERCOM_2_USART_RUNSTDBY 0
#endif
// <q> Immediate Buffer Overflow Notification
// <i> Controls when the BUFOVF status bit is asserted
// <id> usart_arch_ibon
#ifndef CONF_SERCOM_2_USART_IBON
#define CONF_SERCOM_2_USART_IBON 0
#endif
// <q> Start of Frame Detection Enable
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
// <id> usart_arch_sfde
#ifndef CONF_SERCOM_2_USART_SFDE
#define CONF_SERCOM_2_USART_SFDE 0
#endif
// <q> Collision Detection Enable
// <i> Collision detection enable
// <id> usart_arch_cloden
#ifndef CONF_SERCOM_2_USART_CLODEN
#define CONF_SERCOM_2_USART_CLODEN 0
#endif
// <o> Operating Mode
// <0x0=>USART with external clock
// <0x1=>USART with internal clock
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
// <id> usart_arch_clock_mode
#ifndef CONF_SERCOM_2_USART_MODE
#define CONF_SERCOM_2_USART_MODE 0x1
#endif
// <o> Sample Rate
// <0x0=>16x arithmetic
// <0x1=>16x fractional
// <0x2=>8x arithmetic
// <0x3=>8x fractional
// <0x3=>3x
// <i> How many over-sampling bits used when samling data state
// <id> usart_arch_sampr
#ifndef CONF_SERCOM_2_USART_SAMPR
#define CONF_SERCOM_2_USART_SAMPR 0x0
#endif
// <o> Sample Adjustment
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
// <i> Adjust which samples to use for data sampling in asynchronous mode
// <id> usart_arch_sampa
#ifndef CONF_SERCOM_2_USART_SAMPA
#define CONF_SERCOM_2_USART_SAMPA 0x0
#endif
// <o> Fractional Part <0-7>
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
// <id> usart_arch_fractional
#ifndef CONF_SERCOM_2_USART_FRACTIONAL
#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
#endif
// <o> Data Order
// <0=>MSB is transmitted first
// <1=>LSB is transmitted first
// <i> Data order of the data bits in the frame
// <id> usart_arch_dord
#ifndef CONF_SERCOM_2_USART_DORD
#define CONF_SERCOM_2_USART_DORD 1
#endif
// Does not do anything in UART mode
#define CONF_SERCOM_2_USART_CPOL 0
// <o> Encoding Format
// <0=>No encoding
// <1=>IrDA encoded
// <id> usart_arch_enc
#ifndef CONF_SERCOM_2_USART_ENC
#define CONF_SERCOM_2_USART_ENC 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> usart_arch_dbgstop
#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_2_USART_CMODE
#define CONF_SERCOM_2_USART_CMODE 0
#endif
#ifndef CONF_SERCOM_2_USART_RXPO
#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA09 */
#endif
#ifndef CONF_SERCOM_2_USART_TXPO
#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA08 */
#endif
/* Set correct parity settings in register interface based on PARITY setting */
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 0
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 1
#endif
// Calculate BAUD register value in UART mode
#if CONF_SERCOM_2_USART_SAMPR == 0
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 1
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 2
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 3
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 4
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H

678
atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h
View File

@ -1,678 +0,0 @@
/* Auto-generated config file hpl_sysctrl_config.h */
#ifndef HPL_SYSCTRL_CONFIG_H
#define HPL_SYSCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#define CONF_DFLL_OPEN_LOOP_MODE 0
#define CONF_DFLL_CLOSED_LOOP_MODE 1
#define CONF_XOSC_STARTUP_TIME_31MCS 0
#define CONF_XOSC_STARTUP_TIME_61MCS 1
#define CONF_XOSC_STARTUP_TIME_122MCS 2
#define CONF_XOSC_STARTUP_TIME_244MCS 3
#define CONF_XOSC_STARTUP_TIME_488MCS 4
#define CONF_XOSC_STARTUP_TIME_977MCS 5
#define CONF_XOSC_STARTUP_TIME_1953MCS 6
#define CONF_XOSC_STARTUP_TIME_3906MCS 7
#define CONF_XOSC_STARTUP_TIME_7813MCS 8
#define CONF_XOSC_STARTUP_TIME_15625MCS 9
#define CONF_XOSC_STARTUP_TIME_31250MCS 10
#define CONF_XOSC_STARTUP_TIME_62500MCS 11
#define CONF_XOSC_STARTUP_TIME_125000MCS 12
#define CONF_XOSC_STARTUP_TIME_250000MCS 13
#define CONF_XOSC_STARTUP_TIME_500000MCS 14
#define CONF_XOSC_STARTUP_TIME_1000000MCS 15
#define CONF_OSC_STARTUP_TIME_92MCS 0
#define CONF_OSC_STARTUP_TIME_122MCS 1
#define CONF_OSC_STARTUP_TIME_183MCS 2
#define CONF_OSC_STARTUP_TIME_305MCS 3
#define CONF_OSC_STARTUP_TIME_549MCS 4
#define CONF_OSC_STARTUP_TIME_1038MCS 5
#define CONF_OSC_STARTUP_TIME_2014MCS 6
#define CONF_OSC_STARTUP_TIME_3967MCS 7
#define CONF_XOSC32K_STARTUP_TIME_122MCS 0
#define CONF_XOSC32K_STARTUP_TIME_1068MCS 1
#define CONF_XOSC32K_STARTUP_TIME_65592MCS 2
#define CONF_XOSC32K_STARTUP_TIME_125092MCS 3
#define CONF_XOSC32K_STARTUP_TIME_500092MCS 4
#define CONF_XOSC32K_STARTUP_TIME_1000092MCS 5
#define CONF_XOSC32K_STARTUP_TIME_2000092MCS 6
#define CONF_XOSC32K_STARTUP_TIME_4000092MCS 7
// <e> 8MHz Internal Oscillator Configuration
// <i> Indicates whether configuration for OSC8M is enabled or not
// <id> enable_osc8m
#ifndef CONF_OSC8M_CONFIG
#define CONF_OSC8M_CONFIG 1
#endif
// <h> 8MHz Internal Oscillator (OSC8M) Control
// <q> Internal 8M Oscillator Enable
// <i> Indicates whether Internal 8 Mhz Oscillator is enabled or not
// <id> osc8m_arch_enable
#ifndef CONF_OSC8M_ENABLE
#define CONF_OSC8M_ENABLE 1
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not.
// <i> If enabled, the oscillator will only be running when requested by a peripheral.
// <i> If disabled, the oscillator will always be running when enabled.
// <id> osc8m_arch_ondemand
#ifndef CONF_OSC8M_ONDEMAND
#define CONF_OSC8M_ONDEMAND 1
#endif
// <q> Run In Standby
// <i> Run In standby Mode
// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
// <id> osc8m_arch_runstdby
#ifndef CONF_OSC8M_RUNSTDBY
#define CONF_OSC8M_RUNSTDBY 0
#endif
// <y> Prescaler
// <SYSCTRL_OSC8M_PRESC_0_Val"> 1
// <SYSCTRL_OSC8M_PRESC_1_Val"> 2
// <SYSCTRL_OSC8M_PRESC_2_Val"> 4
// <SYSCTRL_OSC8M_PRESC_3_Val"> 8
// <i> Prescaler for Internal 8Mhz OSC
// <i> Default: No Prescaling
// <id> osc8m_presc
#ifndef CONF_OSC8M_PRESC
#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val
#endif
// <q> Overwrite Default Osc Calibration
// <i> Overwrite Default Osc Calibration
// <id> osc8m_arch_overwrite_calibration
#ifndef CONF_OSC8M_OVERWRITE_CALIBRATION
#define CONF_OSC8M_OVERWRITE_CALIBRATION 0
#endif
// <o>Osc Calibration Value <0-65535>
// <i> Set the Oscillator Calibration Value
// <i> Default: 1
// <id> osc8m_arch_calib
#ifndef CONF_OSC8M_CALIB
#define CONF_OSC8M_CALIB 0
#endif
// </h>
// </e>
// <e> 32kHz Internal Oscillator Configuration
// <i> Indicates whether configuration for OSC32K is enabled or not
// <id> enable_osc32k
#ifndef CONF_OSC32K_CONFIG
#define CONF_OSC32K_CONFIG 0
#endif
// <h> 32kHz Internal Oscillator (OSC32K) Control
// <q> Internal 32K Oscillator Enable
// <i> Indicates whether Internal 32K Oscillator is enabled or not
// <id> osc32k_arch_enable
#ifndef CONF_OSC32K_ENABLE
#define CONF_OSC32K_ENABLE 0
#endif
// <q> On Demand Control
// <i> Enable On Demand
// <i> If this bit is 0: The oscillator is always on, if enabled.
// <i> If this bit is 1, the oscillator will only be running when requested by a peripheral.
// <id> osc32k_arch_ondemand
#ifndef CONF_OSC32K_ONDEMAND
#define CONF_OSC32K_ONDEMAND 1
#endif
// <q> Run In Standby
// <i> Run In standby Mode
// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
// <id> osc32k_arch_runstdby
#ifndef CONF_OSC32K_RUNSTDBY
#define CONF_OSC32K_RUNSTDBY 0
#endif
// <q> Enable 32Khz Output
// <i> Enable 32 Khz Output
// <id> osc32k_arch_en32k
#ifndef CONF_OSC32K_EN32K
#define CONF_OSC32K_EN32K 0
#endif
// <q> Enable 1K
// <i> Enable 1K
// <id> osc32k_arch_en1k
#ifndef CONF_OSC32K_EN1K
#define CONF_OSC32K_EN1K 0
#endif
// <q> Write Lock
// <i> Write Lock
// <id> osc32k_arch_wrtlock
#ifndef CONF_OSC32K_WRTLOCK
#define CONF_OSC32K_WRTLOCK 0
#endif
// <y> Start up time for the 32K Oscillator
// <CONF_OSC_STARTUP_TIME_92MCS"> 3 Clock Cycles (92us)
// <CONF_OSC_STARTUP_TIME_122MCS"> 4 Clock Cycles (122us)
// <CONF_OSC_STARTUP_TIME_183MCS"> 6 Clock Cycles (183us)
// <CONF_OSC_STARTUP_TIME_305MCS"> 10 Clock Cycles (305us)
// <CONF_OSC_STARTUP_TIME_549MCS"> 18 Clock Cycles (549us)
// <CONF_OSC_STARTUP_TIME_1038MCS"> 34 Clock Cycles (1038us)
// <CONF_OSC_STARTUP_TIME_2014MCS"> 66 Clock Cycles (2014us)
// <CONF_OSC_STARTUP_TIME_3967MCS"> 130 Clock Cycles (3967us)
// <i> Start Up Time for the 32K Oscillator
// <i> Default: 10 Clock Cycles (305us)
// <id> osc32k_arch_startup
#ifndef CONF_OSC32K_STARTUP
#define CONF_OSC32K_STARTUP CONF_OSC_STARTUP_TIME_92MCS
#endif
// <q> Overwrite Default Osc Calibration
// <i> Overwrite Default Osc Calibration
// <id> osc32k_arch_overwrite_calibration
#ifndef CONF_OSC32K_OVERWRITE_CALIBRATION
#define CONF_OSC32K_OVERWRITE_CALIBRATION 0
#endif
// <o>Osc Calibration Value <0-65535>
// <i> Set the Oscillator Calibration Value
// <i> Default: 0
// <id> osc32k_arch_calib
#ifndef CONF_OSC32K_CALIB
#define CONF_OSC32K_CALIB 0
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 0
#endif
// <h> 32kHz External Crystal Oscillator (XOSC32K) Control
// <q> External 32K Oscillator Enable
// <i> Indicates whether External 32K Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 0
#endif
// <q> On Demand
// <i> Enable On Demand.
// <i> If this bit is 0: The oscillator is always on, if enabled.
// <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 1
#endif
// <q> Run In Standby
// <i> Run In standby Mode
// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 0
#endif
// <q> Enable 1K
// <i> Enable 1K
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 0
#endif
// <q> Enable 32Khz Output
// <i> Enable 32 Khz Output
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 0
#endif
// <q> Enable XTAL
// <i> Enable XTAL
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 0
#endif
// <q> Write Lock
// <i> Write Lock
// <id> xosc32k_arch_wrtlock
#ifndef CONF_XOSC32K_WRTLOCK
#define CONF_XOSC32K_WRTLOCK 0
#endif
// <q> Automatic Amplitude Control Enable
// <i> Indicates whether Automatic Amplitude Control is Enabled or not
// <id> xosc32k_arch_aampen
#ifndef CONF_XOSC32K_AAMPEN
#define CONF_XOSC32K_AAMPEN 0
#endif
// <y> Start up time for the 32K Oscillator
// <CONF_XOSC32K_STARTUP_TIME_122MCS"> 122 us
// <CONF_XOSC32K_STARTUP_TIME_1068MCS"> 1068 us
// <CONF_XOSC32K_STARTUP_TIME_65592MCS"> 62592 us
// <CONF_XOSC32K_STARTUP_TIME_125092MCS"> 1125092 us
// <CONF_XOSC32K_STARTUP_TIME_500092MCS"> 500092 us
// <CONF_XOSC32K_STARTUP_TIME_1000092MCS"> 1000092 us
// <CONF_XOSC32K_STARTUP_TIME_2000092MCS"> 2000092 us
// <CONF_XOSC32K_STARTUP_TIME_4000092MCS"> 4000092 us
// <i> Start Up Time for the 32K Oscillator
// <i> Default: 122 us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP CONF_XOSC32K_STARTUP_TIME_122MCS
#endif
// </h>
// </e>
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for External Multipurpose Osc is enabled or not
// <id> enable_xosc
#ifndef CONF_XOSC_CONFIG
#define CONF_XOSC_CONFIG 0
#endif
// <o> Frequency <400000-32000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC_FREQUENCY 400000
#endif
// <h> External Multipurpose Crystal Oscillator (XOSC) Control
// <q> Enable
// <i> Indicates whether External Multipurpose Oscillator is enabled or not
// <id> xosc_arch_enable
#ifndef CONF_XOSC_ENABLE
#define CONF_XOSC_ENABLE 0
#endif
// <q> On Demand
// <i> Enable On Demand
// <i> If this bit is 0: The oscillator is always on, if enabled.
// <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
// <id> xosc_arch_ondemand
#ifndef CONF_XOSC_ONDEMAND
#define CONF_XOSC_ONDEMAND 1
#endif
// <q> Run In Standby
// <i> Run In standby Mode
// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
// <id> xosc_arch_runstdby
#ifndef CONF_XOSC_RUNSTDBY
#define CONF_XOSC_RUNSTDBY 0
#endif
// <q> Enable XTAL
// <i> Enable XTAL
// <id> xosc_arch_xtalen
#ifndef CONF_XOSC_XTALEN
#define CONF_XOSC_XTALEN 0
#endif
// <q> Automatic Amplitude Control Enable
// <i> Indicates whether Automatic Amplitude Control is Enabled or not
// <id> xosc_arch_ampgc
#ifndef CONF_XOSC_AMPGC
#define CONF_XOSC_AMPGC 0
#endif
// <y> Gain of the Oscillator
// <SYSCTRL_XOSC_GAIN_0_Val"> 2Mhz
// <SYSCTRL_XOSC_GAIN_1_Val"> 4Mhz
// <SYSCTRL_XOSC_GAIN_2_Val"> 8Mhz
// <SYSCTRL_XOSC_GAIN_3_Val"> 16Mhz
// <SYSCTRL_XOSC_GAIN_4_Val"> 30Mhz
// <i> Select the Gain of the oscillator
// <id> xosc_arch_gain
#ifndef CONF_XOSC_GAIN
#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val
#endif
// <y> Start up time for the External Oscillator
// <CONF_XOSC_STARTUP_TIME_31MCS"> 31 us
// <CONF_XOSC_STARTUP_TIME_61MCS"> 61 us
// <CONF_XOSC_STARTUP_TIME_122MCS"> 122 us
// <CONF_XOSC_STARTUP_TIME_244MCS"> 244 us
// <CONF_XOSC_STARTUP_TIME_488MCS"> 488 us
// <CONF_XOSC_STARTUP_TIME_977MCS"> 977 us
// <CONF_XOSC_STARTUP_TIME_1953MCS"> 1953 us
// <CONF_XOSC_STARTUP_TIME_3906MCS"> 3906 us
// <CONF_XOSC_STARTUP_TIME_7813MCS"> 7813 us
// <CONF_XOSC_STARTUP_TIME_15625MCS"> 15625 us
// <CONF_XOSC_STARTUP_TIME_31250MCS"> 31250 us
// <CONF_XOSC_STARTUP_TIME_62500MCS"> 62500 us
// <CONF_XOSC_STARTUP_TIME_125000MCS"> 125000 us
// <CONF_XOSC_STARTUP_TIME_250000MCS"> 250000 us
// <CONF_XOSC_STARTUP_TIME_500000MCS"> 500000 us
// <CONF_XOSC_STARTUP_TIME_1000000MCS"> 1000000 us
// <i> Start Up Time for the External Oscillator
// <i> Default: 31 us
// <id> xosc_arch_startup
#ifndef CONF_XOSC_STARTUP
#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
// <q> Write Lock
// <i> Locks the OSCULP32K register for future writes to fix the OSCULP32K configuration
// <id> osculp32k_arch_wrtlock
#ifndef CONF_OSCULP32K_WRTLOCK
#define CONF_OSCULP32K_WRTLOCK 0
#endif
// <q> Overwrite Default Osc Calibration
// <i> Overwrite Default Osc Calibration
// <id> osculp32k_arch_overwrite_calibration
#ifndef CONF_OSCULP32K_OVERWRITE_CALIBRATION
#define CONF_OSCULP32K_OVERWRITE_CALIBRATION 0
#endif
// <o>Osc Calibration Value <0-255>
// <i> Set the Oscillator Calibration Value
// <i> Default: 0
// <id> osculp32k_arch_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0
#endif
// </h>
// </e>
// <e> DFLL Configuration
// <i> Indicates whether configuration for DFLL is enabled or not
// <id> enable_dfll48m
#ifndef CONF_DFLL_CONFIG
#define CONF_DFLL_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source.
// <id> dfll48m_ref_clock
#ifndef CONF_DFLL_GCLK
#define CONF_DFLL_GCLK GCLK_CLKCTRL_GEN_GCLK4_Val
#endif
// <h> DFLL Control
// <q> DFLL Enable
// <i> Indicates whether DFLL is enabled or not
// <id> dfll48m_arch_enable
#ifndef CONF_DFLL_ENABLE
#define CONF_DFLL_ENABLE 0
#endif
// <q> Wait Lock
// <i> Indicates whether Wait Lock is Enables or not
// <id> dfll48m_arch_waitlock
#ifndef CONF_DFLL_WAITLOCK
#define CONF_DFLL_WAITLOCK 0
#endif
// <q> Bypass Coarse Lock
// <i> Indicates whether Bypass coarse lock is enabled or not
// <id> dfll48m_arch_bplckc
#ifndef CONF_DFLL_BPLCKC
#define CONF_DFLL_BPLCKC 0
#endif
// <q> Quick Lock Disable
// <i> Quick Lock Disable
// <id> dfll48m_arch_qldis
#ifndef CONF_DFLL_QLDIS
#define CONF_DFLL_QLDIS 0
#endif
// <q> Chill Cycle Disable
// <i> Chill Cycle Disable
// <id> dfll48m_arch_ccdis
#ifndef CONF_DFLL_CCDIS
#define CONF_DFLL_CCDIS 0
#endif
// <q> On Demand
// <i> Enable On Demand
// <i> If this bit is 0: The DFLL is always on, if enabled.
// <i> If this bit is 1: the DFLL will only be running when requested by a peripheral.
// <id> dfll48m_arch_ondemand
#ifndef CONF_DFLL_ONDEMAND
#define CONF_DFLL_ONDEMAND 1
#endif
// <q> Run In Standby
// <i> Run In standby Mode
// <i> If this bit is 0: The DFLL is disabled in standby sleep mode.
// <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
// <id> dfll48m_arch_runstdby
#ifndef CONF_DFLL_RUNSTDBY
#define CONF_DFLL_RUNSTDBY 0
#endif
// <q> USB Clock Recovery Mode
// <i> USB Clock Recovery Mode
// <id> dfll48m_arch_usbcrm
#ifndef CONF_DFLL_USBCRM
#define CONF_DFLL_USBCRM 1
#endif
#if CONF_DFLL_USBCRM == 1
#if CONF_DFLL_QLDIS == 1
#warning QLDIS must be cleared to speed up the lock phase
#endif
#if CONF_DFLL_CCDIS == 0
#warning CCDIS should be set to speed up the lock phase
#endif
#endif
// <q> Lose Lock After Wake
// <i> Lose Lock After Wake
// <id> dfll48m_arch_llaw
#ifndef CONF_DFLL_LLAW
#define CONF_DFLL_LLAW 0
#endif
// <q> Stable DFLL Frequency
// <i> Stable DFLL Frequency
// <i> If 0: FINE calibration tracks changes in output frequency.
// <i> If 1: FINE calibration register value will be fixed after a fine lock.
// <id> dfll48m_arch_stable
#ifndef CONF_DFLL_STABLE
#define CONF_DFLL_STABLE 0
#endif
// <y> Operating Mode Selection
// <CONF_DFLL_OPEN_LOOP_MODE"> Open Loop Mode
// <CONF_DFLL_CLOSED_LOOP_MODE"> Closed Loop Mode
// <i> Mode
// <id> dfll48m_mode
#ifndef CONF_DFLL_MODE
#define CONF_DFLL_MODE CONF_DFLL_CLOSED_LOOP_MODE
#endif
// <o> Coarse Maximum Step <0x0-0x1F>
// <id> dfll_arch_cstep
#ifndef CONF_DFLL_CSTEP
#define CONF_DFLL_CSTEP 1
#endif
// <o> Fine Maximum Step <0x0-0x3FF>
// <id> dfll_arch_fstep
#ifndef CONF_DFLL_FSTEP
#define CONF_DFLL_FSTEP 1
#endif
// <o>DFLL Multiply Factor<0-65535>
// <i> Set the DFLL Multiply Factor
// <i> Default: 0
// <id> dfll48m_mul
#ifndef CONF_DFLL_MUL
#define CONF_DFLL_MUL 0
#endif
// <e> DFLL Calibration Overwrite
// <i> Indicates whether Overwrite Calibration value of DFLL
// <id> dfll48m_arch_calibration
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
#define CONF_DFLL_OVERWRITE_CALIBRATION 1
#endif
// <o> Coarse Value <0x0-0x3F>
// <id> dfll48m_arch_coarse
#ifndef CONF_DFLL_COARSE
#define CONF_DFLL_COARSE (0xa)
#endif
// <o> Fine Value <0x0-0x3FF>
// <id> dfll48m_arch_fine
#ifndef CONF_DFLL_FINE
#define CONF_DFLL_FINE (0x200)
#endif
#if CONF_DFLL_OVERWRITE_CALIBRATION == 0
#define CONF_DEFAULT_CORASE \
((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos)
#define CONF_DFLLVAL \
SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \
| SYSCTRL_DFLLVAL_FINE(512)
#else
#define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)
#endif
//</e>
// </h>
// </e>
// <e> DPLL Configuration
// <i> Indicates whether configuration for DPLL is enabled or not
// <id> enable_fdpll96m
#ifndef CONF_DPLL_CONFIG
#define CONF_DPLL_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source.
// <id> fdpll96m_ref_clock
#ifndef CONF_DPLL_GCLK
#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val
#endif
#if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K)
#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val
#elif (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC)
#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val
#else
#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val
#endif
// <h> DPLL Control
// <q> ON Demand
// <i> Enable On Demand
// <i> If this bit is 0: The DFLL is always on, if enabled.
// <i> If this bit is 1: the DFLL will only be running when requested by a peripheral.
// <id> fdpll96m_arch_ondemand
#ifndef CONF_DPLL_ONDEMAND
#define CONF_DPLL_ONDEMAND 1
#endif
// <q> Run In Standby
// <i> Run In standby Mode
// <i> If this bit is 0: The DFLL is disabled in standby sleep mode.
// <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
// <id> fdpll96m_arch_runstdby
#ifndef CONF_DPLL_RUNSTDBY
#define CONF_DPLL_RUNSTDBY 0
#endif
// <q> DPLL Enable
// <i> Indicates whether DPLL is enabled or not
// <id> fdpll96m_arch_enable
#ifndef CONF_DPLL_ENABLE
#define CONF_DPLL_ENABLE 0
#endif
// <q> Lock ByPass
// <i> Enabling it makes the CLK_FDPLL96M always running otherwise it will be turned off when lock signal is low
// <id> fdpll96m_arch_lbypass
#ifndef CONF_DPLL_LBYPASS
#define CONF_DPLL_LBYPASS 0
#endif
// <o>Clock Divider <0-2047>
// <i> Clock Division Factor (Applicable if reference clock is XOSC)
// <id> fdpll96m_clock_div
#ifndef CONF_DPLL_DIV
#define CONF_DPLL_DIV 0
#endif
// <o>DPLL LDRFRAC<0-15>
// <i> Set the fractional part of the frequency multiplier.
// <id> fdpll96m_ldrfrac
#ifndef CONF_DPLL_LDRFRAC
#define CONF_DPLL_LDRFRAC 13
#endif
// <o>DPLL LDR <0-4095>
// <i> Set the integer part of the frequency multiplier.
// <id> fdpll96m_ldr
#ifndef CONF_DPLL_LDR
#define CONF_DPLL_LDR 1463
#endif
// </h>
// </e>
#define CONF_DPLL_LTIME SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val
#define CONF_DPLL_WUF 0
#define CONF_DPLL_LPEN 0
#define CONF_DPLL_FILTER SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val
// <<< end of configuration section >>>
#endif // HPL_SYSCTRL_CONFIG_H

18
atmel-samd/asf4/samd21/config/hpl_systick_config.h
View File

@ -1,18 +0,0 @@
/* Auto-generated config file hpl_systick_config.h */
#ifndef HPL_SYSTICK_CONFIG_H
#define HPL_SYSTICK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Advanced settings
// <q> SysTick exception request
// <i> Indicates whether the generation of SysTick exception is enabled or not
// <id> systick_arch_tickint
#ifndef CONF_SYSTICK_TICKINT
#define CONF_SYSTICK_TICKINT 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_SYSTICK_CONFIG_H

181
atmel-samd/asf4/samd21/config/hpl_tc_config.h
View File

@ -1,181 +0,0 @@
/* Auto-generated config file hpl_tc_config.h */
#ifndef HPL_TC_CONFIG_H
#define HPL_TC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef CONF_TC3_ENABLE
#define CONF_TC3_ENABLE 1
#endif
// <h> Basic settings
// <y> Prescaler
// <TC_CTRLA_PRESCALER_DIV1_Val"> No division
// <TC_CTRLA_PRESCALER_DIV2_Val"> Divide by 2
// <TC_CTRLA_PRESCALER_DIV4_Val"> Divide by 4
// <TC_CTRLA_PRESCALER_DIV8_Val"> Divide by 8
// <TC_CTRLA_PRESCALER_DIV16_Val"> Divide by 16
// <TC_CTRLA_PRESCALER_DIV64_Val"> Divide by 64
// <TC_CTRLA_PRESCALER_DIV256_Val"> Divide by 256
// <TC_CTRLA_PRESCALER_DIV1024_Val"> Divide by 1024
// <i> This defines the prescaler value
// <id> tc_prescaler
#ifndef CONF_TC3_PRESCALER
#define CONF_TC3_PRESCALER TC_CTRLA_PRESCALER_DIV8_Val
#endif
//<o> Period Value <0x00000000-0xFFFFFFFF>
// <id> tc_per
#ifndef CONF_TC3_PER
#define CONF_TC3_PER 0x32
#endif
// </h>
// <h> PWM Waveform Output settings
// <o> Waveform Period Value (uS) <0x00-0xFFFFFFFF>
// <i> The unit of this value is us.
// <id> tc_arch_wave_per_val
#ifndef CONF_TC3_WAVE_PER_VAL
#define CONF_TC3_WAVE_PER_VAL 0x3e8
#endif
// <o> Waveform Duty Value (0.1%) <0x00-0x03E8>
// <i> The unit of this value is 1/1000.
// <id> tc_arch_wave_duty_val
#ifndef CONF_TC3_WAVE_DUTY_VAL
#define CONF_TC3_WAVE_DUTY_VAL 0x1f4
#endif
/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
#if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val
#define CONF_TC3_CC0 \
((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1))
#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val
#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 64000000 - 1))
#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val
#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 256000000 - 1))
#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val
#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1024000000 - 1))
#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
#endif
// </h>
// <h> Advanced settings
// <y> Mode
// <TC_CTRLA_MODE_COUNT16_Val"> Counter in 16-bit mode
// <TC_CTRLA_MODE_COUNT32_Val"> Counter in 32-bit mode
// <i> These bits mode
// <id> tc_arch_mode
#ifndef CONF_TC3_MODE
#define CONF_TC3_MODE TC_CTRLA_MODE_COUNT16_Val
#endif
// </h>
// <h> Advanced settings
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
//#define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val
// <q> Run in standby
// <i> Indicates whether the will continue running in standby sleep mode or not
// <id> tc_arch_runstdby
#ifndef CONF_TC3_RUNSTDBY
#define CONF_TC3_RUNSTDBY 0
#endif
// <y> Prescaler and Counter Synchronization Selection
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
// <id> tc_arch_presync
#ifndef CONF_TC3_PRESCSYNC
#define CONF_TC3_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
#endif
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
//#define CONF_TC3_DIR 0
//#define CONF_TC3_ONESHOT 0
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
//#define CONF_TC3_INVEN0 0
//#define CONF_TC3_INVEN1 0
//#define CONF_TC3_CPTEN0 0
//#define CONF_TC3_CPTEN1 0
// <q> Debug Running Mode
// <i> Indicates whether the Debug Running Mode is enabled or not
// <id> tc_arch_dbgrun
#ifndef CONF_TC3_DBGRUN
#define CONF_TC3_DBGRUN 0
#endif
// </h>
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TC3_EVENT_CONTROL_ENABLE
#define CONF_TC3_EVENT_CONTROL_ENABLE 0
#endif
// <q> Overflow/Underflow Event Output
// <i> Generates event for counter overflows/underflows
// <id> tc_arch_ovfeo
#ifndef CONF_TC3_OVFEO
#define CONF_TC3_OVFEO 0
#endif
// <q> TC Event Asynchronous input
// <i> Enables Asynchronous input events to the TC
// <id> tc_arch_tcei
#ifndef CONF_TC3_TCEI
#define CONF_TC3_TCEI 0
#endif
// <q> TC Inverted Event Input Polarity
// <i> Used to invert the asynchronous input event source
// <id> tc_arch_tceinv
#ifndef CONF_TC3_TCINV
#define CONF_TC3_TCINV 0
#endif
// <y> Event Action
// <i> Defines the event action the TC will perform on an event
// <TC_EVCTRL_EVACT_OFF_Val"> Event action disabled
// <TC_EVCTRL_EVACT_RETRIGGER_Val"> Start, restart or retrigger TC on event
// <TC_EVCTRL_EVACT_COUNT_Val"> Count on event
// <TC_EVCTRL_EVACT_START_Val"> Start TC on event
// <TC_EVCTRL_EVACT_PPW_Val"> Period captured in CC0, pulse width in CC1
// <TC_EVCTRL_EVACT_PWP_Val"> Period captured in CC1, pulse width in CC0
// <id> tc_arch_evact
#ifndef CONF_TC3_EVACT
#define CONF_TC3_EVACT TC_EVCTRL_EVACT_OFF_Val
#endif
// <q> Match/Capture channel 0 Event
// <i> Enables the generation of an event for every match or capture on channel 0
// <id> tc_arch_mceo0
#ifndef CONF_TC3_MCEO0
#define CONF_TC3_MCEO0 0
#endif
// <q> Match/Capture channel 1 Event
// <i> Enables the generation of an event for every match or capture on channel 1
// <id> tc_arch_mceo1
#ifndef CONF_TC3_MCEO1
#define CONF_TC3_MCEO1 0
#endif
// </e>
// <<< end of configuration section >>>
#endif // HPL_TC_CONFIG_H

355
atmel-samd/asf4/samd21/config/hpl_usb_config.h
View File

@ -1,355 +0,0 @@
/* Auto-generated config file hpl_usb_config.h */
#ifndef HPL_USB_CONFIG_H
#define HPL_USB_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#define CONF_USB_N_0 0
#define CONF_USB_N_1 1
#define CONF_USB_N_2 2
#define CONF_USB_N_3 3
#define CONF_USB_N_4 4
#define CONF_USB_N_5 5
#define CONF_USB_N_6 6
#define CONF_USB_N_7 7
#define CONF_USB_N_8 8
#define CONF_USB_N_9 9
#define CONF_USB_N_10 10
#define CONF_USB_N_11 11
#define CONF_USB_N_12 12
#define CONF_USB_N_13 13
#define CONF_USB_N_14 14
#define CONF_USB_N_15 15
#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1)
#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1)
// <h> USB Device HAL Configuration
// <y> Max number of endpoints supported
// <i> Limits the number of endpoints (described by EP address) can be used in app.
// <CONF_USB_N_1"> 1 (EP0 only)
// <CONF_USB_N_2"> 2 (EP0 + 1 endpoint)
// <CONF_USB_N_3"> 3 (EP0 + 2 endpoints)
// <CONF_USB_N_4"> 4 (EP0 + 3 endpoints)
// <CONF_USB_N_5"> 5 (EP0 + 4 endpoints)
// <CONF_USB_N_6"> 6 (EP0 + 5 endpoints)
// <CONF_USB_N_7"> 7 (EP0 + 6 endpoints)
// <CONF_USB_N_8"> 8 (EP0 + 7 endpoints)
// <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config)
// <id> usbd_num_ep_sp
#ifndef CONF_USB_D_NUM_EP_SP
#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4
#endif
// </h>
// <y> Max Endpoint Number supported
// <i> Limits the max endpoint number.
// <i> USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1.
// <i> Reduce the value according to specific device design, to cut-off memory usage.
// <CONF_USB_N_0"> 0 (only EP0)
// <CONF_USB_N_1"> 1 (EP 0x81 or 0x01)
// <CONF_USB_N_2"> 2 (EP 0x82 or 0x02)
// <CONF_USB_N_3"> 3 (EP 0x83 or 0x03)
// <CONF_USB_N_4"> 4 (EP 0x84 or 0x04)
// <CONF_USB_N_5"> 5 (EP 0x85 or 0x05)
// <CONF_USB_N_6"> 6 (EP 0x86 or 0x06)
// <CONF_USB_N_7"> 7 (EP 0x87 or 0x07)
// <CONF_USB_EP_N_MAX"> Max possible (by HW)
// <i> The number of physical endpoints - 1
// <id> usbd_arch_max_ep_n
#ifndef CONF_USB_D_MAX_EP_N
#define CONF_USB_D_MAX_EP_N CONF_USB_N_2
#endif
// <y> USB Speed Limit
// <i> Limits the working speed of the device.
// <USB_SPEED_FS"> Full speed
// <USB_SPEED_LS"> Low Speed
// <id> usbd_arch_speed
#ifndef CONF_USB_D_SPEED
#define CONF_USB_D_SPEED USB_SPEED_FS
#endif
// <o> Cache buffer size for EP0
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time.
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <id> usb_arch_ep0_cache
#ifndef CONF_USB_EP0_CACHE
#define CONF_USB_EP0_CACHE 64
#endif
// <h> Cache configuration EP1
// <o> Cache buffer size for EP1 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep1_cache
#ifndef CONF_USB_EP1_CACHE
#define CONF_USB_EP1_CACHE 64
#endif
// <o> Cache buffer size for EP1 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep1_I_CACHE
#ifndef CONF_USB_EP1_I_CACHE
#define CONF_USB_EP1_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP2
// <o> Cache buffer size for EP2 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep2_cache
#ifndef CONF_USB_EP2_CACHE
#define CONF_USB_EP2_CACHE 64
#endif
// <o> Cache buffer size for EP2 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep2_I_CACHE
#ifndef CONF_USB_EP2_I_CACHE
#define CONF_USB_EP2_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP3
// <o> Cache buffer size for EP3 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep3_cache
#ifndef CONF_USB_EP3_CACHE
#define CONF_USB_EP3_CACHE 64
#endif
// <o> Cache buffer size for EP3 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep3_I_CACHE
#ifndef CONF_USB_EP3_I_CACHE
#define CONF_USB_EP3_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP4
// <o> Cache buffer size for EP4 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep4_cache
#ifndef CONF_USB_EP4_CACHE
#define CONF_USB_EP4_CACHE 64
#endif
// <o> Cache buffer size for EP4 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep4_I_CACHE
#ifndef CONF_USB_EP4_I_CACHE
#define CONF_USB_EP4_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP5
// <o> Cache buffer size for EP5 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep5_cache
#ifndef CONF_USB_EP5_CACHE
#define CONF_USB_EP5_CACHE 64
#endif
// <o> Cache buffer size for EP5 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep5_I_CACHE
#ifndef CONF_USB_EP5_I_CACHE
#define CONF_USB_EP5_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP6
// <o> Cache buffer size for EP6 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep6_cache
#ifndef CONF_USB_EP6_CACHE
#define CONF_USB_EP6_CACHE 64
#endif
// <o> Cache buffer size for EP6 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep6_I_CACHE
#ifndef CONF_USB_EP6_I_CACHE
#define CONF_USB_EP6_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP7
// <o> Cache buffer size for EP7 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep7_cache
#ifndef CONF_USB_EP7_CACHE
#define CONF_USB_EP7_CACHE 64
#endif
// <o> Cache buffer size for EP7 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep7_I_CACHE
#ifndef CONF_USB_EP7_I_CACHE
#define CONF_USB_EP7_I_CACHE 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_USB_CONFIG_H

369
atmel-samd/asf4/samd21/config/peripheral_clk_config.h
View File

@ -1,369 +0,0 @@
/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <y> ADC Clock Source
// <id> adc_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source for ADC.
#ifndef CONF_GCLK_ADC_SRC
#define CONF_GCLK_ADC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_ADC_FREQUENCY
* \brief ADC's Clock frequency
*/
#ifndef CONF_GCLK_ADC_FREQUENCY
#define CONF_GCLK_ADC_FREQUENCY 1000000
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 1000000
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM0_CORE_SRC
#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
* \brief SERCOM0's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 1000000
#endif
/**
* \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
* \brief SERCOM0's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM1_CORE_SRC
#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
* \brief SERCOM1's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 1000000
#endif
/**
* \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
* \brief SERCOM1's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 400000
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 1000000
#endif
/**
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
* \brief SERCOM2's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 400000
#endif
// <y> RTC Clock Source
// <id> rtc_clk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source for RTC.
#ifndef CONF_GCLK_RTC_SRC
#define CONF_GCLK_RTC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_RTC_FREQUENCY
* \brief RTC's Clock frequency
*/
#ifndef CONF_GCLK_RTC_FREQUENCY
#define CONF_GCLK_RTC_FREQUENCY 1000000
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC3_SRC
#define CONF_GCLK_TC3_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC3_FREQUENCY
* \brief TC3's Clock frequency
*/
#ifndef CONF_GCLK_TC3_FREQUENCY
#define CONF_GCLK_TC3_FREQUENCY 1000000
#endif
// <y> DAC Clock Source
// <id> dac_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source for DAC.
#ifndef CONF_GCLK_DAC_SRC
#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_DAC_FREQUENCY
* \brief DAC's Clock frequency
*/
#ifndef CONF_GCLK_DAC_FREQUENCY
#define CONF_GCLK_DAC_FREQUENCY 1000000
#endif
// <y> USB Clock Source
// <id> usb_gclk_selection
// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source for USB.
#ifndef CONF_GCLK_USB_SRC
#define CONF_GCLK_USB_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_USB_FREQUENCY
* \brief USB's Clock frequency
*/
#ifndef CONF_GCLK_USB_FREQUENCY
#define CONF_GCLK_USB_FREQUENCY 1000000
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H

32
atmel-samd/asf4/samd21/documentation/usb_device_composite.rst
View File

@ -1,32 +0,0 @@
====================
USB Device Composite
====================
USB Device Composite is a part of the USB Device Stack library. It provides the support for
combining different USB classes into one USB device application. For more detailed features
or use cases introduction, user can refer to the related class documents.
Features
--------
* Combination of different USB classes.
Applications
------------
* An USB device which is composed by CDC ACM, HID Keyboard,etc.
Dependencies
------------
* USB Device Driver
* USB Device Stack Core
* USB Device CDC
* USB Device HID
Limitations
-----------
N/A

41
atmel-samd/asf4/samd21/documentation/usb_device_core.rst
View File

@ -1,41 +0,0 @@
===============
USB Device Core
===============
USB Device Core is a part of the USB Device Stack library. It handles all the requests
during USB Enumeration process and helps upper class driver to be installed successfully
if only the descriptor configuration is correct. For more detailed description about Bus
Enumeration, user can refer to Chapter 9 (USB Device Framework) in Universal Serial Bus
Specification.
Features
--------
* Initialization/de-initialization
* Enabling/disabling USB device class components
* Data Transfer
* Attaching/detaching control
* Waking up by USB host
* Callbacks management on:
* SOF event
* USB Device state change
* USB Device request handler
Applications
------------
N/A
Dependencies
------------
* USB Device Driver
* USB Protocol Core
Limitations
-----------
* It is recommended that at least one device class should run above the USB
device core.

24
atmel-samd/asf4/samd21/documentation/usb_protocol_cdc.rst
View File

@ -1,24 +0,0 @@
================
USB CDC Protocol
================
USB CDC Protocol is a part of the USB Device Stack library. It provides basic
macro definitions and data structures which are compliant with CDC(Communications
Device Class) Specification version 1.2.
Applications
------------
N/A
Dependencies
------------
N/A
Limitations
-----------
N/A

40
atmel-samd/asf4/samd21/documentation/usb_protocol_core.rst
View File

@ -1,40 +0,0 @@
=================
USB Protocol Core
=================
USB Protocol Core is a part of the USB Device Stack library. It provides basic
macro definitions, data structures and API functions which are compliant with
USB specification version 2.0.0/2.0.1 for user.
In addition, it provides interfaces of USB descriptor searching for the upper
layer to use, which is especially helpful in the USB enumeration process.
Features
--------
* Packaging USB device, configuration, interface, endpoint descriptors.
* Getting the descriptor length or type from an assigned USB descriptor.
* Getting VID, PID value from an assigned USB descriptor.
* Getting the total length of an USB configuration descriptor.
* Finding the next valid descriptor in a given USB descriptor.
* Finding an endpoint descriptor in a given USB descriptor.
* Finding a specific descriptor by an assigned descriptor type.
* Finding a configure descriptor by an assigned configure value.
* Finding a string descriptor by an assigned string index.
Applications
------------
N/A
Dependencies
------------
N/A
Limitations
-----------
N/A

24
atmel-samd/asf4/samd21/documentation/usb_protocol_hid.rst
View File

@ -1,24 +0,0 @@
================
USB HID Protocol
================
USB HID Protocol is a part of the USB Device Stack library. It provides basic
macro definitions and data structures which are compliant with HID(Human Interface
Device) Specification version 1.11.
Applications
------------
N/A
Dependencies
------------
N/A
Limitations
-----------
N/A

32
atmel-samd/asf4/samd21/documentation/usb_protocol_hub.rst
View File

@ -1,32 +0,0 @@
======================
USB Protocol Hub Class
======================
USB Protocol Hub Class is a part of the USB Device Stack library. It provides
basic macro definitions, data structures and API functions which are compliant
with Hub part of USB specification version 2.0.0/2.0.1 for user.
In addition, it provides interfaces of USB requests filling and input data
analyzing for the upper layer to use.
Features
--------
* Hub requests filling
* Hub change bitmap analyzing
Applications
------------
N/A
Dependencies
------------
N/A
Limitations
-----------
N/A

25
atmel-samd/asf4/samd21/documentation/usb_protocol_msc.rst
View File

@ -1,25 +0,0 @@
================
USB MSC Protocol
================
USB MSC Protocol is a part of the USB Device Stack library. It provides basic
macro definitions and data structures which are compliant with Mass Storage
Control/Bulk/Interrupt (CBI) Specification 1.1 and Mass Storage UFI Command
Specification 1.0.
Applications
------------
N/A
Dependencies
------------
N/A
Limitations
-----------
N/A

24
atmel-samd/asf4/samd21/documentation/usb_protocol_vendor.rst
View File

@ -1,24 +0,0 @@
===================
USB Vendor Protocol
===================
USB Vendor Protocol is a part of the USB Device Stack library. It provides basic
macro definitions which are compliant with Universal Serial Bus Specification
Revision 2.0.
Applications
------------
N/A
Dependencies
------------
N/A
Limitations
-----------
N/A

788
atmel-samd/asf4/samd21/driver_init.c
View File

@ -1,788 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
#include <hpl_gclk_base.h>
#include <hpl_pm_base.h>
#include <hpl_adc_base.h>
#include <hpl_rtc_base.h>
struct spi_m_sync_descriptor SPI_0;
struct timer_descriptor TIMER_0;
struct adc_sync_descriptor ADC_0;
struct flash_descriptor FLASH_0;
struct i2c_m_sync_desc I2C_0;
struct usart_sync_descriptor USART_0;
struct pwm_descriptor PWM_0;
struct dac_sync_descriptor DAC_0;
void ADC_0_PORT_init(void)
{
}
void ADC_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBC, ADC);
_gclk_enable_channel(ADC_GCLK_ID, CONF_GCLK_ADC_SRC);
}
void ADC_0_init(void)
{
ADC_0_CLOCK_init();
ADC_0_PORT_init();
adc_sync_init(&ADC_0, ADC, (void *)NULL);
}
void FLASH_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBB, NVMCTRL);
}
void FLASH_0_init(void)
{
FLASH_0_CLOCK_init();
flash_init(&FLASH_0, NVMCTRL);
}
void SPI_0_PORT_init(void)
{
// Set pin direction to output
gpio_set_pin_direction(PA04, GPIO_DIRECTION_OUT);
gpio_set_pin_level(PA04,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0);
// Set pin direction to output
gpio_set_pin_direction(PA05, GPIO_DIRECTION_OUT);
gpio_set_pin_level(PA05,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1);
// Set pin direction to input
gpio_set_pin_direction(PA06, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA06,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA06, PINMUX_PA06D_SERCOM0_PAD2);
}
void SPI_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBC, SERCOM0);
_gclk_enable_channel(SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC);
}
void SPI_0_init(void)
{
SPI_0_CLOCK_init();
spi_m_sync_init(&SPI_0, SERCOM0);
SPI_0_PORT_init();
}
void I2C_0_PORT_init(void)
{
gpio_set_pin_pull_mode(PA16,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA16, PINMUX_PA16C_SERCOM1_PAD0);
gpio_set_pin_pull_mode(PA17,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA17, PINMUX_PA17C_SERCOM1_PAD1);
}
void I2C_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBC, SERCOM1);
_gclk_enable_channel(SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC);
_gclk_enable_channel(SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC);
}
void I2C_0_init(void)
{
I2C_0_CLOCK_init();
i2c_m_sync_init(&I2C_0, SERCOM1);
I2C_0_PORT_init();
}
void USART_0_PORT_init(void)
{
gpio_set_pin_function(PA08, PINMUX_PA08D_SERCOM2_PAD0);
gpio_set_pin_function(PA09, PINMUX_PA09D_SERCOM2_PAD1);
}
void USART_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBC, SERCOM2);
_gclk_enable_channel(SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC);
}
void USART_0_init(void)
{
USART_0_CLOCK_init();
usart_sync_init(&USART_0, SERCOM2, (void *)NULL);
USART_0_PORT_init();
}
void delay_driver_init(void)
{
delay_init(SysTick);
}
/**
* \brief Timer initialization function
*
* Enables Timer peripheral, clocks and initializes Timer driver
*/
static void TIMER_0_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBA, RTC);
_gclk_enable_channel(RTC_GCLK_ID, CONF_GCLK_RTC_SRC);
timer_init(&TIMER_0, RTC, _rtc_get_timer());
}
void PWM_0_PORT_init(void)
{
}
void PWM_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBC, TC3);
_gclk_enable_channel(TC3_GCLK_ID, CONF_GCLK_TC3_SRC);
}
void PWM_0_init(void)
{
PWM_0_CLOCK_init();
PWM_0_PORT_init();
pwm_init(&PWM_0, TC3, _tc_get_pwm());
}
void DAC_0_PORT_init(void)
{
}
void DAC_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBC, DAC);
_gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC);
}
void DAC_0_init(void)
{
DAC_0_CLOCK_init();
dac_sync_init(&DAC_0, DAC);
DAC_0_PORT_init();
}
void USB_0_PORT_init(void)
{
gpio_set_pin_direction(PA24,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(PA24,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA24,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA24,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA24G_USB_DM"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
PINMUX_PA24G_USB_DM);
gpio_set_pin_direction(PA25,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(PA25,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA25,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA25,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA25G_USB_DP"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
PINMUX_PA25G_USB_DP);
}
/* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
* for low speed and full speed operation. */
#if (CONF_GCLK_USB_FREQUENCY > (48000000 + 48000000 / 400)) || (CONF_GCLK_USB_FREQUENCY < (48000000 - 48000000 / 400))
#warning USB clock should be 48MHz ~ 0.25% clock, check your configuration!
#endif
void USB_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBB, USB);
_pm_enable_bus_clock(PM_BUS_AHB, USB);
_gclk_enable_channel(USB_GCLK_ID, CONF_GCLK_USB_SRC);
}
void USB_0_init(void)
{
USB_0_CLOCK_init();
usb_d_init();
USB_0_PORT_init();
}
void system_init(void)
{
init_mcu();
// GPIO on PA00
// Set pin direction to input
gpio_set_pin_direction(PA00, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA00,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA00, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA01
// Set pin direction to input
gpio_set_pin_direction(PA01, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA01,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA01, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA02
// Set pin direction to input
gpio_set_pin_direction(PA02, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA02,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA02, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA03
// Set pin direction to input
gpio_set_pin_direction(PA03, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA03,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA03, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA07
// Set pin direction to input
gpio_set_pin_direction(PA07, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA07,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA07, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA10
// Set pin direction to input
gpio_set_pin_direction(PA10, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA10,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA10, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA11
// Set pin direction to input
gpio_set_pin_direction(PA11, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA11,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA11, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA12
// Set pin direction to input
gpio_set_pin_direction(PA12, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA12,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA12, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA13
// Set pin direction to input
gpio_set_pin_direction(PA13, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA13,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA13, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA14
// Set pin direction to input
gpio_set_pin_direction(PA14, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA14,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA14, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA15
// Set pin direction to input
gpio_set_pin_direction(PA15, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA15,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA15, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA18
// Set pin direction to input
gpio_set_pin_direction(PA18, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA18,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA18, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA19
// Set pin direction to input
gpio_set_pin_direction(PA19, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA19,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA19, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA20
// Set pin direction to input
gpio_set_pin_direction(PA20, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA20,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA20, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA21
// Set pin direction to input
gpio_set_pin_direction(PA21, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA21,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA21, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA22
// Set pin direction to input
gpio_set_pin_direction(PA22, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA22,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA22, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA23
// Set pin direction to input
gpio_set_pin_direction(PA23, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA23,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA23, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA27
// Set pin direction to input
gpio_set_pin_direction(PA27, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA27,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA27, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA28
// Set pin direction to input
gpio_set_pin_direction(PA28, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA28,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA28, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA30
// Set pin direction to input
gpio_set_pin_direction(PA30, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA30,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA30, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA31
// Set pin direction to input
gpio_set_pin_direction(PA31, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PA31,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA31, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB02
// Set pin direction to input
gpio_set_pin_direction(PB02, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB02,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB02, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB03
// Set pin direction to input
gpio_set_pin_direction(PB03, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB03,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB03, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB08
// Set pin direction to input
gpio_set_pin_direction(PB08, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB08,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB08, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB09
// Set pin direction to input
gpio_set_pin_direction(PB09, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB09,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB09, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB10
// Set pin direction to input
gpio_set_pin_direction(PB10, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB10,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB10, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB11
// Set pin direction to input
gpio_set_pin_direction(PB11, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB11,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB11, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB22
// Set pin direction to input
gpio_set_pin_direction(PB22, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB22,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB22, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB23
// Set pin direction to input
gpio_set_pin_direction(PB23, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB23,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB23, GPIO_PIN_FUNCTION_OFF);
ADC_0_init();
FLASH_0_init();
SPI_0_init();
I2C_0_init();
USART_0_init();
delay_driver_init();
TIMER_0_init();
PWM_0_init();
DAC_0_init();
USB_0_init();
}

99
atmel-samd/asf4/samd21/driver_init.h
View File

@ -1,99 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_adc_sync.h>
#include <hal_flash.h>
#include <hal_spi_m_sync.h>
#include <hal_i2c_m_sync.h>
#include <hal_usart_sync.h>
#include <hal_delay.h>
#include <hal_timer.h>
#include <hal_pwm.h>
#include <hpl_tc_base.h>
#include <hal_dac_sync.h>
#include "hal_usb_device.h"
extern struct adc_sync_descriptor ADC_0;
extern struct flash_descriptor FLASH_0;
extern struct spi_m_sync_descriptor SPI_0;
extern struct i2c_m_sync_desc I2C_0;
extern struct usart_sync_descriptor USART_0;
extern struct timer_descriptor TIMER_0;
extern struct pwm_descriptor PWM_0;
extern struct dac_sync_descriptor DAC_0;
void ADC_0_PORT_init(void);
void ADC_0_CLOCK_init(void);
void ADC_0_init(void);
void FLASH_0_init(void);
void FLASH_0_CLOCK_init(void);
void SPI_0_PORT_init(void);
void SPI_0_CLOCK_init(void);
void SPI_0_init(void);
void I2C_0_CLOCK_init(void);
void I2C_0_init(void);
void I2C_0_PORT_init(void);
void USART_0_PORT_init(void);
void USART_0_CLOCK_init(void);
void USART_0_init(void);
void delay_driver_init(void);
void PWM_0_PORT_init(void);
void PWM_0_CLOCK_init(void);
void PWM_0_init(void);
void DAC_0_PORT_init(void);
void DAC_0_CLOCK_init(void);
void DAC_0_init(void);
void USB_0_CLOCK_init(void);
void USB_0_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED

140
atmel-samd/asf4/samd21/examples/driver_examples.c
View File

@ -1,140 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using ADC_0 to generate waveform.
*/
void ADC_0_example(void)
{
uint8_t buffer[2];
adc_sync_enable_channel(&ADC_0, 0);
while (1) {
adc_sync_read_channel(&ADC_0, 0, buffer, 2);
}
}
static uint8_t src_data[128];
static uint8_t chk_data[128];
/**
* Example of using FLASH_0 to read and write buffer.
*/
void FLASH_0_example(void)
{
uint32_t page_size;
uint16_t i;
/* Init source data */
page_size = flash_get_page_size(&FLASH_0);
for (i = 0; i < page_size; i++) {
src_data[i] = i;
}
/* Write data to flash */
flash_write(&FLASH_0, 0x3200, src_data, page_size);
/* Read data from flash */
flash_read(&FLASH_0, 0x3200, chk_data, page_size);
}
/**
* Example of using SPI_0 to write "Hello World" using the IO abstraction.
*/
static uint8_t example_SPI_0[12] = "Hello World!";
void SPI_0_example(void)
{
struct io_descriptor *io;
spi_m_sync_get_io_descriptor(&SPI_0, &io);
spi_m_sync_enable(&SPI_0);
io_write(io, example_SPI_0, 12);
}
void I2C_0_example(void)
{
struct io_descriptor *I2C_0_io;
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
}
/**
* Example of using USART_0 to write "Hello World" using the IO abstraction.
*/
void USART_0_example(void)
{
struct io_descriptor *io;
usart_sync_get_io_descriptor(&USART_0, &io);
usart_sync_enable(&USART_0);
io_write(io, (uint8_t *)"Hello World!", 12);
}
void delay_example(void)
{
delay_ms(5000);
}
static struct timer_task TIMER_0_task1, TIMER_0_task2;
/**
* Example of using TIMER_0.
*/
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
{
}
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
{
}
void TIMER_0_example(void)
{
TIMER_0_task1.interval = 100;
TIMER_0_task1.cb = TIMER_0_task1_cb;
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
TIMER_0_task2.interval = 200;
TIMER_0_task2.cb = TIMER_0_task2_cb;
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
timer_add_task(&TIMER_0, &TIMER_0_task1);
timer_add_task(&TIMER_0, &TIMER_0_task2);
timer_start(&TIMER_0);
}
/**
* Example of using PWM_0.
*/
void PWM_0_example(void)
{
pwm_set_parameters(&PWM_0, 10000, 5000);
pwm_enable(&PWM_0);
}
/**
* Example of using DAC_0 to generate waveform.
*/
void DAC_0_example(void)
{
uint16_t i = 0;
dac_sync_enable_channel(&DAC_0, 0);
for (;;) {
dac_sync_write(&DAC_0, 0, &i, 1);
i = (i + 1) % 1024;
}
}

32
atmel-samd/asf4/samd21/examples/driver_examples.h
View File

@ -1,32 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void ADC_0_example(void);
void FLASH_0_example(void);
void I2C_0_example(void);
void USART_0_example(void);
void delay_example(void);
void PWM_0_example(void);
void DAC_0_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED

286
atmel-samd/asf4/samd21/gcc/Makefile
View File

@ -1,286 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
ifdef SystemRoot
SHELL = cmd.exe
MK_DIR = mkdir
else
ifeq ($(shell uname), Linux)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
MK_DIR = mkdir -p
endif
ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
MK_DIR = mkdir -p
endif
endif
# List the subdirectories for creating object files
SUB_DIRS += \
\
hpl/adc \
hal/src \
examples \
hpl/systick \
hpl/tc \
usb \
hpl/dmac \
usb/class/cdc/device \
hal/utils/src \
hpl/rtc \
usb/class/hid/device \
hpl/usb \
samd21a/gcc/gcc \
hpl/pm \
hpl/sysctrl \
hpl/gclk \
usb/device \
hpl/dac \
samd21a/gcc \
hpl/sercom \
hpl/nvmctrl \
hpl/core \
usb/class/msc/device
# List the object files
OBJS += \
hal/src/hal_io.o \
hpl/systick/hpl_systick.o \
samd21a/gcc/gcc/startup_samd21.o \
usb/usb_protocol.o \
usb/class/hid/device/hiddf_generic.o \
usb/class/cdc/device/cdcdf_acm.o \
hal/utils/src/utils_syscalls.o \
hpl/nvmctrl/hpl_nvmctrl.o \
usb/class/msc/device/mscdf.o \
hal/src/hal_spi_m_sync.o \
hal/src/hal_timer.o \
hal/src/hal_pwm.o \
hpl/usb/hpl_usb.o \
hal/src/hal_i2c_m_sync.o \
hal/src/hal_delay.o \
hpl/sysctrl/hpl_sysctrl.o \
hpl/core/hpl_init.o \
hal/utils/src/utils_list.o \
hpl/core/hpl_core_m0plus_base.o \
hal/utils/src/utils_assert.o \
hpl/dmac/hpl_dmac.o \
hpl/pm/hpl_pm.o \
usb/class/hid/device/hiddf_keyboard.o \
hal/src/hal_usart_sync.o \
hpl/dac/hpl_dac.o \
hpl/gclk/hpl_gclk.o \
hal/src/hal_flash.o \
hal/src/hal_init.o \
hal/src/hal_usb_device.o \
main.o \
samd21a/gcc/system_samd21.o \
hpl/rtc/hpl_rtc.o \
examples/driver_examples.o \
driver_init.o \
hal/src/hal_adc_sync.o \
hal/src/hal_dac_sync.o \
hpl/sercom/hpl_sercom.o \
hal/src/hal_gpio.o \
usb/class/hid/device/hiddf_mouse.o \
hal/utils/src/utils_event.o \
hal/src/hal_sleep.o \
usb_start.o \
atmel_start.o \
usb/device/usbdc.o \
hpl/tc/hpl_tc.o \
hal/src/hal_atomic.o \
hpl/adc/hpl_adc.o
OBJS_AS_ARGS += \
"hal/src/hal_io.o" \
"hpl/systick/hpl_systick.o" \
"samd21a/gcc/gcc/startup_samd21.o" \
"usb/usb_protocol.o" \
"usb/class/hid/device/hiddf_generic.o" \
"usb/class/cdc/device/cdcdf_acm.o" \
"hal/utils/src/utils_syscalls.o" \
"hpl/nvmctrl/hpl_nvmctrl.o" \
"usb/class/msc/device/mscdf.o" \
"hal/src/hal_spi_m_sync.o" \
"hal/src/hal_timer.o" \
"hal/src/hal_pwm.o" \
"hpl/usb/hpl_usb.o" \
"hal/src/hal_i2c_m_sync.o" \
"hal/src/hal_delay.o" \
"hpl/sysctrl/hpl_sysctrl.o" \
"hpl/core/hpl_init.o" \
"hal/utils/src/utils_list.o" \
"hpl/core/hpl_core_m0plus_base.o" \
"hal/utils/src/utils_assert.o" \
"hpl/dmac/hpl_dmac.o" \
"hpl/pm/hpl_pm.o" \
"usb/class/hid/device/hiddf_keyboard.o" \
"hal/src/hal_usart_sync.o" \
"hpl/dac/hpl_dac.o" \
"hpl/gclk/hpl_gclk.o" \
"hal/src/hal_flash.o" \
"hal/src/hal_init.o" \
"hal/src/hal_usb_device.o" \
"main.o" \
"samd21a/gcc/system_samd21.o" \
"hpl/rtc/hpl_rtc.o" \
"examples/driver_examples.o" \
"driver_init.o" \
"hal/src/hal_adc_sync.o" \
"hal/src/hal_dac_sync.o" \
"hpl/sercom/hpl_sercom.o" \
"hal/src/hal_gpio.o" \
"usb/class/hid/device/hiddf_mouse.o" \
"hal/utils/src/utils_event.o" \
"hal/src/hal_sleep.o" \
"usb_start.o" \
"atmel_start.o" \
"usb/device/usbdc.o" \
"hpl/tc/hpl_tc.o" \
"hal/src/hal_atomic.o" \
"hpl/adc/hpl_adc.o"
# List the dependency files
DEPS := $(OBJS:%.o=%.d)
DEPS_AS_ARGS += \
"usb/usb_protocol.d" \
"samd21a/gcc/gcc/startup_samd21.d" \
"hal/utils/src/utils_event.d" \
"hal/src/hal_io.d" \
"hpl/systick/hpl_systick.d" \
"usb/class/hid/device/hiddf_generic.d" \
"hal/utils/src/utils_syscalls.d" \
"usb/class/cdc/device/cdcdf_acm.d" \
"usb/class/hid/device/hiddf_mouse.d" \
"hal/src/hal_i2c_m_sync.d" \
"hpl/usb/hpl_usb.d" \
"usb/class/msc/device/mscdf.d" \
"hpl/nvmctrl/hpl_nvmctrl.d" \
"hal/src/hal_pwm.d" \
"hal/src/hal_timer.d" \
"hal/src/hal_spi_m_sync.d" \
"hpl/core/hpl_core_m0plus_base.d" \
"hal/utils/src/utils_list.d" \
"hpl/dmac/hpl_dmac.d" \
"hal/utils/src/utils_assert.d" \
"hal/src/hal_delay.d" \
"hpl/core/hpl_init.d" \
"hpl/sysctrl/hpl_sysctrl.d" \
"hal/src/hal_flash.d" \
"hpl/gclk/hpl_gclk.d" \
"hal/src/hal_usb_device.d" \
"usb_start.d" \
"hal/src/hal_init.d" \
"hal/src/hal_usart_sync.d" \
"usb/class/hid/device/hiddf_keyboard.d" \
"hpl/dac/hpl_dac.d" \
"driver_init.d" \
"hal/src/hal_adc_sync.d" \
"samd21a/gcc/system_samd21.d" \
"main.d" \
"examples/driver_examples.d" \
"hpl/rtc/hpl_rtc.d" \
"hal/src/hal_sleep.d" \
"hpl/sercom/hpl_sercom.d" \
"hal/src/hal_dac_sync.d" \
"hal/src/hal_gpio.d" \
"hal/src/hal_atomic.d" \
"hpl/tc/hpl_tc.d" \
"usb/device/usbdc.d" \
"hpl/pm/hpl_pm.d" \
"hpl/adc/hpl_adc.d" \
"atmel_start.d"
OUTPUT_FILE_NAME :=AtmelStart
QUOTE := "
OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
vpath %.c ../
vpath %.s ../
vpath %.S ../
# All Target
all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
# Linker target
$(OUTPUT_FILE_PATH): $(OBJS)
@echo Building target: $@
@echo Invoking: ARM/GNU Linker
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \
-Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m0plus \
\
\
-T"../samd21a/gcc/gcc/samd21g18a_flash.ld" \
-L"../samd21a/gcc/gcc"
@echo Finished building target: $@
"arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin"
"arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \
"$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex"
"arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \
.eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \
"$(OUTPUT_FILE_NAME).eep" || exit 0
"arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss"
"arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf"
# Compiler targets
%.o: %.c
@echo Building file: $<
@echo ARM/GNU C Compiler
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAMD21G18A__ -mcpu=cortex-m0plus \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
%.o: %.s
@echo Building file: $<
@echo ARM/GNU Assembler
$(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAMD21G18A__ -mcpu=cortex-m0plus \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
%.o: %.S
@echo Building file: $<
@echo ARM/GNU Preprocessing Assembler
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
-D__SAMD21G18A__ -mcpu=cortex-m0plus \
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
# Detect changes in the dependent files and recompile the respective object files.
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(DEPS)),)
-include $(DEPS)
endif
endif
$(SUB_DIRS):
$(MK_DIR) "$@"
clean:
rm -f $(OBJS_AS_ARGS)
rm -f $(OUTPUT_FILE_PATH)
rm -f $(DEPS_AS_ARGS)
rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \
$(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \
$(OUTPUT_FILE_NAME).srec

142
atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_flash.ld
View File

@ -1,142 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD21G18A
*
* Copyright (c) 2016 Atmel Corporation,
* a wholly owned subsidiary of Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

141
atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_sram.ld
View File

@ -1,141 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD21G18A
*
* Copyright (c) 2016 Atmel Corporation,
* a wholly owned subsidiary of Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

254
atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c
View File

@ -1,254 +0,0 @@
/**
* \file
*
* \brief gcc starttup file for SAMD21
*
* Copyright (c) 2016 Atmel Corporation,
* a wholly owned subsidiary of Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#include "samd21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SYSCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void EIC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void DMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#ifdef ID_USB
void USB_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
void EVSYS_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SERCOM0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SERCOM1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SERCOM2_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void SERCOM3_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#ifdef ID_SERCOM4
void SERCOM4_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_SERCOM5
void SERCOM5_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
void TCC0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TCC1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TCC2_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#ifdef ID_TC6
void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC7
void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_ADC
void ADC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_AC
void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_DAC
void DAC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_PTC
void PTC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
#endif
void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__((section(".vectors"), used)) const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void *)(&_estack),
.pfnReset_Handler = (void *)Reset_Handler,
.pfnNMI_Handler = (void *)NMI_Handler,
.pfnHardFault_Handler = (void *)HardFault_Handler,
.pvReservedM12 = (void *)(0UL), /* Reserved */
.pvReservedM11 = (void *)(0UL), /* Reserved */
.pvReservedM10 = (void *)(0UL), /* Reserved */
.pvReservedM9 = (void *)(0UL), /* Reserved */
.pvReservedM8 = (void *)(0UL), /* Reserved */
.pvReservedM7 = (void *)(0UL), /* Reserved */
.pvReservedM6 = (void *)(0UL), /* Reserved */
.pfnSVC_Handler = (void *)SVC_Handler,
.pvReservedM4 = (void *)(0UL), /* Reserved */
.pvReservedM3 = (void *)(0UL), /* Reserved */
.pfnPendSV_Handler = (void *)PendSV_Handler,
.pfnSysTick_Handler = (void *)SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */
.pfnSYSCTRL_Handler = (void *)SYSCTRL_Handler, /* 1 System Control */
.pfnWDT_Handler = (void *)WDT_Handler, /* 2 Watchdog Timer */
.pfnRTC_Handler = (void *)RTC_Handler, /* 3 Real-Time Counter */
.pfnEIC_Handler = (void *)EIC_Handler, /* 4 External Interrupt Controller */
.pfnNVMCTRL_Handler = (void *)NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
.pfnDMAC_Handler = (void *)DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef ID_USB
.pfnUSB_Handler = (void *)USB_Handler, /* 7 Universal Serial Bus */
#else
.pvReserved7 = (void *)(0UL), /* 7 Reserved */
#endif
.pfnEVSYS_Handler = (void *)EVSYS_Handler, /* 8 Event System Interface */
.pfnSERCOM0_Handler = (void *)SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
.pfnSERCOM1_Handler = (void *)SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
.pfnSERCOM2_Handler = (void *)SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
.pfnSERCOM3_Handler = (void *)SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
.pfnSERCOM4_Handler = (void *)SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
.pvReserved13 = (void *)(0UL), /* 13 Reserved */
#endif
#ifdef ID_SERCOM5
.pfnSERCOM5_Handler = (void *)SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
.pvReserved14 = (void *)(0UL), /* 14 Reserved */
#endif
.pfnTCC0_Handler = (void *)TCC0_Handler, /* 15 Timer Counter Control 0 */
.pfnTCC1_Handler = (void *)TCC1_Handler, /* 16 Timer Counter Control 1 */
.pfnTCC2_Handler = (void *)TCC2_Handler, /* 17 Timer Counter Control 2 */
.pfnTC3_Handler = (void *)TC3_Handler, /* 18 Basic Timer Counter 0 */
.pfnTC4_Handler = (void *)TC4_Handler, /* 19 Basic Timer Counter 1 */
.pfnTC5_Handler = (void *)TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef ID_TC6
.pfnTC6_Handler = (void *)TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
.pvReserved21 = (void *)(0UL), /* 21 Reserved */
#endif
#ifdef ID_TC7
.pfnTC7_Handler = (void *)TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
.pvReserved22 = (void *)(0UL), /* 22 Reserved */
#endif
#ifdef ID_ADC
.pfnADC_Handler = (void *)ADC_Handler, /* 23 Analog Digital Converter */
#else
.pvReserved23 = (void *)(0UL), /* 23 Reserved */
#endif
#ifdef ID_AC
.pfnAC_Handler = (void *)AC_Handler, /* 24 Analog Comparators */
#else
.pvReserved24 = (void *)(0UL), /* 24 Reserved */
#endif
#ifdef ID_DAC
.pfnDAC_Handler = (void *)DAC_Handler, /* 25 Digital Analog Converter */
#else
.pvReserved25 = (void *)(0UL), /* 25 Reserved */
#endif
#ifdef ID_PTC
.pfnPTC_Handler = (void *)PTC_Handler, /* 26 Peripheral Touch Controller */
#else
.pvReserved26 = (void *)(0UL), /* 26 Reserved */
#endif
.pfnI2S_Handler = (void *)I2S_Handler, /* 27 Inter-IC Sound Interface */
.pvReserved28 = (void *)(0UL) /* 28 Reserved */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *)&_sfixed;
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
/* Change default QOS values to have the best performance and correct USB behaviour */
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
#if defined(ID_USB)
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
#endif
DMAC->QOSCTRL.bit.DQOS = 2;
DMAC->QOSCTRL.bit.FQOS = 2;
DMAC->QOSCTRL.bit.WRBQOS = 2;
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
/* Initialize the C library */
//__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1)
;
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

63
atmel-samd/asf4/samd21/gcc/system_samd21.c
View File

@ -1,63 +0,0 @@
/**
* \file
*
* \brief Low-level initialization functions called upon chip startup.
*
* Copyright (c) 2016 Atmel Corporation,
* a wholly owned subsidiary of Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#include "samd21.h"
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (1000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}

74
atmel-samd/asf4/samd21/hal/documentation/adc_sync.rst
View File

@ -1,74 +0,0 @@
======================
ADC Synchronous driver
======================
An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
A reference signal with a known voltage level is quantified into equally
sized chunks, each representing a digital value from 0 to the highest number
possible with the bit resolution supported by the ADC. The input voltage
measured by the ADC is compared against these chunks and the chunk with the
closest voltage level defines the digital value that can be used to represent
the analog input voltage level.
Usually an ADC can operate in either differential or single-ended mode.
In differential mode two signals (V+ and V-) are compared against each other
and the resulting digital value represents the relative voltage level between
V+ and V-. This means that if the input voltage level on V+ is lower than on
V- the digital value is negative, which also means that in differential
mode one bit is lost to the sign. In single-ended mode only V+ is compared
against the reference voltage, and the resulting digital value can only be
positive, but the full bit-range of the ADC can be used.
Usually multiple resolutions are supported by the ADC, lower resolution can
reduce the conversion time, but lose accuracy.
Some ADCs has a gain stage on the input lines which can be used to increase the
dynamic range. The default gain value is usually x1, which means that the
conversion range is from 0V to the reference voltage.
Applications can change the gain stage, to increase or reduce the conversion
range.
The window mode allows the conversion result to be compared to a set of
predefined threshold values. Applications can use callback function to monitor
if the conversion result exceeds predefined threshold value.
Usually multiple reference voltages are supported by the ADC, both internal and
external with difference voltage levels. The reference voltage have an impact
on the accuracy, and should be selected to cover the full range of the analog
input signal and never less than the expected maximum input voltage.
There are two conversion modes supported by ADC, single shot and free running.
In single shot mode the ADC only make one conversion when triggered by the
application, in free running mode it continues to make conversion from it
is triggered until it is stopped by the application. When window monitoring,
the ADC should be set to free running mode.
Features
--------
* Initialization and de-initialization
* Support multiple Conversion Mode, Single or Free run
* Start ADC Conversion
* Read Conversion Result
Applications
------------
* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
* Measurement of external sensor. E.g., Temperature, humidity sensor value.
* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
Dependencies
------------
* ADC hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

41
atmel-samd/asf4/samd21/hal/documentation/dac_sync.rst
View File

@ -1,41 +0,0 @@
======================
DAC Synchronous driver
======================
A DAC (Digital-to-Analog Converter) converts digital value to an analog voltage.
The digital value from 0 to the highest represent the output voltage value.
The digital highest value possible with the bit resolution supported by the
DAC. For example a 10 bit resolution DAC hardware, the highest value is 1024.
The highest output voltage possible with the reference voltage.
The driver can convert a serials digital value. The pre-defined data should
be an data array. Application can invoke dac_sync_write to start the conversation.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
* Support for DACs with channels
* Writing buffers with multiple samples to DAC
Applications
------------
* Generate audio signals by connecting the DAC output to a speaker
* Generate a reference voltage
Dependencies
------------
* DAC hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

52
atmel-samd/asf4/samd21/hal/documentation/flash.rst
View File

@ -1,52 +0,0 @@
The Flash Driver
================
Flash is a re-programmable memory that retains program and data
storage even with power off.
User can write or read several bytes from any valid address in a flash.
As to the erase/lock/unlock command, the input parameter of address should
be a bytes address aligned with the page start, otherwise, the command will fail
to be executed. At the meantime, the number of pages that can be locked or unlocked
at once depends on region size of the flash. User can get the real number
from the function return value which could be different for the different devices.
Features
--------
* Initialization/de-initialization
* Writing/Reading bytes
* Locking/Unlocking/Erasing pages
* Notifications about errors or being ready for a new command
Applications
------------
* Mini disk which can retain program and data storage
* Boot loader
* Non volatile storage
Dependencies
------------
The peripheral which controls a re-programmable flash memory.
Concurrency
-----------
N/A
Limitations
-----------
User should pay attention to set a proper stack size in their application,
since the driver manages a temporary buffer in stack to cache unchanged data
when calling flash write and erase function.
Due to flash memory architecture of SAMD21/D20/L21/L22/C20/C21/D09/D10/D11/R21,
write operation erazes row content before each write.
Known issues and workarounds
----------------------------
N/A

87
atmel-samd/asf4/samd21/hal/documentation/i2c_master_sync.rst
View File

@ -1,87 +0,0 @@
=============================
I2C Master synchronous driver
=============================
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
for on-board low-speed bi-directional communication between controllers and
peripherals. The master device is responsible for initiating and controlling
all transfers on the I2C bus. Only one master device can be active on the I2C
bus at the time, but the master role can be transferred between devices on the
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
resistors.
The stop condition is automatically controlled by the driver if the I/O write and
read functions are used, but can be manually controlled by using the
i2c_m_sync_transfer function.
Often a master accesses different information in the slave by accessing
different registers in the slave. This is done by first sending a message to
the target slave containing the register address, followed by a repeated start
condition (no stop condition between) ending with transferring register data.
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
function, but limited to 8-bit register addresses.
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
stick within the SCL clock frequency range supported by the selected mode.
The requested SCL clock frequency is not validated by the
i2c_m_sync_set_baudrate function against the selected I2C mode.
Features
--------
* I2C Master support
* Initialization and de-initialization
* Enabling and disabling
* Run-time bus speed configuration
* Write and read I2C messages
* Slave register access functions (limited to 8-bit address)
* Manual or automatic stop condition generation
* 10- and 7- bit addressing
* I2C Modes supported
+----------------------+-------------------+
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
+----------------------+-------------------+
|* Fastmode+ | (SCL: 1 - 1000kHz)|
+----------------------+-------------------+
|* Highspeed mode | (SCL: 1 - 3400kHz)|
+----------------------+-------------------+
Applications
------------
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
* Data communication between micro controllers
* Controlling displays
Dependencies
------------
* I2C Master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
General
^^^^^^^
* System Managmenet Bus (SMBus) not supported.
* Power Management Bus (PMBus) not supported.
Clock considerations
^^^^^^^^^^^^^^^^^^^^
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
Known issues and workarounds
----------------------------
N/A

53
atmel-samd/asf4/samd21/hal/documentation/pwm.rst
View File

@ -1,53 +0,0 @@
The PWM Driver(bare-bone)
=========================
Pulse-width modulation (PWM) is used to create an analog behavior
digitally by controlling the amount of power transferred to the
connected peripheral. This is achieved by controlling the high period
(duty-cycle) of a periodic signal.
User can change the period or duty cycle whenever PWM is running. The
function pwm_set_parameters is used to configure these two parameters.
Note these are raw register values and the parameter duty_cycle means
the period of first half during one cycle, which should be not beyond
total period value.
In addition, user can also get multi PWM channels output from different
peripherals at the same time, which is implemented more flexible by the
function pointers.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Run-time control of PWM duty-cycle and period
* Notifications about errors and one PWM cycle is done
Applications
------------
Motor control, ballast, LED, H-bridge, power converters, and
other types of power control applications.
Dependencies
------------
The peripheral which can perform waveform generation like frequency
generation and pulse-width modulation, such as Timer/Counter.
Concurrency
-----------
N/A
Limitations
-----------
The current driver doesn't support the features like recoverable,
non-recoverable faults, dithering, dead-time insertion.
Known issues and workarounds
----------------------------
N/A

51
atmel-samd/asf4/samd21/hal/documentation/spi_master_sync.rst
View File

@ -1,51 +0,0 @@
The SPI Master Synchronous Driver
=================================
The serial peripheral interface (SPI) is a synchronous serial communication
interface.
SPI devices communicate in full duplex mode using a master-slave
architecture with a single master. The master device originates the frame for
reading and writing. Multiple slave devices are supported through selection
with individual slave select (SS) lines.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* SPI mode
* Character size
* Data order
* Data transfer: transmission, reception and full-duplex
Applications
------------
Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
LCD controller, etc.
Dependencies
------------
SPI master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
The slave select (SS) is not automatically inserted during read/write/transfer,
user must use I/O to control the devices' SS.
Known issues and workarounds
----------------------------
N/A

52
atmel-samd/asf4/samd21/hal/documentation/timer.rst
View File

@ -1,52 +0,0 @@
============================
The Timer driver (bare-bone)
============================
The Timer driver provides means for delayed and periodical function invocation.
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
changes execution delays and periods for all tasks in the timers task queue.
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
the period set in the task configuration.
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
reuse the memory of expired task in the callback.
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
Features
--------
* Initialization and de-initialization
* Starting and stopping
* Timer tasks - periodical invocation of functions
* Changing and obtaining of the period of a timer
Applications
------------
* Delayed and periodical function execution for middle-ware stacks and applications.
Dependencies
------------
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
Concurrency
-----------
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
until the task adding or removing is complete.
The task queue is not protected from the access by interrupts not used by the driver. Due to this
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
Limitations
-----------
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
Knows issues and workarounds
----------------------------
Not applicable

58
atmel-samd/asf4/samd21/hal/documentation/usart_sync.rst
View File

@ -1,58 +0,0 @@
The USART Synchronous Driver
============================
The universal synchronous and asynchronous receiver and transmitter
(USART) is usually used to transfer data from one device to the other.
User can set action for flow control pins by function usart_set_flow_control,
if the flow control is enabled. All the available states are defined in union
usart_flow_control_state.
Note that user can set state of flow control pins only if automatic support of
the flow control is not supported by the hardware.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* UART or USRT communication mode
* Character size
* Data order
* Flow control
* Data transfer: transmission, reception
Applications
------------
They are commonly used in a terminal application or low-speed communication
between devices.
Dependencies
------------
USART capable hardware.
Concurrency
-----------
Write buffer should not be changed while data is being sent.
Limitations
-----------
* The driver does not support 9-bit character size.
* The "USART with ISO7816" mode can be only used in ISO7816 capable devices.
And the SCK pin can't be set directly. Application can use a GCLK output PIN
to generate SCK. For example to communicate with a SMARTCARD with ISO7816
(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be
config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification.
Known issues and workarounds
----------------------------
N/A

195
atmel-samd/asf4/samd21/hal/documentation/usb_device_async.rst
View File

@ -1,195 +0,0 @@
The USB Device Asynchronous Driver
==================================
Universal Serial Bus (USB) is an industry standard that defines the cables,
connectors and communication protocols used in a bus for connection,
communication, and power supply between computers and electronic devices.
The USB device driver provides necessary APIs to support USB Device states and
USB data flow. So that the USB Device enumeration, class and vendor support can
be implemented base on it. The driver is asynchronous, which means that all USB
data processing is done in callbacks..
To be recognized by a host, a USB device must handle a subset of the USB events.
The USB device should build up control communication to report its descriptors
to the host and accept host's requests. An application or upper stack that uses
the USB device driver should have its descriptors prepared, catch the callbacks,
monitor the control requests and handle them correctly.
Usually, a USB device application that can be enumerated may use the following
sequence:
* Initialize
* Register callback and handle Reset event, where:
* Initialize endpoint 0
* Register callbacks for endpoint 0, where some of the standard requests
defined in Chapter 9, USB specification
(see `USB 2.0 Documents <http://www.usb.org/developers/docs/usb20_docs>`_)
are handled
* Setup request handling callback
* On *GetDeviceDescriptor* request, sends device descriptor
* On *GetConfigurationDescriptor* request, sends configuration descriptors
* On *SetAddress* request sends no data, just goes to status phase
* On *SetConfigure* request initialize and enable other endpoints, sends
no data, just goes to status phase
* Transfer done handling callback
* On *SetAddress* request apply the new address
* On *SetConfigure* request a global variable can be set to indicates
that the host driver is loaded and device is ready to work
* Enable endpoint 0
* Enable
* Attach device
To support USB transfer on endpoints, endpoints information is stored
by the driver internally, including control request data, endpoint status,
callbacks and transfer data pointers. The number of endpoints that the driver
can support is defined through configuration. To optimize RAM usage, the
number of endpoints the driver needs to support should be minimized.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* USB device attachment/detachment
* USB device address control
* USB working speed status
* USB device frame number and micro frame number status
* Sending remote wakeup to host
* Callback management for following USB events:
* Start of Frame (SOF)
* Other USB events:
* VBus change
* Reset
* Wakeup
* Linked Power Management (LPM) Suspend
* Suspend
* Error
* Endpoints management:
* Endpoint initialization/de-initialization
* Endpoint enabling/disabling
* Control endpoint setup request packet
* Data transfer and abort
* Endpoint halt state control
* Endpoint status, including:
* Endpoint address
* Last transfer result status code
* Last error status code
* Current transfer state
* Transfer size and done count
* Endpoint callback management for endpoint and its transfer events:
* In case a setup request received on control endpoint
* In case transfer finished with/without error
Applications
------------
USB Device stack, to monitor USB events, handle control requests and process
data.
Dependencies
------------
* USB device capable hardware
* 48MHz clock for low-speed and full-speed and 480MHz clock for high-speed
Concurrency
-----------
N/A
Limitations
-----------
* When a buffer is used by a USB endpoint to transfer data, it must be kept
unchanged while the transfer is in progress.
* After receiving a request that has no data expected, the transfer function
must be called with data length zero to complete control status phase.
Known issues and workarounds
----------------------------
N/A
Considerations for D21 USB
--------------------------
Clocks
^^^^^^
DFLL must be used to generate 48MHz clock for USB device with either of the
following mode:
* USB Clock Recovery Mode
* Set "DFLL Enable", "Bypass Coarse Lock", "Chill Cycle Disable",
"USB Clock Recovery Mode", "Stable DFLL Frequency"
* Clear "Wait Lock"
* Leave "Operating Mode Selection" to "Closed Loop Mode"
* Closed Loop Mode
* Set "DFLL Enable"
* Clear "USB Clock Recovery Mode", "Stable DFLL Frequency"
* Select "Closed Loop Mode" of "Operating Mode Selection"
* Set "DFLL Multiply Factor" to 1464 or 1465 (48000000/32768)
* Select "Reference Clock Source" to use 32768Hz source, e.g., use GCLK1 and
for GCLK1 settings:
* Set "Generic Clock Generator Enable"
* Select "XOSC32K" of "Generic clock generator 1 source", and for XOSC32K
settings:
* Set "External 32K Oscillator Enable", "Enable 32KHz Output",
"Enable XTAL"
* Set a right value for "Startup time for the 32K Oscillator", e.g.,
1125092 us
Endpoints
^^^^^^^^^
Each USB device endpoint number supports two endpoint addresses, corresponding
to IN and OUT endpoint. E.g., for endpoint 1, the endpoint IN has address 0x81
and endpoint OUT has address 0x01. Thus, the possible supported endpoint
addresses are almost two times of max endpoint number (endpoint 0 must be used
as control endpoint instead of dedicated IN and OUT endpoints).
Buffering and RAM usage optimization
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
When transferring data through USB device endpoints, buffer pointers can be
used to let endpoint get access to the buffer, but there are some limits:
* For control endpoint there must always be a buffer available to put received
setup packet.
* For IN endpoint (transmit to host) the data must in RAM.
* For OUT endpoint (receive from host) the data pointer must be aligned, and
the data size must be aligned by max endpoint size and not zero.
The driver has option for each endpoint to allocate internal static buffer as
cache to buffer input/output data, to remove upper limits. The configuration
affects the parameter check of transfer functions, and the RAM usage.
* For control endpoints, cache buffer must be enabled to fill setup packet.
In addition, to support unaligned OUT packet and IN packet inside flash, the
buffer size must be equal to or larger than max endpoint size.
* For OUT endpoints, if the cache is allocated, it's possible to pass unaligned
buffer address and buffer size to transfer function. Else the transfer
function only accepts aligned buffer with it's size multiple of endpoint
packet size.
* For IN endpoints, if the cache is allocated, it's possible to pass buffer
pointer to internal flash or other memory part other than RAM to the transfer
function.
To optimize the RAM usage, the configuration of max endpoint number, max number
of endpoints supported and the buffer usage of used input and/or output
endpoints can be adjusted.

287
atmel-samd/asf4/samd21/hal/include/hal_adc_sync.h
View File

@ -1,287 +0,0 @@
/**
* \file
*
* \brief ADC functionality declaration.
*
* Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ADC_SYNC_H_INCLUDED
#define _HAL_ADC_SYNC_H_INCLUDED
#include <hpl_adc_sync.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_adc_sync
*
* @{
*/
/**
* \brief ADC descriptor
*
* The ADC descriptor forward declaration.
*/
struct adc_sync_descriptor;
/**
* \brief ADC descriptor
*/
struct adc_sync_descriptor {
/** ADC device */
struct _adc_sync_device device;
};
/**
* \brief Initialize ADC
*
* This function initializes the given ADC descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr An ADC descriptor to initialize
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Initialization status.
*/
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
/**
* \brief Deinitialize ADC
*
* This function deinitializes the given ADC descriptor.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr An ADC descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
/**
* \brief Enable ADC
*
* Use this function to set the ADC peripheral to enabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Disable ADC
*
* Use this function to set the ADC peripheral to disabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Read data from ADC
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] buf A buffer to read data to
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
const uint16_t length);
/**
* \brief Set ADC reference source
*
* This function sets ADC reference source.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] reference A reference source to set
*
* \return Status of the ADC reference source setting.
*/
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
/**
* \brief Set ADC resolution
*
* This function sets ADC resolution.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] resolution A resolution to set
*
* \return Status of the ADC resolution setting.
*/
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* This function sets ADC positive and negative input sources.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*
* \return Status of the ADC channels setting.
*/
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set ADC conversion mode
*
* This function sets ADC conversion mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A conversion mode to set
*
* \return Status of the ADC conversion mode setting.
*/
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
/**
* \brief Set ADC differential mode
*
* This function sets ADC differential mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*
* \return Status of the ADC differential mode setting.
*/
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set ADC channel gain
*
* This function sets ADC channel gain.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] gain A gain to set
*
* \return Status of the ADC gain setting.
*/
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
const adc_gain_t gain);
/**
* \brief Set ADC window mode
*
* This function sets ADC window mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A window mode to set
*
* \return Status of the ADC window mode setting.
*/
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
/**
* \brief Set ADC thresholds
*
* This function sets ADC positive and negative thresholds.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] low_threshold A lower thresholds to set
* \param[in] up_threshold An upper thresholds to set
*
* \return Status of the ADC thresholds setting.
*/
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* This function retrieves ADC threshold state.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[out] state The threshold state
*
* \return The state of ADC thresholds state retrieving.
*/
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
adc_threshold_status_t *const state);
/**
* \brief Check if conversion is complete
*
* This function checks if the ADC has finished the conversion.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return The status of ADC conversion completion checking.
* \retval 1 The conversion is complete
* \retval 0 The conversion is not complete
*/
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t adc_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#include <hpl_missing_features.h>
#endif /* _HAL_ADC_SYNC_H_INCLUDED */

137
atmel-samd/asf4/samd21/hal/include/hal_atomic.h
View File

@ -1,137 +0,0 @@
/**
* \file
*
* \brief Critical sections related functionality declaration.
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ATOMIC_H_INCLUDED
#define _HAL_ATOMIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_atomic
*
*@{
*/
/**
* \brief Type for the register holding global interrupt enable flag
*/
typedef uint32_t hal_atomic_t;
/**
* \brief Helper macro for entering critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_enterCritical() function to enter critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_ENTER() \
{ \
volatile hal_atomic_t __atomic; \
atomic_enter_critical(&__atomic);
/**
* \brief Helper macro for leaving critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_leaveCritical() function to leave critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Some critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_LEAVE() \
atomic_leave_critical(&__atomic); \
}
/**
* \brief Disable interrupts, enter critical section
*
* Disables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[out] atomic The pointer to a variable to store the value of global
* interrupt enable flag
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic);
/**
* \brief Exit atomic section
*
* Enables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[in] atomic The pointer to a variable, which stores the latest stored
* value of the global interrupt enable flag
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t atomic_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_ATOMIC_H_INCLUDED */

134
atmel-samd/asf4/samd21/hal/include/hal_dac_sync.h
View File

@ -1,134 +0,0 @@
/**
* \file
*
* \brief DAC functionality declaration.
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef HAL_SYNC_DAC_H_INCLUDED
#define HAL_SYNC_DAC_H_INCLUDED
#include <hpl_dac_sync.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_dac_sync
*
*@{
*/
/**
* \brief DAC synchronous descriptor.
*
* The DAC descriptor forward declaration.
*/
struct dac_sync_descriptor;
/**
* \brief DAC synchronous channel descriptor.
*
*/
struct dac_sync_channel {
/** Pointer to buffer what to be converted */
uint16_t *buffer;
/** The length of buffer */
uint32_t length;
};
/**
* \brief DAC synchronous descriptor
*/
struct dac_sync_descriptor {
/** DAC device */
struct _dac_sync_device device;
/** DAC selected channel */
struct dac_sync_channel sel_ch[CHANNEL_NUM];
};
/** \brief Initialize the DAC HAL instance and hardware.
* \param[out] descr A DAC descriptor to initialize
* \param[in] hw The pointer to hardware instance
* \return Operation status.
*/
int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw);
/** \brief Deinitialize the DAC HAL instance and hardware.
* \param[in] descr Pointer to the HAL DAC descriptor
* \return Operation status.
*/
int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr);
/** \brief Enable DAC channel.
* \param[in] descr Pointer to the HAL DAC descriptor
* \param[in] ch Channel number
* \return Operation status.
*/
int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch);
/** \brief Disable DAC channel.
* \param[in] descr Pointer to the HAL DAC descriptor
* \param[in] ch Channel number
* \return Operation status.
*/
int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch);
/** \brief DAC converts digital data to analog output.
* \param[in] descr Pointer to the HAL DAC descriptor
* \param[in] ch the Channel selected to output
* \param[in] buffer Pointer to digital data or buffer
* \param[in] length The number of elements in the buffer
* \return Operation status.
*/
int32_t dac_sync_write(struct dac_sync_descriptor *const descr, const uint8_t ch, uint16_t *buffer, uint32_t length);
/** \brief Get DAC driver version
*
* \return Current driver version.
*/
uint32_t dac_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* HAL_DAC_H_INCLUDED */

99
atmel-samd/asf4/samd21/hal/include/hal_delay.h
View File

@ -1,99 +0,0 @@
/**
* \file
*
* \brief HAL delay related functionality declaration.
*
* Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#ifndef _HAL_DELAY_H_INCLUDED
#define _HAL_DELAY_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_delay Delay Driver
*
*@{
*/
/**
* \brief Initialize Delay driver
*
* \param[in] hw The pointer to hardware instance
*/
void delay_init(void *const hw);
/**
* \brief Perform delay in us
*
* This function performs delay for the given amount of microseconds.
*
* \param[in] us The amount delay in us
*/
void delay_us(const uint16_t us);
/**
* \brief Perform delay in ms
*
* This function performs delay for the given amount of milliseconds.
*
* \param[in] ms The amount delay in ms
*/
void delay_ms(const uint16_t ms);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t delay_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_DELAY_H_INCLUDED */

219
atmel-samd/asf4/samd21/hal/include/hal_flash.h
View File

@ -1,219 +0,0 @@
/**
* \file
*
* \brief Flash related functionality declaration.
*
* Copyright (C) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_FLASH_H_INCLUDED
#define _HAL_FLASH_H_INCLUDED
#include <hpl_flash.h>
/**
* \addtogroup doc_driver_hal_flash
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/* Forward declaration of flash_descriptor. */
struct flash_descriptor;
/** The callback types */
enum flash_cb_type {
/** Callback type for ready to accept a new command */
FLASH_CB_READY,
/** Callback type for error */
FLASH_CB_ERROR,
FLASH_CB_N
};
/** \brief Prototype of callback on FLASH
*
*/
typedef void (*flash_cb_t)(struct flash_descriptor *const descr);
/** \brief FLASH HAL callbacks
*
*/
struct flash_callbacks {
/** Callback invoked when ready to accept a new command */
flash_cb_t cb_ready;
/** Callback invoked when error occurs */
flash_cb_t cb_error;
};
/** \brief FLASH HAL driver struct for asynchronous access
*/
struct flash_descriptor {
/** Pointer to FLASH device instance */
struct _flash_device dev;
/** Callbacks for asynchronous transfer */
struct flash_callbacks callbacks;
};
/** \brief Initialize the FLASH HAL instance and hardware for callback mode
*
* Initialize FLASH HAL with interrupt mode (uses callbacks).
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \param[in] hw Pointer to the hardware base.
* \return Initialize status.
*/
int32_t flash_init(struct flash_descriptor *flash, void *const hw);
/** \brief Deinitialize the FLASH HAL instance
*
* Abort transfer, disable and reset FLASH, and deinitialize software.
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \return Deinitialze status.
*/
int32_t flash_deinit(struct flash_descriptor *flash);
/** \brief Writes a number of bytes to a page in the internal Flash
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \param[in] dst_addr Destination bytes address to write into flash
* \param[in] buffer Pointer to a buffer where the content
* will be written to the flash
* \param[in] length Number of bytes to write
* \return Write status.
*/
int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length);
/** \brief Appends a number of bytes to a page in the internal Flash
*
* This functions never erases the flash before writing.
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \param[in] dst_addr Destination bytes address to write to flash
* \param[in] buffer Pointer to a buffer with data to write to flash
* \param[in] length Number of bytes to append
* \return Append status.
*/
int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length);
/** \brief Reads a number of bytes to a page in the internal Flash
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \param[in] src_addr Source bytes address to read from flash
* \param[out] buffer Pointer to a buffer where the content
* of the read pages will be stored
* \param[in] length Number of bytes to read
* \return Read status.
*/
int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length);
/** \brief Register a function as FLASH transfer completion callback
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \param[in] type Callback type (\ref flash_cb_type).
* \param[in] func Pointer to callback function.
* \retval 0 Success
* \retval -1 Error
*/
int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func);
/** \brief Execute lock in the internal flash
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \param[in] dst_addr Destination bytes address aligned with page
* start to be locked
* \param[in] page_nums Number of pages to be locked
*
* \return Real locked numbers of pages.
*/
int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums);
/** \brief Execute unlock in the internal flash
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \param[in] dst_addr Destination bytes address aligned with page
* start to be unlocked
* \param[in] page_nums Number of pages to be unlocked
*
* \return Real unlocked numbers of pages.
*/
int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums);
/** \brief Execute erase in the internal flash
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
* \param[in] dst_addr Destination bytes address aligned with page
* start to be erased
* \param[in] page_nums Number of pages to be erased
* \retval 0 Success
* \retval -1 Error
*/
int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums);
/**
* \brief Get the flash page size
*
* \param[in, out] flash Pointer to the HAL FLASH instance
*
* \return The flash page size
*/
uint32_t flash_get_page_size(struct flash_descriptor *flash);
/**
* \brief Get the number of flash page
*
* \param[in, out] flash Pointer to the HAL FLASH instance.
*
* \return The flash total page numbers
*/
uint32_t flash_get_total_pages(struct flash_descriptor *flash);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t flash_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HAL_FLASH_H_INCLUDED */

212
atmel-samd/asf4/samd21/hal/include/hal_gpio.h
View File

@ -1,212 +0,0 @@
/**
* \file
*
* \brief Port
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*/
#ifndef _HAL_GPIO_INCLUDED_
#define _HAL_GPIO_INCLUDED_
#include <hpl_gpio.h>
#include <utils_assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Set gpio pull mode
*
* Set pin pull mode, non existing pull modes throws an fatal assert
*
* \param[in] pin The pin number for device
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin high with internal
* resistor
* GPIO_PULL_UP = Pull pin low with internal resistor
* GPIO_PULL_OFF = Disable pin pull mode
*/
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
{
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
}
/**
* \brief Set pin function
*
* Select which function a pin will be used for
*
* \param[in] pin The pin number for device
* \param[in] function The pin function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
{
_gpio_set_pin_function(pin, function);
}
/**
* \brief Set port data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction)
{
_gpio_set_direction(port, mask, direction);
}
/**
* \brief Set gpio data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] pin The pin number for device
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
{
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
}
/**
* \brief Set port level
*
* Sets output level on the pins defined by the bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
* pin
* \param[in] level true = Pin levels set to "high" state
* false = Pin levels set to "low" state
*/
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
{
_gpio_set_level(port, mask, level);
}
/**
* \brief Set gpio level
*
* Sets output level on a pin
*
* \param[in] pin The pin number for device
* \param[in] level true = Pin level set to "high" state
* false = Pin level set to "low" state
*/
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
{
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
}
/**
* \brief Toggle out level on pins
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
* pin
*/
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
{
_gpio_toggle_level(port, mask);
}
/**
* \brief Toggle output level on pin
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] pin The pin number for device
*/
static inline void gpio_toggle_pin_level(const uint8_t pin)
{
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
}
/**
* \brief Get input level on pins
*
* Read the input level on pins connected to a port
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
{
return _gpio_get_level(port);
}
/**
* \brief Get level on pin
*
* Reads the level on pins connected to a port
*
* \param[in] pin The pin number for device
*/
static inline bool gpio_get_pin_level(const uint8_t pin)
{
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
}
/**
* \brief Get current driver version
*/
uint32_t gpio_get_version(void);
#ifdef __cplusplus
}
#endif
#endif

254
atmel-samd/asf4/samd21/hal/include/hal_i2c_m_sync.h
View File

@ -1,254 +0,0 @@
/**
* \file
*
* \brief Sync I2C Hardware Abstraction Layer(HAL) declaration.
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_I2C_M_SYNC_H_INCLUDED
#define _HAL_I2C_M_SYNC_H_INCLUDED
#include <hpl_i2c_m_sync.h>
#include <hal_io.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_i2c_master_sync
*
* @{
*/
#define I2C_M_MAX_RETRY 1
/**
* \brief I2C descriptor structure, embed i2c_device & i2c_interface
*/
struct i2c_m_sync_desc {
struct _i2c_m_sync_device device;
struct io_descriptor io;
uint16_t slave_addr;
};
/**
* \brief Initialize synchronous I2C interface
*
* This function initializes the given I/O descriptor to be used as a
* synchronous I2C interface descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
* \retval -1 The passed parameters were invalid or the interface is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw);
/**
* \brief Deinitialize I2C interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Uninitialization status.
* \retval -1 The passed parameters were invalid or the interface is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c);
/**
* \brief Set the slave device address
*
* This function sets the next transfer target slave I2C device address.
* It takes no effect to any already started access.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] addr The slave address to access
* \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
*
* \return Masked slave address. The mask is a maximum 10-bit address, and 10th
* bit is set if a 10-bit address is used
*/
int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len);
/**
* \brief Set baudrate
*
* This function sets the I2C device to the specified baudrate.
* It only takes effect when the hardware is disabled.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] clkrate Unused parameter. Should always be 0
* \param[in] baudrate The baudrate value set to master
*
* \return Whether successfully set the baudrate
* \retval -1 The passed parameters were invalid or the device is already enabled
* \retval 0 The baudrate set is completed successfully
*/
int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Sync version of enable hardware
*
* This function enables the I2C device, and then waits for this enabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully enable the device
* \retval -1 The passed parameters were invalid or the device enable failed
* \retval 0 The hardware enabling is completed successfully
*/
int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of disable hardware
*
* This function disables the I2C device and then waits for this disabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully disable the device
* \retval -1 The passed parameters were invalid or the device disable failed
* \retval 0 The hardware disabling is completed successfully
*/
int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of write command to I2C slave
*
* This function will write the value to a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer holding data to write to the I2C slave device
* \param[in] length The length (in bytes) to write to the I2C slave device
*
* \return Whether successfully write to the device
* \retval <0 The passed parameters were invalid or write fail
* \retval 0 Writing to register is completed successfully
*/
int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of read register value from I2C slave
*
* This function will read a byte value from a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer to hold the read data from the I2C slave device
* \param[in] length The length (in bytes) to read from the I2C slave device
*
* \return Whether successfully read from the device
* \retval <0 The passed parameters were invalid or read fail
* \retval 0 Reading from register is completed successfully
*/
int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of transfer message to/from the I2C slave
*
* This function will transfer a message between the I2C slave and the master. This function will wait for the operation
* to be done.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] msg An i2c_m_msg struct
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg);
/**
* \brief Sync version of send stop condition on the i2c bus
*
* This function will create a stop condition on the i2c bus to release the bus
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c);
/**
* \brief Return I/O descriptor for this I2C instance
*
* This function will return a I/O instance for this I2C driver instance
*
* \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C
* \param[in] io_descriptor A pointer to an I/O descriptor pointer type
*
* \return Error code
* \retval 0 No error detected
* \retval <0 Error code
*/
int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t i2c_m_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

82
atmel-samd/asf4/samd21/hal/include/hal_init.h
View File

@ -1,82 +0,0 @@
/**
* \file
*
* \brief HAL initialization related functionality declaration.
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_INIT_H_INCLUDED
#define _HAL_INIT_H_INCLUDED
#include <hpl_init.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_init Init Driver
*
*@{
*/
/**
* \brief Initialize the hardware abstraction layer
*
* This function calls the various initialization functions.
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
}
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t init_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_INIT_H_INCLUDED */

120
atmel-samd/asf4/samd21/hal/include/hal_io.h
View File

@ -1,120 +0,0 @@
/**
* \file
*
* \brief I/O related functionality declaration.
*
* Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_IO_INCLUDED
#define _HAL_IO_INCLUDED
/**
* \addtogroup doc_driver_hal_helper_io I/O Driver
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I/O descriptor
*
* The I/O descriptor forward declaration.
*/
struct io_descriptor;
/**
* \brief I/O write function pointer type
*/
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read function pointer type
*/
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
/**
* \brief I/O descriptor
*/
struct io_descriptor {
io_write_t write; /*! The write function pointer. */
io_read_t read; /*! The read function pointer. */
};
/**
* \brief I/O write interface
*
* This function writes up to \p length of bytes to a given I/O descriptor.
* It returns the number of bytes actually write.
*
* \param[in] descr An I/O descriptor to write
* \param[in] buf The buffer pointer to story the write data
* \param[in] length The number of bytes to write
*
* \return The number of bytes written
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read interface
*
* This function reads up to \p length bytes from a given I/O descriptor, and
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
* actually read.
*
* \param[in] descr An I/O descriptor to read
* \param[in] buf The buffer pointer to story the read data
* \param[in] length The number of bytes to read
*
* \return The number of bytes actually read. This number can be less than the
* requested length. E.g., in a driver that uses ring buffer for
* reception, it may depend on the availability of data in the
* ring buffer.
*/
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_IO_INCLUDED */

161
atmel-samd/asf4/samd21/hal/include/hal_pwm.h
View File

@ -1,161 +0,0 @@
/**
* \file
*
* \brief PWM functionality declaration.
*
* Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef HAL_PWM_H_INCLUDED
#define HAL_PWM_H_INCLUDED
#include <hpl_pwm.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_pwm_async
*
*@{
*/
/**
* \brief PWM descriptor
*
* The PWM descriptor forward declaration.
*/
struct pwm_descriptor;
/**
* \brief PWM callback type
*/
typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr);
/**
* \brief PWM callback types
*/
enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB };
/**
* \brief PWM callbacks
*/
struct pwm_callbacks {
pwm_cb_t period;
pwm_cb_t error;
};
/** \brief PWM descriptor
*/
struct pwm_descriptor {
/** PWM device */
struct _pwm_device device;
/** PWM callback structure */
struct pwm_callbacks pwm_cb;
};
/** \brief Initialize the PWM HAL instance and hardware
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Operation status.
*/
int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func);
/** \brief Deinitialize the PWM HAL instance and hardware
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_deinit(struct pwm_descriptor *const descr);
/** \brief PWM output start
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_enable(struct pwm_descriptor *const descr);
/** \brief PWM output stop
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_disable(struct pwm_descriptor *const descr);
/** \brief Register PWM callback
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] type Callback type
* \param[in] cb A callback function, passing NULL de-registers callback
*
* \return Operation status.
* \retval 0 Success
* \retval -1 Error
*/
int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb);
/** \brief Change PWM parameter
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] period Total period of one PWM cycle
* \param[in] duty_cycle Period of PWM first half during one cycle
*
* \return Operation status.
*/
int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period,
const pwm_period_t duty_cycle);
/** \brief Get PWM driver version
*
* \return Current driver version.
*/
uint32_t pwm_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* HAL_PWM;_H_INCLUDED */

84
atmel-samd/asf4/samd21/hal/include/hal_sleep.h
View File

@ -1,84 +0,0 @@
/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SLEEP_H_INCLUDED
#define _HAL_SLEEP_H_INCLUDED
#include <hpl_sleep.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_sleep
*
*@{
*/
/**
* \brief Set the sleep mode of the device and put the MCU to sleep
*
* For an overview of which systems are disabled in sleep for the different
* sleep modes, see the data sheet.
*
* \param[in] mode Sleep mode to use
*
* \return The status of a sleep request
* \retval -1 The requested sleep mode was invalid or not available
* \retval 0 The operation completed successfully, returned after leaving the
* sleep
*/
int sleep(const uint8_t mode);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t sleep_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SLEEP_H_INCLUDED */

220
atmel-samd/asf4/samd21/hal/include/hal_spi_m_sync.h
View File

@ -1,220 +0,0 @@
/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SPI_M_SYNC_H_INCLUDED
#define _HAL_SPI_M_SYNC_H_INCLUDED
#include <hal_io.h>
#include <hpl_spi_m_sync.h>
/**
* \addtogroup doc_driver_hal_spi_master_sync
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** \brief SPI HAL driver struct for polling mode
*
*/
struct spi_m_sync_descriptor {
/** SPI device instance */
struct _spi_sync_dev dev;
/** I/O read/write */
struct io_descriptor io;
/** Flags for HAL driver */
uint16_t flags;
};
/** \brief Initialize SPI HAL instance and hardware for polling mode
*
* Initialize SPI HAL with polling mode.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] hw Pointer to the hardware base.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_INVALID_DATA Error, initialized.
*/
int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw);
/** \brief Deinitialize the SPI HAL instance and hardware
*
* Abort transfer, disable and reset SPI, deinit software.
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi);
/** \brief Enable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_sync_enable(struct spi_m_sync_descriptor *spi);
/** \brief Disable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_sync_disable(struct spi_m_sync_descriptor *spi);
/** \brief Set SPI baudrate
*
* Works if SPI is initialized as master, it sets the baudrate.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] baud_val The target baudrate value
* (see "baudrate calculation" for calculating the value).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy
* \retval ERR_INVALID_ARG The baudrate is not supported.
*/
int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val);
/** \brief Set SPI mode
*
* Set the SPI transfer mode (\ref spi_transfer_mode),
* which controls the clock polarity and clock phase:
* - Mode 0: leading edge is rising edge, data sample on leading edge.
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
* - Mode 2: leading edge is falling edge, data sample on leading edge.
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] mode The mode (0~3).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy
* \retval ERR_INVALID_ARG The mode is not supported.
*/
int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode);
/** \brief Set SPI transfer character size in number of bits
*
* The character size (\ref spi_char_size) influence the way the data is
* sent/received.
* For char size <= 8-bit, data is stored byte by byte.
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
* Note that the default and recommended char size is 8-bit since it's
* supported by all system.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] char_size The char size (~16, recommended 8).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy
* \retval ERR_INVALID_ARG The char size is not supported.
*/
int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size);
/** \brief Set SPI transfer data order
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] dord The data order: send LSB/MSB first.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy
* \retval ERR_INVALID_ARG The data order is not supported.
*/
int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord);
/** \brief Perform the SPI data transfer (TX and RX) in polling way
*
* Activate CS, do TX and RX and deactivate CS. It blocks.
*
* \param[in, out] spi Pointer to the HAL SPI instance.
* \param[in] xfer Pointer to the transfer information (\ref spi_xfer).
*
* \retval size Success.
* \retval >=0 Timeout, with number of characters transferred.
* \retval ERR_BUSY SPI is busy
*/
int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer);
/**
* \brief Return the I/O descriptor for this SPI instance
*
* This function will return an I/O instance for this SPI driver instance.
*
* \param[in] spi An SPI master descriptor, which is used to communicate through
* SPI
* \param[in, out] io A pointer to an I/O descriptor pointer type
*
* \retval ERR_NONE
*/
int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t spi_m_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */

216
atmel-samd/asf4/samd21/hal/include/hal_timer.h
View File

@ -1,216 +0,0 @@
/**
* \file
*
* \brief Timer task functionality declaration.
*
* Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_TIMER_H_INCLUDED
#define _HAL_TIMER_H_INCLUDED
#include <utils_list.h>
#include <hpl_timer.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_timer
*
* @{
*/
/**
* \brief Timer mode type
*/
enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
/**
* \brief Timer task descriptor
*
* The timer task descriptor forward declaration.
*/
struct timer_task;
/**
* \brief Timer task callback function type
*/
typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
/**
* \brief Timer task structure
*/
struct timer_task {
struct list_element elem; /*! List element. */
uint32_t time_label; /*! Absolute timer start time. */
uint32_t interval; /*! Number of timer ticks before calling the task. */
timer_cb_t cb; /*! Function pointer to the task. */
enum timer_task_mode mode; /*! Task mode: one shot or repeat. */
};
/**
* \brief Timer structure
*/
struct timer_descriptor {
struct _timer_device device;
uint32_t time;
struct list_descriptor tasks; /*! Timer tasks list. */
volatile uint8_t flags;
};
/**
* \brief Initialize timer
*
* This function initializes the given timer.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr A timer descriptor to initialize
* \param[in] hw The pointer to the hardware instance
* \param[in] func The pointer to a set of function pointers
*
* \return Initialization status.
*/
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
/**
* \brief Deinitialize timer
*
* This function deinitializes the given timer.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr A timer descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t timer_deinit(struct timer_descriptor *const descr);
/**
* \brief Start timer
*
* This function starts the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to start
*
* \return Timer starting status.
*/
int32_t timer_start(struct timer_descriptor *const descr);
/**
* \brief Stop timer
*
* This function stops the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
*
* \return Timer stopping status.
*/
int32_t timer_stop(struct timer_descriptor *const descr);
/**
* \brief Set amount of clock cycles per timer tick
*
* This function sets the amount of clock cycles per timer tick for the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
* \param[in] clock_cycles The amount of clock cycles per tick to set
*
* \return Setting clock cycles amount status.
*/
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
/**
* \brief Retrieve the amount of clock cycles in a tick
*
* This function retrieves how many clock cycles there are in a single timer tick.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to convert ticks to
* clock cycles
* \param[out] cycles The amount of clock cycles
*
* \return The status of clock cycles retrieving.
*/
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
/**
* \brief Add timer task
*
* This function adds the given timer task to the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to add task to
* \param[in] task A task to add
*
* \return Timer's task adding status.
*/
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
/**
* \brief Remove timer task
*
* This function removes the given timer task from the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to remove task from
* \param[in] task A task to remove
*
* \return Timer's task removing status.
*/
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t timer_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_TIMER_H_INCLUDED */

257
atmel-samd/asf4/samd21/hal/include/hal_usart_sync.h
View File

@ -1,257 +0,0 @@
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SYNC_USART_H_INCLUDED
#define _HAL_SYNC_USART_H_INCLUDED
#include "hal_io.h"
#include <hpl_usart_sync.h>
/**
* \addtogroup doc_driver_hal_usart_sync
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Synchronous USART descriptor
*/
struct usart_sync_descriptor {
struct io_descriptor io;
struct _usart_sync_device device;
};
/**
* \brief Initialize USART interface
*
* This function initializes the given I/O descriptor to be used
* as USART interface descriptor.
* It checks if the given hardware is not initialized and
* if the given hardware is permitted to be initialized.
*
* \param[out] descr A USART descriptor which is used to communicate via USART
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to as set of functions pointers
*
* \return Initialization status.
*/
int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func);
/**
* \brief Deinitialize USART interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and
* if the given hardware is permitted to be deinitialized.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return De-initialization status.
*/
int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr);
/**
* \brief Enable USART interface
*
* Enables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Enabling status.
*/
int32_t usart_sync_enable(struct usart_sync_descriptor *const descr);
/**
* \brief Disable USART interface
*
* Disables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Disabling status.
*/
int32_t usart_sync_disable(struct usart_sync_descriptor *const descr);
/**
* \brief Retrieve I/O descriptor
*
* This function retrieves the I/O descriptor of the given USART descriptor.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] io An I/O descriptor to retrieve
*
* \return The status of the I/O descriptor retrieving.
*/
int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io);
/**
* \brief Specify action for flow control pins
*
* This function sets the action (or state) for the flow control pins
* if the flow control is enabled.
* It sets the state of flow control pins only if the automatic support of
* the flow control is not supported by the hardware.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] state A state to set the flow control pins
*
* \return The status of flow control action setup.
*/
int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr,
const union usart_flow_control_state state);
/**
* \brief Set USART baud rate
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] baud_rate A baud rate to set
*
* \return The status of baud rate setting.
*/
int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate);
/**
* \brief Set USART data order
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] data_order A data order to set
*
* \return The status of data order setting.
*/
int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order);
/**
* \brief Set USART mode
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] mode A mode to set
*
* \return The status of mode setting.
*/
int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode);
/**
* \brief Set USART parity
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] parity A parity to set
*
* \return The status of parity setting.
*/
int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity);
/**
* \brief Set USART stop bits
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] stop_bits Stop bits to set
*
* \return The status of stop bits setting.
*/
int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits);
/**
* \brief Set USART character size
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] size A character size to set
*
* \return The status of character size setting.
*/
int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins
* if the flow control is enabled.
* Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
* if the flow control is done by the hardware
* and the pins state cannot be read out.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] state The state of flow control pins
*
* \return The status of flow control state reading.
*/
int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
union usart_flow_control_state *const state);
/**
* \brief Check if the USART transmitter is empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART TX empty checking.
* \retval 0 The USART transmitter is not empty
* \retval 1 The USART transmitter is empty
*/
int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr);
/**
* \brief Check if the USART receiver is not empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART RX empty checking.
* \retval 1 The USART receiver is not empty
* \retval 0 The USART receiver is empty
*/
int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t usart_sync_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_SYNC_USART_H_INCLUDED */

305
atmel-samd/asf4/samd21/hal/include/hal_usb_device.h
View File

@ -1,305 +0,0 @@
/**
* \file
*
* \brief SAM USB device HAL
*
* Copyright (C) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_USB_DEVICE_H_INCLUDED
#define _HAL_USB_DEVICE_H_INCLUDED
#include <hpl_usb_device.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_usb_device
*
* @{
*/
/** USB device endpoint status structure. */
struct usb_d_ep_status {
/** Endpoint address, including direction. */
uint8_t ep;
/** Endpoint transfer status code that triggers the callback.
* \ref usb_xfer_code. */
uint8_t code;
/** Endpoint error, if \c code is \ref USB_TRANS_ERROR. */
uint8_t error;
/** Transfer state, \ref usb_ep_state. */
uint8_t state;
/** Transfer count. */
uint32_t count;
/** Transfer size. */
uint32_t size;
};
/** Prototype function for callback that is invoked on USB device SOF. */
typedef void (*usb_d_sof_cb_t)(void);
/** Prototype function for callback that is invoked on USB device events. */
typedef void (*usb_d_event_cb_t)(const enum usb_event event, const uint32_t param);
/** USB device callbacks. */
struct usb_d_callbacks {
/** Callback that is invoked on SOF. */
usb_d_sof_cb_t sof;
/** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */
usb_d_event_cb_t event;
};
/** Callback that is invoked when setup packet is received.
* Return \c true if request has been handled, or control endpoint will
* stall IN/OUT transactions.
*/
typedef bool (*usb_d_ep_cb_setup_t)(const uint8_t ep, const uint8_t *req);
/** Callback that is invoked when buffer is done without error, but last packet
* is full size packet without ZLP.
* Return \c true if more data has been requested.
*/
typedef bool (*usb_d_ep_cb_more_t)(const uint8_t ep, const uint32_t count);
/** Callback that is invoked when all data is finished, including background
* transfer, or error happens.
* In control transfer data stage, return value is checked,
* return \c false if no error happens.
*/
typedef bool (*usb_d_ep_cb_xfer_t)(const uint8_t ep, const enum usb_xfer_code code, void *param);
/**
* \brief Initialize the USB device driver
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error code.
*/
int32_t usb_d_init(void);
/**
* \brief Deinitialize the USB device driver
*/
void usb_d_deinit(void);
/**
* \brief Register the USB device callback
* \param[in] type The callback type to register.
* \param[in] func The callback function, NULL to disable callback.
*/
void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func);
/**
* \brief Enable the USB device driver
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error code.
*/
int32_t usb_d_enable(void);
/**
* \brief Disable the USB device driver
*/
void usb_d_disable(void);
/**
* \brief Attach the USB device
*/
void usb_d_attach(void);
/**
* \brief Detach the USB device
*/
void usb_d_detach(void);
/**
* \brief Retrieve current USB working speed.
* \return USB Speed. See \ref usb_speed.
*/
enum usb_speed usb_d_get_speed(void);
/**
* \brief Retrieve current USB frame number.
* \return Frame number.
*/
uint16_t usb_d_get_frame_num(void);
/**
* \brief Retrieve current USB micro frame number.
* \return Micro frame number inside a frame (0~7).
* 0 if not available (not HS).
*/
uint8_t usb_d_get_uframe_num(void);
/**
* \brief Set the USB address that is used.
* \param[in] addr The address to set.
*/
void usb_d_set_address(const uint8_t addr);
/**
* \brief Send remote wakeup to host
* \return Operation status.
*/
void usb_d_send_remotewakeup(void);
/**
* \brief Initialize the endpoint 0.
*
* Note that endpoint 0 must be initialized as control endpoint.
*
* \param[in] max_pkt_size Max. packet size of EP0.
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error code.
*/
int32_t usb_d_ep0_init(const uint8_t max_pkt_size);
/**
* \brief Initialize the endpoint.
*
* \param[in] ep The endpoint address.
* \param[in] attr The endpoint attributes.
* \param[in] max_pkt_size Max. packet size of EP0.
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error code.
*/
int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size);
/**
* \brief Disable and deinitialize the endpoint.
* \param[in] ep The endpoint address to deinitialize.
*/
void usb_d_ep_deinit(const uint8_t ep);
/**
* \brief Register the USB device endpoint callback on initialized endpoint.
*
* \param[in] ep The endpoint address.
* \param[in] type The callback type to register.
* \param[in] func The callback function, NULL to disable callback.
*/
void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func);
/**
* \brief Enabled the initialized endpoint.
*
* Setup request will be monitored after enabling a control endpoint.
*
* \param[in] ep The endpoint address.
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error code.
*/
int32_t usb_d_ep_enable(const uint8_t ep);
/**
* \brief Disable the initialized endpoint.
* \param[in] ep The endpoint address.
*/
void usb_d_ep_disable(const uint8_t ep);
/**
* \brief Get request data pointer to access received setup request packet
* \param[in] ep The endpoint address.
* \return Pointer to the request data.
* \retval NULL The endpoint is not a control endpoint.
*/
uint8_t *usb_d_ep_get_req(const uint8_t ep);
/**
* \brief Endpoint transfer.
*
* For control endpoints, start the transfer according to the direction in the bmRequest
* type, and finish with STATUS stage.
* For non-control endpoints, the transfer will be unique direction. Defined by
* bit 8 of the endpoint address.
*
* \param[in] xfer Pointer to the transfer description.
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error code.
*/
int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer);
/**
* \brief Abort an on-going transfer on a specific endpoint.
*
* \param[in] ep The endpoint address.
*/
void usb_d_ep_abort(const uint8_t ep);
/**
* \brief Retrieve the endpoint status.
*
* \param[in] ep The endpoint address.
* \param[out] stat Pointer to the buffer to fill the status description.
*
* \return Endpoint status.
* \retval 1 Busy.
* \retval 0 Idle.
* \retval <0 Error code.
*/
int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat);
/**
* \brief Endpoint halt control.
*
* \param[in] ep The endpoint address.
* \param[in] ctrl Control code (SET/CLEAR/GET).
*
* \return Operation status or HALT state (if \c ctrl is \ref USB_EP_HALT_GET).
*/
int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t usb_d_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_USB_DEVICE_H_INCLUDED */

274
atmel-samd/asf4/samd21/hal/include/hpl_adc_async.h
View File

@ -1,274 +0,0 @@
/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_ASYNC_H_INCLUDED
#define _HPL_ADC_ASYNC_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_async_adc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_adc_sync.h"
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC device structure
*
* The ADC device structure forward declaration.
*/
struct _adc_async_device;
/**
* \brief ADC callback types
*/
enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB };
/**
* \brief ADC interrupt callbacks
*/
struct _adc_async_callbacks {
void (*window_cb)(struct _adc_async_device *device, const uint8_t channel);
void (*error_cb)(struct _adc_async_device *device, const uint8_t channel);
};
/**
* \brief ADC channel interrupt callbacks
*/
struct _adc_async_ch_callbacks {
void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data);
};
/**
* \brief ADC descriptor device structure
*/
struct _adc_async_device {
struct _adc_async_callbacks adc_async_cb;
struct _adc_async_ch_callbacks adc_async_ch_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_async_deinit(struct _adc_async_device *const device);
/**
* \brief Enable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Disable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_async_convert(struct _adc_async_device *const device);
/**
* \brief Retrieve the conversion result
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* The result value
*/
uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode);
/**
* \brief Set lower threshold
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower threshold to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state);
/**
* \brief Enable/disable ADC channel interrupt
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] type The type of interrupt to disable/enable if applicable
* \param[in] state Enable or disable
*/
void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
const enum _adc_async_callback_type type, const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_ASYNC_H_INCLUDED */

253
atmel-samd/asf4/samd21/hal/include/hpl_adc_dma.h
View File

@ -1,253 +0,0 @@
/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (C) 2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_DMA_H_INCLUDED
#define _HPL_ADC_DMA_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_dma_adc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <hpl_adc_sync.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC device structure
*
* The ADC device structure forward declaration.
*/
struct _adc_dma_device;
/**
* \brief ADC callback types
*/
enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB };
/**
* \brief ADC interrupt callbacks
*/
struct _adc_dma_callbacks {
void (*complete)(struct _adc_dma_device *device, const uint16_t data);
void (*error)(struct _adc_dma_device *device);
};
/**
* \brief ADC descriptor device structure
*/
struct _adc_dma_device {
struct _adc_dma_callbacks adc_dma_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_dma_deinit(struct _adc_dma_device *const device);
/**
* \brief Enable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel);
/**
* \brief Disable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel);
/**
* \brief Return address of ADC DMA source
*
* \param[in] device The pointer to ADC device instance
*
* \return ADC DMA source address
*/
uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_dma_convert(struct _adc_dma_device *const device);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode);
/**
* \brief Set thresholds
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower thresholds to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_DMA_H_INCLUDED */

281
atmel-samd/asf4/samd21/hal/include/hpl_adc_sync.h
View File

@ -1,281 +0,0 @@
/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_SYNC_H_INCLUDED
#define _HPL_ADC_SYNC_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_adc_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC reference source
*/
typedef uint8_t adc_reference_t;
/**
* \brief ADC resolution
*/
typedef uint8_t adc_resolution_t;
/**
* \brief ADC positive input for channel
*/
typedef uint8_t adc_pos_input_t;
/**
* \brief ADC negative input for channel
*/
typedef uint8_t adc_neg_input_t;
/**
* \brief ADC threshold
*/
typedef uint16_t adc_threshold_t;
/**
* \brief ADC gain
*/
typedef uint8_t adc_gain_t;
/**
* \brief ADC conversion mode
*/
enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN };
/**
* \brief ADC differential mode
*/
enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL };
/**
* \brief ADC window mode
*/
typedef uint8_t adc_window_mode_t;
/**
* \brief ADC threshold status
*/
typedef bool adc_threshold_status_t;
/**
* \brief ADC sync descriptor device structure
*/
struct _adc_sync_device {
void *hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_sync_deinit(struct _adc_sync_device *const device);
/**
* \brief Enable ADC
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Disable ADC
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_sync_convert(struct _adc_sync_device *const device);
/**
* \brief Retrieve the conversion result
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The result value of channel
*/
uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode);
/**
* \brief Set threshold
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower threshold to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_SYNC_H_INCLUDED */

252
atmel-samd/asf4/samd21/hal/include/hpl_calendar.h
View File

@ -1,252 +0,0 @@
/**
* \file
*
* \brief Generic CALENDAR functionality declaration.
*
* Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CALENDER_H_INCLUDED
#define _HPL_CALENDER_H_INCLUDED
#include <compiler.h>
#include <utils_list.h>
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Calendar structure
*
* The Calendar structure forward declaration.
*/
struct calendar_dev;
/**
* \brief Available mask options for alarms.
*
* Available mask options for alarms.
*/
enum calendar_alarm_option {
/** Alarm disabled. */
CALENDAR_ALARM_MATCH_DISABLED = 0,
/** Alarm match on second. */
CALENDAR_ALARM_MATCH_SEC,
/** Alarm match on second and minute. */
CALENDAR_ALARM_MATCH_MIN,
/** Alarm match on second, minute, and hour. */
CALENDAR_ALARM_MATCH_HOUR,
/** Alarm match on second, minute, hour, and day. */
CALENDAR_ALARM_MATCH_DAY,
/** Alarm match on second, minute, hour, day, and month. */
CALENDAR_ALARM_MATCH_MONTH,
/** Alarm match on second, minute, hour, day, month and year. */
CALENDAR_ALARM_MATCH_YEAR
};
/**
* \brief Available mode for alarms.
*/
enum calendar_alarm_mode { ONESHOT = 1, REPEAT };
/**
* \brief Prototype of callback on alarm match
*/
typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev);
/**
* \brief Structure of Calendar instance
*/
struct calendar_dev {
/** Pointer to the hardware base */
void *hw;
/** Alarm match callback */
calendar_drv_cb_alarm_t callback;
/** IRQ struct */
struct _irq_descriptor irq;
};
/**
* \brief Time struct for calendar
*/
struct calendar_time {
/*range from 0 to 59*/
uint8_t sec;
/*range from 0 to 59*/
uint8_t min;
/*range from 0 to 23*/
uint8_t hour;
};
/**
* \brief Time struct for calendar
*/
struct calendar_date {
/*range from 1 to 28/29/30/31*/
uint8_t day;
/*range from 1 to 12*/
uint8_t month;
/*absolute year>= 1970(such as 2000)*/
uint16_t year;
};
/** \brief Calendar driver struct
*
*/
struct calendar_descriptor {
struct calendar_dev device;
struct list_descriptor alarms;
/*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/
uint32_t base_year;
uint8_t flags;
};
/** \brief Date&Time struct for calendar
*/
struct calendar_date_time {
struct calendar_time time;
struct calendar_date date;
};
/** \brief struct for alarm time
*/
struct _calendar_alarm {
struct calendar_date_time datetime;
uint32_t timestamp;
enum calendar_alarm_option option;
enum calendar_alarm_mode mode;
};
/**
* \brief Initialize Calendar instance
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_init(struct calendar_dev *const dev);
/**
* \brief Deinitialize Calendar instance
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_deinit(struct calendar_dev *const dev);
/**
* \brief Enable Calendar instance
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_enable(struct calendar_dev *const dev);
/**
* \brief Disable Calendar instance
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_disable(struct calendar_dev *const dev);
/**
* \brief Set time for calendar
*
* \param[in] dev The pointer to calendar device struct
* \param[in] p_calendar_time Pointer to the time configuration
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_set_time(struct calendar_dev *const dev, struct calendar_time *const p_calendar_time);
/**
* \brief Set date for calendar
*
* \param[in] dev The pointer to calendar device struct
* \param[in] p_calendar_date Pointer to the date configuration
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_set_date(struct calendar_dev *const dev, struct calendar_date *const p_calendar_date);
/**
* \brief Get the time for calendar HAL instance and hardware
* Retrieve the time from calendar instance.
*
* \param[in] dev The pointer to calendar device struct
* \param[in] date_time Pointer to value that will be filled with current time
*
* \return Return current counter value
*/
uint32_t _calendar_get_date_time(struct calendar_dev *const dev, struct calendar_date_time *const date_time);
/**
* \brief Set compare value for calendar
*
* \param[in] dev The pointer to calendar device struct
* \param[in] alarm Pointer to the configuration
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_set_alarm(struct calendar_dev *const dev, struct _calendar_alarm *const alarm);
/**
* \brief Register callback for calendar alarm
*
* \param[in] dev The pointer to calendar device struct
* \param[in] callback The pointer to callback function
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback);
/**
* \brief Set calendar IRQ
*
* \param[in] dev The pointer to calendar device struct
*/
void _calendar_set_irq(struct calendar_dev *const dev);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_RTC_H_INCLUDED */

66
atmel-samd/asf4/samd21/hal/include/hpl_core.h
View File

@ -1,66 +0,0 @@
/**
* \file
*
* \brief CPU core related functionality declaration.
*
* Copyright (C) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CORE_H_INCLUDED
#define _HPL_CORE_H_INCLUDED
/**
* \addtogroup HPL Core
*
* \section hpl_core_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_core_port.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_CORE_H_INCLUDED */

182
atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h
View File

@ -1,182 +0,0 @@
/**
* \file
*
* \brief DAC related functionality declaration.
*
* Copyright (C) 2014-2017 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DAC_H_INCLUDED
#define _HPL_DAC_H_INCLUDED
/**
* \addtogroup hpl__dac__group DAC HPL APIs
* See interface description here: \ref hpl__dac__doc
*
*/
/**@{*/
#include <compiler.h>
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* DAC hardware Channel Number
*/
#ifndef CHANNEL_NUM
#define CHANNEL_NUM 1
#endif
/**
* \brief DAC callback types
*/
enum _dac_callback_type { DAC_DEVICE_CONVERSION_DONE_CB, DAC_DEVICE_ERROR_CB };
/**
* \brief DAC device structure
*
* The DAC device structure forward declaration.
*/
struct _dac_async_device;
/**
* \brief DAC interrupt handlers structure
*/
struct _dac_callback {
/** Transmit ready(Data Buffer empty) handler */
void (*tx_ready_cb)(struct _dac_async_device *device, const uint8_t ch);
/** Error handler */
void (*tx_error_cb)(struct _dac_async_device *device, const uint8_t ch);
};
/**
* \brief DAC descriptor device structure.
*/
struct _dac_async_device {
struct _dac_callback dac_cb; /*!< Interrupt handers */
struct _irq_descriptor irq; /*!< Interrupt descriptor */
void * hw; /*!< Hardware module instance handler */
};
/**
* \brief Initialize asynchronous DAC.
*
* This function does low level DAC configuration.
*
* \param[in] device The pointer to DAC device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw);
/**
* \brief Deinitialize DAC.
*
* \param[in] device The pointer to DAC device instance
*/
void _dac_async_deinit(struct _dac_async_device *const device);
/**
* \brief Enable DAC Channel.
*
* \param[in] device The pointer to DAC device instance
* \param[in] ch channel number
*/
void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch);
/**
* \brief Disable DAC Channel.
*
* \param[in] device The pointer to DAC device instance
* \param[in] ch channel number
*/
void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch);
/**
* \brief Checks if DAC channel is enabled
*
* \param[in] device The pointer to DAC device instance
* \param[in] ch channel number
*
* \return true channel is enabled, false otherwise
*/
bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch);
/**
* \brief Write DAC data for output.
*
* \param[in] device The pointer to DAC device instance
* \param[in] data Digital data which to be converted
* \param[in] ch The channel selected to output
*/
void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch);
/**
* \brief Enable/disable DAC interrupt
*
* param[in] device The pointer to DAC device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type,
const bool state);
#ifdef __cplusplus
}
#endif
/**@}*/
/**
* \page hpl__dac__doc DAC HPL Interface Driver
*
* \section hpl__dac__desc DAC HPL Description
*
* The following device can use this HPL driver
* - Atmel | SMART SAM D21
*
* \section hpl__dac__imple DAC HPL Implements
* - \subpage hpl__dac__hw_module1__doc
*/
#endif /* _HPL_DAC_H_INCLUDED */

148
atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h
View File

@ -1,148 +0,0 @@
/**
* \file
*
* \brief DAC related functionality declaration.
*
* Copyright (C) 2014-2017 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DAC_SYNC_H_INCLUDED
#define _HPL_DAC_SYNC_H_INCLUDED
/**
* \addtogroup hpl__dac__group DAC HPL APIs
* See interface description here: \ref hpl__dac__doc
*
*/
/**@{*/
#include <compiler.h>
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* DAC hardware Channel Number
*/
#ifndef CHANNEL_NUM
#define CHANNEL_NUM 1
#endif
/**
* \brief DAC sync descriptor device structure.
*/
struct _dac_sync_device {
void *hw; /*!< Hardware module instance handler */
};
/**
* \brief Initialize synchronous DAC.
*
* This function does low level DAC configuration.
*
* \param[in] device The pointer to DAC device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw);
/**
* \brief Deinitialize DAC.
*
* \param[in] device The pointer to DAC device instance
*/
void _dac_sync_deinit(struct _dac_sync_device *const device);
/**
* \brief Enable DAC Channel.
*
* \param[in] device The pointer to DAC device instance
* \param[in] ch channel number
*/
void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch);
/**
* \brief Disable DAC Channel.
*
* \param[in] device The pointer to DAC device instance
* \param[in] ch channel number
*/
void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch);
/**
* \brief Checks if DAC channel is enabled
*
* \param[in] device The pointer to DAC device instance
* \param[in] ch channel number
*
* \return true channel is enabled, false otherwise
*/
bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch);
/**
* \brief Write synchronous DAC data for output.
*
* \param[in] device The pointer to DAC device instance
* \param[in] data Digital data which to be converted
* \param[in] ch The channel selected to output
*/
void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch);
#ifdef __cplusplus
}
#endif
/**@}*/
/**
* \page hpl__dac__doc DAC HPL Interface Driver
*
* \section hpl__dac__desc DAC HPL Description
*
* The following device can use this HPL driver
* - Atmel | SMART SAM D21
*
* \section hpl__dac__imple DAC HPL Implements
* - \subpage hpl__dac__hw_module1__doc
*/
#endif /* _HPL_DAC_SYNC_H_INCLUDED */

Some files were not shown because too many files have changed in this diff Show More