djsundog/circuitpython
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Hosted Weblate 2022-02-19 21:22:39 +01:00
commit b6caac0f9e
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6 changed files with 20 additions and 5 deletions
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2
extmod/ulab

@ -1 +1 @@
Subproject commit 0c7c6b88f3ec1b1d11d2f7d8b185e28ac657c06d
Subproject commit 5d01882c41dbc4115bc94f0b61c093d5a6b812b6

2
py/py.mk
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@ -55,7 +55,7 @@ endif
ifeq ($(CIRCUITPY_ULAB),1)
ULAB_SRCS := $(shell find $(TOP)/extmod/ulab/code -type f -name "*.c")
SRC_MOD += $(patsubst $(TOP)/%,%,$(ULAB_SRCS))
CFLAGS_MOD += -DCIRCUITPY_ULAB=1 -DMODULE_ULAB_ENABLED=1 -iquote $(TOP)/extmod/ulab/code
CFLAGS_MOD += -DCIRCUITPY_ULAB=1 -DMODULE_ULAB_ENABLED=1 -DULAB_HAS_USER_MODULE=0 -iquote $(TOP)/extmod/ulab/code
$(BUILD)/extmod/ulab/code/%.o: CFLAGS += -Wno-missing-declarations -Wno-missing-prototypes -Wno-unused-parameter -Wno-float-equal -Wno-sign-compare -Wno-cast-align -Wno-shadow -DCIRCUITPY
endif

2
shared-bindings/adafruit_bus_device/__init__.c
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@ -78,3 +78,5 @@ const mp_obj_module_t adafruit_bus_device_module = {
};
MP_REGISTER_MODULE(MP_QSTR_adafruit_bus_device, adafruit_bus_device_module, CIRCUITPY_BUSDEVICE);
MP_REGISTER_MODULE(MP_QSTR_adafruit_bus_device_dot_i2c_device, adafruit_bus_device_i2c_device_module, CIRCUITPY_BUSDEVICE);
MP_REGISTER_MODULE(MP_QSTR_adafruit_bus_device_dot_spi_device, adafruit_bus_device_spi_device_module, CIRCUITPY_BUSDEVICE);

9
tests/circuitpython/builtin_submodule.py Normal file
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@ -0,0 +1,9 @@
try:
import ulab
except:
print("SKIP")
raise SystemExit(0)
import ulab.scipy.linalg
print(ulab.scipy.linalg)

1
tests/circuitpython/builtin_submodule.py.exp Normal file
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@ -0,0 +1 @@
<module 'linalg'>

9
tests/unix/extra_coverage.py.exp
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@ -37,9 +37,12 @@ gc gifio hashlib json
math qrio rainbowio re
sys termios traceback ubinascii
uctypes uerrno uheapq uio
ujson ulab uos urandom
ure uselect ustruct utime
utimeq uzlib
ujson ulab ulab.fft ulab.linalg
ulab.numpy ulab.scipy ulab.scipy.linalg
ulab.scipy.optimize ulab.scipy.signal
ulab.scipy.special ulab.utils uos
urandom ure uselect ustruct
utime utimeq uzlib
ime
utime utimeq