samd/clock_config: Set up the clock configuration.
Clock settings: - GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51). - GCLK1: 32768 Hz for driving the PLL. - GCLK2: 48 MHz for tzhe peripheral clock. - GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer. - GCLK8: 1 kHz for WDT (SAMD21 only). If a 32 kHz crystal is present, it will be used as clock source. Otherwise the DFLL48M in open-loop mode is used. GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified range is 96 MHz - 120 MHz.
This commit is contained in:
robert-hh
Damien George
parent
949a808076
commit
b4d29fd47a
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@ -83,6 +83,7 @@ LDFLAGS += -L"$(shell dirname $(LIBSTDCPP_FILE_NAME))"
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endif
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SRC_C = \
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clock_config.c \
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help.c \
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machine_led.c \
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machine_pin.c \
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@ -0,0 +1,348 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* This file provides functions for configuring the clocks.
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include "py/runtime.h"
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#include "samd_soc.h"
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static uint32_t cpu_freq = CPU_FREQ;
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static uint32_t apb_freq = APB_FREQ;
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#if defined(MCU_SAMD21)
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int sercom_gclk_id[] = {
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GCLK_CLKCTRL_ID_SERCOM0_CORE, GCLK_CLKCTRL_ID_SERCOM1_CORE,
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GCLK_CLKCTRL_ID_SERCOM2_CORE, GCLK_CLKCTRL_ID_SERCOM3_CORE,
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GCLK_CLKCTRL_ID_SERCOM4_CORE, GCLK_CLKCTRL_ID_SERCOM5_CORE
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};
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#elif defined(MCU_SAMD51)
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int sercom_gclk_id[] = {
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SERCOM0_GCLK_ID_CORE, SERCOM1_GCLK_ID_CORE,
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SERCOM2_GCLK_ID_CORE, SERCOM3_GCLK_ID_CORE,
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SERCOM4_GCLK_ID_CORE, SERCOM5_GCLK_ID_CORE,
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#if defined(SERCOM7_GCLK_ID_CORE)
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SERCOM6_GCLK_ID_CORE, SERCOM7_GCLK_ID_CORE,
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#endif
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};
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#endif
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uint32_t get_cpu_freq(void) {
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return cpu_freq;
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}
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uint32_t get_apb_freq(void) {
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return apb_freq;
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}
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#if defined(MCU_SAMD21)
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void set_cpu_freq(uint32_t cpu_freq_arg) {
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cpu_freq = cpu_freq_arg;
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}
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#elif defined(MCU_SAMD51)
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void set_cpu_freq(uint32_t cpu_freq_arg) {
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cpu_freq = cpu_freq_arg;
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// Setup GCLK0 for 48MHz as default state to keep the MCU running during config change.
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GCLK->GENCTRL[0].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL0) {
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}
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// Setup DPLL0 for 120 MHz
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// first: disable DPLL0 in case it is running
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OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 0;
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while (OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.ENABLE == 1) {
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}
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// Now configure the registers
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(1) | OSCCTRL_DPLLCTRLB_LBYPASS |
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OSCCTRL_DPLLCTRLB_REFCLK(0) | OSCCTRL_DPLLCTRLB_WUF | OSCCTRL_DPLLCTRLB_FILTER(0x01);
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uint32_t div = cpu_freq / DPLLx_REF_FREQ;
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uint32_t frac = (cpu_freq - div * DPLLx_REF_FREQ) / (DPLLx_REF_FREQ / 32);
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OSCCTRL->Dpll[0].DPLLRATIO.reg = (frac << 16) + div - 1;
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// enable it again
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OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE | OSCCTRL_DPLLCTRLA_RUNSTDBY;
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// Per errata 2.13.1
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while (!(OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 1)) {
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}
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// Setup GCLK0 for DPLL0 output (48 or 48-200MHz)
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GCLK->GENCTRL[0].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DPLL0;
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while (GCLK->SYNCBUSY.bit.GENCTRL0) {
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}
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}
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#endif
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void init_clocks(uint32_t cpu_freq) {
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#if defined(MCU_SAMD21)
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// SAMD21 Clock settings
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// GCLK0: 48MHz from DFLL open loop mode or closed loop mode from 32k Crystal
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// GCLK1: 32768 Hz from 32K ULP or 32k Crystal
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// GCLK2: 48MHz from DFLL for Peripherals
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// GCLK3: 1Mhz for the us-counter (TC3/TC4)
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// GCLK8: 1kHz clock for WDT
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NVMCTRL->CTRLB.bit.MANW = 1; // errata "Spurious Writes"
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NVMCTRL->CTRLB.bit.RWS = 1; // 1 read wait state for 48MHz
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#if MICROPY_HW_XOSC32K
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// Set up OSC32K according datasheet 17.6.3
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP(0x3) | SYSCTRL_XOSC32K_EN32K |
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SYSCTRL_XOSC32K_XTALEN;
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SYSCTRL->XOSC32K.bit.ENABLE = 1;
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while (SYSCTRL->PCLKSR.bit.XOSC32KRDY == 0) {
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}
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// Set up the DFLL48 according to the data sheet 17.6.7.1.2
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// Step 1: Set up the reference clock
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// Connect the OSC32K via GCLK1 to the DFLL input and for further use.
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(1) | GCLK_GENDIV_DIV(1);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(1);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_DFLL48 | GCLK_CLKCTRL_GEN_GCLK1 | GCLK_CLKCTRL_CLKEN;
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// Enable access to the DFLLCTRL reg acc. to Errata 1.2.1
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
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while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
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}
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// Step 2: Set the coarse and fine values.
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// The coarse setting will be taken from the calibration data. So the value used here
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// does not matter. Get the coarse value from the calib data. In case it is not set,
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// set a midrange value.
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uint32_t coarse = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR) & FUSES_DFLL48M_COARSE_CAL_Msk)
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>> FUSES_DFLL48M_COARSE_CAL_Pos;
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if (coarse == 0x3f) {
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coarse = 0x1f;
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}
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SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) | SYSCTRL_DFLLVAL_FINE(512);
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while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
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}
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// Step 3: Set the multiplication values. The offset of 16384 to the freq is for rounding.
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_MUL((CPU_FREQ + 16384) / 32768) |
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SYSCTRL_DFLLMUL_FSTEP(1) | SYSCTRL_DFLLMUL_CSTEP(1);
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while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
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}
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// Step 4: Start the DFLL and wait for the PLL lock. We just wait for the fine lock, since
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// coarse adjusting is bypassed.
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_WAITLOCK |
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SYSCTRL_DFLLCTRL_BPLCKC | SYSCTRL_DFLLCTRL_ENABLE;
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while (SYSCTRL->PCLKSR.bit.DFLLLCKF == 0) {
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}
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#else // MICROPY_HW_XOSC32K
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// Enable DFLL48M
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {
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}
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(1) | SYSCTRL_DFLLMUL_FSTEP(1)
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| SYSCTRL_DFLLMUL_MUL(48000);
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uint32_t coarse = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR) & FUSES_DFLL48M_COARSE_CAL_Msk)
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>> FUSES_DFLL48M_COARSE_CAL_Pos;
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if (coarse == 0x3f) {
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coarse = 0x1f;
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}
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SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) | SYSCTRL_DFLLVAL_FINE(512);
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_CCDIS | SYSCTRL_DFLLCTRL_USBCRM
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| SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {
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}
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// Enable 32768 Hz on GCLK1 for consistency
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(1) | GCLK_GENDIV_DIV(48016384 / 32768);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(1);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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#endif // MICROPY_HW_XOSC32K
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// Enable GCLK output: 48M on both CCLK0 and GCLK2
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(0) | GCLK_GENDIV_DIV(1);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(0);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(1);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(2);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Enable GCLK output: 1MHz on GCLK3 for TC3
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(3) | GCLK_GENDIV_DIV(48);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(3);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Set GCLK8 to 1 kHz.
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(8) | GCLK_GENDIV_DIV(32);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K | GCLK_GENCTRL_ID(8);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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#elif defined(MCU_SAMD51)
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// SAMD51 clock settings
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// GCLK0: 48MHz from DFLL48M or 48 - 200 MHz from DPLL0 (SAMD51)
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// GCLK1: DPLLx_REF_FREQ 32768 Hz from 32KULP or 32k Crystal
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// GCLK2: 48MHz from DFLL48M for Peripheral devices
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// GCLK3: 16Mhz for the us-counter (TC0/TC1)
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// DPLL0: 48 - 200 MHz
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// Steps to set up clocks:
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// Reset Clocks
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// Switch GCLK0 to DFLL 48MHz
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// Setup 32768 Hz source and DFLL48M in closed loop mode, if a crystal is present.
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// Setup GCLK1 to the DPLL0 Reference freq. of 32768 Hz
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// Setup GCLK1 to drive peripheral channel 1
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// Setup DPLL0 to 120MHz
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// Setup GCLK0 to 120MHz
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// Setup GCLK2 to 48MHz for Peripherals
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// Setup GCLK3 to 8MHz for TC0/TC1
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// Setup GCLK0 for 48MHz as default state to keep the MCU running during config change.
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GCLK->GENCTRL[0].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL0) {
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}
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#if MICROPY_HW_XOSC32K
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// OSCILLATOR CONTROL
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// Setup XOSC32K
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OSC32KCTRL->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY | OSC32KCTRL_INTFLAG_XOSC32KFAIL;
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OSC32KCTRL->XOSC32K.bit.CGM = OSC32KCTRL_XOSC32K_CGM_HS_Val;
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OSC32KCTRL->XOSC32K.bit.XTALEN = 1; // 0: Generator 1: Crystal
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OSC32KCTRL->XOSC32K.bit.EN32K = 1;
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OSC32KCTRL->XOSC32K.bit.ONDEMAND = 0;
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OSC32KCTRL->XOSC32K.bit.RUNSTDBY = 1;
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OSC32KCTRL->XOSC32K.bit.STARTUP = 4;
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OSC32KCTRL->CFDCTRL.bit.CFDEN = 1; // Fall back to internal Osc on crystal fail
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OSC32KCTRL->XOSC32K.bit.ENABLE = 1;
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// make sure osc32kcrtl is ready
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while (OSC32KCTRL->STATUS.bit.XOSC32KRDY == 0) {
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}
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// Setup GCLK1 for 32kHz crystal
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GCLK->GENCTRL[1].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K;
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while (GCLK->SYNCBUSY.bit.GENCTRL1) {
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}
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// Set-up the DFLL48M in closed loop mode with input from the 32kHz crystal
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// Step 1: Peripheral channel 0 is driven by GCLK1 and it feeds DFLL48M
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GCLK->PCHCTRL[0].reg = GCLK_PCHCTRL_GEN_GCLK1 | GCLK_PCHCTRL_CHEN;
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while (GCLK->PCHCTRL[0].bit.CHEN == 0) {
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}
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// Step 2: Set the multiplication values. The offset of 16384 to the freq is for rounding.
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OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_MUL((APB_FREQ + DPLLx_REF_FREQ / 2) / DPLLx_REF_FREQ) |
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OSCCTRL_DFLLMUL_FSTEP(1) | OSCCTRL_DFLLMUL_CSTEP(1);
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while (OSCCTRL->DFLLSYNC.bit.DFLLMUL == 1) {
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}
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// Step 3: Set the mode to closed loop
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OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_BPLCKC | OSCCTRL_DFLLCTRLB_MODE;
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while (OSCCTRL->DFLLSYNC.bit.DFLLCTRLB == 1) {
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}
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// Wait for lock fine
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while (OSCCTRL->STATUS.bit.DFLLLCKF == 0) {
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}
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// Step 4: Start the DFLL.
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OSCCTRL->DFLLCTRLA.reg = OSCCTRL_DFLLCTRLA_RUNSTDBY | OSCCTRL_DFLLCTRLA_ENABLE;
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while (OSCCTRL->DFLLSYNC.bit.ENABLE == 1) {
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}
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#else // MICROPY_HW_XOSC32K
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// Set GCLK1 to DPLL0_REF_FREQ as defined in mpconfigboard.h (e.g. 32768 Hz)
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GCLK->GENCTRL[1].reg = ((APB_FREQ + DPLLx_REF_FREQ / 2) / DPLLx_REF_FREQ) << GCLK_GENCTRL_DIV_Pos
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| GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL1) {
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}
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#endif // MICROPY_HW_XOSC32K
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// Peripheral channel 1 is driven by GCLK1 and it feeds DPLL0
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GCLK->PCHCTRL[1].reg = GCLK_PCHCTRL_GEN_GCLK1 | GCLK_PCHCTRL_CHEN;
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while (GCLK->PCHCTRL[1].bit.CHEN == 0) {
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}
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set_cpu_freq(cpu_freq);
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apb_freq = APB_FREQ; // To be changed if CPU_FREQ < 48M
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// Setup GCLK2 for DPLL1 output (48 MHz)
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GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL2) {
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}
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// Setup GCLK3 for 8MHz, Used for TC0/1 counter
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GCLK->GENCTRL[3].reg = GCLK_GENCTRL_DIV(6) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL3) {
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}
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#endif // defined(MCU_SAMD51)
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}
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void enable_sercom_clock(int id) {
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// Next: Set up the clocks
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#if defined(MCU_SAMD21)
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// Enable synchronous clock. The bits are nicely arranged
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PM->APBCMASK.reg |= 0x04 << id;
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// Select multiplexer generic clock source and enable.
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | sercom_gclk_id[id];
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// Wait while it updates synchronously.
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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#elif defined(MCU_SAMD51)
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GCLK->PCHCTRL[sercom_gclk_id[id]].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK2;
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// no easy way to set the clocks, except enabling all of them
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switch (id) {
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case 0:
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MCLK->APBAMASK.bit.SERCOM0_ = 1;
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break;
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case 1:
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MCLK->APBAMASK.bit.SERCOM1_ = 1;
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break;
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case 2:
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MCLK->APBBMASK.bit.SERCOM2_ = 1;
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break;
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case 3:
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MCLK->APBBMASK.bit.SERCOM3_ = 1;
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break;
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case 4:
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MCLK->APBDMASK.bit.SERCOM4_ = 1;
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break;
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case 5:
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MCLK->APBDMASK.bit.SERCOM5_ = 1;
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break;
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#ifdef SERCOM7_GCLK_ID_CORE
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case 6:
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MCLK->APBDMASK.bit.SERCOM6_ = 1;
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break;
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case 7:
|
||||
MCLK->APBDMASK.bit.SERCOM7_ = 1;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* This file provides functions for configuring the clocks.
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2022 Robert Hammelrath
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
void init_clocks(uint32_t cpu_freq);
|
||||
void set_cpu_freq(uint32_t cpu_freq);
|
||||
uint32_t get_cpu_freq(void);
|
||||
uint32_t get_apb_freq(void);
|
||||
void enable_sercom_clock(int id);
|
||||
|
|
@ -10,6 +10,7 @@
|
|||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Damien P. George
|
||||
* Copyright (c) 2022 Robert Hammelrath
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,6 +34,7 @@
|
|||
#include "py/runtime.h"
|
||||
#include "modmachine.h"
|
||||
#include "samd_soc.h"
|
||||
#include "sam.h"
|
||||
#include "tusb.h"
|
||||
|
||||
static void usb_init(void) {
|
||||
|
|
@ -43,7 +45,7 @@ static void usb_init(void) {
|
|||
PM->APBBMASK.bit.USB_ = 1;
|
||||
uint8_t alt = 6; // alt G, USB
|
||||
#elif defined(MCU_SAMD51)
|
||||
GCLK->PCHCTRL[USB_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK1;
|
||||
GCLK->PCHCTRL[USB_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK2;
|
||||
while (GCLK->PCHCTRL[USB_GCLK_ID].bit.CHEN == 0) {
|
||||
}
|
||||
MCLK->AHBMASK.bit.USB_ = 1;
|
||||
|
|
@ -61,43 +63,51 @@ static void usb_init(void) {
|
|||
tusb_init();
|
||||
}
|
||||
|
||||
void samd_init(void) {
|
||||
// Initialize the microsecond counter on TC 0/1
|
||||
void init_us_counter(void) {
|
||||
#if defined(MCU_SAMD21)
|
||||
|
||||
NVMCTRL->CTRLB.bit.MANW = 1; // errata "Spurious Writes"
|
||||
NVMCTRL->CTRLB.bit.RWS = 1; // 1 read wait state for 48MHz
|
||||
|
||||
// Enable DFLL48M
|
||||
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
|
||||
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {
|
||||
}
|
||||
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(1) | SYSCTRL_DFLLMUL_FSTEP(1)
|
||||
| SYSCTRL_DFLLMUL_MUL(48000);
|
||||
uint32_t coarse = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR) & FUSES_DFLL48M_COARSE_CAL_Msk)
|
||||
>> FUSES_DFLL48M_COARSE_CAL_Pos;
|
||||
if (coarse == 0x3f) {
|
||||
coarse = 0x1f;
|
||||
}
|
||||
uint32_t fine = 512;
|
||||
SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) | SYSCTRL_DFLLVAL_FINE(fine);
|
||||
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_CCDIS | SYSCTRL_DFLLCTRL_USBCRM
|
||||
| SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_ENABLE;
|
||||
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {
|
||||
}
|
||||
|
||||
GCLK->GENDIV.reg = GCLK_GENDIV_ID(0) | GCLK_GENDIV_DIV(1);
|
||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(0);
|
||||
PM->APBCMASK.bit.TC3_ = 1; // Enable TC3 clock
|
||||
PM->APBCMASK.bit.TC4_ = 1; // Enable TC4 clock
|
||||
// Select multiplexer generic clock source and enable.
|
||||
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_TC4_TC5;
|
||||
// Wait while it updates synchronously.
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
|
||||
// configure the timer
|
||||
TC4->COUNT32.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT32_Val;
|
||||
TC4->COUNT32.CTRLA.bit.RUNSTDBY = 1;
|
||||
TC4->COUNT32.CTRLA.bit.ENABLE = 1;
|
||||
while (TC4->COUNT32.STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
TC4->COUNT32.READREQ.reg = TC_READREQ_RREQ | TC_READREQ_RCONT | 0x10;
|
||||
while (TC4->COUNT32.STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
|
||||
#elif defined(MCU_SAMD51)
|
||||
|
||||
GCLK->GENCTRL[1].reg = 1 << GCLK_GENCTRL_DIV_Pos | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
|
||||
while (GCLK->SYNCBUSY.bit.GENCTRL1) {
|
||||
MCLK->APBAMASK.bit.TC0_ = 1; // Enable TC0 clock
|
||||
MCLK->APBAMASK.bit.TC1_ = 1; // Enable TC1 clock
|
||||
// Peripheral channel 9 is driven by GCLK3, 8 MHz.
|
||||
GCLK->PCHCTRL[TC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
|
||||
while (GCLK->PCHCTRL[TC0_GCLK_ID].bit.CHEN == 0) {
|
||||
}
|
||||
|
||||
// configure the timer
|
||||
TC0->COUNT32.CTRLA.bit.PRESCALER = 0;
|
||||
TC0->COUNT32.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT32_Val;
|
||||
TC0->COUNT32.CTRLA.bit.RUNSTDBY = 1;
|
||||
TC0->COUNT32.CTRLA.bit.ENABLE = 1;
|
||||
while (TC0->COUNT32.SYNCBUSY.bit.ENABLE) {
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
SysTick_Config(CPU_FREQ / 1000);
|
||||
void samd_init(void) {
|
||||
init_clocks(get_cpu_freq());
|
||||
SysTick_Config(get_cpu_freq() / 1000);
|
||||
init_us_counter();
|
||||
usb_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
|
||||
#include <stdint.h>
|
||||
#include "sam.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
void samd_init(void);
|
||||
void samd_main(void);
|
||||
|
|
@ -38,4 +39,14 @@ void USB_1_Handler_wrapper(void);
|
|||
void USB_2_Handler_wrapper(void);
|
||||
void USB_3_Handler_wrapper(void);
|
||||
|
||||
void common_uart_irq_handler(int uart_nr);
|
||||
void common_spi_irq_handler(int spi_nr);
|
||||
void common_i2c_irq_handler(int i2c_nr);
|
||||
void sercom_enable(Sercom *spi, int state);
|
||||
void sercom_register_irq(int sercom_id, int mode);
|
||||
|
||||
#define SERCOM_IRQ_TYPE_UART (0)
|
||||
#define SERCOM_IRQ_TYPE_SPI (1)
|
||||
#define SERCOM_IRQ_TYPE_I2C (2)
|
||||
|
||||
#endif // MICROPY_INCLUDED_SAMD_SAMD_SOC_H
|
||||
|
|
|
|||
Loading…
Reference in New Issue