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renesas-ra: Update boards and ra directory files to support FSP v4.4.0.

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* Update boards and ra files
* Remove unreferenced files, board_init.c and board_leds.c, from Makefile
* Remove unreferenced FSP instances from ra_gen/*.[ch]
* Remove unreferenced FSP config files ra_cfg/*.h
* e2 studio generates FSP instances but renesas-ra uses only followings:
  lpm, flash, ioport

Signed-off-by: Takeo Takahashi <takeo.takahashi.xv@renesas.com>
This commit is contained in:
Takeo Takahashi 2023-05-01 22:48:52 +09:00 committed by Damien George
parent 0c58e29074
commit b4834e5cba
114 changed files with 1331 additions and 5489 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
ports/renesas-ra/Makefile
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@ -342,11 +342,6 @@ SRC_O += \
SRC_O += \
shared/runtime/gchelper_thumb2.o
HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/board/$(BOARD_LOW)/,\
board_init.c \
board_leds.c \
)
HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/fsp/src/bsp/mcu/all/,\
bsp_clocks.c \
bsp_common.c \

21
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
@ -14,7 +18,13 @@
#define BSP_CFG_RTOS (0)
#endif
#endif
#ifndef BSP_CFG_RTC_USED
#define BSP_CFG_RTC_USED (1)
#endif
#undef RA_NOT_DEFINED
#if defined(_RA_BOOT_IMAGE)
#define BSP_CFG_BOOT_IMAGE (1)
#endif
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
#define BSP_CFG_HEAP_BYTES (0x4980)
@ -25,15 +35,14 @@
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_EARLY_INIT ((0))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
@ -46,4 +55,8 @@
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_CFG_H_ */

1
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
View File

@ -2,6 +2,7 @@
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA4M1AB3CFP
#define BSP_MCU_FEATURE_SET ('A')
#define BSP_ROM_SIZE_BYTES (262144)
#define BSP_RAM_SIZE_BYTES (32768)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)

13
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
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@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
@ -22,7 +26,6 @@
#endif
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
#define BSP_MCU_VBATT_SUPPORT (1)
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
@ -50,7 +53,9 @@
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
@ -71,4 +76,8 @@
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_adc_cfg.h
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@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_ADC_CFG_H_
#define R_ADC_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_ADC_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_agt_cfg.h
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@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_AGT_CFG_H_
#define R_AGT_CFG_H_
#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
#endif /* R_AGT_CFG_H_ */

6
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_dtc_cfg.h
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@ -1,6 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_DTC_CFG_H_
#define R_DTC_CFG_H_
#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
#endif /* R_DTC_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h
View File

@ -1,7 +1,15 @@
/* generated configuration header file - do not edit */
#ifndef R_FLASH_LP_CFG_H_
#define R_FLASH_LP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1)
#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0)
#ifdef __cplusplus
}
#endif
#endif /* R_FLASH_LP_CFG_H_ */

5
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_icu_cfg.h
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@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_ioport_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_IOPORT_CFG_H_ */

9
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_lpm_cfg.h
View File

@ -1,5 +1,14 @@
/* generated configuration header file - do not edit */
#ifndef R_LPM_CFG_H_
#define R_LPM_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define LPM_CFG_STANDBY_LIMIT (0)
#ifdef __cplusplus
}
#endif
#endif /* R_LPM_CFG_H_ */

5
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_rtc_cfg.h
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@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_RTC_CFG_H_
#define R_RTC_CFG_H_
#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_RTC_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
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@ -1,8 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#endif /* R_SCI_UART_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_spi_cfg.h
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@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_SPI_CFG_H_
#define R_SPI_CFG_H_
#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SPI_DTC_SUPPORT_ENABLE (1)
#define SPI_TRANSMIT_FROM_RXI_ISR (0)
#endif /* R_SPI_CFG_H_ */

2
ports/renesas-ra/boards/EK_RA4M1/ra_gen/bsp_clock_cfg.h
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@ -7,7 +7,7 @@
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_8_0 /* PLL Mul x8 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U, 0U) /* PLL Mul x8 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */

2
ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.c
View File

@ -3,5 +3,3 @@
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport =
{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
void g_common_init(void) {
}

4
ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.h
View File

@ -3,14 +3,16 @@
#define COMMON_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_ioport.h"
#include "bsp_pin_cfg.h"
FSP_HEADER
/* IOPORT Instance */
extern const ioport_instance_t g_ioport;
/* IOPORT control structure. */
extern ioport_instance_ctrl_t g_ioport_ctrl;
void g_common_init(void);
FSP_FOOTER
#endif /* COMMON_DATA_H_ */

453
ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.c
View File

@ -1,52 +1,15 @@
/* generated HAL source file - do not edit */
#include "hal_data.h"
/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
adc_instance_ctrl_t g_adc0_ctrl;
const adc_extended_cfg_t g_adc0_cfg_extend =
{ .add_average_count = ADC_ADD_OFF,
.clearing = ADC_CLEAR_AFTER_READ_ON,
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
const adc_cfg_t g_adc0_cfg =
{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment =
(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend,
#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
#else
.scan_end_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
#else
.scan_end_b_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
const adc_channel_cfg_t g_adc0_channel_cfg =
{ .scan_mask = 0,
.scan_mask_group_b = 0,
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
.add_mask = 0,
.sample_hold_mask = 0,
.sample_hold_states = 24, };
/* Instance structure to use this module. */
const adc_instance_t g_adc0 =
{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
lpm_instance_ctrl_t g_lpm0_ctrl;
const lpm_cfg_t g_lpm0_cfg =
{ .low_power_mode = LPM_MODE_SLEEP,
{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM
| (lpm_standby_wake_source_t)0,
#if BSP_FEATURE_LPM_HAS_SNOOZE
.snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0,
.snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
.snooze_end_sources = (lpm_snooze_end_t)0,
.dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
#endif
#if BSP_FEATURE_LPM_HAS_SBYCR_OPE
.output_port_enable = 0,
#endif
@ -56,171 +19,23 @@ const lpm_cfg_t g_lpm0_cfg =
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
#endif
#if BSP_FEATURE_LPM_HAS_PDRAMSCR
.ram_retention_cfg.ram_retention = (uint8_t)(0),
.ram_retention_cfg.tcm_retention = false,
#endif
#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP
.ram_retention_cfg.standby_ram_retention = false,
#endif
#if BSP_FEATURE_LPM_HAS_LDO_CONTROL
.ldo_standby_cfg.pll1_ldo = false,
.ldo_standby_cfg.pll2_ldo = false,
.ldo_standby_cfg.hoco_ldo = false,
#endif
.p_extend = NULL, };
const lpm_instance_t g_lpm0 =
{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg };
dtc_instance_ctrl_t g_transfer1_ctrl;
transfer_info_t g_transfer1_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer1_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_RXI, };
const transfer_cfg_t g_transfer1_cfg =
{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer1 =
{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc };
dtc_instance_ctrl_t g_transfer0_ctrl;
transfer_info_t g_transfer0_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer0_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_TXI, };
const transfer_cfg_t g_transfer0_cfg =
{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer0 =
{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc };
spi_instance_ctrl_t g_spi0_ctrl;
/** SPI extended configuration for SPI HAL driver */
const spi_extended_cfg_t g_spi0_ext_cfg =
{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
.ssl_polarity = SPI_SSLP_LOW,
.ssl_select = SPI_SSL_SELECT_SSL0,
.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
.parity = SPI_PARITY_MODE_DISABLE,
.byte_swap = SPI_BYTE_SWAP_DISABLE,
.spck_div =
{
/* Actual calculated bitrate: 12000000. */ .spbr = 1,
.brdv = 0
},
.spck_delay = SPI_DELAY_COUNT_1,
.ssl_negation_delay = SPI_DELAY_COUNT_1,
.next_access_delay = SPI_DELAY_COUNT_1 };
/** SPI configuration for SPI HAL driver */
const spi_cfg_t g_spi0_cfg =
{ .channel = 0,
#if defined(VECTOR_NUMBER_SPI0_RXI)
.rxi_irq = VECTOR_NUMBER_SPI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TXI)
.txi_irq = VECTOR_NUMBER_SPI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TEI)
.tei_irq = VECTOR_NUMBER_SPI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_ERI)
.eri_irq = VECTOR_NUMBER_SPI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.rxi_ipl = (12),
.txi_ipl = (12),
.tei_ipl = (12),
.eri_ipl = (12),
.operating_mode = SPI_MODE_MASTER,
.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
.clk_polarity = SPI_CLK_POLARITY_LOW,
.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
.bit_order = SPI_BIT_ORDER_MSB_FIRST,
.p_transfer_tx = g_spi0_P_TRANSFER_TX,
.p_transfer_rx = g_spi0_P_TRANSFER_RX,
.p_callback = spi_callback,
.p_context = NULL,
.p_extend = (void *)&g_spi0_ext_cfg, };
/* Instance structure to use this module. */
const spi_instance_t g_spi0 =
{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi };
icu_instance_ctrl_t g_external_irq0_ctrl;
const external_irq_cfg_t g_external_irq0_cfg =
{ .channel = 0,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ0)
.irq = VECTOR_NUMBER_ICU_IRQ0,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq0 =
{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu };
agt_instance_ctrl_t g_timer0_ctrl;
const agt_extended_cfg_t g_timer0_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer0_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer0_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT0_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer0 =
{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
flash_lp_instance_ctrl_t g_flash0_ctrl;
const flash_cfg_t g_flash0_cfg =
{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED),
@ -233,239 +48,3 @@ const flash_cfg_t g_flash0_cfg =
/* Instance structure to use this module. */
const flash_instance_t g_flash0 =
{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp };
rtc_instance_ctrl_t g_rtc0_ctrl;
const rtc_error_adjustment_cfg_t g_rtc0_err_cfg =
{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC,
.adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND,
.adjustment_type = RTC_ERROR_ADJUSTMENT_NONE,
.adjustment_value = 0, };
const rtc_cfg_t g_rtc0_cfg =
{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback =
NULL,
.p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14),
#if defined(VECTOR_NUMBER_RTC_ALARM)
.alarm_irq = VECTOR_NUMBER_RTC_ALARM,
#else
.alarm_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_PERIOD)
.periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
#else
.periodic_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_CARRY)
.carry_irq = VECTOR_NUMBER_RTC_CARRY,
#else
.carry_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const rtc_instance_t g_rtc0 =
{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc };
sci_uart_instance_ctrl_t g_uart2_ctrl;
baud_setting_t g_uart2_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart2_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart2_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart2_cfg =
{ .channel = 2, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart2_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI2_RXI)
.rxi_irq = VECTOR_NUMBER_SCI2_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_TXI)
.txi_irq = VECTOR_NUMBER_SCI2_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_TEI)
.tei_irq = VECTOR_NUMBER_SCI2_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_ERI)
.eri_irq = VECTOR_NUMBER_SCI2_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart2 =
{ .p_ctrl = &g_uart2_ctrl, .p_cfg = &g_uart2_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart1_ctrl;
baud_setting_t g_uart1_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart1_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart1_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart1_cfg =
{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart1_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI1_RXI)
.rxi_irq = VECTOR_NUMBER_SCI1_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_TXI)
.txi_irq = VECTOR_NUMBER_SCI1_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_TEI)
.tei_irq = VECTOR_NUMBER_SCI1_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_ERI)
.eri_irq = VECTOR_NUMBER_SCI1_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart1 =
{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart0_ctrl;
baud_setting_t g_uart0_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart0_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart0_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart0_cfg =
{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart0_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI0_RXI)
.rxi_irq = VECTOR_NUMBER_SCI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TXI)
.txi_irq = VECTOR_NUMBER_SCI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TEI)
.tei_irq = VECTOR_NUMBER_SCI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_ERI)
.eri_irq = VECTOR_NUMBER_SCI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart0 =
{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci };
void g_hal_init(void) {
g_common_init();
}

123
ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.h
View File

@ -2,99 +2,20 @@
#ifndef HAL_DATA_H_
#define HAL_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "common_data.h"
#include "r_adc.h"
#include "r_adc_api.h"
#include "r_lpm.h"
#include "r_lpm_api.h"
#include "r_dtc.h"
#include "r_transfer_api.h"
#include "r_spi.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_agt.h"
#include "r_timer_api.h"
#include "r_flash_lp.h"
#include "r_flash_api.h"
#include "r_rtc.h"
#include "r_rtc_api.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
FSP_HEADER
/** ADC on ADC Instance. */
extern const adc_instance_t g_adc0;
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
extern adc_instance_ctrl_t g_adc0_ctrl;
extern const adc_cfg_t g_adc0_cfg;
extern const adc_channel_cfg_t g_adc0_channel_cfg;
#ifndef NULL
void NULL(adc_callback_args_t *p_args);
#endif
/** lpm Instance */
extern const lpm_instance_t g_lpm0;
/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */
extern lpm_instance_ctrl_t g_lpm0_ctrl;
extern const lpm_cfg_t g_lpm0_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer1;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer1_ctrl;
extern const transfer_cfg_t g_transfer1_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer0;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer0_ctrl;
extern const transfer_cfg_t g_transfer0_cfg;
/** SPI on SPI Instance. */
extern const spi_instance_t g_spi0;
/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
extern spi_instance_ctrl_t g_spi0_ctrl;
extern const spi_cfg_t g_spi0_cfg;
/** Callback used by SPI Instance. */
#ifndef spi_callback
void spi_callback(spi_callback_args_t *p_args);
#endif
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == g_transfer0)
#define g_spi0_P_TRANSFER_TX (NULL)
#else
#define g_spi0_P_TRANSFER_TX (&g_transfer0)
#endif
#if (RA_NOT_DEFINED == g_transfer1)
#define g_spi0_P_TRANSFER_RX (NULL)
#else
#define g_spi0_P_TRANSFER_RX (&g_transfer1)
#endif
#undef RA_NOT_DEFINED
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq0;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq0_ctrl;
extern const external_irq_cfg_t g_external_irq0_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer0;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer0_ctrl;
extern const timer_cfg_t g_timer0_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/* Flash on Flash LP Instance. */
extern const flash_instance_t g_flash0;
@ -105,50 +26,8 @@ extern const flash_cfg_t g_flash0_cfg;
#ifndef NULL
void NULL(flash_callback_args_t *p_args);
#endif
/* RTC Instance. */
extern const rtc_instance_t g_rtc0;
/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */
extern rtc_instance_ctrl_t g_rtc0_ctrl;
extern const rtc_cfg_t g_rtc0_cfg;
#ifndef NULL
void NULL(rtc_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart2;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart2_ctrl;
extern const uart_cfg_t g_uart2_cfg;
extern const sci_uart_extended_cfg_t g_uart2_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart1;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart1_ctrl;
extern const uart_cfg_t g_uart1_cfg;
extern const sci_uart_extended_cfg_t g_uart1_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart0;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart0_ctrl;
extern const uart_cfg_t g_uart0_cfg;
extern const sci_uart_extended_cfg_t g_uart0_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
void hal_entry(void);
void g_hal_init(void);
FSP_FOOTER
#endif /* HAL_DATA_H_ */

188
ports/renesas-ra/boards/EK_RA4M1/ra_gen/pin_data.c
View File

@ -1,105 +1,91 @@
/* generated pin source file - do not edit */
#include "bsp_api.h"
#include "r_ioport_api.h"
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{
.pin = BSP_IO_PORT_00_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE),
},
{
.pin = BSP_IO_PORT_01_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_03,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
{
.pin = BSP_IO_PORT_01_PIN_06,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_01_PIN_08,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_09,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_15,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU),
},
{
.pin = BSP_IO_PORT_02_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU),
},
{
.pin = BSP_IO_PORT_03_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_03_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_03_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_04_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_03,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_04_PIN_07,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS),
},
{
.pin = BSP_IO_PORT_04_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_11,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_09_PIN_14,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS),
},
{
.pin = BSP_IO_PORT_09_PIN_15,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS),
},
};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] =
{
{ .pin = BSP_IO_PORT_00_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
{ .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE
| (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) },
{ .pin = BSP_IO_PORT_01_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) },
{ .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_01_PIN_15, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_CTSU) },
{ .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_CTSU) },
{ .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_03_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_03_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_04_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) },
{ .pin = BSP_IO_PORT_04_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_04_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) },
{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_USB_FS) },
{ .pin = BSP_IO_PORT_04_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_04_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_USB_FS) },
{ .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_USB_FS) },
};
const ioport_cfg_t g_bsp_pin_cfg =
{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], };
#if BSP_TZ_SECURE_BUILD
void R_BSP_PinCfgSecurityInit(void);
/* Initialize SAR registers for secure pins. */
void R_BSP_PinCfgSecurityInit(void) {
#if (2U == BSP_FEATURE_IOPORT_VERSION)
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#else
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#endif
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
{
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
uint32_t port = port_pin >> 8U;
uint32_t pin = port_pin & 0xFFU;
pmsar[port] &= (uint16_t) ~(1U << pin);
}
for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
{
#if (2U == BSP_FEATURE_IOPORT_VERSION)
R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i];
#else
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
#endif
}
}
#endif

46
ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.c
View File

@ -4,7 +4,7 @@
#if VECTOR_DATA_IRQ_COUNT > 0
BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
{
[0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */
[0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */
[1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */
[2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */
[3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */
@ -14,17 +14,17 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS
[7] = sci_uart_eri_isr, /* SCI1 ERI (Receive error) */
[8] = sci_uart_rxi_isr, /* SCI2 RXI (Received data full) */
[9] = sci_uart_txi_isr, /* SCI2 TXI (Transmit data empty) */
[10] = sci_uart_tei_isr, /* SCI2 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[17] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[18] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[19] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[20] = spi_eri_isr, /* SPI0 ERI (Error) */
[10] = sci_uart_tei_isr, /* SCI2 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[17] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[18] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[19] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[20] = spi_eri_isr, /* SPI0 ERI (Error) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
@ -38,16 +38,16 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT
[7] = BSP_PRV_IELS_ENUM(EVENT_SCI1_ERI), /* SCI1 ERI (Receive error) */
[8] = BSP_PRV_IELS_ENUM(EVENT_SCI2_RXI), /* SCI2 RXI (Received data full) */
[9] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TXI), /* SCI2 TXI (Transmit data empty) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TEI), /* SCI2 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[17] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[18] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[19] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[20] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TEI), /* SCI2 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[17] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[18] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[19] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[20] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
};
#endif

62
ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.h
View File

@ -1,6 +1,9 @@
/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (21)
@ -21,59 +24,48 @@ void spi_eri_isr(void);
/* Vector table allocations */
#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
#define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
#define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
#define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
#define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
#define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */
#define SCI1_RXI_IRQn ((IRQn_Type)4) /* SCI1 RXI (Received data full) */
#define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */
#define SCI1_TXI_IRQn ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */
#define SCI1_TEI_IRQn ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */
#define SCI1_ERI_IRQn ((IRQn_Type)7) /* SCI1 ERI (Receive error) */
#define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)8) /* SCI2 RXI (Received data full) */
#define SCI2_RXI_IRQn ((IRQn_Type)8) /* SCI2 RXI (Received data full) */
#define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */
#define SCI2_TXI_IRQn ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */
#define SCI2_TEI_IRQn ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)11) /* SCI2 ERI (Receive error) */
#define SCI2_ERI_IRQn ((IRQn_Type)11) /* SCI2 ERI (Receive error) */
#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */
#define ICU_IRQ0_IRQn ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */
#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */
#define SPI0_RXI_IRQn ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */
#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */
#define SPI0_TXI_IRQn ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */
#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */
#define SPI0_TEI_IRQn ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */
#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)20) /* SPI0 ERI (Error) */
typedef enum IRQn
{
Reset_IRQn = -15,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SecureFault_IRQn = -9,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */
SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */
SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */
SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */
SCI1_RXI_IRQn = 4, /* SCI1 RXI (Received data full) */
SCI1_TXI_IRQn = 5, /* SCI1 TXI (Transmit data empty) */
SCI1_TEI_IRQn = 6, /* SCI1 TEI (Transmit end) */
SCI1_ERI_IRQn = 7, /* SCI1 ERI (Receive error) */
SCI2_RXI_IRQn = 8, /* SCI2 RXI (Received data full) */
SCI2_TXI_IRQn = 9, /* SCI2 TXI (Transmit data empty) */
SCI2_TEI_IRQn = 10, /* SCI2 TEI (Transmit end) */
SCI2_ERI_IRQn = 11, /* SCI2 ERI (Receive error) */
RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */
RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */
RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */
AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */
ICU_IRQ0_IRQn = 16, /* ICU IRQ0 (External pin interrupt 0) */
SPI0_RXI_IRQn = 17, /* SPI0 RXI (Receive buffer full) */
SPI0_TXI_IRQn = 18, /* SPI0 TXI (Transmit buffer empty) */
SPI0_TEI_IRQn = 19, /* SPI0 TEI (Transmission complete event) */
SPI0_ERI_IRQn = 20, /* SPI0 ERI (Error) */
} IRQn_Type;
#define SPI0_ERI_IRQn ((IRQn_Type)20) /* SPI0 ERI (Error) */
#ifdef __cplusplus
}
#endif
#endif /* VECTOR_DATA_H */

21
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
@ -14,7 +18,13 @@
#define BSP_CFG_RTOS (0)
#endif
#endif
#ifndef BSP_CFG_RTC_USED
#define BSP_CFG_RTC_USED (1)
#endif
#undef RA_NOT_DEFINED
#if defined(_RA_BOOT_IMAGE)
#define BSP_CFG_BOOT_IMAGE (1)
#endif
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x4000)
#define BSP_CFG_HEAP_BYTES (0xf000)
@ -25,15 +35,14 @@
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_EARLY_INIT ((0))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
@ -46,4 +55,8 @@
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_CFG_H_ */

1
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
View File

@ -2,6 +2,7 @@
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA4W1AD2CNG
#define BSP_MCU_FEATURE_SET ('A')
#define BSP_ROM_SIZE_BYTES (524288)
#define BSP_RAM_SIZE_BYTES (98304)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)

13
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h"
@ -22,7 +26,6 @@
#endif
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
#define BSP_MCU_VBATT_SUPPORT (1)
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
@ -50,7 +53,9 @@
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
@ -71,4 +76,8 @@
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_adc_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_ADC_CFG_H_
#define R_ADC_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_ADC_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_agt_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_AGT_CFG_H_
#define R_AGT_CFG_H_
#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
#endif /* R_AGT_CFG_H_ */

6
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_dtc_cfg.h
View File

@ -1,6 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_DTC_CFG_H_
#define R_DTC_CFG_H_
#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
#endif /* R_DTC_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h
View File

@ -1,7 +1,15 @@
/* generated configuration header file - do not edit */
#ifndef R_FLASH_LP_CFG_H_
#define R_FLASH_LP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1)
#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0)
#ifdef __cplusplus
}
#endif
#endif /* R_FLASH_LP_CFG_H_ */

5
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_icu_cfg.h
View File

@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_iic_master_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_IIC_MASTER_CFG_H_
#define R_IIC_MASTER_CFG_H_
#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define IIC_MASTER_CFG_DTC_ENABLE (0)
#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0)
#endif /* R_IIC_MASTER_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_ioport_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_IOPORT_CFG_H_ */

9
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_lpm_cfg.h
View File

@ -1,5 +1,14 @@
/* generated configuration header file - do not edit */
#ifndef R_LPM_CFG_H_
#define R_LPM_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define LPM_CFG_STANDBY_LIMIT (0)
#ifdef __cplusplus
}
#endif
#endif /* R_LPM_CFG_H_ */

5
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_rtc_cfg.h
View File

@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_RTC_CFG_H_
#define R_RTC_CFG_H_
#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_RTC_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
View File

@ -1,8 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#endif /* R_SCI_UART_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_spi_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_SPI_CFG_H_
#define R_SPI_CFG_H_
#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SPI_DTC_SUPPORT_ENABLE (1)
#define SPI_TRANSMIT_FROM_RXI_ISR (0)
#endif /* R_SPI_CFG_H_ */

4
ports/renesas-ra/boards/EK_RA4W1/ra_gen/bsp_clock_cfg.h
View File

@ -7,15 +7,13 @@
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_12_0) /* PLL Mul x12 */
#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(12U, 0U)) /* PLL Mul x12 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */

2
ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.c
View File

@ -3,5 +3,3 @@
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport =
{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
void g_common_init(void) {
}

5
ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.h
View File

@ -5,12 +5,15 @@
#include "bsp_api.h"
#include "r_ioport.h"
#include "bsp_pin_cfg.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
FSP_HEADER
/* IOPORT Instance */
extern const ioport_instance_t g_ioport;
/* IOPORT control structure. */
extern ioport_instance_ctrl_t g_ioport_ctrl;
void g_common_init(void);
FSP_FOOTER
#endif /* COMMON_DATA_H_ */

605
ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.c
View File

@ -1,98 +1,15 @@
/* generated HAL source file - do not edit */
#include "hal_data.h"
/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
adc_instance_ctrl_t g_adc0_ctrl;
const adc_extended_cfg_t g_adc0_cfg_extend =
{ .add_average_count = ADC_ADD_OFF,
.clearing = ADC_CLEAR_AFTER_READ_ON,
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
const adc_cfg_t g_adc0_cfg =
{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment =
(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend,
#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
#else
.scan_end_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
#else
.scan_end_b_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
const adc_channel_cfg_t g_adc0_channel_cfg =
{ .scan_mask = 0,
.scan_mask_group_b = 0,
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
.add_mask = 0,
.sample_hold_mask = 0,
.sample_hold_states = 24, };
/* Instance structure to use this module. */
const adc_instance_t g_adc0 =
{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
iic_master_instance_ctrl_t g_i2c_master0_ctrl;
const iic_master_extended_cfg_t g_i2c_master0_extend =
{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT,
/* Actual calculated bitrate: 99272. Actual calculated duty cycle: 49%. */ .clock_settings.brl_value = 27,
.clock_settings.brh_value = 26, .clock_settings.cks_value = 2, };
const i2c_master_cfg_t g_i2c_master0_cfg =
{ .channel = 0, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.p_callback = callback_iic,
.p_context = NULL,
#if defined(VECTOR_NUMBER_IIC0_RXI)
.rxi_irq = VECTOR_NUMBER_IIC0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC0_TXI)
.txi_irq = VECTOR_NUMBER_IIC0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC0_TEI)
.tei_irq = VECTOR_NUMBER_IIC0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC0_ERI)
.eri_irq = VECTOR_NUMBER_IIC0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.ipl = (12),
.p_extend = &g_i2c_master0_extend, };
/* Instance structure to use this module. */
const i2c_master_instance_t g_i2c_master0 =
{ .p_ctrl = &g_i2c_master0_ctrl, .p_cfg = &g_i2c_master0_cfg, .p_api = &g_i2c_master_on_iic };
lpm_instance_ctrl_t g_lpm0_ctrl;
const lpm_cfg_t g_lpm0_cfg =
{ .low_power_mode = LPM_MODE_SLEEP,
{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM
| (lpm_standby_wake_source_t)0,
#if BSP_FEATURE_LPM_HAS_SNOOZE
.snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0,
.snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
.snooze_end_sources = (lpm_snooze_end_t)0,
.dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
#endif
#if BSP_FEATURE_LPM_HAS_SBYCR_OPE
.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
#endif
@ -102,278 +19,24 @@ const lpm_cfg_t g_lpm0_cfg =
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
#endif
#if BSP_FEATURE_LPM_HAS_PDRAMSCR
.ram_retention_cfg.ram_retention = (uint8_t)(0),
.ram_retention_cfg.tcm_retention = false,
#endif
#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP
.ram_retention_cfg.standby_ram_retention = false,
#endif
#if BSP_FEATURE_LPM_HAS_LDO_CONTROL
.ldo_standby_cfg.pll1_ldo = false,
.ldo_standby_cfg.pll2_ldo = false,
.ldo_standby_cfg.hoco_ldo = false,
#endif
.p_extend = NULL, };
const lpm_instance_t g_lpm0 =
{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg };
dtc_instance_ctrl_t g_transfer1_ctrl;
transfer_info_t g_transfer1_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer1_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_RXI, };
const transfer_cfg_t g_transfer1_cfg =
{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer1 =
{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc };
dtc_instance_ctrl_t g_transfer0_ctrl;
transfer_info_t g_transfer0_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer0_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_TXI, };
const transfer_cfg_t g_transfer0_cfg =
{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer0 =
{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc };
spi_instance_ctrl_t g_spi0_ctrl;
/** SPI extended configuration for SPI HAL driver */
const spi_extended_cfg_t g_spi0_ext_cfg =
{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
.ssl_polarity = SPI_SSLP_LOW,
.ssl_select = SPI_SSL_SELECT_SSL0,
.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
.parity = SPI_PARITY_MODE_DISABLE,
.byte_swap = SPI_BYTE_SWAP_DISABLE,
.spck_div =
{
/* Actual calculated bitrate: 12000000. */ .spbr = 1,
.brdv = 0
},
.spck_delay = SPI_DELAY_COUNT_1,
.ssl_negation_delay = SPI_DELAY_COUNT_1,
.next_access_delay = SPI_DELAY_COUNT_1 };
/** SPI configuration for SPI HAL driver */
const spi_cfg_t g_spi0_cfg =
{ .channel = 0,
#if defined(VECTOR_NUMBER_SPI0_RXI)
.rxi_irq = VECTOR_NUMBER_SPI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TXI)
.txi_irq = VECTOR_NUMBER_SPI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TEI)
.tei_irq = VECTOR_NUMBER_SPI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_ERI)
.eri_irq = VECTOR_NUMBER_SPI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.rxi_ipl = (12),
.txi_ipl = (12),
.tei_ipl = (12),
.eri_ipl = (12),
.operating_mode = SPI_MODE_MASTER,
.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
.clk_polarity = SPI_CLK_POLARITY_LOW,
.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
.bit_order = SPI_BIT_ORDER_MSB_FIRST,
.p_transfer_tx = g_spi0_P_TRANSFER_TX,
.p_transfer_rx = g_spi0_P_TRANSFER_RX,
.p_callback = spi_callback,
.p_context = NULL,
.p_extend = (void *)&g_spi0_ext_cfg, };
/* Instance structure to use this module. */
const spi_instance_t g_spi0 =
{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi };
icu_instance_ctrl_t g_external_irq4_ctrl;
const external_irq_cfg_t g_external_irq4_cfg =
{ .channel = 4,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ4)
.irq = VECTOR_NUMBER_ICU_IRQ4,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq4 =
{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq3_ctrl;
const external_irq_cfg_t g_external_irq3_cfg =
{ .channel = 3,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ3)
.irq = VECTOR_NUMBER_ICU_IRQ3,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq3 =
{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq2_ctrl;
const external_irq_cfg_t g_external_irq2_cfg =
{ .channel = 2,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ2)
.irq = VECTOR_NUMBER_ICU_IRQ2,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq2 =
{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq1_ctrl;
const external_irq_cfg_t g_external_irq1_cfg =
{ .channel = 1,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ1)
.irq = VECTOR_NUMBER_ICU_IRQ1,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq1 =
{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq0_ctrl;
const external_irq_cfg_t g_external_irq0_cfg =
{ .channel = 0,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ0)
.irq = VECTOR_NUMBER_ICU_IRQ0,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq0 =
{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu };
agt_instance_ctrl_t g_timer1_ctrl;
const agt_extended_cfg_t g_timer1_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer1_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 1, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer1_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT1_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT1_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer1 =
{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt };
agt_instance_ctrl_t g_timer0_ctrl;
const agt_extended_cfg_t g_timer0_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer0_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer0_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT0_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer0 =
{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
flash_lp_instance_ctrl_t g_flash0_ctrl;
const flash_cfg_t g_flash0_cfg =
{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED),
@ -386,239 +49,3 @@ const flash_cfg_t g_flash0_cfg =
/* Instance structure to use this module. */
const flash_instance_t g_flash0 =
{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp };
rtc_instance_ctrl_t g_rtc0_ctrl;
const rtc_error_adjustment_cfg_t g_rtc0_err_cfg =
{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC,
.adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND,
.adjustment_type = RTC_ERROR_ADJUSTMENT_NONE,
.adjustment_value = 0, };
const rtc_cfg_t g_rtc0_cfg =
{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback =
NULL,
.p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14),
#if defined(VECTOR_NUMBER_RTC_ALARM)
.alarm_irq = VECTOR_NUMBER_RTC_ALARM,
#else
.alarm_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_PERIOD)
.periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
#else
.periodic_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_CARRY)
.carry_irq = VECTOR_NUMBER_RTC_CARRY,
#else
.carry_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const rtc_instance_t g_rtc0 =
{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc };
sci_uart_instance_ctrl_t g_uart9_ctrl;
baud_setting_t g_uart9_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart9_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart9_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart9_cfg =
{ .channel = 9, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart9_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI9_RXI)
.rxi_irq = VECTOR_NUMBER_SCI9_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI9_TXI)
.txi_irq = VECTOR_NUMBER_SCI9_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI9_TEI)
.tei_irq = VECTOR_NUMBER_SCI9_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI9_ERI)
.eri_irq = VECTOR_NUMBER_SCI9_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart9 =
{ .p_ctrl = &g_uart9_ctrl, .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart4_ctrl;
baud_setting_t g_uart4_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart4_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart4_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart4_cfg =
{ .channel = 4, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart4_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI4_RXI)
.rxi_irq = VECTOR_NUMBER_SCI4_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI4_TXI)
.txi_irq = VECTOR_NUMBER_SCI4_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI4_TEI)
.tei_irq = VECTOR_NUMBER_SCI4_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI4_ERI)
.eri_irq = VECTOR_NUMBER_SCI4_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart4 =
{ .p_ctrl = &g_uart4_ctrl, .p_cfg = &g_uart4_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart1_ctrl;
baud_setting_t g_uart1_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart1_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart1_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart1_cfg =
{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart1_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI1_RXI)
.rxi_irq = VECTOR_NUMBER_SCI1_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_TXI)
.txi_irq = VECTOR_NUMBER_SCI1_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_TEI)
.tei_irq = VECTOR_NUMBER_SCI1_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_ERI)
.eri_irq = VECTOR_NUMBER_SCI1_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart1 =
{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci };
void g_hal_init(void) {
g_common_init();
}

185
ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.h
View File

@ -2,161 +2,20 @@
#ifndef HAL_DATA_H_
#define HAL_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "common_data.h"
#include "r_adc.h"
#include "r_adc_api.h"
#include "r_iic_master.h"
#include "r_i2c_master_api.h"
#include "r_lpm.h"
#include "r_lpm_api.h"
#include "r_dtc.h"
#include "r_transfer_api.h"
#include "r_spi.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_agt.h"
#include "r_timer_api.h"
#include "r_flash_lp.h"
#include "r_flash_api.h"
#include "r_rtc.h"
#include "r_rtc_api.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
FSP_HEADER
/** ADC on ADC Instance. */
extern const adc_instance_t g_adc0;
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
extern adc_instance_ctrl_t g_adc0_ctrl;
extern const adc_cfg_t g_adc0_cfg;
extern const adc_channel_cfg_t g_adc0_channel_cfg;
#ifndef NULL
void NULL(adc_callback_args_t *p_args);
#endif
/* I2C Master on IIC Instance. */
extern const i2c_master_instance_t g_i2c_master0;
/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */
extern iic_master_instance_ctrl_t g_i2c_master0_ctrl;
extern const i2c_master_cfg_t g_i2c_master0_cfg;
#ifndef callback_iic
void callback_iic(i2c_master_callback_args_t *p_args);
#endif
/** lpm Instance */
extern const lpm_instance_t g_lpm0;
/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */
extern lpm_instance_ctrl_t g_lpm0_ctrl;
extern const lpm_cfg_t g_lpm0_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer1;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer1_ctrl;
extern const transfer_cfg_t g_transfer1_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer0;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer0_ctrl;
extern const transfer_cfg_t g_transfer0_cfg;
/** SPI on SPI Instance. */
extern const spi_instance_t g_spi0;
/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
extern spi_instance_ctrl_t g_spi0_ctrl;
extern const spi_cfg_t g_spi0_cfg;
/** Callback used by SPI Instance. */
#ifndef spi_callback
void spi_callback(spi_callback_args_t *p_args);
#endif
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == g_transfer0)
#define g_spi0_P_TRANSFER_TX (NULL)
#else
#define g_spi0_P_TRANSFER_TX (&g_transfer0)
#endif
#if (RA_NOT_DEFINED == g_transfer1)
#define g_spi0_P_TRANSFER_RX (NULL)
#else
#define g_spi0_P_TRANSFER_RX (&g_transfer1)
#endif
#undef RA_NOT_DEFINED
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq4;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq4_ctrl;
extern const external_irq_cfg_t g_external_irq4_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq3;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq3_ctrl;
extern const external_irq_cfg_t g_external_irq3_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq2;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq2_ctrl;
extern const external_irq_cfg_t g_external_irq2_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq1;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq1_ctrl;
extern const external_irq_cfg_t g_external_irq1_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq0;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq0_ctrl;
extern const external_irq_cfg_t g_external_irq0_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer1;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer1_ctrl;
extern const timer_cfg_t g_timer1_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer0;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer0_ctrl;
extern const timer_cfg_t g_timer0_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/* Flash on Flash LP Instance. */
extern const flash_instance_t g_flash0;
@ -167,50 +26,8 @@ extern const flash_cfg_t g_flash0_cfg;
#ifndef NULL
void NULL(flash_callback_args_t *p_args);
#endif
/* RTC Instance. */
extern const rtc_instance_t g_rtc0;
/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */
extern rtc_instance_ctrl_t g_rtc0_ctrl;
extern const rtc_cfg_t g_rtc0_cfg;
#ifndef NULL
void NULL(rtc_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart9;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart9_ctrl;
extern const uart_cfg_t g_uart9_cfg;
extern const sci_uart_extended_cfg_t g_uart9_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart4;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart4_ctrl;
extern const uart_cfg_t g_uart4_cfg;
extern const sci_uart_extended_cfg_t g_uart4_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart1;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart1_ctrl;
extern const uart_cfg_t g_uart1_cfg;
extern const sci_uart_extended_cfg_t g_uart1_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
void hal_entry(void);
void g_hal_init(void);
FSP_FOOTER
#endif /* HAL_DATA_H_ */

135
ports/renesas-ra/boards/EK_RA4W1/ra_gen/pin_data.c
View File

@ -1,69 +1,74 @@
/* generated pin source file - do not edit */
#include "bsp_api.h"
#include "r_ioport_api.h"
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{
.pin = BSP_IO_PORT_01_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_03,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH),
},
{
.pin = BSP_IO_PORT_01_PIN_06,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH),
},
{
.pin = BSP_IO_PORT_01_PIN_09,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_01_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_01_PIN_11,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH),
},
{
.pin = BSP_IO_PORT_02_PIN_04,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH),
},
{
.pin = BSP_IO_PORT_02_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_02_PIN_06,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_02_PIN_12,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_02_PIN_13,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
{
.pin = BSP_IO_PORT_04_PIN_04,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH),
},
};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] =
{
{ .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) },
{ .pin = BSP_IO_PORT_01_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) },
{ .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_01_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) },
{ .pin = BSP_IO_PORT_02_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) },
{ .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_02_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_02_PIN_12, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_02_PIN_13, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE
| (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) },
{ .pin = BSP_IO_PORT_04_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) },
};
const ioport_cfg_t g_bsp_pin_cfg =
{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], };
#if BSP_TZ_SECURE_BUILD
void R_BSP_PinCfgSecurityInit(void);
/* Initialize SAR registers for secure pins. */
void R_BSP_PinCfgSecurityInit(void) {
#if (2U == BSP_FEATURE_IOPORT_VERSION)
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#else
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#endif
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
{
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
uint32_t port = port_pin >> 8U;
uint32_t pin = port_pin & 0xFFU;
pmsar[port] &= (uint16_t) ~(1U << pin);
}
for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
{
#if (2U == BSP_FEATURE_IOPORT_VERSION)
R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i];
#else
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
#endif
}
}
#endif

80
ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.c
View File

@ -14,26 +14,26 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS
[7] = sci_uart_eri_isr, /* SCI4 ERI (Receive error) */
[8] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */
[9] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */
[10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */
[17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */
[19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */
[20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */
[21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */
[22] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[23] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[24] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[25] = spi_eri_isr, /* SPI0 ERI (Error) */
[26] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */
[27] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */
[28] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */
[29] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */
[10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */
[17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */
[19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */
[20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */
[21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */
[22] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[23] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[24] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[25] = spi_eri_isr, /* SPI0 ERI (Error) */
[26] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */
[27] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */
[28] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */
[29] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
@ -47,25 +47,25 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT
[7] = BSP_PRV_IELS_ENUM(EVENT_SCI4_ERI), /* SCI4 ERI (Receive error) */
[8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */
[9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */
[17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */
[19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */
[20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */
[21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */
[22] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[23] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[24] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[25] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
[26] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */
[27] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */
[28] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */
[29] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */
[17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */
[19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */
[20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */
[21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */
[22] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[23] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[24] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[25] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
[26] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */
[27] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */
[28] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */
[29] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */
};
#endif

80
ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.h
View File

@ -1,6 +1,9 @@
/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (30)
@ -25,77 +28,66 @@ void iic_master_eri_isr(void);
/* Vector table allocations */
#define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)0) /* SCI1 RXI (Received data full) */
#define SCI1_RXI_IRQn ((IRQn_Type)0) /* SCI1 RXI (Received data full) */
#define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)1) /* SCI1 TXI (Transmit data empty) */
#define SCI1_TXI_IRQn ((IRQn_Type)1) /* SCI1 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)2) /* SCI1 TEI (Transmit end) */
#define SCI1_TEI_IRQn ((IRQn_Type)2) /* SCI1 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)3) /* SCI1 ERI (Receive error) */
#define SCI1_ERI_IRQn ((IRQn_Type)3) /* SCI1 ERI (Receive error) */
#define VECTOR_NUMBER_SCI4_RXI ((IRQn_Type)4) /* SCI4 RXI (Received data full) */
#define SCI4_RXI_IRQn ((IRQn_Type)4) /* SCI4 RXI (Received data full) */
#define VECTOR_NUMBER_SCI4_TXI ((IRQn_Type)5) /* SCI4 TXI (Transmit data empty) */
#define SCI4_TXI_IRQn ((IRQn_Type)5) /* SCI4 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI4_TEI ((IRQn_Type)6) /* SCI4 TEI (Transmit end) */
#define SCI4_TEI_IRQn ((IRQn_Type)6) /* SCI4 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type)7) /* SCI4 ERI (Receive error) */
#define SCI4_ERI_IRQn ((IRQn_Type)7) /* SCI4 ERI (Receive error) */
#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */
#define SCI9_RXI_IRQn ((IRQn_Type)8) /* SCI9 RXI (Received data full) */
#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */
#define SCI9_TXI_IRQn ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */
#define SCI9_TEI_IRQn ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */
#define SCI9_ERI_IRQn ((IRQn_Type)11) /* SCI9 ERI (Receive error) */
#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */
#define AGT1_INT_IRQn ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */
#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */
#define ICU_IRQ0_IRQn ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */
#define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */
#define ICU_IRQ1_IRQn ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */
#define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */
#define ICU_IRQ2_IRQn ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */
#define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */
#define ICU_IRQ3_IRQn ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */
#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */
#define ICU_IRQ4_IRQn ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */
#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)22) /* SPI0 RXI (Receive buffer full) */
#define SPI0_RXI_IRQn ((IRQn_Type)22) /* SPI0 RXI (Receive buffer full) */
#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)23) /* SPI0 TXI (Transmit buffer empty) */
#define SPI0_TXI_IRQn ((IRQn_Type)23) /* SPI0 TXI (Transmit buffer empty) */
#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)24) /* SPI0 TEI (Transmission complete event) */
#define SPI0_TEI_IRQn ((IRQn_Type)24) /* SPI0 TEI (Transmission complete event) */
#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)25) /* SPI0 ERI (Error) */
#define SPI0_ERI_IRQn ((IRQn_Type)25) /* SPI0 ERI (Error) */
#define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type)26) /* IIC0 RXI (Receive data full) */
#define IIC0_RXI_IRQn ((IRQn_Type)26) /* IIC0 RXI (Receive data full) */
#define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type)27) /* IIC0 TXI (Transmit data empty) */
#define IIC0_TXI_IRQn ((IRQn_Type)27) /* IIC0 TXI (Transmit data empty) */
#define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type)28) /* IIC0 TEI (Transmit end) */
#define IIC0_TEI_IRQn ((IRQn_Type)28) /* IIC0 TEI (Transmit end) */
#define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type)29) /* IIC0 ERI (Transfer error) */
typedef enum IRQn
{
Reset_IRQn = -15,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SecureFault_IRQn = -9,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
SCI1_RXI_IRQn = 0, /* SCI1 RXI (Received data full) */
SCI1_TXI_IRQn = 1, /* SCI1 TXI (Transmit data empty) */
SCI1_TEI_IRQn = 2, /* SCI1 TEI (Transmit end) */
SCI1_ERI_IRQn = 3, /* SCI1 ERI (Receive error) */
SCI4_RXI_IRQn = 4, /* SCI4 RXI (Received data full) */
SCI4_TXI_IRQn = 5, /* SCI4 TXI (Transmit data empty) */
SCI4_TEI_IRQn = 6, /* SCI4 TEI (Transmit end) */
SCI4_ERI_IRQn = 7, /* SCI4 ERI (Receive error) */
SCI9_RXI_IRQn = 8, /* SCI9 RXI (Received data full) */
SCI9_TXI_IRQn = 9, /* SCI9 TXI (Transmit data empty) */
SCI9_TEI_IRQn = 10, /* SCI9 TEI (Transmit end) */
SCI9_ERI_IRQn = 11, /* SCI9 ERI (Receive error) */
RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */
RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */
RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */
AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */
AGT1_INT_IRQn = 16, /* AGT1 INT (AGT interrupt) */
ICU_IRQ0_IRQn = 17, /* ICU IRQ0 (External pin interrupt 0) */
ICU_IRQ1_IRQn = 18, /* ICU IRQ1 (External pin interrupt 1) */
ICU_IRQ2_IRQn = 19, /* ICU IRQ2 (External pin interrupt 2) */
ICU_IRQ3_IRQn = 20, /* ICU IRQ3 (External pin interrupt 3) */
ICU_IRQ4_IRQn = 21, /* ICU IRQ4 (External pin interrupt 4) */
SPI0_RXI_IRQn = 22, /* SPI0 RXI (Receive buffer full) */
SPI0_TXI_IRQn = 23, /* SPI0 TXI (Transmit buffer empty) */
SPI0_TEI_IRQn = 24, /* SPI0 TEI (Transmission complete event) */
SPI0_ERI_IRQn = 25, /* SPI0 ERI (Error) */
IIC0_RXI_IRQn = 26, /* IIC0 RXI (Receive data full) */
IIC0_TXI_IRQn = 27, /* IIC0 TXI (Transmit data empty) */
IIC0_TEI_IRQn = 28, /* IIC0 TEI (Transmit end) */
IIC0_ERI_IRQn = 29, /* IIC0 ERI (Transfer error) */
} IRQn_Type;
#define IIC0_ERI_IRQn ((IRQn_Type)29) /* IIC0 ERI (Transfer error) */
#ifdef __cplusplus
}
#endif
#endif /* VECTOR_DATA_H */

21
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
@ -14,7 +18,13 @@
#define BSP_CFG_RTOS (0)
#endif
#endif
#ifndef BSP_CFG_RTC_USED
#define BSP_CFG_RTC_USED (1)
#endif
#undef RA_NOT_DEFINED
#if defined(_RA_BOOT_IMAGE)
#define BSP_CFG_BOOT_IMAGE (1)
#endif
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x4000)
#define BSP_CFG_HEAP_BYTES (0x2d000)
@ -25,15 +35,14 @@
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_EARLY_INIT ((0))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
@ -46,4 +55,8 @@
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_CFG_H_ */

1
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
View File

@ -2,6 +2,7 @@
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA6M1AD3CFP
#define BSP_MCU_FEATURE_SET ('A')
#define BSP_ROM_SIZE_BYTES (524288)
#define BSP_RAM_SIZE_BYTES (262144)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)

13
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
@ -23,7 +27,6 @@
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
#define BSP_MCU_VBATT_SUPPORT (1)
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
@ -50,7 +53,9 @@
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
@ -71,4 +76,8 @@
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_adc_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_ADC_CFG_H_
#define R_ADC_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_ADC_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_agt_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_AGT_CFG_H_
#define R_AGT_CFG_H_
#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
#endif /* R_AGT_CFG_H_ */

6
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_dtc_cfg.h
View File

@ -1,6 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_DTC_CFG_H_
#define R_DTC_CFG_H_
#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
#endif /* R_DTC_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_flash_hp_cfg.h
View File

@ -1,7 +1,15 @@
/* generated configuration header file - do not edit */
#ifndef R_FLASH_HP_CFG_H_
#define R_FLASH_HP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1)
#define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0)
#ifdef __cplusplus
}
#endif
#endif /* R_FLASH_HP_CFG_H_ */

5
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_icu_cfg.h
View File

@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_iic_master_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_IIC_MASTER_CFG_H_
#define R_IIC_MASTER_CFG_H_
#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define IIC_MASTER_CFG_DTC_ENABLE (0)
#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0)
#endif /* R_IIC_MASTER_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_ioport_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_IOPORT_CFG_H_ */

9
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_lpm_cfg.h
View File

@ -1,5 +1,14 @@
/* generated configuration header file - do not edit */
#ifndef R_LPM_CFG_H_
#define R_LPM_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define LPM_CFG_STANDBY_LIMIT (0)
#ifdef __cplusplus
}
#endif
#endif /* R_LPM_CFG_H_ */

5
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_rtc_cfg.h
View File

@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_RTC_CFG_H_
#define R_RTC_CFG_H_
#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_RTC_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
View File

@ -1,8 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#endif /* R_SCI_UART_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_spi_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_SPI_CFG_H_
#define R_SPI_CFG_H_
#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SPI_DTC_SUPPORT_ENABLE (1)
#define SPI_TRANSMIT_FROM_RXI_ISR (0)
#endif /* R_SPI_CFG_H_ */

4
ports/renesas-ra/boards/EK_RA6M1/ra_gen/bsp_clock_cfg.h
View File

@ -7,7 +7,7 @@
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U, 0U) /* PLL Mul x20.0 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
@ -15,7 +15,7 @@
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */

3
ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.c
View File

@ -1,7 +1,4 @@
/* generated common source file - do not edit */
#include "common_data.h"
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport =
{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
void g_common_init(void) {
}

4
ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.h
View File

@ -3,14 +3,16 @@
#define COMMON_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_ioport.h"
#include "bsp_pin_cfg.h"
FSP_HEADER
/* IOPORT Instance */
extern const ioport_instance_t g_ioport;
/* IOPORT control structure. */
extern ioport_instance_ctrl_t g_ioport_ctrl;
void g_common_init(void);
FSP_FOOTER
#endif /* COMMON_DATA_H_ */

810
ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.c
View File

@ -1,131 +1,15 @@
/* generated HAL source file - do not edit */
#include "hal_data.h"
/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
adc_instance_ctrl_t g_adc1_ctrl;
const adc_extended_cfg_t g_adc1_cfg_extend =
{ .add_average_count = ADC_ADD_OFF,
.clearing = ADC_CLEAR_AFTER_READ_ON,
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
const adc_cfg_t g_adc1_cfg =
{ .unit = 1, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment =
(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc1_cfg_extend,
#if defined(VECTOR_NUMBER_ADC1_SCAN_END)
.scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END,
#else
.scan_end_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_ADC1_SCAN_END_B)
.scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B,
#else
.scan_end_b_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
const adc_channel_cfg_t g_adc1_channel_cfg =
{ .scan_mask = 0,
.scan_mask_group_b = 0,
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
.add_mask = 0,
.sample_hold_mask = 0,
.sample_hold_states = 24, };
/* Instance structure to use this module. */
const adc_instance_t g_adc1 =
{ .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg, .p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc };
iic_master_instance_ctrl_t g_i2c_master0_ctrl;
const iic_master_extended_cfg_t g_i2c_master0_extend =
{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT,
/* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15,
.clock_settings.brh_value = 16, .clock_settings.cks_value = 4, };
const i2c_master_cfg_t g_i2c_master0_cfg =
{ .channel = 0, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.p_callback = callback_iic,
.p_context = NULL,
#if defined(VECTOR_NUMBER_IIC0_RXI)
.rxi_irq = VECTOR_NUMBER_IIC0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC0_TXI)
.txi_irq = VECTOR_NUMBER_IIC0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC0_TEI)
.tei_irq = VECTOR_NUMBER_IIC0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC0_ERI)
.eri_irq = VECTOR_NUMBER_IIC0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.ipl = (12),
.p_extend = &g_i2c_master0_extend, };
/* Instance structure to use this module. */
const i2c_master_instance_t g_i2c_master0 =
{ .p_ctrl = &g_i2c_master0_ctrl, .p_cfg = &g_i2c_master0_cfg, .p_api = &g_i2c_master_on_iic };
adc_instance_ctrl_t g_adc0_ctrl;
const adc_extended_cfg_t g_adc0_cfg_extend =
{ .add_average_count = ADC_ADD_OFF,
.clearing = ADC_CLEAR_AFTER_READ_ON,
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
const adc_cfg_t g_adc0_cfg =
{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment =
(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend,
#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
#else
.scan_end_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
#else
.scan_end_b_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
const adc_channel_cfg_t g_adc0_channel_cfg =
{ .scan_mask = 0,
.scan_mask_group_b = 0,
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
.add_mask = 0,
.sample_hold_mask = 0,
.sample_hold_states = 24, };
/* Instance structure to use this module. */
const adc_instance_t g_adc0 =
{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
lpm_instance_ctrl_t g_lpm0_ctrl;
const lpm_cfg_t g_lpm0_cfg =
{ .low_power_mode = LPM_MODE_SLEEP,
{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM
| (lpm_standby_wake_source_t)0,
#if BSP_FEATURE_LPM_HAS_SNOOZE
.snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0,
.snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
.snooze_end_sources = (lpm_snooze_end_t)0,
.dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
#endif
#if BSP_FEATURE_LPM_HAS_SBYCR_OPE
.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
#endif
@ -135,449 +19,23 @@ const lpm_cfg_t g_lpm0_cfg =
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
#endif
#if BSP_FEATURE_LPM_HAS_PDRAMSCR
.ram_retention_cfg.ram_retention = (uint8_t)(0),
.ram_retention_cfg.tcm_retention = false,
#endif
#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP
.ram_retention_cfg.standby_ram_retention = false,
#endif
#if BSP_FEATURE_LPM_HAS_LDO_CONTROL
.ldo_standby_cfg.pll1_ldo = false,
.ldo_standby_cfg.pll2_ldo = false,
.ldo_standby_cfg.hoco_ldo = false,
#endif
.p_extend = NULL, };
const lpm_instance_t g_lpm0 =
{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg };
dtc_instance_ctrl_t g_transfer1_ctrl;
transfer_info_t g_transfer1_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer1_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_RXI, };
const transfer_cfg_t g_transfer1_cfg =
{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer1 =
{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc };
dtc_instance_ctrl_t g_transfer0_ctrl;
transfer_info_t g_transfer0_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer0_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_TXI, };
const transfer_cfg_t g_transfer0_cfg =
{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer0 =
{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc };
spi_instance_ctrl_t g_spi0_ctrl;
/** SPI extended configuration for SPI HAL driver */
const spi_extended_cfg_t g_spi0_ext_cfg =
{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
.ssl_polarity = SPI_SSLP_LOW,
.ssl_select = SPI_SSL_SELECT_SSL0,
.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
.parity = SPI_PARITY_MODE_DISABLE,
.byte_swap = SPI_BYTE_SWAP_DISABLE,
.spck_div =
{
/* Actual calculated bitrate: 15000000. */ .spbr = 3,
.brdv = 0
},
.spck_delay = SPI_DELAY_COUNT_1,
.ssl_negation_delay = SPI_DELAY_COUNT_1,
.next_access_delay = SPI_DELAY_COUNT_1 };
/** SPI configuration for SPI HAL driver */
const spi_cfg_t g_spi0_cfg =
{ .channel = 0,
#if defined(VECTOR_NUMBER_SPI0_RXI)
.rxi_irq = VECTOR_NUMBER_SPI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TXI)
.txi_irq = VECTOR_NUMBER_SPI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TEI)
.tei_irq = VECTOR_NUMBER_SPI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_ERI)
.eri_irq = VECTOR_NUMBER_SPI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.rxi_ipl = (12),
.txi_ipl = (12),
.tei_ipl = (12),
.eri_ipl = (12),
.operating_mode = SPI_MODE_MASTER,
.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
.clk_polarity = SPI_CLK_POLARITY_LOW,
.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
.bit_order = SPI_BIT_ORDER_MSB_FIRST,
.p_transfer_tx = g_spi0_P_TRANSFER_TX,
.p_transfer_rx = g_spi0_P_TRANSFER_RX,
.p_callback = spi_callback,
.p_context = NULL,
.p_extend = (void *)&g_spi0_ext_cfg, };
/* Instance structure to use this module. */
const spi_instance_t g_spi0 =
{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi };
icu_instance_ctrl_t g_external_irq13_ctrl;
const external_irq_cfg_t g_external_irq13_cfg =
{ .channel = 13,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ13)
.irq = VECTOR_NUMBER_ICU_IRQ13,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq13 =
{ .p_ctrl = &g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq12_ctrl;
const external_irq_cfg_t g_external_irq12_cfg =
{ .channel = 12,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ12)
.irq = VECTOR_NUMBER_ICU_IRQ12,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq12 =
{ .p_ctrl = &g_external_irq12_ctrl, .p_cfg = &g_external_irq12_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq11_ctrl;
const external_irq_cfg_t g_external_irq11_cfg =
{ .channel = 11,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ11)
.irq = VECTOR_NUMBER_ICU_IRQ11,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq11 =
{ .p_ctrl = &g_external_irq11_ctrl, .p_cfg = &g_external_irq11_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq10_ctrl;
const external_irq_cfg_t g_external_irq10_cfg =
{ .channel = 10,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ10)
.irq = VECTOR_NUMBER_ICU_IRQ10,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq10 =
{ .p_ctrl = &g_external_irq10_ctrl, .p_cfg = &g_external_irq10_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq9_ctrl;
const external_irq_cfg_t g_external_irq9_cfg =
{ .channel = 9,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ9)
.irq = VECTOR_NUMBER_ICU_IRQ9,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq9 =
{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq8_ctrl;
const external_irq_cfg_t g_external_irq8_cfg =
{ .channel = 8,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ8)
.irq = VECTOR_NUMBER_ICU_IRQ8,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq8 =
{ .p_ctrl = &g_external_irq8_ctrl, .p_cfg = &g_external_irq8_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq7_ctrl;
const external_irq_cfg_t g_external_irq7_cfg =
{ .channel = 7,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ7)
.irq = VECTOR_NUMBER_ICU_IRQ7,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq7 =
{ .p_ctrl = &g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq6_ctrl;
const external_irq_cfg_t g_external_irq6_cfg =
{ .channel = 6,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ6)
.irq = VECTOR_NUMBER_ICU_IRQ6,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq6 =
{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq5_ctrl;
const external_irq_cfg_t g_external_irq5_cfg =
{ .channel = 5,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ5)
.irq = VECTOR_NUMBER_ICU_IRQ5,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq5 =
{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq4_ctrl;
const external_irq_cfg_t g_external_irq4_cfg =
{ .channel = 4,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ4)
.irq = VECTOR_NUMBER_ICU_IRQ4,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq4 =
{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq3_ctrl;
const external_irq_cfg_t g_external_irq3_cfg =
{ .channel = 3,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ3)
.irq = VECTOR_NUMBER_ICU_IRQ3,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq3 =
{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq2_ctrl;
const external_irq_cfg_t g_external_irq2_cfg =
{ .channel = 2,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ2)
.irq = VECTOR_NUMBER_ICU_IRQ2,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq2 =
{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq1_ctrl;
const external_irq_cfg_t g_external_irq1_cfg =
{ .channel = 1,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ1)
.irq = VECTOR_NUMBER_ICU_IRQ1,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq1 =
{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq0_ctrl;
const external_irq_cfg_t g_external_irq0_cfg =
{ .channel = 0,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ0)
.irq = VECTOR_NUMBER_ICU_IRQ0,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq0 =
{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu };
agt_instance_ctrl_t g_timer1_ctrl;
const agt_extended_cfg_t g_timer1_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer1_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 1, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer1_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT1_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT1_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer1 =
{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt };
agt_instance_ctrl_t g_timer0_ctrl;
const agt_extended_cfg_t g_timer0_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer0_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer0_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT0_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer0 =
{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
flash_hp_instance_ctrl_t g_flash0_ctrl;
const flash_cfg_t g_flash0_cfg =
{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL,
@ -596,239 +54,3 @@ const flash_cfg_t g_flash0_cfg =
/* Instance structure to use this module. */
const flash_instance_t g_flash0 =
{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp };
rtc_instance_ctrl_t g_rtc0_ctrl;
const rtc_error_adjustment_cfg_t g_rtc0_err_cfg =
{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC,
.adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND,
.adjustment_type = RTC_ERROR_ADJUSTMENT_NONE,
.adjustment_value = 0, };
const rtc_cfg_t g_rtc0_cfg =
{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback =
NULL,
.p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14),
#if defined(VECTOR_NUMBER_RTC_ALARM)
.alarm_irq = VECTOR_NUMBER_RTC_ALARM,
#else
.alarm_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_PERIOD)
.periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
#else
.periodic_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_CARRY)
.carry_irq = VECTOR_NUMBER_RTC_CARRY,
#else
.carry_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const rtc_instance_t g_rtc0 =
{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc };
sci_uart_instance_ctrl_t g_uart8_ctrl;
baud_setting_t g_uart8_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart8_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart8_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart8_cfg =
{ .channel = 8, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart8_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI8_RXI)
.rxi_irq = VECTOR_NUMBER_SCI8_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI8_TXI)
.txi_irq = VECTOR_NUMBER_SCI8_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI8_TEI)
.tei_irq = VECTOR_NUMBER_SCI8_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI8_ERI)
.eri_irq = VECTOR_NUMBER_SCI8_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart8 =
{ .p_ctrl = &g_uart8_ctrl, .p_cfg = &g_uart8_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart2_ctrl;
baud_setting_t g_uart2_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart2_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart2_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart2_cfg =
{ .channel = 2, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart2_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI2_RXI)
.rxi_irq = VECTOR_NUMBER_SCI2_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_TXI)
.txi_irq = VECTOR_NUMBER_SCI2_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_TEI)
.tei_irq = VECTOR_NUMBER_SCI2_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_ERI)
.eri_irq = VECTOR_NUMBER_SCI2_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart2 =
{ .p_ctrl = &g_uart2_ctrl, .p_cfg = &g_uart2_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart0_ctrl;
baud_setting_t g_uart0_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart0_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart0_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart0_cfg =
{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart0_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI0_RXI)
.rxi_irq = VECTOR_NUMBER_SCI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TXI)
.txi_irq = VECTOR_NUMBER_SCI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TEI)
.tei_irq = VECTOR_NUMBER_SCI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_ERI)
.eri_irq = VECTOR_NUMBER_SCI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart0 =
{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci };
void g_hal_init(void) {
g_common_init();
}

286
ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.h
View File

@ -2,262 +2,20 @@
#ifndef HAL_DATA_H_
#define HAL_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "common_data.h"
#include "r_adc.h"
#include "r_adc_api.h"
#include "r_iic_master.h"
#include "r_i2c_master_api.h"
#include "r_lpm.h"
#include "r_lpm_api.h"
#include "r_dtc.h"
#include "r_transfer_api.h"
#include "r_spi.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_agt.h"
#include "r_timer_api.h"
#include "r_flash_hp.h"
#include "r_flash_api.h"
#include "r_rtc.h"
#include "r_rtc_api.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
FSP_HEADER
/** ADC on ADC Instance. */
extern const adc_instance_t g_adc1;
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
extern adc_instance_ctrl_t g_adc1_ctrl;
extern const adc_cfg_t g_adc1_cfg;
extern const adc_channel_cfg_t g_adc1_channel_cfg;
#ifndef NULL
void NULL(adc_callback_args_t *p_args);
#endif
/* I2C Master on IIC Instance. */
extern const i2c_master_instance_t g_i2c_master0;
/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */
extern iic_master_instance_ctrl_t g_i2c_master0_ctrl;
extern const i2c_master_cfg_t g_i2c_master0_cfg;
#ifndef callback_iic
void callback_iic(i2c_master_callback_args_t *p_args);
#endif
/** ADC on ADC Instance. */
extern const adc_instance_t g_adc0;
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
extern adc_instance_ctrl_t g_adc0_ctrl;
extern const adc_cfg_t g_adc0_cfg;
extern const adc_channel_cfg_t g_adc0_channel_cfg;
#ifndef NULL
void NULL(adc_callback_args_t *p_args);
#endif
/** lpm Instance */
extern const lpm_instance_t g_lpm0;
/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */
extern lpm_instance_ctrl_t g_lpm0_ctrl;
extern const lpm_cfg_t g_lpm0_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer1;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer1_ctrl;
extern const transfer_cfg_t g_transfer1_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer0;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer0_ctrl;
extern const transfer_cfg_t g_transfer0_cfg;
/** SPI on SPI Instance. */
extern const spi_instance_t g_spi0;
/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
extern spi_instance_ctrl_t g_spi0_ctrl;
extern const spi_cfg_t g_spi0_cfg;
/** Callback used by SPI Instance. */
#ifndef spi_callback
void spi_callback(spi_callback_args_t *p_args);
#endif
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == g_transfer0)
#define g_spi0_P_TRANSFER_TX (NULL)
#else
#define g_spi0_P_TRANSFER_TX (&g_transfer0)
#endif
#if (RA_NOT_DEFINED == g_transfer1)
#define g_spi0_P_TRANSFER_RX (NULL)
#else
#define g_spi0_P_TRANSFER_RX (&g_transfer1)
#endif
#undef RA_NOT_DEFINED
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq13;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq13_ctrl;
extern const external_irq_cfg_t g_external_irq13_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq12;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq12_ctrl;
extern const external_irq_cfg_t g_external_irq12_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq11;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq11_ctrl;
extern const external_irq_cfg_t g_external_irq11_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq10;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq10_ctrl;
extern const external_irq_cfg_t g_external_irq10_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq9;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq9_ctrl;
extern const external_irq_cfg_t g_external_irq9_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq8;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq8_ctrl;
extern const external_irq_cfg_t g_external_irq8_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq7;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq7_ctrl;
extern const external_irq_cfg_t g_external_irq7_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq6;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq6_ctrl;
extern const external_irq_cfg_t g_external_irq6_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq5;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq5_ctrl;
extern const external_irq_cfg_t g_external_irq5_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq4;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq4_ctrl;
extern const external_irq_cfg_t g_external_irq4_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq3;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq3_ctrl;
extern const external_irq_cfg_t g_external_irq3_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq2;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq2_ctrl;
extern const external_irq_cfg_t g_external_irq2_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq1;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq1_ctrl;
extern const external_irq_cfg_t g_external_irq1_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq0;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq0_ctrl;
extern const external_irq_cfg_t g_external_irq0_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer1;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer1_ctrl;
extern const timer_cfg_t g_timer1_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer0;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer0_ctrl;
extern const timer_cfg_t g_timer0_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/* Flash on Flash HP Instance */
extern const flash_instance_t g_flash0;
@ -268,50 +26,8 @@ extern const flash_cfg_t g_flash0_cfg;
#ifndef NULL
void NULL(flash_callback_args_t *p_args);
#endif
/* RTC Instance. */
extern const rtc_instance_t g_rtc0;
/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */
extern rtc_instance_ctrl_t g_rtc0_ctrl;
extern const rtc_cfg_t g_rtc0_cfg;
#ifndef NULL
void NULL(rtc_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart8;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart8_ctrl;
extern const uart_cfg_t g_uart8_cfg;
extern const sci_uart_extended_cfg_t g_uart8_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart2;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart2_ctrl;
extern const uart_cfg_t g_uart2_cfg;
extern const sci_uart_extended_cfg_t g_uart2_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart0;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart0_ctrl;
extern const uart_cfg_t g_uart0_cfg;
extern const sci_uart_extended_cfg_t g_uart0_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
void hal_entry(void);
void g_hal_init(void);
FSP_FOOTER
#endif /* HAL_DATA_H_ */

193
ports/renesas-ra/boards/EK_RA6M1/ra_gen/pin_data.c
View File

@ -1,109 +1,92 @@
/* generated pin source file - do not edit */
#include "bsp_api.h"
#include "r_ioport_api.h"
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{
.pin = BSP_IO_PORT_00_PIN_04,
.pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE),
},
{
.pin = BSP_IO_PORT_01_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_03,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_04,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_01_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_01_PIN_06,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_01_PIN_07,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_01_PIN_08,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_09,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_12,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_02_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
{
.pin = BSP_IO_PORT_02_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU),
},
{
.pin = BSP_IO_PORT_02_PIN_07,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU),
},
{
.pin = BSP_IO_PORT_03_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_03_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_03_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC),
},
{
.pin = BSP_IO_PORT_04_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC),
},
{
.pin = BSP_IO_PORT_04_PIN_07,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS),
},
{
.pin = BSP_IO_PORT_04_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_11,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_15,
.pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] =
{
{ .pin = BSP_IO_PORT_00_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
{ .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_01_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_01_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) },
{ .pin = BSP_IO_PORT_01_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) },
{ .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_01_PIN_12, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) },
{ .pin = BSP_IO_PORT_02_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) },
{ .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_CTSU) },
{ .pin = BSP_IO_PORT_02_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_CTSU) },
{ .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_03_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_03_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_04_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID
| (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) },
{ .pin = BSP_IO_PORT_04_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID
| (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) },
{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_USB_FS) },
{ .pin = BSP_IO_PORT_04_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_04_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_04_PIN_15, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE
| (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) },
};
const ioport_cfg_t g_bsp_pin_cfg =
{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], };
#if BSP_TZ_SECURE_BUILD
void R_BSP_PinCfgSecurityInit(void);
/* Initialize SAR registers for secure pins. */
void R_BSP_PinCfgSecurityInit(void) {
#if (2U == BSP_FEATURE_IOPORT_VERSION)
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#else
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#endif
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
{
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
uint32_t port = port_pin >> 8U;
uint32_t pin = port_pin & 0xFFU;
pmsar[port] &= (uint16_t) ~(1U << pin);
}
for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
{
#if (2U == BSP_FEATURE_IOPORT_VERSION)
R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i];
#else
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
#endif
}
}
#endif

118
ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.c
View File

@ -4,7 +4,7 @@
#if VECTOR_DATA_IRQ_COUNT > 0
BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
{
[0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */
[0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */
[1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */
[2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */
[3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */
@ -14,35 +14,35 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS
[7] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */
[8] = sci_uart_rxi_isr, /* SCI8 RXI (Received data full) */
[9] = sci_uart_txi_isr, /* SCI8 TXI (Transmit data empty) */
[10] = sci_uart_tei_isr, /* SCI8 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI8 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */
[17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */
[19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */
[20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */
[21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */
[22] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */
[23] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */
[24] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */
[25] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */
[26] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */
[27] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */
[28] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */
[29] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */
[30] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */
[31] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[32] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[33] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[34] = spi_eri_isr, /* SPI0 ERI (Error) */
[35] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */
[36] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */
[37] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */
[38] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */
[10] = sci_uart_tei_isr, /* SCI8 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI8 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */
[17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */
[19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */
[20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */
[21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */
[22] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */
[23] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */
[24] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */
[25] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */
[26] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */
[27] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */
[28] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */
[29] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */
[30] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */
[31] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[32] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[33] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[34] = spi_eri_isr, /* SPI0 ERI (Error) */
[35] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */
[36] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */
[37] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */
[38] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
@ -56,34 +56,34 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT
[7] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */
[8] = BSP_PRV_IELS_ENUM(EVENT_SCI8_RXI), /* SCI8 RXI (Received data full) */
[9] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TXI), /* SCI8 TXI (Transmit data empty) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TEI), /* SCI8 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI8_ERI), /* SCI8 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */
[17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */
[19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */
[20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */
[21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */
[22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */
[23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */
[24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */
[25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */
[26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */
[27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */
[28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */
[29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */
[30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */
[31] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
[35] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */
[36] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */
[37] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */
[38] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TEI), /* SCI8 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI8_ERI), /* SCI8 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */
[17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */
[19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */
[20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */
[21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */
[22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */
[23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */
[24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */
[25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */
[26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */
[27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */
[28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */
[29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */
[30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */
[31] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
[35] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */
[36] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */
[37] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */
[38] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */
};
#endif

98
ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.h
View File

@ -1,6 +1,9 @@
/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (39)
@ -25,95 +28,84 @@ void iic_master_eri_isr(void);
/* Vector table allocations */
#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
#define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
#define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
#define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
#define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
#define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)4) /* SCI2 RXI (Received data full) */
#define SCI2_RXI_IRQn ((IRQn_Type)4) /* SCI2 RXI (Received data full) */
#define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)5) /* SCI2 TXI (Transmit data empty) */
#define SCI2_TXI_IRQn ((IRQn_Type)5) /* SCI2 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)6) /* SCI2 TEI (Transmit end) */
#define SCI2_TEI_IRQn ((IRQn_Type)6) /* SCI2 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)7) /* SCI2 ERI (Receive error) */
#define SCI2_ERI_IRQn ((IRQn_Type)7) /* SCI2 ERI (Receive error) */
#define VECTOR_NUMBER_SCI8_RXI ((IRQn_Type)8) /* SCI8 RXI (Received data full) */
#define SCI8_RXI_IRQn ((IRQn_Type)8) /* SCI8 RXI (Received data full) */
#define VECTOR_NUMBER_SCI8_TXI ((IRQn_Type)9) /* SCI8 TXI (Transmit data empty) */
#define SCI8_TXI_IRQn ((IRQn_Type)9) /* SCI8 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI8_TEI ((IRQn_Type)10) /* SCI8 TEI (Transmit end) */
#define SCI8_TEI_IRQn ((IRQn_Type)10) /* SCI8 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI8_ERI ((IRQn_Type)11) /* SCI8 ERI (Receive error) */
#define SCI8_ERI_IRQn ((IRQn_Type)11) /* SCI8 ERI (Receive error) */
#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */
#define AGT1_INT_IRQn ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */
#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */
#define ICU_IRQ0_IRQn ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */
#define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */
#define ICU_IRQ1_IRQn ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */
#define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */
#define ICU_IRQ2_IRQn ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */
#define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */
#define ICU_IRQ3_IRQn ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */
#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */
#define ICU_IRQ4_IRQn ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */
#define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)22) /* ICU IRQ5 (External pin interrupt 5) */
#define ICU_IRQ5_IRQn ((IRQn_Type)22) /* ICU IRQ5 (External pin interrupt 5) */
#define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)23) /* ICU IRQ6 (External pin interrupt 6) */
#define ICU_IRQ6_IRQn ((IRQn_Type)23) /* ICU IRQ6 (External pin interrupt 6) */
#define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)24) /* ICU IRQ7 (External pin interrupt 7) */
#define ICU_IRQ7_IRQn ((IRQn_Type)24) /* ICU IRQ7 (External pin interrupt 7) */
#define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type)25) /* ICU IRQ8 (External pin interrupt 8) */
#define ICU_IRQ8_IRQn ((IRQn_Type)25) /* ICU IRQ8 (External pin interrupt 8) */
#define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)26) /* ICU IRQ9 (External pin interrupt 9) */
#define ICU_IRQ9_IRQn ((IRQn_Type)26) /* ICU IRQ9 (External pin interrupt 9) */
#define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type)27) /* ICU IRQ10 (External pin interrupt 10) */
#define ICU_IRQ10_IRQn ((IRQn_Type)27) /* ICU IRQ10 (External pin interrupt 10) */
#define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type)28) /* ICU IRQ11 (External pin interrupt 11) */
#define ICU_IRQ11_IRQn ((IRQn_Type)28) /* ICU IRQ11 (External pin interrupt 11) */
#define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type)29) /* ICU IRQ12 (External pin interrupt 12) */
#define ICU_IRQ12_IRQn ((IRQn_Type)29) /* ICU IRQ12 (External pin interrupt 12) */
#define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)30) /* ICU IRQ13 (External pin interrupt 13) */
#define ICU_IRQ13_IRQn ((IRQn_Type)30) /* ICU IRQ13 (External pin interrupt 13) */
#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)31) /* SPI0 RXI (Receive buffer full) */
#define SPI0_RXI_IRQn ((IRQn_Type)31) /* SPI0 RXI (Receive buffer full) */
#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)32) /* SPI0 TXI (Transmit buffer empty) */
#define SPI0_TXI_IRQn ((IRQn_Type)32) /* SPI0 TXI (Transmit buffer empty) */
#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)33) /* SPI0 TEI (Transmission complete event) */
#define SPI0_TEI_IRQn ((IRQn_Type)33) /* SPI0 TEI (Transmission complete event) */
#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)34) /* SPI0 ERI (Error) */
#define SPI0_ERI_IRQn ((IRQn_Type)34) /* SPI0 ERI (Error) */
#define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type)35) /* IIC0 RXI (Receive data full) */
#define IIC0_RXI_IRQn ((IRQn_Type)35) /* IIC0 RXI (Receive data full) */
#define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type)36) /* IIC0 TXI (Transmit data empty) */
#define IIC0_TXI_IRQn ((IRQn_Type)36) /* IIC0 TXI (Transmit data empty) */
#define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type)37) /* IIC0 TEI (Transmit end) */
#define IIC0_TEI_IRQn ((IRQn_Type)37) /* IIC0 TEI (Transmit end) */
#define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type)38) /* IIC0 ERI (Transfer error) */
typedef enum IRQn
{
Reset_IRQn = -15,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SecureFault_IRQn = -9,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */
SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */
SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */
SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */
SCI2_RXI_IRQn = 4, /* SCI2 RXI (Received data full) */
SCI2_TXI_IRQn = 5, /* SCI2 TXI (Transmit data empty) */
SCI2_TEI_IRQn = 6, /* SCI2 TEI (Transmit end) */
SCI2_ERI_IRQn = 7, /* SCI2 ERI (Receive error) */
SCI8_RXI_IRQn = 8, /* SCI8 RXI (Received data full) */
SCI8_TXI_IRQn = 9, /* SCI8 TXI (Transmit data empty) */
SCI8_TEI_IRQn = 10, /* SCI8 TEI (Transmit end) */
SCI8_ERI_IRQn = 11, /* SCI8 ERI (Receive error) */
RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */
RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */
RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */
AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */
AGT1_INT_IRQn = 16, /* AGT1 INT (AGT interrupt) */
ICU_IRQ0_IRQn = 17, /* ICU IRQ0 (External pin interrupt 0) */
ICU_IRQ1_IRQn = 18, /* ICU IRQ1 (External pin interrupt 1) */
ICU_IRQ2_IRQn = 19, /* ICU IRQ2 (External pin interrupt 2) */
ICU_IRQ3_IRQn = 20, /* ICU IRQ3 (External pin interrupt 3) */
ICU_IRQ4_IRQn = 21, /* ICU IRQ4 (External pin interrupt 4) */
ICU_IRQ5_IRQn = 22, /* ICU IRQ5 (External pin interrupt 5) */
ICU_IRQ6_IRQn = 23, /* ICU IRQ6 (External pin interrupt 6) */
ICU_IRQ7_IRQn = 24, /* ICU IRQ7 (External pin interrupt 7) */
ICU_IRQ8_IRQn = 25, /* ICU IRQ8 (External pin interrupt 8) */
ICU_IRQ9_IRQn = 26, /* ICU IRQ9 (External pin interrupt 9) */
ICU_IRQ10_IRQn = 27, /* ICU IRQ10 (External pin interrupt 10) */
ICU_IRQ11_IRQn = 28, /* ICU IRQ11 (External pin interrupt 11) */
ICU_IRQ12_IRQn = 29, /* ICU IRQ12 (External pin interrupt 12) */
ICU_IRQ13_IRQn = 30, /* ICU IRQ13 (External pin interrupt 13) */
SPI0_RXI_IRQn = 31, /* SPI0 RXI (Receive buffer full) */
SPI0_TXI_IRQn = 32, /* SPI0 TXI (Transmit buffer empty) */
SPI0_TEI_IRQn = 33, /* SPI0 TEI (Transmission complete event) */
SPI0_ERI_IRQn = 34, /* SPI0 ERI (Error) */
IIC0_RXI_IRQn = 35, /* IIC0 RXI (Receive data full) */
IIC0_TXI_IRQn = 36, /* IIC0 TXI (Transmit data empty) */
IIC0_TEI_IRQn = 37, /* IIC0 TEI (Transmit end) */
IIC0_ERI_IRQn = 38, /* IIC0 ERI (Transfer error) */
} IRQn_Type;
#define IIC0_ERI_IRQn ((IRQn_Type)38) /* IIC0 ERI (Transfer error) */
#ifdef __cplusplus
}
#endif
#endif /* VECTOR_DATA_H */

21
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
@ -14,7 +18,13 @@
#define BSP_CFG_RTOS (0)
#endif
#endif
#ifndef BSP_CFG_RTC_USED
#define BSP_CFG_RTC_USED (1)
#endif
#undef RA_NOT_DEFINED
#if defined(_RA_BOOT_IMAGE)
#define BSP_CFG_BOOT_IMAGE (1)
#endif
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x4000)
#define BSP_CFG_HEAP_BYTES (0x4d000)
@ -25,15 +35,14 @@
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_EARLY_INIT ((0))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
@ -46,4 +55,8 @@
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_CFG_H_ */

1
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
View File

@ -2,6 +2,7 @@
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA6M2AF3CFB
#define BSP_MCU_FEATURE_SET ('A')
#define BSP_ROM_SIZE_BYTES (1048576)
#define BSP_RAM_SIZE_BYTES (393216)
#define BSP_DATA_FLASH_SIZE_BYTES (32768)

13
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h"
@ -23,7 +27,6 @@
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
#define BSP_MCU_VBATT_SUPPORT (1)
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
@ -50,7 +53,9 @@
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
@ -71,4 +76,8 @@
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_adc_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_ADC_CFG_H_
#define R_ADC_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_ADC_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_agt_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_AGT_CFG_H_
#define R_AGT_CFG_H_
#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
#endif /* R_AGT_CFG_H_ */

6
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_dtc_cfg.h
View File

@ -1,6 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_DTC_CFG_H_
#define R_DTC_CFG_H_
#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
#endif /* R_DTC_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_flash_hp_cfg.h
View File

@ -1,7 +1,15 @@
/* generated configuration header file - do not edit */
#ifndef R_FLASH_HP_CFG_H_
#define R_FLASH_HP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1)
#define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0)
#ifdef __cplusplus
}
#endif
#endif /* R_FLASH_HP_CFG_H_ */

5
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_icu_cfg.h
View File

@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_iic_master_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_IIC_MASTER_CFG_H_
#define R_IIC_MASTER_CFG_H_
#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define IIC_MASTER_CFG_DTC_ENABLE (0)
#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0)
#endif /* R_IIC_MASTER_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_ioport_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_IOPORT_CFG_H_ */

9
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_lpm_cfg.h
View File

@ -1,5 +1,14 @@
/* generated configuration header file - do not edit */
#ifndef R_LPM_CFG_H_
#define R_LPM_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define LPM_CFG_STANDBY_LIMIT (0)
#ifdef __cplusplus
}
#endif
#endif /* R_LPM_CFG_H_ */

5
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_rtc_cfg.h
View File

@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_RTC_CFG_H_
#define R_RTC_CFG_H_
#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_RTC_CFG_H_ */

8
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
View File

@ -1,8 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#endif /* R_SCI_UART_CFG_H_ */

7
ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_spi_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_SPI_CFG_H_
#define R_SPI_CFG_H_
#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SPI_DTC_SUPPORT_ENABLE (1)
#define SPI_TRANSMIT_FROM_RXI_ISR (0)
#endif /* R_SPI_CFG_H_ */

6
ports/renesas-ra/boards/EK_RA6M2/ra_gen/bsp_clock_cfg.h
View File

@ -7,16 +7,16 @@
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U, 0U) /* PLL Mul x20.0 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLKout On */
#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */

4
ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.c
View File

@ -1,7 +1,5 @@
/* generated common source file - do not edit */
#include "common_data.h"
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport =
{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
void g_common_init(void) {
}

5
ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.h
View File

@ -1,16 +1,17 @@
/* generated common header file - do not edit */
#ifndef COMMON_DATA_H_
#define COMMON_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_ioport.h"
#include "bsp_pin_cfg.h"
FSP_HEADER
/* IOPORT Instance */
extern const ioport_instance_t g_ioport;
/* IOPORT control structure. */
extern ioport_instance_ctrl_t g_ioport_ctrl;
void g_common_init(void);
FSP_FOOTER
#endif /* COMMON_DATA_H_ */

959
ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.c
View File

@ -1,131 +1,16 @@
/* generated HAL source file - do not edit */
#include "hal_data.h"
/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
iic_master_instance_ctrl_t g_i2c_master2_ctrl;
const iic_master_extended_cfg_t g_i2c_master2_extend =
{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT,
/* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15,
.clock_settings.brh_value = 16, .clock_settings.cks_value = 4, };
const i2c_master_cfg_t g_i2c_master2_cfg =
{ .channel = 2, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.p_callback = callback_iic,
.p_context = NULL,
#if defined(VECTOR_NUMBER_IIC2_RXI)
.rxi_irq = VECTOR_NUMBER_IIC2_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC2_TXI)
.txi_irq = VECTOR_NUMBER_IIC2_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC2_TEI)
.tei_irq = VECTOR_NUMBER_IIC2_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC2_ERI)
.eri_irq = VECTOR_NUMBER_IIC2_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.ipl = (12),
.p_extend = &g_i2c_master2_extend, };
/* Instance structure to use this module. */
const i2c_master_instance_t g_i2c_master2 =
{ .p_ctrl = &g_i2c_master2_ctrl, .p_cfg = &g_i2c_master2_cfg, .p_api = &g_i2c_master_on_iic };
adc_instance_ctrl_t g_adc1_ctrl;
const adc_extended_cfg_t g_adc1_cfg_extend =
{ .add_average_count = ADC_ADD_OFF,
.clearing = ADC_CLEAR_AFTER_READ_ON,
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
const adc_cfg_t g_adc1_cfg =
{ .unit = 1, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment =
(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc1_cfg_extend,
#if defined(VECTOR_NUMBER_ADC1_SCAN_END)
.scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END,
#else
.scan_end_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_ADC1_SCAN_END_B)
.scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B,
#else
.scan_end_b_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
const adc_channel_cfg_t g_adc1_channel_cfg =
{ .scan_mask = 0,
.scan_mask_group_b = 0,
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
.add_mask = 0,
.sample_hold_mask = 0,
.sample_hold_states = 24, };
/* Instance structure to use this module. */
const adc_instance_t g_adc1 =
{ .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg, .p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc };
adc_instance_ctrl_t g_adc0_ctrl;
const adc_extended_cfg_t g_adc0_cfg_extend =
{ .add_average_count = ADC_ADD_OFF,
.clearing = ADC_CLEAR_AFTER_READ_ON,
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
const adc_cfg_t g_adc0_cfg =
{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment =
(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend,
#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
#else
.scan_end_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
#else
.scan_end_b_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
const adc_channel_cfg_t g_adc0_channel_cfg =
{ .scan_mask = 0,
.scan_mask_group_b = 0,
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
.add_mask = 0,
.sample_hold_mask = 0,
.sample_hold_states = 24, };
/* Instance structure to use this module. */
const adc_instance_t g_adc0 =
{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
lpm_instance_ctrl_t g_lpm0_ctrl;
const lpm_cfg_t g_lpm0_cfg =
{ .low_power_mode = LPM_MODE_SLEEP,
{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM
| (lpm_standby_wake_source_t)0,
#if BSP_FEATURE_LPM_HAS_SNOOZE
.snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0,
.snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
.snooze_end_sources = (lpm_snooze_end_t)0,
.dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
#endif
#if BSP_FEATURE_LPM_HAS_SBYCR_OPE
.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
#endif
@ -135,598 +20,24 @@ const lpm_cfg_t g_lpm0_cfg =
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
#endif
#if BSP_FEATURE_LPM_HAS_PDRAMSCR
.ram_retention_cfg.ram_retention = (uint8_t)(0),
.ram_retention_cfg.tcm_retention = false,
#endif
#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP
.ram_retention_cfg.standby_ram_retention = false,
#endif
#if BSP_FEATURE_LPM_HAS_LDO_CONTROL
.ldo_standby_cfg.pll1_ldo = false,
.ldo_standby_cfg.pll2_ldo = false,
.ldo_standby_cfg.hoco_ldo = false,
#endif
.p_extend = NULL, };
const lpm_instance_t g_lpm0 =
{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg };
dtc_instance_ctrl_t g_transfer3_ctrl;
transfer_info_t g_transfer3_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer3_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI1_RXI, };
const transfer_cfg_t g_transfer3_cfg =
{ .p_info = &g_transfer3_info, .p_extend = &g_transfer3_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer3 =
{ .p_ctrl = &g_transfer3_ctrl, .p_cfg = &g_transfer3_cfg, .p_api = &g_transfer_on_dtc };
dtc_instance_ctrl_t g_transfer2_ctrl;
transfer_info_t g_transfer2_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer2_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI1_TXI, };
const transfer_cfg_t g_transfer2_cfg =
{ .p_info = &g_transfer2_info, .p_extend = &g_transfer2_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer2 =
{ .p_ctrl = &g_transfer2_ctrl, .p_cfg = &g_transfer2_cfg, .p_api = &g_transfer_on_dtc };
spi_instance_ctrl_t g_spi1_ctrl;
/** SPI extended configuration for SPI HAL driver */
const spi_extended_cfg_t g_spi1_ext_cfg =
{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
.ssl_polarity = SPI_SSLP_LOW,
.ssl_select = SPI_SSL_SELECT_SSL0,
.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
.parity = SPI_PARITY_MODE_DISABLE,
.byte_swap = SPI_BYTE_SWAP_DISABLE,
.spck_div =
{
/* Actual calculated bitrate: 15000000. */ .spbr = 3,
.brdv = 0
},
.spck_delay = SPI_DELAY_COUNT_1,
.ssl_negation_delay = SPI_DELAY_COUNT_1,
.next_access_delay = SPI_DELAY_COUNT_1 };
/** SPI configuration for SPI HAL driver */
const spi_cfg_t g_spi1_cfg =
{ .channel = 1,
#if defined(VECTOR_NUMBER_SPI1_RXI)
.rxi_irq = VECTOR_NUMBER_SPI1_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI1_TXI)
.txi_irq = VECTOR_NUMBER_SPI1_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI1_TEI)
.tei_irq = VECTOR_NUMBER_SPI1_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI1_ERI)
.eri_irq = VECTOR_NUMBER_SPI1_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.rxi_ipl = (12),
.txi_ipl = (12),
.tei_ipl = (12),
.eri_ipl = (12),
.operating_mode = SPI_MODE_MASTER,
.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
.clk_polarity = SPI_CLK_POLARITY_LOW,
.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
.bit_order = SPI_BIT_ORDER_MSB_FIRST,
.p_transfer_tx = g_spi1_P_TRANSFER_TX,
.p_transfer_rx = g_spi1_P_TRANSFER_RX,
.p_callback = spi_callback,
.p_context = NULL,
.p_extend = (void *)&g_spi1_ext_cfg, };
/* Instance structure to use this module. */
const spi_instance_t g_spi1 =
{ .p_ctrl = &g_spi1_ctrl, .p_cfg = &g_spi1_cfg, .p_api = &g_spi_on_spi };
dtc_instance_ctrl_t g_transfer1_ctrl;
transfer_info_t g_transfer1_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer1_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_RXI, };
const transfer_cfg_t g_transfer1_cfg =
{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer1 =
{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc };
dtc_instance_ctrl_t g_transfer0_ctrl;
transfer_info_t g_transfer0_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer0_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_TXI, };
const transfer_cfg_t g_transfer0_cfg =
{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer0 =
{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc };
spi_instance_ctrl_t g_spi0_ctrl;
/** SPI extended configuration for SPI HAL driver */
const spi_extended_cfg_t g_spi0_ext_cfg =
{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
.ssl_polarity = SPI_SSLP_LOW,
.ssl_select = SPI_SSL_SELECT_SSL0,
.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
.parity = SPI_PARITY_MODE_DISABLE,
.byte_swap = SPI_BYTE_SWAP_DISABLE,
.spck_div =
{
/* Actual calculated bitrate: 15000000. */ .spbr = 3,
.brdv = 0
},
.spck_delay = SPI_DELAY_COUNT_1,
.ssl_negation_delay = SPI_DELAY_COUNT_1,
.next_access_delay = SPI_DELAY_COUNT_1 };
/** SPI configuration for SPI HAL driver */
const spi_cfg_t g_spi0_cfg =
{ .channel = 0,
#if defined(VECTOR_NUMBER_SPI0_RXI)
.rxi_irq = VECTOR_NUMBER_SPI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TXI)
.txi_irq = VECTOR_NUMBER_SPI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TEI)
.tei_irq = VECTOR_NUMBER_SPI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_ERI)
.eri_irq = VECTOR_NUMBER_SPI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.rxi_ipl = (12),
.txi_ipl = (12),
.tei_ipl = (12),
.eri_ipl = (12),
.operating_mode = SPI_MODE_MASTER,
.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
.clk_polarity = SPI_CLK_POLARITY_LOW,
.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
.bit_order = SPI_BIT_ORDER_MSB_FIRST,
.p_transfer_tx = g_spi0_P_TRANSFER_TX,
.p_transfer_rx = g_spi0_P_TRANSFER_RX,
.p_callback = spi_callback,
.p_context = NULL,
.p_extend = (void *)&g_spi0_ext_cfg, };
/* Instance structure to use this module. */
const spi_instance_t g_spi0 =
{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi };
icu_instance_ctrl_t g_external_irq15_ctrl;
const external_irq_cfg_t g_external_irq15_cfg =
{ .channel = 15,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ15)
.irq = VECTOR_NUMBER_ICU_IRQ15,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq15 =
{ .p_ctrl = &g_external_irq15_ctrl, .p_cfg = &g_external_irq15_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq14_ctrl;
const external_irq_cfg_t g_external_irq14_cfg =
{ .channel = 14,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ14)
.irq = VECTOR_NUMBER_ICU_IRQ14,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq14 =
{ .p_ctrl = &g_external_irq14_ctrl, .p_cfg = &g_external_irq14_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq13_ctrl;
const external_irq_cfg_t g_external_irq13_cfg =
{ .channel = 13,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ13)
.irq = VECTOR_NUMBER_ICU_IRQ13,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq13 =
{ .p_ctrl = &g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq12_ctrl;
const external_irq_cfg_t g_external_irq12_cfg =
{ .channel = 12,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ12)
.irq = VECTOR_NUMBER_ICU_IRQ12,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq12 =
{ .p_ctrl = &g_external_irq12_ctrl, .p_cfg = &g_external_irq12_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq11_ctrl;
const external_irq_cfg_t g_external_irq11_cfg =
{ .channel = 11,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ11)
.irq = VECTOR_NUMBER_ICU_IRQ11,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq11 =
{ .p_ctrl = &g_external_irq11_ctrl, .p_cfg = &g_external_irq11_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq10_ctrl;
const external_irq_cfg_t g_external_irq10_cfg =
{ .channel = 10,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ10)
.irq = VECTOR_NUMBER_ICU_IRQ10,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq10 =
{ .p_ctrl = &g_external_irq10_ctrl, .p_cfg = &g_external_irq10_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq9_ctrl;
const external_irq_cfg_t g_external_irq9_cfg =
{ .channel = 9,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ9)
.irq = VECTOR_NUMBER_ICU_IRQ9,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq9 =
{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq8_ctrl;
const external_irq_cfg_t g_external_irq8_cfg =
{ .channel = 8,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ8)
.irq = VECTOR_NUMBER_ICU_IRQ8,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq8 =
{ .p_ctrl = &g_external_irq8_ctrl, .p_cfg = &g_external_irq8_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq7_ctrl;
const external_irq_cfg_t g_external_irq7_cfg =
{ .channel = 7,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ7)
.irq = VECTOR_NUMBER_ICU_IRQ7,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq7 =
{ .p_ctrl = &g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq6_ctrl;
const external_irq_cfg_t g_external_irq6_cfg =
{ .channel = 6,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ6)
.irq = VECTOR_NUMBER_ICU_IRQ6,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq6 =
{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq5_ctrl;
const external_irq_cfg_t g_external_irq5_cfg =
{ .channel = 5,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ5)
.irq = VECTOR_NUMBER_ICU_IRQ5,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq5 =
{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq4_ctrl;
const external_irq_cfg_t g_external_irq4_cfg =
{ .channel = 4,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ4)
.irq = VECTOR_NUMBER_ICU_IRQ4,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq4 =
{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq3_ctrl;
const external_irq_cfg_t g_external_irq3_cfg =
{ .channel = 3,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ3)
.irq = VECTOR_NUMBER_ICU_IRQ3,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq3 =
{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq2_ctrl;
const external_irq_cfg_t g_external_irq2_cfg =
{ .channel = 2,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ2)
.irq = VECTOR_NUMBER_ICU_IRQ2,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq2 =
{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq1_ctrl;
const external_irq_cfg_t g_external_irq1_cfg =
{ .channel = 1,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ1)
.irq = VECTOR_NUMBER_ICU_IRQ1,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq1 =
{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq0_ctrl;
const external_irq_cfg_t g_external_irq0_cfg =
{ .channel = 0,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ0)
.irq = VECTOR_NUMBER_ICU_IRQ0,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq0 =
{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu };
agt_instance_ctrl_t g_timer1_ctrl;
const agt_extended_cfg_t g_timer1_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer1_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer1_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT0_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer1 =
{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt };
agt_instance_ctrl_t g_timer0_ctrl;
const agt_extended_cfg_t g_timer0_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer0_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer0_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT0_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer0 =
{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
flash_hp_instance_ctrl_t g_flash0_ctrl;
const flash_cfg_t g_flash0_cfg =
{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL,
@ -745,239 +56,3 @@ const flash_cfg_t g_flash0_cfg =
/* Instance structure to use this module. */
const flash_instance_t g_flash0 =
{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp };
rtc_instance_ctrl_t g_rtc0_ctrl;
const rtc_error_adjustment_cfg_t g_rtc0_err_cfg =
{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC,
.adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND,
.adjustment_type = RTC_ERROR_ADJUSTMENT_NONE,
.adjustment_value = 0, };
const rtc_cfg_t g_rtc0_cfg =
{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback =
NULL,
.p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14),
#if defined(VECTOR_NUMBER_RTC_ALARM)
.alarm_irq = VECTOR_NUMBER_RTC_ALARM,
#else
.alarm_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_PERIOD)
.periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
#else
.periodic_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_CARRY)
.carry_irq = VECTOR_NUMBER_RTC_CARRY,
#else
.carry_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const rtc_instance_t g_rtc0 =
{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc };
sci_uart_instance_ctrl_t g_uart9_ctrl;
baud_setting_t g_uart9_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart9_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart9_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart9_cfg =
{ .channel = 9, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart9_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI9_RXI)
.rxi_irq = VECTOR_NUMBER_SCI9_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI9_TXI)
.txi_irq = VECTOR_NUMBER_SCI9_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI9_TEI)
.tei_irq = VECTOR_NUMBER_SCI9_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI9_ERI)
.eri_irq = VECTOR_NUMBER_SCI9_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart9 =
{ .p_ctrl = &g_uart9_ctrl, .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart7_ctrl;
baud_setting_t g_uart7_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart7_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart7_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart7_cfg =
{ .channel = 7, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart7_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI7_RXI)
.rxi_irq = VECTOR_NUMBER_SCI7_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI7_TXI)
.txi_irq = VECTOR_NUMBER_SCI7_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI7_TEI)
.tei_irq = VECTOR_NUMBER_SCI7_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI7_ERI)
.eri_irq = VECTOR_NUMBER_SCI7_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart7 =
{ .p_ctrl = &g_uart7_ctrl, .p_cfg = &g_uart7_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart0_ctrl;
baud_setting_t g_uart0_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart0_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart0_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart0_cfg =
{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart0_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI0_RXI)
.rxi_irq = VECTOR_NUMBER_SCI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TXI)
.txi_irq = VECTOR_NUMBER_SCI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TEI)
.tei_irq = VECTOR_NUMBER_SCI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_ERI)
.eri_irq = VECTOR_NUMBER_SCI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart0 =
{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci };
void g_hal_init(void) {
g_common_init();
}

345
ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.h
View File

@ -2,318 +2,20 @@
#ifndef HAL_DATA_H_
#define HAL_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "common_data.h"
#include "r_iic_master.h"
#include "r_i2c_master_api.h"
#include "r_adc.h"
#include "r_adc_api.h"
#include "r_lpm.h"
#include "r_lpm_api.h"
#include "r_dtc.h"
#include "r_transfer_api.h"
#include "r_spi.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_agt.h"
#include "r_timer_api.h"
#include "r_flash_hp.h"
#include "r_flash_api.h"
#include "r_rtc.h"
#include "r_rtc_api.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
FSP_HEADER
/* I2C Master on IIC Instance. */
extern const i2c_master_instance_t g_i2c_master2;
/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */
extern iic_master_instance_ctrl_t g_i2c_master2_ctrl;
extern const i2c_master_cfg_t g_i2c_master2_cfg;
#ifndef callback_iic
void callback_iic(i2c_master_callback_args_t *p_args);
#endif
/** ADC on ADC Instance. */
extern const adc_instance_t g_adc1;
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
extern adc_instance_ctrl_t g_adc1_ctrl;
extern const adc_cfg_t g_adc1_cfg;
extern const adc_channel_cfg_t g_adc1_channel_cfg;
#ifndef NULL
void NULL(adc_callback_args_t *p_args);
#endif
/** ADC on ADC Instance. */
extern const adc_instance_t g_adc0;
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
extern adc_instance_ctrl_t g_adc0_ctrl;
extern const adc_cfg_t g_adc0_cfg;
extern const adc_channel_cfg_t g_adc0_channel_cfg;
#ifndef NULL
void NULL(adc_callback_args_t *p_args);
#endif
/** lpm Instance */
extern const lpm_instance_t g_lpm0;
/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */
extern lpm_instance_ctrl_t g_lpm0_ctrl;
extern const lpm_cfg_t g_lpm0_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer3;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer3_ctrl;
extern const transfer_cfg_t g_transfer3_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer2;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer2_ctrl;
extern const transfer_cfg_t g_transfer2_cfg;
/** SPI on SPI Instance. */
extern const spi_instance_t g_spi1;
/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
extern spi_instance_ctrl_t g_spi1_ctrl;
extern const spi_cfg_t g_spi1_cfg;
/** Callback used by SPI Instance. */
#ifndef spi_callback
void spi_callback(spi_callback_args_t *p_args);
#endif
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == g_transfer2)
#define g_spi1_P_TRANSFER_TX (NULL)
#else
#define g_spi1_P_TRANSFER_TX (&g_transfer2)
#endif
#if (RA_NOT_DEFINED == g_transfer3)
#define g_spi1_P_TRANSFER_RX (NULL)
#else
#define g_spi1_P_TRANSFER_RX (&g_transfer3)
#endif
#undef RA_NOT_DEFINED
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer1;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer1_ctrl;
extern const transfer_cfg_t g_transfer1_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer0;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer0_ctrl;
extern const transfer_cfg_t g_transfer0_cfg;
/** SPI on SPI Instance. */
extern const spi_instance_t g_spi0;
/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
extern spi_instance_ctrl_t g_spi0_ctrl;
extern const spi_cfg_t g_spi0_cfg;
/** Callback used by SPI Instance. */
#ifndef spi_callback
void spi_callback(spi_callback_args_t *p_args);
#endif
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == g_transfer0)
#define g_spi0_P_TRANSFER_TX (NULL)
#else
#define g_spi0_P_TRANSFER_TX (&g_transfer0)
#endif
#if (RA_NOT_DEFINED == g_transfer1)
#define g_spi0_P_TRANSFER_RX (NULL)
#else
#define g_spi0_P_TRANSFER_RX (&g_transfer1)
#endif
#undef RA_NOT_DEFINED
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq15;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq15_ctrl;
extern const external_irq_cfg_t g_external_irq15_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq14;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq14_ctrl;
extern const external_irq_cfg_t g_external_irq14_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq13;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq13_ctrl;
extern const external_irq_cfg_t g_external_irq13_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq12;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq12_ctrl;
extern const external_irq_cfg_t g_external_irq12_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq11;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq11_ctrl;
extern const external_irq_cfg_t g_external_irq11_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq10;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq10_ctrl;
extern const external_irq_cfg_t g_external_irq10_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq9;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq9_ctrl;
extern const external_irq_cfg_t g_external_irq9_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq8;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq8_ctrl;
extern const external_irq_cfg_t g_external_irq8_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq7;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq7_ctrl;
extern const external_irq_cfg_t g_external_irq7_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq6;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq6_ctrl;
extern const external_irq_cfg_t g_external_irq6_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq5;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq5_ctrl;
extern const external_irq_cfg_t g_external_irq5_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq4;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq4_ctrl;
extern const external_irq_cfg_t g_external_irq4_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq3;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq3_ctrl;
extern const external_irq_cfg_t g_external_irq3_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq2;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq2_ctrl;
extern const external_irq_cfg_t g_external_irq2_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq1;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq1_ctrl;
extern const external_irq_cfg_t g_external_irq1_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq0;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq0_ctrl;
extern const external_irq_cfg_t g_external_irq0_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer1;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer1_ctrl;
extern const timer_cfg_t g_timer1_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer0;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer0_ctrl;
extern const timer_cfg_t g_timer0_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/* Flash on Flash HP Instance */
extern const flash_instance_t g_flash0;
@ -321,53 +23,6 @@ extern const flash_instance_t g_flash0;
extern flash_hp_instance_ctrl_t g_flash0_ctrl;
extern const flash_cfg_t g_flash0_cfg;
#ifndef NULL
void NULL(flash_callback_args_t *p_args);
#endif
/* RTC Instance. */
extern const rtc_instance_t g_rtc0;
/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */
extern rtc_instance_ctrl_t g_rtc0_ctrl;
extern const rtc_cfg_t g_rtc0_cfg;
#ifndef NULL
void NULL(rtc_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart9;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart9_ctrl;
extern const uart_cfg_t g_uart9_cfg;
extern const sci_uart_extended_cfg_t g_uart9_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart7;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart7_ctrl;
extern const uart_cfg_t g_uart7_cfg;
extern const sci_uart_extended_cfg_t g_uart7_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart0;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart0_ctrl;
extern const uart_cfg_t g_uart0_cfg;
extern const sci_uart_extended_cfg_t g_uart0_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
void hal_entry(void);
void g_hal_init(void);
FSP_FOOTER
#endif /* HAL_DATA_H_ */

206
ports/renesas-ra/boards/EK_RA6M2/ra_gen/pin_data.c
View File

@ -1,117 +1,97 @@
/* generated pin source file - do not edit */
#include "bsp_api.h"
#include "r_ioport_api.h"
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{
.pin = BSP_IO_PORT_00_PIN_04,
.pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE),
},
{
.pin = BSP_IO_PORT_01_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_03,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
{
.pin = BSP_IO_PORT_01_PIN_06,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_01_PIN_08,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_09,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_02_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU),
},
{
.pin = BSP_IO_PORT_02_PIN_07,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU),
},
{
.pin = BSP_IO_PORT_03_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_04_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_04_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_07,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS),
},
{
.pin = BSP_IO_PORT_04_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_11,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_05_PIN_11,
.pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC),
},
{
.pin = BSP_IO_PORT_05_PIN_12,
.pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC),
},
{
.pin = BSP_IO_PORT_06_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_06_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_07_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_07_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_07_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_07_PIN_03,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] =
{
{ .pin = BSP_IO_PORT_00_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
{ .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_01_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE
| (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) },
{ .pin = BSP_IO_PORT_01_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) },
{ .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_CTSU) },
{ .pin = BSP_IO_PORT_02_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_CTSU) },
{ .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
{ .pin = BSP_IO_PORT_04_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) },
{ .pin = BSP_IO_PORT_04_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_USB_FS) },
{ .pin = BSP_IO_PORT_04_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_04_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
{ .pin = BSP_IO_PORT_05_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID
| (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) },
{ .pin = BSP_IO_PORT_05_PIN_12, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID
| (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) },
{ .pin = BSP_IO_PORT_06_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_06_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
{ .pin = BSP_IO_PORT_07_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_07_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_07_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
{ .pin = BSP_IO_PORT_07_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
| (uint32_t)IOPORT_PERIPHERAL_SPI) },
};
const ioport_cfg_t g_bsp_pin_cfg =
{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], };
#if BSP_TZ_SECURE_BUILD
void R_BSP_PinCfgSecurityInit(void);
/* Initialize SAR registers for secure pins. */
void R_BSP_PinCfgSecurityInit(void) {
#if (2U == BSP_FEATURE_IOPORT_VERSION)
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#else
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#endif
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
{
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
uint32_t port = port_pin >> 8U;
uint32_t pin = port_pin & 0xFFU;
pmsar[port] &= (uint16_t) ~(1U << pin);
}
for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
{
#if (2U == BSP_FEATURE_IOPORT_VERSION)
R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i];
#else
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
#endif
}
}
#endif

136
ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.c
View File

@ -14,40 +14,40 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS
[7] = sci_uart_eri_isr, /* SCI7 ERI (Receive error) */
[8] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */
[9] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */
[10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[17] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */
[18] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */
[19] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */
[20] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */
[21] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */
[22] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */
[23] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */
[24] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */
[25] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */
[26] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */
[27] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */
[28] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */
[29] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */
[30] = r_icu_isr, /* ICU IRQ14 (External pin interrupt 14) */
[31] = r_icu_isr, /* ICU IRQ15 (External pin interrupt 15) */
[32] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[33] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[34] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[35] = spi_eri_isr, /* SPI0 ERI (Error) */
[36] = spi_rxi_isr, /* SPI1 RXI (Receive buffer full) */
[37] = spi_txi_isr, /* SPI1 TXI (Transmit buffer empty) */
[38] = spi_tei_isr, /* SPI1 TEI (Transmission complete event) */
[39] = spi_eri_isr, /* SPI1 ERI (Error) */
[40] = iic_master_rxi_isr, /* IIC2 RXI (Receive data full) */
[41] = iic_master_txi_isr, /* IIC2 TXI (Transmit data empty) */
[42] = iic_master_tei_isr, /* IIC2 TEI (Transmit end) */
[43] = iic_master_eri_isr, /* IIC2 ERI (Transfer error) */
[10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[17] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */
[18] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */
[19] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */
[20] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */
[21] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */
[22] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */
[23] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */
[24] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */
[25] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */
[26] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */
[27] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */
[28] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */
[29] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */
[30] = r_icu_isr, /* ICU IRQ14 (External pin interrupt 14) */
[31] = r_icu_isr, /* ICU IRQ15 (External pin interrupt 15) */
[32] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[33] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[34] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[35] = spi_eri_isr, /* SPI0 ERI (Error) */
[36] = spi_rxi_isr, /* SPI1 RXI (Receive buffer full) */
[37] = spi_txi_isr, /* SPI1 TXI (Transmit buffer empty) */
[38] = spi_tei_isr, /* SPI1 TEI (Transmission complete event) */
[39] = spi_eri_isr, /* SPI1 ERI (Error) */
[40] = iic_master_rxi_isr, /* IIC2 RXI (Receive data full) */
[41] = iic_master_txi_isr, /* IIC2 TXI (Transmit data empty) */
[42] = iic_master_tei_isr, /* IIC2 TEI (Transmit end) */
[43] = iic_master_eri_isr, /* IIC2 ERI (Transfer error) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
@ -61,39 +61,39 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT
[7] = BSP_PRV_IELS_ENUM(EVENT_SCI7_ERI), /* SCI7 ERI (Receive error) */
[8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */
[9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */
[18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */
[19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */
[20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */
[21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */
[22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */
[23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */
[24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */
[25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */
[26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */
[27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */
[28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */
[29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */
[30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ14), /* ICU IRQ14 (External pin interrupt 14) */
[31] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ15), /* ICU IRQ15 (External pin interrupt 15) */
[32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[35] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
[36] = BSP_PRV_IELS_ENUM(EVENT_SPI1_RXI), /* SPI1 RXI (Receive buffer full) */
[37] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TXI), /* SPI1 TXI (Transmit buffer empty) */
[38] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TEI), /* SPI1 TEI (Transmission complete event) */
[39] = BSP_PRV_IELS_ENUM(EVENT_SPI1_ERI), /* SPI1 ERI (Error) */
[40] = BSP_PRV_IELS_ENUM(EVENT_IIC2_RXI), /* IIC2 RXI (Receive data full) */
[41] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TXI), /* IIC2 TXI (Transmit data empty) */
[42] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TEI), /* IIC2 TEI (Transmit end) */
[43] = BSP_PRV_IELS_ENUM(EVENT_IIC2_ERI), /* IIC2 ERI (Transfer error) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */
[18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */
[19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */
[20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */
[21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */
[22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */
[23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */
[24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */
[25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */
[26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */
[27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */
[28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */
[29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */
[30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ14), /* ICU IRQ14 (External pin interrupt 14) */
[31] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ15), /* ICU IRQ15 (External pin interrupt 15) */
[32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[35] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
[36] = BSP_PRV_IELS_ENUM(EVENT_SPI1_RXI), /* SPI1 RXI (Receive buffer full) */
[37] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TXI), /* SPI1 TXI (Transmit buffer empty) */
[38] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TEI), /* SPI1 TEI (Transmission complete event) */
[39] = BSP_PRV_IELS_ENUM(EVENT_SPI1_ERI), /* SPI1 ERI (Error) */
[40] = BSP_PRV_IELS_ENUM(EVENT_IIC2_RXI), /* IIC2 RXI (Receive data full) */
[41] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TXI), /* IIC2 TXI (Transmit data empty) */
[42] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TEI), /* IIC2 TEI (Transmit end) */
[43] = BSP_PRV_IELS_ENUM(EVENT_IIC2_ERI), /* IIC2 ERI (Transfer error) */
};
#endif

108
ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.h
View File

@ -1,6 +1,9 @@
/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (44)
@ -25,105 +28,94 @@ void iic_master_eri_isr(void);
/* Vector table allocations */
#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
#define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
#define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
#define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
#define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
#define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type)4) /* SCI7 RXI (Received data full) */
#define SCI7_RXI_IRQn ((IRQn_Type)4) /* SCI7 RXI (Received data full) */
#define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */
#define SCI7_TXI_IRQn ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */
#define SCI7_TEI_IRQn ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type)7) /* SCI7 ERI (Receive error) */
#define SCI7_ERI_IRQn ((IRQn_Type)7) /* SCI7 ERI (Receive error) */
#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */
#define SCI9_RXI_IRQn ((IRQn_Type)8) /* SCI9 RXI (Received data full) */
#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */
#define SCI9_TXI_IRQn ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */
#define SCI9_TEI_IRQn ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */
#define SCI9_ERI_IRQn ((IRQn_Type)11) /* SCI9 ERI (Receive error) */
#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */
#define ICU_IRQ0_IRQn ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */
#define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)17) /* ICU IRQ1 (External pin interrupt 1) */
#define ICU_IRQ1_IRQn ((IRQn_Type)17) /* ICU IRQ1 (External pin interrupt 1) */
#define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)18) /* ICU IRQ2 (External pin interrupt 2) */
#define ICU_IRQ2_IRQn ((IRQn_Type)18) /* ICU IRQ2 (External pin interrupt 2) */
#define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)19) /* ICU IRQ3 (External pin interrupt 3) */
#define ICU_IRQ3_IRQn ((IRQn_Type)19) /* ICU IRQ3 (External pin interrupt 3) */
#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)20) /* ICU IRQ4 (External pin interrupt 4) */
#define ICU_IRQ4_IRQn ((IRQn_Type)20) /* ICU IRQ4 (External pin interrupt 4) */
#define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)21) /* ICU IRQ5 (External pin interrupt 5) */
#define ICU_IRQ5_IRQn ((IRQn_Type)21) /* ICU IRQ5 (External pin interrupt 5) */
#define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)22) /* ICU IRQ6 (External pin interrupt 6) */
#define ICU_IRQ6_IRQn ((IRQn_Type)22) /* ICU IRQ6 (External pin interrupt 6) */
#define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)23) /* ICU IRQ7 (External pin interrupt 7) */
#define ICU_IRQ7_IRQn ((IRQn_Type)23) /* ICU IRQ7 (External pin interrupt 7) */
#define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type)24) /* ICU IRQ8 (External pin interrupt 8) */
#define ICU_IRQ8_IRQn ((IRQn_Type)24) /* ICU IRQ8 (External pin interrupt 8) */
#define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)25) /* ICU IRQ9 (External pin interrupt 9) */
#define ICU_IRQ9_IRQn ((IRQn_Type)25) /* ICU IRQ9 (External pin interrupt 9) */
#define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type)26) /* ICU IRQ10 (External pin interrupt 10) */
#define ICU_IRQ10_IRQn ((IRQn_Type)26) /* ICU IRQ10 (External pin interrupt 10) */
#define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type)27) /* ICU IRQ11 (External pin interrupt 11) */
#define ICU_IRQ11_IRQn ((IRQn_Type)27) /* ICU IRQ11 (External pin interrupt 11) */
#define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type)28) /* ICU IRQ12 (External pin interrupt 12) */
#define ICU_IRQ12_IRQn ((IRQn_Type)28) /* ICU IRQ12 (External pin interrupt 12) */
#define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)29) /* ICU IRQ13 (External pin interrupt 13) */
#define ICU_IRQ13_IRQn ((IRQn_Type)29) /* ICU IRQ13 (External pin interrupt 13) */
#define VECTOR_NUMBER_ICU_IRQ14 ((IRQn_Type)30) /* ICU IRQ14 (External pin interrupt 14) */
#define ICU_IRQ14_IRQn ((IRQn_Type)30) /* ICU IRQ14 (External pin interrupt 14) */
#define VECTOR_NUMBER_ICU_IRQ15 ((IRQn_Type)31) /* ICU IRQ15 (External pin interrupt 15) */
#define ICU_IRQ15_IRQn ((IRQn_Type)31) /* ICU IRQ15 (External pin interrupt 15) */
#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)32) /* SPI0 RXI (Receive buffer full) */
#define SPI0_RXI_IRQn ((IRQn_Type)32) /* SPI0 RXI (Receive buffer full) */
#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)33) /* SPI0 TXI (Transmit buffer empty) */
#define SPI0_TXI_IRQn ((IRQn_Type)33) /* SPI0 TXI (Transmit buffer empty) */
#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)34) /* SPI0 TEI (Transmission complete event) */
#define SPI0_TEI_IRQn ((IRQn_Type)34) /* SPI0 TEI (Transmission complete event) */
#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)35) /* SPI0 ERI (Error) */
#define SPI0_ERI_IRQn ((IRQn_Type)35) /* SPI0 ERI (Error) */
#define VECTOR_NUMBER_SPI1_RXI ((IRQn_Type)36) /* SPI1 RXI (Receive buffer full) */
#define SPI1_RXI_IRQn ((IRQn_Type)36) /* SPI1 RXI (Receive buffer full) */
#define VECTOR_NUMBER_SPI1_TXI ((IRQn_Type)37) /* SPI1 TXI (Transmit buffer empty) */
#define SPI1_TXI_IRQn ((IRQn_Type)37) /* SPI1 TXI (Transmit buffer empty) */
#define VECTOR_NUMBER_SPI1_TEI ((IRQn_Type)38) /* SPI1 TEI (Transmission complete event) */
#define SPI1_TEI_IRQn ((IRQn_Type)38) /* SPI1 TEI (Transmission complete event) */
#define VECTOR_NUMBER_SPI1_ERI ((IRQn_Type)39) /* SPI1 ERI (Error) */
#define SPI1_ERI_IRQn ((IRQn_Type)39) /* SPI1 ERI (Error) */
#define VECTOR_NUMBER_IIC2_RXI ((IRQn_Type)40) /* IIC2 RXI (Receive data full) */
#define IIC2_RXI_IRQn ((IRQn_Type)40) /* IIC2 RXI (Receive data full) */
#define VECTOR_NUMBER_IIC2_TXI ((IRQn_Type)41) /* IIC2 TXI (Transmit data empty) */
#define IIC2_TXI_IRQn ((IRQn_Type)41) /* IIC2 TXI (Transmit data empty) */
#define VECTOR_NUMBER_IIC2_TEI ((IRQn_Type)42) /* IIC2 TEI (Transmit end) */
#define IIC2_TEI_IRQn ((IRQn_Type)42) /* IIC2 TEI (Transmit end) */
#define VECTOR_NUMBER_IIC2_ERI ((IRQn_Type)43) /* IIC2 ERI (Transfer error) */
typedef enum IRQn
{
Reset_IRQn = -15,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SecureFault_IRQn = -9,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */
SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */
SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */
SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */
SCI7_RXI_IRQn = 4, /* SCI7 RXI (Received data full) */
SCI7_TXI_IRQn = 5, /* SCI7 TXI (Transmit data empty) */
SCI7_TEI_IRQn = 6, /* SCI7 TEI (Transmit end) */
SCI7_ERI_IRQn = 7, /* SCI7 ERI (Receive error) */
SCI9_RXI_IRQn = 8, /* SCI9 RXI (Received data full) */
SCI9_TXI_IRQn = 9, /* SCI9 TXI (Transmit data empty) */
SCI9_TEI_IRQn = 10, /* SCI9 TEI (Transmit end) */
SCI9_ERI_IRQn = 11, /* SCI9 ERI (Receive error) */
RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */
RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */
RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */
AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */
ICU_IRQ0_IRQn = 16, /* ICU IRQ0 (External pin interrupt 0) */
ICU_IRQ1_IRQn = 17, /* ICU IRQ1 (External pin interrupt 1) */
ICU_IRQ2_IRQn = 18, /* ICU IRQ2 (External pin interrupt 2) */
ICU_IRQ3_IRQn = 19, /* ICU IRQ3 (External pin interrupt 3) */
ICU_IRQ4_IRQn = 20, /* ICU IRQ4 (External pin interrupt 4) */
ICU_IRQ5_IRQn = 21, /* ICU IRQ5 (External pin interrupt 5) */
ICU_IRQ6_IRQn = 22, /* ICU IRQ6 (External pin interrupt 6) */
ICU_IRQ7_IRQn = 23, /* ICU IRQ7 (External pin interrupt 7) */
ICU_IRQ8_IRQn = 24, /* ICU IRQ8 (External pin interrupt 8) */
ICU_IRQ9_IRQn = 25, /* ICU IRQ9 (External pin interrupt 9) */
ICU_IRQ10_IRQn = 26, /* ICU IRQ10 (External pin interrupt 10) */
ICU_IRQ11_IRQn = 27, /* ICU IRQ11 (External pin interrupt 11) */
ICU_IRQ12_IRQn = 28, /* ICU IRQ12 (External pin interrupt 12) */
ICU_IRQ13_IRQn = 29, /* ICU IRQ13 (External pin interrupt 13) */
ICU_IRQ14_IRQn = 30, /* ICU IRQ14 (External pin interrupt 14) */
ICU_IRQ15_IRQn = 31, /* ICU IRQ15 (External pin interrupt 15) */
SPI0_RXI_IRQn = 32, /* SPI0 RXI (Receive buffer full) */
SPI0_TXI_IRQn = 33, /* SPI0 TXI (Transmit buffer empty) */
SPI0_TEI_IRQn = 34, /* SPI0 TEI (Transmission complete event) */
SPI0_ERI_IRQn = 35, /* SPI0 ERI (Error) */
SPI1_RXI_IRQn = 36, /* SPI1 RXI (Receive buffer full) */
SPI1_TXI_IRQn = 37, /* SPI1 TXI (Transmit buffer empty) */
SPI1_TEI_IRQn = 38, /* SPI1 TEI (Transmission complete event) */
SPI1_ERI_IRQn = 39, /* SPI1 ERI (Error) */
IIC2_RXI_IRQn = 40, /* IIC2 RXI (Receive data full) */
IIC2_TXI_IRQn = 41, /* IIC2 TXI (Transmit data empty) */
IIC2_TEI_IRQn = 42, /* IIC2 TEI (Transmit end) */
IIC2_ERI_IRQn = 43, /* IIC2 ERI (Transfer error) */
} IRQn_Type;
#define IIC2_ERI_IRQn ((IRQn_Type)43) /* IIC2 ERI (Transfer error) */
#ifdef __cplusplus
}
#endif
#endif /* VECTOR_DATA_H */

8
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
void bsp_init(void *p_args);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_CFG_H_ */

21
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
@ -14,7 +18,13 @@
#define BSP_CFG_RTOS (0)
#endif
#endif
#ifndef BSP_CFG_RTC_USED
#define BSP_CFG_RTC_USED (1)
#endif
#undef RA_NOT_DEFINED
#if defined(_RA_BOOT_IMAGE)
#define BSP_CFG_BOOT_IMAGE (1)
#endif
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
#define BSP_CFG_HEAP_BYTES (0x4980)
@ -25,15 +35,14 @@
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_EARLY_INIT ((0))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
@ -46,4 +55,8 @@
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_CFG_H_ */

1
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
View File

@ -2,6 +2,7 @@
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA4M1AB3CFM
#define BSP_MCU_FEATURE_SET ('A')
#define BSP_ROM_SIZE_BYTES (262144)
#define BSP_RAM_SIZE_BYTES (32768)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)

13
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
View File

@ -1,6 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
@ -22,7 +26,6 @@
#endif
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
#define BSP_MCU_VBATT_SUPPORT (1)
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
@ -50,7 +53,9 @@
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
@ -71,4 +76,8 @@
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

8
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_ADC_CFG_H_
#define R_ADC_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_ADC_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_agt_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_AGT_CFG_H_
#define R_AGT_CFG_H_
#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
#endif /* R_AGT_CFG_H_ */

6
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_dtc_cfg.h
View File

@ -1,6 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_DTC_CFG_H_
#define R_DTC_CFG_H_
#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
#endif /* R_DTC_CFG_H_ */

8
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h
View File

@ -1,7 +1,15 @@
/* generated configuration header file - do not edit */
#ifndef R_FLASH_LP_CFG_H_
#define R_FLASH_LP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1)
#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0)
#ifdef __cplusplus
}
#endif
#endif /* R_FLASH_LP_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_icu_cfg.h
View File

@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_iic_master_cfg.h
View File

@ -1,7 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_IIC_MASTER_CFG_H_
#define R_IIC_MASTER_CFG_H_
#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define IIC_MASTER_CFG_DTC_ENABLE (0)
#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0)
#endif /* R_IIC_MASTER_CFG_H_ */

8
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_IOPORT_CFG_H_ */

9
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h
View File

@ -1,5 +1,14 @@
/* generated configuration header file - do not edit */
#ifndef R_LPM_CFG_H_
#define R_LPM_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define LPM_CFG_STANDBY_LIMIT (0)
#ifdef __cplusplus
}
#endif
#endif /* R_LPM_CFG_H_ */

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