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stm: Upgrade ST peripheral library from 1.1.0 to 1.3.0.

This commit is contained in:
Damien George 2014-01-19 17:40:35 +00:00
parent 1277753812
commit b2ebb161d4
41 changed files with 6294 additions and 450 deletions
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3
stm/Makefile
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@ -22,7 +22,7 @@ LD = arm-none-eabi-ld
OBJCOPY = arm-none-eabi-objcopy
SIZE = arm-none-eabi-size
CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion -DSTM32F40XX -DHSE_VALUE=8000000
CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion -DSTM32F40_41xxx -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000
CFLAGS = -I. -I$(PY_SRC) -I$(FATFSSRC) -I$(CMSIS) -I$(STMSRC) -Wall -ansi -std=gnu99 $(CFLAGS_CORTEX_M4) -D$(TARGET)
#CFLAGS += -I$(STMOTGSRC) -DUSE_HOST_MODE -DUSE_OTG_MODE
@ -85,6 +85,7 @@ SRC_STM = \
stm32f4xx_spi.c \
stm32f4xx_dac.c \
stm32f4xx_rng.c \
stm32f4xx_i2c.c \
usb_core.c \
usb_dcd.c \
usb_dcd_int.c \

8
stm/adc.c
View File

@ -1,7 +1,5 @@
#include <stdio.h>
#include <stm32f4xx_rcc.h>
#include <stm32f4xx_gpio.h>
#include <stm32f4xx_adc.h>
#include <stm32f4xx.h>
#include "misc.h"
#include "mpconfig.h"
@ -14,7 +12,7 @@
#define ADC_NUM_CHANNELS (16)
/* Internally connected ADC channels Temp/VBAT/VREF*/
#if defined (STM32F40XX) || defined(STM32F41XX)
#if defined (STM32F40XX) || defined(STM32F41XX) || defined(STM32F40_41xxx)
#define ADC_TEMP_CHANNEL (16)
#define ADC_VBAT_CHANNEL (18)
#define ADC_VREF_CHANNEL (17)
@ -29,7 +27,7 @@
#define CORE_TEMP_AVG_SLOPE (3) /* (2.5mv/3.3v)*(2^ADC resoultion) */
/* VBAT divider */
#if defined (STM32F40XX) || defined(STM32F41XX)
#if defined (STM32F40XX) || defined(STM32F41XX) || defined(STM32F40_41xxx)
#define VBAT_DIV (2)
#elif defined (STM32F42XX) || defined(STM32F43XX)
#define VBAT_DIV (4)

2
stm/i2c.c
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@ -1,8 +1,6 @@
#include <stdio.h>
#include <stm32f4xx.h>
#include <stm32f4xx_rcc.h>
#include <stm32f4xx_gpio.h>
#include "misc.h"
#include "systick.h"

2112
stm/lib/stm32f4xx.h
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File diff suppressed because it is too large Load Diff

1
stm/lib/stm32f4xx_adc.c
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@ -105,7 +105,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_adc.h"
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_conf.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{

76
stm/lib/stm32f4xx_conf.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
* @author MCD Application Team
* @version V1.1.0
* @date 18-January-2013
* @version V1.3.0
* @date 13-November-2013
* @brief Library configuration file.
******************************************************************************
* @attention
@ -31,32 +31,60 @@
/* Includes ------------------------------------------------------------------*/
/* Uncomment the line below to enable peripheral header file inclusion */
//#include "stm32f4xx_adc.h"
//#include "stm32f4xx_can.h"
#include "stm32f4xx_adc.h"
//#include "stm32f4xx_crc.h"
//#include "stm32f4xx_cryp.h"
//#include "stm32f4xx_dac.h"
//#include "stm32f4xx_dbgmcu.h"
//#include "stm32f4xx_dcmi.h"
//#include "stm32f4xx_dma.h"
//#include "stm32f4xx_exti.h"
//#include "stm32f4xx_flash.h"
//#include "stm32f4xx_fsmc.h"
//#include "stm32f4xx_hash.h"
//#include "stm32f4xx_gpio.h"
//#include "stm32f4xx_i2c.h"
#include "stm32f4xx_dma.h"
#include "stm32f4xx_exti.h"
#include "stm32f4xx_flash.h"
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_i2c.h"
//#include "stm32f4xx_iwdg.h"
//#include "stm32f4xx_pwr.h"
//#include "stm32f4xx_rcc.h"
//#include "stm32f4xx_rng.h"
//#include "stm32f4xx_rtc.h"
//#include "stm32f4xx_sdio.h"
//#include "stm32f4xx_spi.h"
//#include "stm32f4xx_syscfg.h"
//#include "stm32f4xx_tim.h"
//#include "stm32f4xx_usart.h"
#include "stm32f4xx_pwr.h"
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_rtc.h"
#include "stm32f4xx_sdio.h"
#include "stm32f4xx_spi.h"
#include "stm32f4xx_syscfg.h"
#include "stm32f4xx_tim.h"
#include "stm32f4xx_usart.h"
//#include "stm32f4xx_wwdg.h"
//#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#include "stm_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#if defined (STM32F429_439xx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_fmc.h"
#include "stm32f4xx_ltdc.h"
#include "stm32f4xx_sai.h"
#endif /* STM32F429_439xx */
#if defined (STM32F427_437xx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_fmc.h"
#include "stm32f4xx_sai.h"
#endif /* STM32F427_437xx */
#if defined (STM32F40_41xxx)
//#include "stm32f4xx_cryp.h"
//#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
//#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
//#include "stm32f4xx_dcmi.h"
//#include "stm32f4xx_fsmc.h"
#endif /* STM32F40_41xxx */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

5
stm/lib/stm32f4xx_dac.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dac.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* + DAC channels configuration: trigger, output buffer, data format
@ -128,7 +128,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_rcc.h"

4
stm/lib/stm32f4xx_dac.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dac.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************

5
stm/lib/stm32f4xx_dma.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* + Initialization and Configuration
@ -121,7 +121,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_dma.h"
#include "stm32f4xx_rcc.h"

4
stm/lib/stm32f4xx_dma.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************

12
stm/lib/stm32f4xx_exti.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_exti.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* + Initialization and Configuration
@ -65,7 +65,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_exti.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
@ -264,13 +263,11 @@ void EXTI_ClearFlag(uint32_t EXTI_Line)
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
enablestatus = EXTI->IMR & EXTI_Line;
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
@ -279,6 +276,7 @@ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
bitstatus = RESET;
}
return bitstatus;
}
/**

4
stm/lib/stm32f4xx_exti.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_exti.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************

485
stm/lib/stm32f4xx_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* + FLASH Interface configuration
@ -70,7 +70,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_flash.h"
#include "stm32f4xx_conf.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@ -108,6 +107,8 @@
To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device.
[..]
For STM32F405xx/07xx and STM32F415xx/17xx devices
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
@ -124,11 +125,57 @@
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
|5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
+---------------|----------------|----------------|-----------------|-----------------+
[..]
For STM32F42xxx/43xxx devices
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
|---------------|----------------|----------------|-----------------|-----------------|
|8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
+-------------------------------------------------------------------------------------+
[..]
For STM32F401x devices
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
+-------------------------------------------------------------------------------------+
[..]
@ -140,16 +187,20 @@
|---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
|PSIZE[1:0] | 10 | 01 | 00 | 11 |
+-------------------------------------------------------------------------------------------------------------------+
-@- When VOS bit (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
-@- On STM32F40xx/41xx devices:
(++) when VOS = '0', the maximum value of fHCLK = 144MHz.
(++) when VOS = '1', the maximum value of fHCLK = 168MHz.
-@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
(++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
(++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
[..]
On STM32F427x/437x devices:
(++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
(++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
(++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
On STM32F42xxx/43xxx devices:
(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
(++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
[..]
On STM32F401x devices:
(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
For more details please refer product DataSheet
You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
(+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
@ -176,9 +227,22 @@
* @arg FLASH_Latency_4: FLASH Four Latency cycles
* @arg FLASH_Latency_5: FLASH Five Latency cycles
* @arg FLASH_Latency_6: FLASH Six Latency cycles
* @arg FLASH_Latency_7: FLASH Seven Latency cycles
* For STM32F40xx/41xx and STM32F427x/437x devices this parameter can be
* a value between FLASH_Latency_0 and FLASH_Latency_7.
* @arg FLASH_Latency_7: FLASH Seven Latency cycles
* @arg FLASH_Latency_8: FLASH Eight Latency cycles
* @arg FLASH_Latency_9: FLASH Nine Latency cycles
* @arg FLASH_Latency_10: FLASH Teen Latency cycles
* @arg FLASH_Latency_11: FLASH Eleven Latency cycles
* @arg FLASH_Latency_12: FLASH Twelve Latency cycles
* @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
* @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
* @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
*
* @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx devices this parameter
* can be a value between FLASH_Latency_0 and FLASH_Latency_7.
*
* @note For STM32F42xxx/43xxx devices this parameter can be a value between
* FLASH_Latency_0 and FLASH_Latency_15.
*
* @retval None
*/
void FLASH_SetLatency(uint32_t FLASH_Latency)
@ -296,7 +360,10 @@ void FLASH_DataCacheReset(void)
(+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
(+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
(+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
(+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
(+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
The following functions can be used only for STM32F42xxx/43xxx devices.
(+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
(+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
[..]
Any operation of erase or program should follow these steps:
(#) Call the FLASH_Unlock() function to enable the FLASH control register access
@ -343,10 +410,15 @@ void FLASH_Lock(void)
* the erase operation is performed before the program one.
*
* @param FLASH_Sector: The Sector number to be erased.
* For STM32F40xx/41xx devices this parameter can be a value between
* FLASH_Sector_0 and FLASH_Sector_11.
* For STM32F427x/437x devices this parameter can be a value between
* FLASH_Sector_0 and FLASH_Sector_23.
*
* @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can
* be a value between FLASH_Sector_0 and FLASH_Sector_11.
*
* For STM32F42xxx/43xxx devices this parameter can be a value between
* FLASH_Sector_0 and FLASH_Sector_23.
*
* For STM32F401xx devices this parameter can be a value between
* FLASH_Sector_0 and FLASH_Sector_5.
*
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
@ -458,7 +530,7 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all sectors */
#if defined (STM32F427X)
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
@ -469,9 +541,9 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
#endif /* STM32F427X */
#endif /* STM32F427_437xx || STM32F429_439xx */
#ifdef STM32F40XX
#if defined (STM32F40_41xxx) || defined (STM32F401xx)
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= FLASH_CR_MER;
@ -482,7 +554,140 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= (~FLASH_CR_MER);
#endif /* STM32F40XX */
#endif /* STM32F40_41xxx || STM32F401xx */
}
/* Return the Erase Status */
return status;
}
/**
* @brief Erases all FLASH Sectors in Bank 1.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
* FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
*/
FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
{
uint32_t tmp_psize = 0x0;
FLASH_Status status = FLASH_COMPLETE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation();
assert_param(IS_VOLTAGERANGE(VoltageRange));
if(VoltageRange == VoltageRange_1)
{
tmp_psize = FLASH_PSIZE_BYTE;
}
else if(VoltageRange == VoltageRange_2)
{
tmp_psize = FLASH_PSIZE_HALF_WORD;
}
else if(VoltageRange == VoltageRange_3)
{
tmp_psize = FLASH_PSIZE_WORD;
}
else
{
tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
}
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all sectors */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= FLASH_CR_MER1;
FLASH->CR |= FLASH_CR_STRT;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation();
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= (~FLASH_CR_MER1);
}
/* Return the Erase Status */
return status;
}
/**
* @brief Erases all FLASH Sectors in Bank 2.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
* FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
*/
FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
{
uint32_t tmp_psize = 0x0;
FLASH_Status status = FLASH_COMPLETE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation();
assert_param(IS_VOLTAGERANGE(VoltageRange));
if(VoltageRange == VoltageRange_1)
{
tmp_psize = FLASH_PSIZE_BYTE;
}
else if(VoltageRange == VoltageRange_2)
{
tmp_psize = FLASH_PSIZE_HALF_WORD;
}
else if(VoltageRange == VoltageRange_3)
{
tmp_psize = FLASH_PSIZE_WORD;
}
else
{
tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
}
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all sectors */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= FLASH_CR_MER2;
FLASH->CR |= FLASH_CR_STRT;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation();
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= (~FLASH_CR_MER2);
}
/* Return the Erase Status */
@ -676,6 +881,9 @@ FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
(+) void FLASH_OB_Lock(void)
(+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
(+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
(+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
(+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
(+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
(+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
(+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
(+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
@ -683,9 +891,14 @@ FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
(+) FLASH_Status FLASH_OB_Launch(void)
(+) uint32_t FLASH_OB_GetUser(void)
(+) uint8_t FLASH_OB_GetWRP(void)
(+) uint8_t FLASH_OB_GetWRP1(void)
(+) uint8_t FLASH_OB_GetWRP1(void)
(+) uint8_t FLASH_OB_GetPCROP(void)
(+) uint8_t FLASH_OB_GetPCROP1(void)
(+) uint8_t FLASH_OB_GetRDP(void)
(+) uint8_t FLASH_OB_GetBOR(void)
[..]
The following function can be used only for STM32F42xxx/43xxx devices.
(+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
[..]
Any operation of erase or program should follow these steps:
(#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
@ -742,7 +955,8 @@ void FLASH_OB_Lock(void)
}
/**
* @brief Enables or disables the write protection of the desired sectors
* @brief Enables or disables the write protection of the desired sectors, for the first
* 1 Mb of the Flash
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM4
@ -781,8 +995,11 @@ void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
}
/**
* @brief Enables or disables the write protection of the desired sectors
* @note This function can be used only for STM32F427x/437x devices.
* @brief Enables or disables the write protection of the desired sectors, for the second
* 1 Mb of the Flash
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @note When the memory read out protection is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM4
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
@ -819,6 +1036,124 @@ void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
}
}
/**
* @brief Select the Protection Mode (SPRMOD).
*
* @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices.
*
* @note After PCROP activation, Option Byte modification is not possible.
* Exception made for the global Read Out Protection modification level (level1 to level0)
* @note Once SPRMOD bit is active unprotection of a protected sector is not possible
*
* @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
*
* @note Some Precautions should be taken when activating the PCROP feature :
* The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
* and WRPi = 1 (default value), then the user sector i is read/write protected.
* In order to avoid activation of PCROP Mode for undesired sectors, please follow the
* below safety sequence :
* - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function
* for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
* - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
* - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
*
* @param OB_PCROP: Select the Protection Mode of nWPRi bits
* This parameter can be one of the following values:
* @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
* @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
* @retval None
*/
void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
{
uint8_t optiontmp = 0xFF;
/* Check the parameters */
assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
/* Mask SPRMOD bit */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
/* Update Option Byte */
*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp);
}
/**
* @brief Enables or disables the read/write protection (PCROP) of the desired
* sectors, for the first 1 MB of the Flash.
*
* @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices.
*
* @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
* This parameter can be one of the following values:
* @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for
* STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and
* OB_PCROP_Sector5 for STM32F401xx devices.
* @arg OB_PCROP_Sector_All
* @param Newstate: new state of the Write Protection.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_OB_PCROP(OB_PCROP));
assert_param(IS_FUNCTIONAL_STATE(NewState));
status = FLASH_WaitForLastOperation();
if(status == FLASH_COMPLETE)
{
if(NewState != DISABLE)
{
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
}
else
{
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
}
}
}
/**
* @brief Enables or disables the read/write protection (PCROP) of the desired
* sectors
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
* This parameter can be one of the following values:
* @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
* @arg OB_PCROP_Sector_All
* @param Newstate: new state of the Write Protection.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_OB_PCROP(OB_PCROP));
assert_param(IS_FUNCTIONAL_STATE(NewState));
status = FLASH_WaitForLastOperation();
if(status == FLASH_COMPLETE)
{
if(NewState != DISABLE)
{
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
}
else
{
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
}
}
}
/**
* @brief Sets the read protection level.
* @param OB_RDP: specifies the read protection level.
@ -827,7 +1162,7 @@ void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
* @arg OB_RDP_Level_1: Read protection of the memory
* @arg OB_RDP_Level_2: Full chip protection
*
* !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
* /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
*
* @retval None
*/
@ -878,14 +1213,43 @@ void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
if(status == FLASH_COMPLETE)
{
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
/* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx) || defined (STM32F401xx)
/* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
#endif /* STM32F40_41xxx || STM32F401xx */
/* Update User Option Byte */
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
}
}
/**
* @brief Configure the Dual Bank Boot.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @param OB_BOOT: specifies the Dual Bank Boot Option byte.
* This parameter can be one of the following values:
* @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
* @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
* @retval None
*/
void FLASH_OB_BootConfig(uint8_t OB_BOOT)
{
/* Check the parameters */
assert_param(IS_OB_BOOT(OB_BOOT));
/* Set Dual Bank Boot */
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT;
}
/**
* @brief Sets the BOR Level.
* @param OB_BOR: specifies the Option Bytes BOR Reset Level.
@ -951,7 +1315,9 @@ uint16_t FLASH_OB_GetWRP(void)
/**
* @brief Returns the FLASH Write Protection Option Bytes value.
* @note This function can be used only for STM32F427x/437x devices.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @param None
* @retval The FLASH Write Protection Option Bytes value
*/
@ -961,6 +1327,34 @@ uint16_t FLASH_OB_GetWRP1(void)
return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
}
/**
* @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
*
* @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx devices.
*
* @param None
* @retval The FLASH PC Read/Write Protection Option Bytes value
*/
uint16_t FLASH_OB_GetPCROP(void)
{
/* Return the FLASH PC Read/write protection Register value */
return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
}
/**
* @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @param None
* @retval The FLASH PC Read/Write Protection Option Bytes value
*/
uint16_t FLASH_OB_GetPCROP1(void)
{
/* Return the FLASH write protection Register value */
return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
}
/**
* @brief Returns the FLASH Read Protection level.
* @param None
@ -1049,6 +1443,7 @@ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
* @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42/43xxx and STM32F401xx devices)
* @arg FLASH_FLAG_BSY: FLASH Busy flag
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
@ -1079,7 +1474,8 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
* @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42/43xxx and STM32F401xx devices)
* @retval None
*/
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
@ -1095,7 +1491,7 @@ void FLASH_ClearFlag(uint32_t FLASH_FLAG)
* @brief Returns the FLASH Status.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
* FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
* FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
*/
FLASH_Status FLASH_GetStatus(void)
{
@ -1113,19 +1509,26 @@ FLASH_Status FLASH_GetStatus(void)
}
else
{
if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
{
flashstatus = FLASH_ERROR_RD;
}
else
{
flashstatus = FLASH_ERROR_PROGRAM;
}
else
{
if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
{
flashstatus = FLASH_ERROR_OPERATION;
flashstatus = FLASH_ERROR_PROGRAM;
}
else
{
flashstatus = FLASH_COMPLETE;
if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
{
flashstatus = FLASH_ERROR_OPERATION;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
}

104
stm/lib/stm32f4xx_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
@ -52,6 +52,7 @@
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_RD,
FLASH_ERROR_PGS,
FLASH_ERROR_PGP,
FLASH_ERROR_PGA,
@ -78,6 +79,15 @@ typedef enum
#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */
#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */
#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */
#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */
#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */
#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */
#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */
#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
@ -86,8 +96,15 @@ typedef enum
((LATENCY) == FLASH_Latency_4) || \
((LATENCY) == FLASH_Latency_5) || \
((LATENCY) == FLASH_Latency_6) || \
((LATENCY) == FLASH_Latency_7))
((LATENCY) == FLASH_Latency_7) || \
((LATENCY) == FLASH_Latency_8) || \
((LATENCY) == FLASH_Latency_9) || \
((LATENCY) == FLASH_Latency_10) || \
((LATENCY) == FLASH_Latency_11) || \
((LATENCY) == FLASH_Latency_12) || \
((LATENCY) == FLASH_Latency_13) || \
((LATENCY) == FLASH_Latency_14) || \
((LATENCY) == FLASH_Latency_15))
/**
* @}
*/
@ -149,8 +166,20 @@ typedef enum
((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\
((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23))
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
#endif /* STM32F401xx */
/**
* @}
*/
@ -189,6 +218,50 @@ typedef enum
* @}
*/
/** @defgroup Selection_Protection_Mode
* @{
*/
#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
/**
* @}
*/
/** @defgroup Option_Bytes_PC_ReadWrite_Protection
* @{
*/
#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */
#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */
#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */
#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */
#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */
#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */
#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */
#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */
#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */
#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */
#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */
#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */
#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */
#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */
#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_Read_Protection
* @{
*/
@ -246,6 +319,16 @@ typedef enum
/**
* @}
*/
/** @defgroup FLASH_Dual_Boot
* @{
*/
#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
@ -266,12 +349,13 @@ typedef enum
#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */
#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
((FLAG) == FLASH_FLAG_BSY))
((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR))
/**
* @}
*/
@ -346,23 +430,31 @@ void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
/* Option Bytes Programming functions *****************************************/
void FLASH_OB_Unlock(void);
void FLASH_OB_Unlock(void);
void FLASH_OB_Lock(void);
void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
void FLASH_OB_RDPConfig(uint8_t OB_RDP);
void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
void FLASH_OB_BORConfig(uint8_t OB_BOR);
void FLASH_OB_BootConfig(uint8_t OB_BOOT);
FLASH_Status FLASH_OB_Launch(void);
uint8_t FLASH_OB_GetUser(void);
uint16_t FLASH_OB_GetWRP(void);
uint16_t FLASH_OB_GetWRP1(void);
uint16_t FLASH_OB_GetPCROP(void);
uint16_t FLASH_OB_GetPCROP1(void);
FlagStatus FLASH_OB_GetRDP(void);
uint8_t FLASH_OB_GetBOR(void);

96
stm/lib/stm32f4xx_gpio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_gpio.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* + Initialization and Configuration
@ -81,7 +81,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_rcc.h"
@ -120,8 +119,9 @@
/**
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval None
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
@ -169,20 +169,32 @@ void GPIO_DeInit(GPIO_TypeDef* GPIOx)
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
}
else if (GPIOx == GPIOI)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
}
else if (GPIOx == GPIOJ)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE);
}
else
{
if (GPIOx == GPIOI)
if (GPIOx == GPIOK)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE);
}
}
}
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
@ -255,8 +267,9 @@ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
@ -300,8 +313,9 @@ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value.
@ -327,8 +341,9 @@ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Reads the specified GPIO input data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval GPIO input data port value.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
@ -341,8 +356,9 @@ uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
/**
* @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The output port pin value.
@ -368,8 +384,9 @@ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval GPIO output data port value.
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
@ -385,8 +402,9 @@ uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
@ -405,8 +423,9 @@ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
@ -422,8 +441,9 @@ void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* @param BitVal: specifies the value to be written to the selected bit.
@ -451,8 +471,9 @@ void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param PortVal: specifies the value to be written to the port output data register.
* @retval None
*/
@ -466,8 +487,9 @@ void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
/**
* @brief Toggles the specified GPIO pins..
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
@ -497,8 +519,9 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Changes the mapping of the specified pin.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_PinSource: specifies the pin for the Alternate function.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* @param GPIO_AFSelection: selects the pin to used as Alternate function.
@ -524,7 +547,8 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
* @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
* @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
* @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
* @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
* @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.
* @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
* @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
* @arg GPIO_AF_USART1: Connect USART1 pins to AF7
@ -543,10 +567,12 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
* @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
* @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
* @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.
* @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
* @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
* @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
* @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
* @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices.
* @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
* @retval None
*/

92
stm/lib/stm32f4xx_gpio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_gpio.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the GPIO firmware
* library.
******************************************************************************
@ -55,9 +55,10 @@
((PERIPH) == GPIOF) || \
((PERIPH) == GPIOG) || \
((PERIPH) == GPIOH) || \
((PERIPH) == GPIOI))
((PERIPH) == GPIOI) || \
((PERIPH) == GPIOJ) || \
((PERIPH) == GPIOK))
/**
* @brief GPIO Configuration Mode enumeration
*/
@ -87,13 +88,20 @@ typedef enum
*/
typedef enum
{
GPIO_Speed_2MHz = 0x00, /*!< Low speed */
GPIO_Speed_25MHz = 0x01, /*!< Medium speed */
GPIO_Speed_50MHz = 0x02, /*!< Fast speed */
GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
GPIO_Low_Speed = 0x00, /*!< Low speed */
GPIO_Medium_Speed = 0x01, /*!< Medium speed */
GPIO_Fast_Speed = 0x02, /*!< Fast speed */
GPIO_High_Speed = 0x03 /*!< High speed */
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz))
/* Add legacy definition */
#define GPIO_Speed_2MHz GPIO_Low_Speed
#define GPIO_Speed_25MHz GPIO_Medium_Speed
#define GPIO_Speed_50MHz GPIO_Fast_Speed
#define GPIO_Speed_100MHz GPIO_High_Speed
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
/**
* @brief GPIO Configuration PullUp PullDown enumeration
@ -282,6 +290,8 @@ typedef struct
*/
#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
@ -308,6 +318,9 @@ typedef struct
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx Devices) */
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx Devices) */
/**
* @brief AF 10 selection
*/
@ -322,7 +335,13 @@ typedef struct
/**
* @brief AF 12 selection
*/
#if defined (STM32F40_41xxx)
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#endif /* STM32F427_437xx || STM32F429_439xx */
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
@ -332,11 +351,56 @@ typedef struct
*/
#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#if defined (STM32F40_41xxx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
#endif /* STM32F401xx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
@ -357,8 +421,10 @@ typedef struct
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
((AF) == GPIO_AF_FSMC))
((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
((AF) == GPIO_AF_LTDC))
#endif /* STM32F427_437xx || STM32F429_439xx */
/**
* @}
*/

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stm/lib/stm32f4xx_i2c.c Normal file
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711
stm/lib/stm32f4xx_i2c.h Normal file
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@ -0,0 +1,711 @@
/**
******************************************************************************
* @file stm32f4xx_i2c.h
* @author MCD Application Team
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_I2C_H
#define __STM32F4xx_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief I2C Init structure definition
*/
typedef struct
{
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
}I2C_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants
* @{
*/
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
((PERIPH) == I2C2) || \
((PERIPH) == I2C3))
/** @defgroup I2C_Digital_Filter
* @{
*/
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
/**
* @}
*/
/** @defgroup I2C_mode
* @{
*/
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
((MODE) == I2C_Mode_SMBusDevice) || \
((MODE) == I2C_Mode_SMBusHost))
/**
* @}
*/
/** @defgroup I2C_duty_cycle_in_fast_mode
* @{
*/
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
((CYCLE) == I2C_DutyCycle_2))
/**
* @}
*/
/** @defgroup I2C_acknowledgement
* @{
*/
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
((STATE) == I2C_Ack_Disable))
/**
* @}
*/
/** @defgroup I2C_transfer_direction
* @{
*/
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
/**
* @}
*/
/** @defgroup I2C_acknowledged_address
* @{
*/
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/**
* @}
*/
/** @defgroup I2C_registers
* @{
*/
#define I2C_Register_CR1 ((uint8_t)0x00)
#define I2C_Register_CR2 ((uint8_t)0x04)
#define I2C_Register_OAR1 ((uint8_t)0x08)
#define I2C_Register_OAR2 ((uint8_t)0x0C)
#define I2C_Register_DR ((uint8_t)0x10)
#define I2C_Register_SR1 ((uint8_t)0x14)
#define I2C_Register_SR2 ((uint8_t)0x18)
#define I2C_Register_CCR ((uint8_t)0x1C)
#define I2C_Register_TRISE ((uint8_t)0x20)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
((REGISTER) == I2C_Register_CR2) || \
((REGISTER) == I2C_Register_OAR1) || \
((REGISTER) == I2C_Register_OAR2) || \
((REGISTER) == I2C_Register_DR) || \
((REGISTER) == I2C_Register_SR1) || \
((REGISTER) == I2C_Register_SR2) || \
((REGISTER) == I2C_Register_CCR) || \
((REGISTER) == I2C_Register_TRISE))
/**
* @}
*/
/** @defgroup I2C_NACK_position
* @{
*/
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
((POSITION) == I2C_NACKPosition_Current))
/**
* @}
*/
/** @defgroup I2C_SMBus_alert_pin_level
* @{
*/
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
((ALERT) == I2C_SMBusAlert_High))
/**
* @}
*/
/** @defgroup I2C_PEC_position
* @{
*/
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
((POSITION) == I2C_PECPosition_Current))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
/**
* @}
*/
/** @defgroup I2C_flags_definition
* @{
*/
/**
* @brief SR2 register flags
*/
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/**
* @brief SR1 register flags
*/
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
((FLAG) == I2C_FLAG_SB))
/**
* @}
*/
/** @defgroup I2C_Events
* @{
*/
/**
===============================================================================
I2C Master Events (Events grouped in order of communication)
===============================================================================
*/
/**
* @brief Communication start
*
* After sending the START condition (I2C_GenerateSTART() function) the master
* has to wait for this event. It means that the Start condition has been correctly
* released on the I2C bus (the bus is free, no other devices is communicating).
*
*/
/* --EV5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/**
* @brief Address Acknowledge
*
* After checking on EV5 (start condition correctly released on the bus), the
* master sends the address of the slave(s) with which it will communicate
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
* his address. If an acknowledge is sent on the bus, one of the following events will
* be set:
*
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
* event is set.
*
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
* is set
*
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
* function). Then master should wait on EV9. It means that the 10-bit addressing
* header has been correctly sent on the bus. Then master should send the second part of
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
* should wait for event EV6.
*
*/
/* --EV6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/* --EV9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/**
* @brief Communication events
*
* If a communication is established (START condition generated and slave address
* acknowledged) then the master has to check on one of the following events for
* communication procedures:
*
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
* the data received from the slave (I2C_ReceiveData() function).
*
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
* function) then to wait on event EV8 or EV8_2.
* These two events are similar:
* - EV8 means that the data has been written in the data register and is
* being shifted out.
* - EV8_2 means that the data has been physically shifted out and output
* on the bus.
* In most cases, using EV8 is sufficient for the application.
* Using EV8_2 leads to a slower communication but ensure more reliable test.
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
* (before Stop condition generation).
*
* @note In case the user software does not guarantee that this event EV7 is
* managed before the current byte end of transfer, then user may check on EV7
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Master RECEIVER mode -----------------------------*/
/* --EV7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master TRANSMITTER mode --------------------------*/
/* --EV8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* --EV8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/**
===============================================================================
I2C Slave Events (Events grouped in order of communication)
===============================================================================
*/
/**
* @brief Communication start events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a Start condition on the bus (generated by master
* device) followed by the peripheral address. The peripheral generates an ACK
* condition on the bus (if the acknowledge feature is enabled through function
* I2C_AcknowledgeConfig()) and the events listed above are set :
*
* 1) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* 2) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* 3) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* --EV1 (all the events below are variants of EV1) */
/* 1) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* 2) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* 3) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/**
* @brief Communication events
*
* Wait on one of these events when EV1 has already been checked and:
*
* - Slave RECEIVER mode:
* - EV2: When the application is expecting a data byte to be received.
* - EV4: When the application is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EV3: When a byte has been transmitted by the slave and the application is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
* used when the user software doesn't guarantee the EV3 is managed before the
* current byte end of transfer.
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
* shall end (before sending the STOP condition). In this case slave has to stop sending
* data bytes and expect a Stop condition on the bus.
*
* @note In case the user software does not guarantee that the event EV2 is
* managed before the current byte end of transfer, then user may check on EV2
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Slave RECEIVER mode --------------------------*/
/* --EV2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* --EV4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave TRANSMITTER mode -----------------------*/
/* --EV3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/* --EV3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
/*
===============================================================================
End of Events Description
===============================================================================
*/
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
/**
* @}
*/
/** @defgroup I2C_own_address1
* @{
*/
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
/**
* @}
*/
/** @defgroup I2C_clock_speed
* @{
*/
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the I2C configuration to the default reset state *****/
void I2C_DeInit(I2C_TypeDef* I2Cx);
/* Initialization and Configuration functions *********************************/
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
/* Data transfers functions ***************************************************/
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
/* PEC management functions ***************************************************/
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
/* DMA transfers management functions *****************************************/
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
/* Interrupts, events and flags management functions **************************/
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
/*
===============================================================================
I2C State Monitoring Functions
===============================================================================
This I2C driver provides three different ways for I2C state monitoring
depending on the application requirements and constraints:
1. Basic state monitoring (Using I2C_CheckEvent() function)
-----------------------------------------------------------
It compares the status registers (SR1 and SR2) content to a given event
(can be the combination of one or more flags).
It returns SUCCESS if the current status includes the given flags
and returns ERROR if one or more flags are missing in the current status.
- When to use
- This function is suitable for most applications as well as for startup
activity since the events are fully described in the product reference
manual (RM0090).
- It is also suitable for users who need to define their own events.
- Limitations
- If an error occurs (ie. error flags are set besides to the monitored
flags), the I2C_CheckEvent() function may return SUCCESS despite
the communication hold or corrupted real state.
In this case, it is advised to use error interrupts to monitor
the error events and handle them in the interrupt IRQ handler.
Note
For error management, it is advised to use the following functions:
- I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
Where x is the peripheral instance (I2C1, I2C2 ...)
- I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
and/or I2C_GenerateStop() in order to clear the error flag and source
and return to correct communication status.
2. Advanced state monitoring (Using the function I2C_GetLastEvent())
--------------------------------------------------------------------
Using the function I2C_GetLastEvent() which returns the image of both status
registers in a single word (uint32_t) (Status Register 2 value is shifted left
by 16 bits and concatenated to Status Register 1).
- When to use
- This function is suitable for the same applications above but it
allows to overcome the mentioned limitation of I2C_GetFlagStatus()
function.
- The returned value could be compared to events already defined in
this file or to custom values defined by user.
This function is suitable when multiple flags are monitored at the
same time.
- At the opposite of I2C_CheckEvent() function, this function allows
user to choose when an event is accepted (when all events flags are
set and no other flags are set or just when the needed flags are set
like I2C_CheckEvent() function.
- Limitations
- User may need to define his own events.
- Same remark concerning the error management is applicable for this
function if user decides to check only regular communication flags
(and ignores error flags).
3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
-----------------------------------------------------------------------
Using the function I2C_GetFlagStatus() which simply returns the status of
one single flag (ie. I2C_FLAG_RXNE ...).
- When to use
- This function could be used for specific applications or in debug
phase.
- It is suitable when only one flag checking is needed (most I2C
events are monitored through multiple flags).
- Limitations:
- When calling this function, the Status register is accessed.
Some flags are cleared when the status register is accessed.
So checking the status of one Flag, may clear other ones.
- Function may need to be called twice or more in order to monitor
one single event.
*/
/*
===============================================================================
1. Basic state monitoring
===============================================================================
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/*
===============================================================================
2. Advanced state monitoring
===============================================================================
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/*
===============================================================================
3. Flag-based state monitoring
===============================================================================
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F4xx_I2C_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

248
stm/lib/stm32f4xx_pwr.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_pwr.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Backup Domain Access
@ -35,7 +35,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_pwr.h"
#include "stm32f4xx_rcc.h"
@ -72,6 +71,13 @@
#define PMODE_BitNumber 0x0E
#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
/* Alias word address of ODEN bit */
#define ODEN_BitNumber 0x10
#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
/* Alias word address of ODSWEN bit */
#define ODSWEN_BitNumber 0x11
#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
/* --- CSR Register ---*/
@ -87,7 +93,7 @@
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define CR_DS_MASK ((uint32_t)0xFFFFF3FC)
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
@ -284,20 +290,56 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
key, from being accessed. The backup SRAM can be erased only through
the Flash interface when a protection level change from level 1 to
level 0 is requested.
-@- Refer to the description of Read protection (RDP) in the Flash
programming manual.
-@- Refer to the description of Read protection (RDP) in the reference manual.
(+) The main internal regulator can be configured to have a tradeoff between
performance and power consumption when the device does not operate at
the maximum frequency. This is done through PWR_MainRegulatorModeConfig()
function which configure VOS bit in PWR_CR register:
the maximum frequency.
(+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be
configured on the fly through PWR_MainRegulatorModeConfig() function which
configure VOS bit in PWR_CR register:
(++) When this bit is set (Regulator voltage output Scale 1 mode selected)
the System frequency can go up to 168 MHz.
(++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
the System frequency can go up to 144 MHz.
(+) For STM32F42xxx/43xxx Devices, the regulator can be configured through
PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in
PWR_CR register:
which configure VOS[1:0] bits in PWR_CR register:
(++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected)
the System frequency can go up to 168 MHz.
(++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected)
the System frequency can go up to 144 MHz.
(++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected)
the System frequency can go up to 120 MHz.
(+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL
is OFF and the HSI or HSE clock source is selected as system clock.
The new value programmed is active only when the PLL is ON.
When the PLL is OFF, the voltage scale 3 is automatically selected.
Refer to the datasheets for more details.
(+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
2 operating modes available:
(++) Normal mode: The CPU and core logic operate at maximum frequency at a given
voltage scaling (scale 1, scale 2 or scale 3)
(++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
higher frequency than the normal mode for a given voltage scaling (scale 1,
scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and
PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow
the sequence described in Reference manual.
(+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator
supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
and internal SRAM. 2 operating modes are available:
(++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
available when the main regulator or the low power regulator is used in Scale 3 or
low voltage mode.
(++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
available when the main regulator or the low power regulator is in low voltage mode.
This mode is enabled through PWR_UnderDriveCmd() function.
@endverbatim
* @{
*/
@ -327,12 +369,12 @@ void PWR_BackupRegulatorCmd(FunctionalState NewState)
* @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
* System frequency up to 144 MHz.
* @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode,
* System frequency up to 120 MHz
* System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices)
* @retval None
*/
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
@ -349,6 +391,84 @@ void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
PWR->CR = tmpreg;
}
/**
* @brief Enables or disables the Over-Drive.
*
* @note This function can be used only for STM32F42xxx/STM3243xxx devices.
* This mode allows the CPU and the core logic to operate at a higher frequency
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
*
* @note It is recommended to enter or exit Over-drive mode when the application is not running
* critical tasks and when the system clock source is either HSI or HSE.
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
*
* @param NewState: new state of the Over Drive mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_OverDriveCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set/Reset the ODEN bit to enable/disable the Over Drive mode */
*(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Over-Drive switching.
*
* @note This function can be used only for STM32F42xxx/STM3243xxx devices.
*
* @param NewState: new state of the Over Drive switching mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_OverDriveSWCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */
*(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Under-Drive mode.
*
* @note This function can be used only for STM32F42xxx/STM3243xxx devices.
* @note This mode is enabled only with STOP low power mode.
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
* mode is only available when the main regulator or the low power regulator
* is in low voltage mode
*
* @note If the Under-drive mode was enabled, it is automatically disabled after
* exiting Stop mode.
* When the voltage regulator operates in Under-drive mode, an additional
* startup delay is induced when waking up from Stop mode.
*
* @param NewState: new state of the Under Drive mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_UnderDriveCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Set the UDEN[1:0] bits to enable the Under Drive mode */
PWR->CR |= (uint32_t)PWR_CR_UDEN;
}
else
{
/* Reset the UDEN[1:0] bits to disable the Under Drive mode */
PWR->CR &= (uint32_t)(~PWR_CR_UDEN);
}
}
/**
* @}
*/
@ -423,8 +543,10 @@ void PWR_FlashPowerDownCmd(FunctionalState NewState)
the Stop mode using the PWR_FlashPowerDownCmd() function.
(+) Entry:
(++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
function with regulator in LowPower or with Regulator ON.
(++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON)
function with:
(+++) Main regulator ON.
(+++) Low Power regulator ON.
(+) Exit:
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
@ -508,12 +630,12 @@ void PWR_FlashPowerDownCmd(FunctionalState NewState)
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
* is higher although the startup time is reduced.
*
* @param PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_Regulator_ON: STOP mode with regulator ON
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
* @arg PWR_MainRegulator_ON: STOP mode with regulator ON
* @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
@ -530,10 +652,74 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDSR bits */
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_MASK;
/* Set LPDSR bit according to PWR_Regulator value */
/* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Enters in Under-Drive STOP mode.
*
* @note This mode is only available for STM32F42xxx/STM3243xxx devices.
*
* @note This mode can be selected only when the Under-Drive is already active
*
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
*
* @param PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode
* and Flash memory in power-down when the device is in Stop under-drive mode
* @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode
* and Flash memory in power-down when the device is in Stop under-drive mode
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* @retval None
*/
void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_MASK;
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
@ -622,7 +808,13 @@ void PWR_EnterSTANDBYMode(void)
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* scaling output selection is ready.
* @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
* is ready (STM32F42xxx/43xxx devices)
* @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
* switcching is ready (STM32F42xxx/43xxx devices)
* @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
* is enabled in Stop mode (STM32F42xxx/43xxx devices)
* @retval The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
@ -650,14 +842,28 @@ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
* @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices)
* @retval None
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
if (PWR_FLAG != PWR_FLAG_UDRDY)
{
PWR->CR |= PWR_FLAG << 2;
}
else
{
PWR->CSR |= PWR_FLAG_UDRDY;
}
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx) || defined (STM32F401xx)
PWR->CR |= PWR_FLAG << 2;
#endif /* STM32F40_41xxx */
}
/**

60
stm/lib/stm32f4xx_pwr.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_pwr.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
@ -55,7 +55,6 @@
/** @defgroup PWR_PVD_detection_level
* @{
*/
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
@ -77,11 +76,29 @@
/** @defgroup PWR_Regulator_state_in_STOP_mode
* @{
*/
#define PWR_MainRegulator_ON ((uint32_t)0x00000000)
#define PWR_LowPowerRegulator_ON PWR_CR_LPDS
/* --- PWR_Legacy ---*/
#define PWR_Regulator_ON PWR_MainRegulator_ON
#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
((REGULATOR) == PWR_LowPowerRegulator_ON))
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_UnderDrive_mode
* @{
*/
#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS
#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower PWR_CR_LPDS
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/**
* @}
*/
@ -89,22 +106,22 @@
/** @defgroup PWR_STOP_mode_entry
* @{
*/
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_Regulator_Voltage_Scale
* @{
*/
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000)
#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000)
#define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
/**
* @}
*/
@ -112,26 +129,27 @@
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_BRR PWR_CSR_BRR
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
/** @defgroup PWR_Flag_Legacy
* @{
*/
/* --- FLAG Legacy ---*/
#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
/**
* @}
*/
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
((FLAG) == PWR_FLAG_VOSRDY))
((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_UDRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/**
* @}
*/
@ -159,12 +177,16 @@ void PWR_WakeUpPinCmd(FunctionalState NewState);
/* Main and Backup Regulators configuration functions *************************/
void PWR_BackupRegulatorCmd(FunctionalState NewState);
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
void PWR_OverDriveCmd(FunctionalState NewState);
void PWR_OverDriveSWCmd(FunctionalState NewState);
void PWR_UnderDriveCmd(FunctionalState NewState);
/* FLASH Power Down configuration functions ***********************************/
void PWR_FlashPowerDownCmd(FunctionalState NewState);
/* Low Power modes configuration functions ************************************/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
/* Flags management functions *************************************************/

416
stm/lib/stm32f4xx_rcc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rcc.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Reset and clock control (RCC) peripheral:
* + Internal/external clocks, PLL, CSS and MCO configuration
@ -57,7 +57,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_conf.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@ -87,6 +86,10 @@
#define PLLI2SON_BitNumber 0x1A
#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
/* Alias word address of PLLSAION bit */
#define PLLSAION_BitNumber 0x1C
#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
/* --- CFGR Register ---*/
/* Alias word address of I2SSRC bit */
#define CFGR_OFFSET (RCC_OFFSET + 0x08)
@ -172,7 +175,11 @@ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6
the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
(#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
high-quality audio performance on the I2S interface.
high-quality audio performance on the I2S interface or SAI interface in case
of STM32F429x/439x devices.
(#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI
interface and LCD TFT controller available only for STM32F42xxx/43xxx devices.
(#) CSS (Clock security system), once enable and if a HSE clock failure occurs
(HSE used directly or through PLL as System clock source), the System clock
@ -211,8 +218,8 @@ void RCC_DeInit(void)
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON, PLLON and PLLI2S bits */
RCC->CR &= (uint32_t)0xFAF6FFFF;
/* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */
RCC->CR &= (uint32_t)0xEAF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
@ -220,16 +227,17 @@ void RCC_DeInit(void)
/* Reset PLLI2SCFGR register */
RCC->PLLI2SCFGR = 0x20003000;
/* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */
RCC->PLLSAICFGR = 0x24003000;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef STM32F427X
/* Disable Timers clock prescalers selection */
RCC->DCKCFGR = 0x00000000;
#endif /* STM32F427X */
/* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */
RCC->DCKCFGR = 0x00000000;
}
@ -482,9 +490,13 @@ void RCC_PLLCmd(FunctionalState NewState)
*(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
}
#if defined (STM32F40_41xxx) || defined (STM32F401xx)
/**
* @brief Configures the PLLI2S clock multiplication and division factors.
*
* @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx
* or STM32F401xx devices.
*
* @note This function must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* RCC_PLLConfig function )
@ -509,6 +521,44 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
}
#endif /* STM32F40_41xxx || STM32F401xx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
/**
* @brief Configures the PLLI2S clock multiplication and division factors.
*
* @note This function can be used only for STM32F42xxx/43xxx devices
*
* @note This function must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* RCC_PLLConfig function )
*
* @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
* This parameter must be a number between 192 and 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
* output frequency is between 192 and 432 MHz.
*
* @param PLLI2SQ: specifies the division factor for SAI1 clock
* This parameter must be a number between 2 and 15.
*
* @param PLLI2SR: specifies the division factor for I2S clock
* This parameter must be a number between 2 and 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
* @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.
*
* @retval None
*/
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
{
/* Check the parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
}
#endif /* STM32F427_437xx || STM32F429_439xx */
/**
* @brief Enables or disables the PLLI2S.
@ -523,6 +573,53 @@ void RCC_PLLI2SCmd(FunctionalState NewState)
*(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
}
/**
* @brief Configures the PLLSAI clock multiplication and division factors.
*
* @note This function can be used only for STM32F42xxx/43xxx devices
*
* @note This function must be used only when the PLLSAI is disabled.
* @note PLLSAI clock source is common with the main PLL (configured in
* RCC_PLLConfig function )
*
* @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
* This parameter must be a number between 192 and 432.
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
* output frequency is between 192 and 432 MHz.
*
* @param PLLSAIQ: specifies the division factor for SAI1 clock
* This parameter must be a number between 2 and 15.
*
* @param PLLSAIR: specifies the division factor for LTDC clock
* This parameter must be a number between 2 and 7.
*
* @retval None
*/
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
{
/* Check the parameters */
assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
}
/**
* @brief Enables or disables the PLLSAI.
*
* @note This function can be used only for STM32F42xxx/43xxx devices
*
* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
* @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void RCC_PLLSAICmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Clock Security System.
* @note If a failure is detected on the HSE oscillator clock, this oscillator
@ -653,8 +750,33 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
to 48. This clock is derived of the main PLL through PLLQ divider.
(+@) IWDG clock which is always the LSI clock.
(#) The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz
and PCLK1 42 MHz. Depending on the device voltage range, the maximum
(#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency
of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending
on the device voltage range, the maximum frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
+---------------|----------------|----------------|-----------------|-----------------+
(#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz,
PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
@ -662,24 +784,58 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
+-------------------------------------------------------------------------------------+
-@- When VOS bits (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
|7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
|---------------|----------------|----------------|-----------------|-----------------|
|8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
+-------------------------------------------------------------------------------------+
(#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
+-------------------------------------------------------------------------------------+
-@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
(++) when VOS = '0', the maximum value of fHCLK = 144MHz.
(++) when VOS = '1', the maximum value of fHCLK = 168MHz.
[..]
On STM32F42xxx/43xxx devices:
(++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
(++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
(++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
[..]
On STM32F401x devices:
(++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
(++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
@endverbatim
* @{
@ -1071,10 +1227,180 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
*(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
}
/**
* @brief Configures the SAI clock Divider coming from PLLI2S.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @note This function must be called before enabling the PLLI2S.
*
* @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock .
* This parameter must be a number between 1 and 32.
* SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
*
* @retval None
*/
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ));
tmpreg = RCC->DCKCFGR;
/* Clear PLLI2SDIVQ[4:0] bits */
tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ);
/* Set PLLI2SDIVQ values */
tmpreg |= (RCC_PLLI2SDivQ - 1);
/* Store the new value */
RCC->DCKCFGR = tmpreg;
}
/**
* @brief Configures the SAI clock Divider coming from PLLSAI.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @note This function must be called before enabling the PLLSAI.
*
* @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock .
* This parameter must be a number between 1 and 32.
* SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
*
* @retval None
*/
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
tmpreg = RCC->DCKCFGR;
/* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ);
/* Set PLLSAIDIVQ values */
tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
/* Store the new value */
RCC->DCKCFGR = tmpreg;
}
/**
* @brief Configures SAI1BlockA clock source selection.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
* @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
* This parameter can be one of the following values:
* @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
* as SAI1 Block A clock
* @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
* as SAI1 Block A clock
* @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin
* used as SAI1 Block A clock
* @retval None
*/
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
tmpreg = RCC->DCKCFGR;
/* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
tmpreg &= ~RCC_DCKCFGR_SAI1ASRC;
/* Set SAI Block A source selection value */
tmpreg |= RCC_SAIBlockACLKSource;
/* Store the new value */
RCC->DCKCFGR = tmpreg;
}
/**
* @brief Configures SAI1BlockB clock source selection.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
* @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
* This parameter can be one of the following values:
* @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
* as SAI1 Block B clock
* @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
* as SAI1 Block B clock
* @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin
* used as SAI1 Block B clock
* @retval None
*/
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
tmpreg = RCC->DCKCFGR;
/* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */
tmpreg &= ~RCC_DCKCFGR_SAI1BSRC;
/* Set SAI Block B source selection value */
tmpreg |= RCC_SAIBlockBCLKSource;
/* Store the new value */
RCC->DCKCFGR = tmpreg;
}
/**
* @brief Configures the LTDC clock Divider coming from PLLSAI.
*
* @note The LTDC peripheral is only available with STM32F429xx/439xx Devices.
*
* @note This function must be called before enabling the PLLSAI.
*
* @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock .
* This parameter must be a number between 2 and 16.
* LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR
*
* @retval None
*/
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR));
tmpreg = RCC->DCKCFGR;
/* Clear PLLSAIDIVR[2:0] bits */
tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR;
/* Set PLLSAIDIVR values */
tmpreg |= RCC_PLLSAIDivR;
/* Store the new value */
RCC->DCKCFGR = tmpreg;
}
/**
* @brief Configures the Timers clocks prescalers selection.
*
* @note This feature is only available with STM32F427x/437x Devices.
* @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices.
*
* @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
* This parameter can be one of the following values:
* @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is
@ -1112,12 +1438,15 @@ void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
* @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
* @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
* @arg RCC_AHB1Periph_CRC: CRC clock
* @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
* @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
* @arg RCC_AHB1Periph_DMA1: DMA1 clock
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
* @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
* @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
* @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
@ -1183,7 +1512,7 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
* using it.
* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
* This parameter must be: RCC_AHB3Periph_FSMC
*
* or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices)
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1279,6 +1608,8 @@ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
* @arg RCC_APB2Periph_TIM11: TIM11 clock
* @arg RCC_APB2Periph_SPI5: SPI5 clock
* @arg RCC_APB2Periph_SPI6: SPI6 clock
* @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
* @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1311,10 +1642,13 @@ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
* @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
* @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices)
* @arg RCC_AHB1Periph_CRC: CRC clock
* @arg RCC_AHB1Periph_DMA1: DMA1 clock
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
* @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
* @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
*
@ -1371,7 +1705,7 @@ void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
* @brief Forces or releases AHB3 peripheral reset.
* @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
* This parameter must be: RCC_AHB3Periph_FSMC
*
* or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices)
* @param NewState: new state of the specified peripheral reset.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1459,7 +1793,9 @@ void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
* @arg RCC_APB2Periph_TIM10: TIM10 clock
* @arg RCC_APB2Periph_TIM11: TIM11 clock
* @arg RCC_APB2Periph_SPI5: SPI5 clock
* @arg RCC_APB2Periph_SPI6: SPI6 clock
* @arg RCC_APB2Periph_SPI6: SPI6 clock
* @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
* @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
* @param NewState: new state of the specified peripheral reset.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1495,11 +1831,14 @@ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
* @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
* @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
* @arg RCC_AHB1Periph_CRC: CRC clock
* @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
* @arg RCC_AHB1Periph_DMA1: DMA1 clock
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
* @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
* @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
* @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
@ -1565,7 +1904,7 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
* This parameter must be: RCC_AHB3Periph_FSMC
*
* or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1660,7 +1999,9 @@ void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewSt
* @arg RCC_APB2Periph_TIM10: TIM10 clock
* @arg RCC_APB2Periph_TIM11: TIM11 clock
* @arg RCC_APB2Periph_SPI5: SPI5 clock
* @arg RCC_APB2Periph_SPI6: SPI6 clock
* @arg RCC_APB2Periph_SPI6: SPI6 clock
* @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
* @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1706,7 +2047,7 @@ void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewSt
* @arg RCC_IT_HSERDY: HSE ready interrupt
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
*
* @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
* @param NewState: new state of the specified RCC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1736,6 +2077,7 @@ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
* @arg RCC_FLAG_PLLRDY: main PLL clock ready
* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
* @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices)
* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
@ -1807,7 +2149,8 @@ void RCC_ClearFlag(void)
* @arg RCC_IT_HSIRDY: HSI ready interrupt
* @arg RCC_IT_HSERDY: HSE ready interrupt
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
* @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices)
* @arg RCC_IT_CSS: Clock Security System interrupt
* @retval The new state of RCC_IT (SET or RESET).
*/
@ -1841,6 +2184,7 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT)
* @arg RCC_IT_HSERDY: HSE ready interrupt
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
* @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
* @arg RCC_IT_CSS: Clock Security System interrupt
* @retval None
*/

176
stm/lib/stm32f4xx_rcc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rcc.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the RCC firmware library.
******************************************************************************
* @attention
@ -85,6 +85,23 @@ typedef struct
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
((VALUE) == RCC_PLLSAIDivR_Div16))
/**
* @}
@ -147,15 +164,16 @@ typedef struct
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
((IT) == RCC_IT_PLLI2SRDY))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
/**
* @}
@ -255,6 +273,34 @@ typedef struct
* @}
*/
/** @defgroup RCC_SAI_BlockA_Clock_Source
* @{
*/
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
((SOURCE) == RCC_SAIACLKSource_Ext))
/**
* @}
*/
/** @defgroup RCC_SAI_BlockB_Clock_Source
* @{
*/
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
((SOURCE) == RCC_SAIBCLKSource_Ext))
/**
* @}
*/
/** @defgroup RCC_TIM_PRescaler_Selection
* @{
*/
@ -277,7 +323,9 @@ typedef struct
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
@ -287,6 +335,7 @@ typedef struct
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
@ -294,10 +343,9 @@ typedef struct
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81906E00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
@ -319,7 +367,13 @@ typedef struct
/** @defgroup RCC_AHB3_Peripherals
* @{
*/
#if defined (STM32F40_41xxx)
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx */
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
/**
@ -379,10 +433,11 @@ typedef struct
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC880CC) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFC886CC) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
@ -439,6 +494,7 @@ typedef struct
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_BORRST ((uint8_t)0x79)
@ -449,13 +505,13 @@ typedef struct
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_PLLI2SRDY))
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
@ -479,54 +535,68 @@ void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
void RCC_PLLCmd(FunctionalState NewState);
#if defined (STM32F40_41xxx) || defined (STM32F401xx)
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
#endif /* STM32F40_41xxx || STM32F401xx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
#endif /* STM32F41_43xxx */
void RCC_PLLI2SCmd(FunctionalState NewState);
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
void RCC_PLLSAICmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
/* Peripheral clocks configuration functions **********************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}

5
stm/lib/stm32f4xx_rng.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rng.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
* + Initialization and Configuration
@ -53,7 +53,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_rcc.h"

4
stm/lib/stm32f4xx_rng.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rng.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the Random
* Number Generator(RNG) firmware library.
******************************************************************************

5
stm/lib/stm32f4xx_rtc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rtc.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* + Initialization
@ -282,7 +282,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_rtc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver

4
stm/lib/stm32f4xx_rtc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rtc.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************

5
stm/lib/stm32f4xx_sdio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_sdio.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Secure digital input/output interface (SDIO)
* peripheral:
@ -153,7 +153,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_sdio.h"
#include "stm32f4xx_rcc.h"

8
stm/lib/stm32f4xx_sdio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_sdio.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
@ -459,8 +459,8 @@ typedef struct
* @{
*/
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
/**

5
stm/lib/stm32f4xx_spi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_spi.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Serial peripheral interface (SPI):
* + Initialization and Configuration
@ -156,7 +156,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_spi.h"
#include "stm32f4xx_rcc.h"

4
stm/lib/stm32f4xx_spi.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_spi.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
******************************************************************************

53
stm/lib/stm32f4xx_syscfg.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_syscfg.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the SYSCFG peripheral.
*
@verbatim
@ -14,7 +14,10 @@
[..] This driver provides functions for:
(#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
(#) Swapping the internal flash Bank1 and Bank2 this features is only visible for
STM32F42xxx/43xxx devices Devices.
(#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
(#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
@ -44,7 +47,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_syscfg.h"
#include "stm32f4xx_rcc.h"
@ -61,6 +63,12 @@
/* Private define ------------------------------------------------------------*/
/* ------------ RCC registers bit address in the alias region ----------- */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- MEMRMP Register ---*/
/* Alias word address of UFB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
#define UFB_MODE_BitNumber ((uint8_t)0x8)
#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
/* --- PMC Register ---*/
/* Alias word address of MII_RMII_SEL bit */
@ -101,8 +109,10 @@ void SYSCFG_DeInit(void)
* This parameter can be one of the following values:
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices.
* @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
* @retval None
*/
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
@ -113,16 +123,39 @@ void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
}
/**
* @brief Enables or disables the Interal FLASH Bank Swapping.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @param NewState: new state of Interal FLASH Bank swapping.
* This parameter can be one of the following values:
* @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
* @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
* @retval None
*/
void SYSCFG_MemorySwappingBank(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState;
}
/**
* @brief Selects the GPIO pin used as EXTI Line.
* @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
* EXTI lines where x can be (A..I) for STM32F40xx/STM32F41xx
* and STM32F427x/STM32F437x devices.
* EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I)
* for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H)
* for STM32401xx devices.
*
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
* This parameter can be EXTI_PinSourcex where x can be (0..15, except
* for EXTI_PortSourceGPIOI x can be (0..11) for STM32F40xx/STM32F41xx
* and STM32F427x/STM32F437x devices.
* for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx
* and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can
* be (0..7) for STM32F42xxx/43xxx devices.
*
* @retval None
*/

41
stm/lib/stm32f4xx_syscfg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_syscfg.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************
@ -64,7 +64,9 @@
#define EXTI_PortSourceGPIOG ((uint8_t)0x06)
#define EXTI_PortSourceGPIOH ((uint8_t)0x07)
#define EXTI_PortSourceGPIOI ((uint8_t)0x08)
#define EXTI_PortSourceGPIOJ ((uint8_t)0x09)
#define EXTI_PortSourceGPIOK ((uint8_t)0x0A)
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
@ -73,7 +75,9 @@
((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
((PORTSOURCE) == EXTI_PortSourceGPIOI))
((PORTSOURCE) == EXTI_PortSourceGPIOI) || \
((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \
((PORTSOURCE) == EXTI_PortSourceGPIOK))
/**
* @}
@ -126,12 +130,36 @@
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
#if defined (STM32F40_41xxx)
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02)
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FSMC))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM))
#endif /* STM32F401xx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FMC))
#endif /* STM32F427_437xx || STM32F429_439xx */
/**
* @}
@ -157,8 +185,9 @@
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void SYSCFG_DeInit(void);
void SYSCFG_DeInit(void);
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
void SYSCFG_MemorySwappingBank(FunctionalState NewState);
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
void SYSCFG_CompensationCellCmd(FunctionalState NewState);

5
stm/lib/stm32f4xx_tim.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_tim.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the TIM peripheral:
* + TimeBase management
@ -116,7 +116,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_tim.h"
#include "stm32f4xx_rcc.h"

4
stm/lib/stm32f4xx_tim.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_tim.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************

5
stm/lib/stm32f4xx_usart.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_usart.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Universal synchronous asynchronous receiver
* transmitter (USART):
@ -89,7 +89,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm32f4xx_usart.h"
#include "stm32f4xx_rcc.h"

4
stm/lib/stm32f4xx_usart.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_usart.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************

5
stm/lib/stm_misc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file misc.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
*
@ -73,7 +73,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_conf.h"
#include "stm_misc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver

4
stm/lib/stm_misc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file misc.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************

4
stm/lib/system_stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 08-November-2013
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention

7
stm/startup_stm32f40xx.s
View File

@ -2,9 +2,10 @@
******************************************************************************
* @file startup_stm32f40xx.s
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @brief STM32F40xx/41xx Devices vector table for RIDE7 toolchain.
* @version V1.3.0
* @date 08-November-2013
* @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain.
* Same as startup_stm32f40xx.s and maintained for legacy purpose
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,

486
stm/system_stm32f4xx.c
View File

@ -1,13 +1,11 @@
/**
******************************************************************************
* @file system_stm32f4xx.c
* @file Project/STM32F4xx_StdPeriph_Templates/system_stm32f4xx.c
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @version V1.3.0
* @date 13-November-2013
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices,
* and is generated by the clock configuration tool
* stm32f4xx_Clock_Configuration_V1.1.0.xls
* This file contains the system clock configuration for STM32F4xx devices.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
@ -42,7 +40,7 @@
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F40xx/41xx/427x/437x devices
* Supported STM32F40xxx/41xxx devices
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
@ -88,6 +86,100 @@
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
*=============================================================================
* Supported STM32F42xxx/43xxx devices
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 180000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 180000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 360
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Main regulator output voltage | Scale1 mode
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
*=============================================================================
* Supported STM32F401xx devices
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 84000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 84000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 2
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 336
*-----------------------------------------------------------------------------
* PLL_P | 4
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Main regulator output voltage | Scale1 mode
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 2
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
@ -139,9 +231,16 @@
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM324xG_EVAL/STM324x7I_EVAL boards as data memory */
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */
#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
/* #define DATA_IN_ExtSDRAM */
#endif /* STM32F427_437x || STM32F429_439xx */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@ -153,14 +252,27 @@
/************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 8
#define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
#if defined (STM32F40_41xxx)
#define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define PLL_N 360
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
#endif /* STM32F427_437x || STM32F429_439xx */
#if defined (STM32F401xx)
#define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 4
#endif /* STM32F401xx */
/******************************************************************************/
/**
@ -179,7 +291,17 @@
* @{
*/
#if defined (STM32F40_41xxx)
uint32_t SystemCoreClock = 168000000;
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
uint32_t SystemCoreClock = 180000000;
#endif /* STM32F427_437x || STM32F429_439xx */
#if defined (STM32F401xx)
uint32_t SystemCoreClock = 84000000;
#endif /* STM32F401xx */
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
@ -192,9 +314,10 @@
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
@ -236,9 +359,9 @@ void SystemInit(void)
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
@ -372,19 +495,29 @@ static void SetSysClock(void)
if (HSEStatus == (uint32_t)0x01)
{
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
#if defined (STM32F401xx)
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
#endif /* STM32F401xx */
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
@ -397,8 +530,29 @@ static void SetSysClock(void)
{
}
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
PWR->CR |= PWR_CR_ODEN;
while((PWR->CSR & PWR_CSR_ODRDY) == 0)
{
}
PWR->CR |= PWR_CR_ODSWEN;
while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
#endif /* STM32F427_437x || STM32F429_439xx */
#if defined (STM32F40_41xxx)
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx)
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
#endif /* STM32F401xx */
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
@ -435,31 +589,28 @@ void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 |
| PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 |
| PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+
| PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 |
+-------------------| PE12 <-> FSMC_D9 |
| PE13 <-> FSMC_D10 |
| PE14 <-> FSMC_D11 |
| PE15 <-> FSMC_D12 |
+--------------------+
+-------------------+--------------------+------------------+--------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+--------------+
| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
| PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
| PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
| PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
| PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
| PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
| PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
| PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
| | PE15 <-> FMC_D12 |
+------------------+------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcccccccc;
/* Configure PDx pins in Alternate function mode */
@ -471,7 +622,7 @@ void SystemInit_ExtMemCtl(void)
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xcccccccc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
@ -483,7 +634,7 @@ void SystemInit_ExtMemCtl(void)
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
@ -495,7 +646,7 @@ void SystemInit_ExtMemCtl(void)
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
@ -507,24 +658,34 @@ void SystemInit_ExtMemCtl(void)
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
/*-- FMC Configuration ------------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx)
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F40_41xxx */
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 1;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 2;
p.FSMC_BusTurnAroundDuration = 0;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
In case of FSMC configuration
NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
NORSRAMTimingStructure.FSMC_CLKDivision = 0;
NORSRAMTimingStructure.FSMC_DataLatency = 0;
NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
@ -539,11 +700,219 @@ void SystemInit_ExtMemCtl(void)
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
In case of FMC configuration
NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
NORSRAMTimingStructure.FMC_DataSetupTime = 2;
NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
NORSRAMTimingStructure.FMC_CLKDivision = 0;
NORSRAMTimingStructure.FMC_DataLatency = 0;
NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
*/
}
#endif /* DATA_IN_ExtSRAM */
#ifdef DATA_IN_ExtSDRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external SDRAM mounted on STM324x9I_EVAL board
* This SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001FC;
/* Connect PCx pins to FMC Alternate function */
GPIOC->AFR[0] = 0x0000000c;
GPIOC->AFR[1] = 0x00007700;
/* Configure PCx pins in Alternate function mode */
GPIOC->MODER = 0x00a00002;
/* Configure PCx pins speed to 50 MHz */
GPIOC->OSPEEDR = 0x00a00002;
/* Configure PCx pins Output type to push-pull */
GPIOC->OTYPER = 0x00000000;
/* No pull-up, pull-down for PCx pins */
GPIOC->PUPDR = 0x00500000;
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xcccccccc;
GPIOF->AFR[1] = 0xcccccccc;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xcccccccc;
GPIOG->AFR[1] = 0xcccccccc;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xaaaaaaaa;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xaaaaaaaa;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration ------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Configure and enable SDRAM bank1 */
FMC_Bank5_6->SDCR[0] = 0x000039D0;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) & (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) & (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF;
while((tmpreg != 0) & (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) & (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
/*
Bank1_SDRAM is configured as follow:
FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
*/
}
#endif /* DATA_IN_ExtSDRAM */
/**
@ -558,4 +927,3 @@ void SystemInit_ExtMemCtl(void)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/