Merge branch 'master' into nrf52840_usbboot
This commit is contained in:
hathach
commit
b14b28067e
18
.travis.yml
18
.travis.yml
@ -3,6 +3,8 @@ dist: trusty
|
||||
language: c
|
||||
compiler:
|
||||
- gcc
|
||||
git:
|
||||
depth: 1
|
||||
env:
|
||||
- TRAVIS_BOARD=feather_huzzah
|
||||
- TRAVIS_BOARD=arduino_zero
|
||||
@ -46,17 +48,11 @@ notifications:
|
||||
|
||||
before_script:
|
||||
- sudo dpkg --add-architecture i386
|
||||
- |
|
||||
sudo apt-get install -y python3 gcc-multilib pkg-config libffi-dev libffi-dev:i386 qemu-system ||
|
||||
sleep 30 ||
|
||||
sudo apt-get install -y python3 gcc-multilib pkg-config libffi-dev libffi-dev:i386 qemu-system
|
||||
|
||||
- ([[ -z "$TRAVIS_TEST" ]] || sudo apt-get install -y qemu-system)
|
||||
- ([[ -z "$TRAVIS_BOARD" ]] || (wget https://s3.amazonaws.com/adafruit-circuit-python/gcc-arm-embedded_7-2017q4-1~trusty3_amd64.deb && sudo dpkg -i gcc-arm-embedded*_amd64.deb))
|
||||
- ([[ $TRAVIS_TEST != "qemu" ]] || (wget https://s3.amazonaws.com/adafruit-circuit-python/gcc-arm-embedded_7-2017q4-1~trusty3_amd64.deb && sudo dpkg -i gcc-arm-embedded*_amd64.deb))
|
||||
|
||||
# For teensy build
|
||||
- sudo apt-get install realpath
|
||||
# For nrf builds
|
||||
- ([[ $TRAVIS_BOARD != "feather52832" && $TRAVIS_BOARD != "pca10056" ]] || sudo ports/nrf/drivers/bluetooth/download_ble_stack.sh)
|
||||
# For huzzah builds
|
||||
@ -71,7 +67,7 @@ before_script:
|
||||
script:
|
||||
# Build mpy-cross first because other builds depend on it.
|
||||
- echo 'Building mpy-cross' && echo -en 'travis_fold:start:mpy-cross\\r'
|
||||
- make -C mpy-cross
|
||||
- make -C mpy-cross -j2
|
||||
- echo -en 'travis_fold:end:mpy-cross\\r'
|
||||
|
||||
- echo 'Building Adafruit binaries' && echo -en 'travis_fold:start:adafruit-bins\\r'
|
||||
@ -79,13 +75,13 @@ script:
|
||||
- echo -en 'travis_fold:end:adafruit-bins\\r'
|
||||
|
||||
- echo 'Building unix' && echo -en 'travis_fold:start:unix\\r'
|
||||
- ([[ $TRAVIS_TEST != "unix" ]] || make -C ports/unix deplibs)
|
||||
- ([[ $TRAVIS_TEST != "unix" ]] || make -C ports/unix)
|
||||
- ([[ $TRAVIS_TEST != "unix" ]] || make -C ports/unix coverage)
|
||||
- ([[ $TRAVIS_TEST != "unix" ]] || make -C ports/unix deplibs -j2)
|
||||
- ([[ $TRAVIS_TEST != "unix" ]] || make -C ports/unix -j2)
|
||||
- ([[ $TRAVIS_TEST != "unix" ]] || make -C ports/unix coverage -j2)
|
||||
- echo -en 'travis_fold:end:unix\\r'
|
||||
|
||||
- echo 'Building qemu' && echo -en 'travis_fold:start:qemu\\r'
|
||||
- ([[ $TRAVIS_TEST != "qemu" ]] || make -C ports/qemu-arm test)
|
||||
- ([[ $TRAVIS_TEST != "qemu" ]] || make -C ports/qemu-arm test -j2)
|
||||
- echo -en 'travis_fold:end:qemu\\r'
|
||||
|
||||
# run tests without coverage info
|
||||
|
||||
@ -135,7 +135,7 @@ DRESULT disk_read (
|
||||
if (nlr_push(&nlr) == 0) {
|
||||
mp_obj_t ret = mp_call_method_n_kw(2, 0, vfs->readblocks);
|
||||
nlr_pop();
|
||||
if (mp_obj_get_int(ret) != 0) {
|
||||
if (ret != mp_const_none && MP_OBJ_SMALL_INT_VALUE(ret) != 0) {
|
||||
return RES_ERROR;
|
||||
}
|
||||
} else {
|
||||
@ -180,7 +180,7 @@ DRESULT disk_write (
|
||||
if (nlr_push(&nlr) == 0) {
|
||||
mp_obj_t ret = mp_call_method_n_kw(2, 0, vfs->writeblocks);
|
||||
nlr_pop();
|
||||
if (mp_obj_get_int(ret) != 0) {
|
||||
if (ret != mp_const_none && MP_OBJ_SMALL_INT_VALUE(ret) != 0) {
|
||||
return RES_ERROR;
|
||||
}
|
||||
} else {
|
||||
|
||||
@ -2,11 +2,13 @@
|
||||
PYTHON2 ?= $(which python2 || which python2.7)
|
||||
PYTHON3 ?= python3
|
||||
|
||||
# Select the board to build for: if not given on the command line,
|
||||
# then default to PYBV10.
|
||||
BOARD ?= metro_m0_express
|
||||
ifeq ($(wildcard boards/$(BOARD)/.),)
|
||||
$(error Invalid BOARD specified)
|
||||
# Select the board to build for.
|
||||
ifeq ($(BOARD),)
|
||||
$(error You must provide a BOARD parameter)
|
||||
else
|
||||
ifeq ($(wildcard boards/$(BOARD)/.),)
|
||||
$(error Invalid BOARD specified)
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Subproject commit cdde379f78989436590a556cadbc0e201666ee04
|
||||
Subproject commit 88a67f9c83eeb225fe65f596078f8aaa3f6de1ec
|
||||
@ -43,13 +43,14 @@ INC += -I$(BUILD)
|
||||
INC += -I$(BUILD)/genhdr
|
||||
INC += -I./../../lib/cmsis/inc
|
||||
INC += -I./boards/$(BOARD)
|
||||
INC += -I./device
|
||||
INC += -I./device/$(MCU_VARIANT)
|
||||
INC += -I./hal
|
||||
INC += -I./hal/$(MCU_VARIANT)
|
||||
INC += -I./modules/ubluepy
|
||||
INC += -I./modules/random
|
||||
INC += -I./modules/ble
|
||||
INC += -I./nrfx
|
||||
INC += -I./nrfx/hal
|
||||
INC += -I./nrfx/mdk
|
||||
INC += -I./nrfx/drivers/include
|
||||
INC += -I../../lib/mp-readline
|
||||
INC += -I./drivers/bluetooth
|
||||
INC += -I./drivers
|
||||
@ -60,7 +61,7 @@ CFLAGS += -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion
|
||||
CFLAGS += -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
|
||||
CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) $(CFLAGS_MOD)
|
||||
CFLAGS += -fno-strict-aliasing
|
||||
CFLAGS += -fstack-usage
|
||||
CFLAGS += -fstack-usage -fno-builtin -fshort-enums
|
||||
CFLAGS += -fdata-sections -ffunction-sections
|
||||
CFLAGS += -DNRF5_HAL_H='<$(MCU_VARIANT)_hal.h>'
|
||||
CFLAGS += -D__START=main
|
||||
@ -90,18 +91,13 @@ LIBS += -L $(dir $(LIBGCC_FILE_NAME)) -lgcc
|
||||
|
||||
SRC_HAL = $(addprefix hal/,\
|
||||
hal_uart.c \
|
||||
hal_uarte.c \
|
||||
hal_spi.c \
|
||||
hal_spie.c \
|
||||
hal_time.c \
|
||||
hal_timer.c \
|
||||
hal_twi.c \
|
||||
hal_adc.c \
|
||||
hal_adce.c \
|
||||
hal_temp.c \
|
||||
hal_gpio.c \
|
||||
hal_rng.c \
|
||||
hal_pwm.c \
|
||||
)
|
||||
|
||||
SRC_NRFX = $(addprefix nrfx/,\
|
||||
drivers/src/nrfx_spim.c \
|
||||
drivers/src/nrfx_twim.c \
|
||||
)
|
||||
|
||||
SRC_C += \
|
||||
@ -219,6 +215,7 @@ FROZEN_MPY_MPY_FILES := $(addprefix $(BUILD)/,$(FROZEN_MPY_PY_FILES:.py=.mpy))
|
||||
OBJ += $(PY_O) $(SUPERVISOR_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
|
||||
OBJ += $(BUILD)/pins_gen.o
|
||||
OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o))
|
||||
OBJ += $(addprefix $(BUILD)/, $(SRC_NRFX:.c=.o))
|
||||
OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o))
|
||||
OBJ += $(addprefix $(BUILD)/, $(SRC_COMMON_HAL_EXPANDED:.c=.o))
|
||||
OBJ += $(addprefix $(BUILD)/, $(SRC_SHARED_MODULE_EXPANDED:.c=.o))
|
||||
|
||||
@ -1,18 +1,6 @@
|
||||
#ifndef BLUETOOTH_CONF_H__
|
||||
#define BLUETOOTH_CONF_H__
|
||||
|
||||
// SD specific configurations.
|
||||
|
||||
#if (BLUETOOTH_SD == 110)
|
||||
|
||||
#define MICROPY_PY_BLE (1)
|
||||
#define MICROPY_PY_BLE_NUS (0)
|
||||
#define BLUETOOTH_WEBBLUETOOTH_REPL (0)
|
||||
#define MICROPY_PY_UBLUEPY (1)
|
||||
#define MICROPY_PY_UBLUEPY_PERIPHERAL (1)
|
||||
|
||||
#elif (BLUETOOTH_SD == 132 || BLUETOOTH_SD == 140)
|
||||
|
||||
#define MICROPY_PY_BLE (1)
|
||||
#define MICROPY_PY_BLE_NUS (0)
|
||||
#define BLUETOOTH_WEBBLUETOOTH_REPL (0)
|
||||
@ -20,18 +8,4 @@
|
||||
#define MICROPY_PY_UBLUEPY_PERIPHERAL (1)
|
||||
#define MICROPY_PY_UBLUEPY_CENTRAL (1)
|
||||
|
||||
#else
|
||||
#error "SD not supported"
|
||||
#endif
|
||||
|
||||
// Default defines.
|
||||
|
||||
#ifndef MICROPY_PY_BLE
|
||||
#define MICROPY_PY_BLE (0)
|
||||
#endif
|
||||
|
||||
#ifndef MICROPY_PY_BLE_NUS
|
||||
#define MICROPY_PY_BLE_NUS (0)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Scott Shawcroft for Adafruit Industries
|
||||
* Copyright (c) 2018 Artur Pacholec
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
@ -25,24 +26,19 @@
|
||||
*/
|
||||
|
||||
#include "common-hal/analogio/AnalogIn.h"
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "py/gc.h"
|
||||
#include "py/nlr.h"
|
||||
#include "py/runtime.h"
|
||||
#include "py/binary.h"
|
||||
#include "py/mphal.h"
|
||||
#include "shared-bindings/analogio/AnalogIn.h"
|
||||
#include "nrf.h"
|
||||
|
||||
void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self, const mcu_pin_obj_t *pin) {
|
||||
if (!pin->adc_channel) {
|
||||
// No ADC function on that pin
|
||||
#include "nrfx_saadc.h"
|
||||
#include "nrf_gpio.h"
|
||||
|
||||
#define CHANNEL_NO 0
|
||||
|
||||
void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self, const mcu_pin_obj_t *pin) {
|
||||
if (pin->adc_channel == 0)
|
||||
mp_raise_ValueError("Pin does not have ADC capabilities");
|
||||
}
|
||||
|
||||
hal_gpio_cfg_pin(pin->port, pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
|
||||
|
||||
self->pin = pin;
|
||||
}
|
||||
|
||||
@ -51,66 +47,61 @@ bool common_hal_analogio_analogin_deinited(analogio_analogin_obj_t *self) {
|
||||
}
|
||||
|
||||
void common_hal_analogio_analogin_deinit(analogio_analogin_obj_t *self) {
|
||||
if (common_hal_analogio_analogin_deinited(self)) {
|
||||
if (common_hal_analogio_analogin_deinited(self))
|
||||
return;
|
||||
}
|
||||
reset_pin(self->pin->pin);
|
||||
|
||||
nrf_gpio_cfg_default(NRF_GPIO_PIN_MAP(self->pin->port, self->pin->pin));
|
||||
|
||||
self->pin = mp_const_none;
|
||||
}
|
||||
|
||||
void analogin_reset() {
|
||||
}
|
||||
|
||||
uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) {
|
||||
// Something else might have used the ADC in a different way,
|
||||
// so we completely re-initialize it.
|
||||
// Something else might have used the ADC in a different way,
|
||||
// so we completely re-initialize it.
|
||||
|
||||
int16_t value;
|
||||
nrf_saadc_value_t value;
|
||||
|
||||
NRF_SAADC->RESOLUTION = SAADC_RESOLUTION_VAL_14bit;
|
||||
NRF_SAADC->ENABLE = 1;
|
||||
const nrf_saadc_channel_config_t config = {
|
||||
.resistor_p = NRF_SAADC_RESISTOR_DISABLED,
|
||||
.resistor_n = NRF_SAADC_RESISTOR_DISABLED,
|
||||
.gain = NRF_SAADC_GAIN1_6,
|
||||
.reference = NRF_SAADC_REFERENCE_INTERNAL,
|
||||
.acq_time = NRF_SAADC_ACQTIME_3US,
|
||||
.mode = NRF_SAADC_MODE_SINGLE_ENDED,
|
||||
.burst = NRF_SAADC_BURST_DISABLED,
|
||||
.pin_p = self->pin->adc_channel,
|
||||
.pin_n = self->pin->adc_channel,
|
||||
};
|
||||
|
||||
for (int i = 0; i < 8; i++) {
|
||||
NRF_SAADC->CH[i].PSELN = SAADC_CH_PSELP_PSELP_NC;
|
||||
NRF_SAADC->CH[i].PSELP = SAADC_CH_PSELP_PSELP_NC;
|
||||
}
|
||||
nrf_saadc_resolution_set(NRF_SAADC_RESOLUTION_14BIT);
|
||||
nrf_saadc_oversample_set(NRF_SAADC_OVERSAMPLE_DISABLED);
|
||||
nrf_saadc_enable();
|
||||
|
||||
NRF_SAADC->CH[0].CONFIG = ((SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk)
|
||||
| ((SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk)
|
||||
| ((SAADC_CH_CONFIG_GAIN_Gain1_6 << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk)
|
||||
| ((SAADC_CH_CONFIG_REFSEL_Internal << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
|
||||
| ((SAADC_CH_CONFIG_TACQ_3us << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk)
|
||||
| ((SAADC_CH_CONFIG_MODE_SE << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk);
|
||||
NRF_SAADC->CH[0].PSELN = self->pin->adc_channel;
|
||||
NRF_SAADC->CH[0].PSELP = self->pin->adc_channel;
|
||||
for (uint32_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; i++)
|
||||
nrf_saadc_channel_input_set(i, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED);
|
||||
|
||||
nrf_saadc_channel_init(CHANNEL_NO, &config);
|
||||
nrf_saadc_buffer_init(&value, 1);
|
||||
|
||||
NRF_SAADC->RESULT.PTR = (uint32_t)&value;
|
||||
NRF_SAADC->RESULT.MAXCNT = 1;
|
||||
nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
|
||||
while (nrf_saadc_event_check(NRF_SAADC_EVENT_STARTED) == 0);
|
||||
nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED);
|
||||
|
||||
NRF_SAADC->TASKS_START = 0x01UL;
|
||||
nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE);
|
||||
while (nrf_saadc_event_check(NRF_SAADC_EVENT_END) == 0);
|
||||
nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
|
||||
|
||||
while (!NRF_SAADC->EVENTS_STARTED);
|
||||
NRF_SAADC->EVENTS_STARTED = 0x00UL;
|
||||
nrf_saadc_task_trigger(NRF_SAADC_TASK_STOP);
|
||||
while (nrf_saadc_event_check(NRF_SAADC_EVENT_STOPPED) == 0);
|
||||
nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED);
|
||||
|
||||
NRF_SAADC->TASKS_SAMPLE = 0x01UL;
|
||||
nrf_saadc_disable();
|
||||
|
||||
while (!NRF_SAADC->EVENTS_END);
|
||||
NRF_SAADC->EVENTS_END = 0x00UL;
|
||||
if (value < 0)
|
||||
value = 0;
|
||||
|
||||
NRF_SAADC->TASKS_STOP = 0x01UL;
|
||||
|
||||
while (!NRF_SAADC->EVENTS_STOPPED);
|
||||
NRF_SAADC->EVENTS_STOPPED = 0x00UL;
|
||||
|
||||
if (value < 0) {
|
||||
value = 0;
|
||||
}
|
||||
|
||||
NRF_SAADC->ENABLE = 0;
|
||||
|
||||
// Map value to from 14 to 16 bits
|
||||
return (value << 2);
|
||||
// Map value to from 14 to 16 bits
|
||||
return (value << 2);
|
||||
}
|
||||
|
||||
float common_hal_analogio_analogin_get_reference_voltage(analogio_analogin_obj_t *self) {
|
||||
|
||||
@ -36,6 +36,4 @@ typedef struct {
|
||||
const mcu_pin_obj_t * pin;
|
||||
} analogio_analogin_obj_t;
|
||||
|
||||
void analogin_reset(void);
|
||||
|
||||
#endif // MICROPY_INCLUDED_NRF_COMMON_HAL_ANALOGIO_ANALOGIN_H
|
||||
|
||||
@ -24,11 +24,5 @@
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "py/runtime.h"
|
||||
#include "py/mphal.h"
|
||||
#include "common-hal/microcontroller/Pin.h"
|
||||
|
||||
// Pins aren't actually defined here. They are in the board specific directory
|
||||
// such as boards/arduino_zero/pins.c.
|
||||
// such as boards/feather52832/pins.csv
|
||||
|
||||
@ -5,6 +5,7 @@
|
||||
*
|
||||
* Copyright (c) 2016 Sandeep Mistry All right reserved.
|
||||
* Copyright (c) 2017 hathach
|
||||
* Copyright (c) 2018 Artur Pacholec
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
@ -29,67 +30,103 @@
|
||||
#include "py/mperrno.h"
|
||||
#include "py/runtime.h"
|
||||
|
||||
#include "pins.h"
|
||||
#include "nrf.h"
|
||||
#include "nrfx_twim.h"
|
||||
#include "nrf_gpio.h"
|
||||
|
||||
void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda, uint32_t frequency, uint32_t timeout ) {
|
||||
if (scl->pin == sda->pin) {
|
||||
#define INST_NO 0
|
||||
|
||||
static uint8_t twi_error_to_mp(const nrfx_err_t err) {
|
||||
switch (err) {
|
||||
case NRFX_ERROR_DRV_TWI_ERR_ANACK:
|
||||
return MP_ENODEV;
|
||||
case NRFX_ERROR_BUSY:
|
||||
return MP_EBUSY;
|
||||
case NRFX_ERROR_DRV_TWI_ERR_DNACK:
|
||||
case NRFX_ERROR_INVALID_ADDR:
|
||||
return MP_EIO;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) {
|
||||
if (scl->pin == sda->pin)
|
||||
mp_raise_ValueError("Invalid pins");
|
||||
|
||||
const nrfx_twim_t instance = NRFX_TWIM_INSTANCE(INST_NO);
|
||||
self->twim = instance;
|
||||
|
||||
nrfx_twim_config_t config = NRFX_TWIM_DEFAULT_CONFIG;
|
||||
config.scl = NRF_GPIO_PIN_MAP(scl->port, scl->pin);
|
||||
config.sda = NRF_GPIO_PIN_MAP(sda->port, sda->pin);
|
||||
|
||||
// change freq. only if it's less than the default 400K
|
||||
if (frequency < 100000) {
|
||||
config.frequency = NRF_TWIM_FREQ_100K;
|
||||
} else if (frequency < 250000) {
|
||||
config.frequency = NRF_TWIM_FREQ_250K;
|
||||
}
|
||||
|
||||
NRF_GPIO->PIN_CNF[scl->pin] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos)
|
||||
| ((uint32_t)GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos);
|
||||
nrfx_err_t err = nrfx_twim_init(&self->twim, &config, NULL, NULL);
|
||||
|
||||
NRF_GPIO->PIN_CNF[sda->pin] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos)
|
||||
| ((uint32_t)GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos);
|
||||
|
||||
// 1 for I2C, 0 for SPI
|
||||
self->twi = NRF_TWIM1;
|
||||
|
||||
if ( frequency < 100000 ) {
|
||||
self->twi->FREQUENCY = TWIM_FREQUENCY_FREQUENCY_K100;
|
||||
}else if ( frequency < 250000 ) {
|
||||
self->twi->FREQUENCY = TWIM_FREQUENCY_FREQUENCY_K250;
|
||||
}else {
|
||||
self->twi->FREQUENCY = TWIM_FREQUENCY_FREQUENCY_K400;
|
||||
// A soft reset doesn't uninit the driver so we might end up with a invalid state
|
||||
if (err == NRFX_ERROR_INVALID_STATE) {
|
||||
nrfx_twim_uninit(&self->twim);
|
||||
err = nrfx_twim_init(&self->twim, &config, NULL, NULL);
|
||||
}
|
||||
|
||||
self->twi->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
|
||||
|
||||
self->twi->PSEL.SCL = scl->pin;
|
||||
self->twi->PSEL.SDA = sda->pin;
|
||||
if (err != NRFX_SUCCESS)
|
||||
mp_raise_OSError(MP_EIO);
|
||||
|
||||
self->inited = true;
|
||||
}
|
||||
|
||||
bool common_hal_busio_i2c_deinited(busio_i2c_obj_t *self) {
|
||||
return self->twi->ENABLE == 0;
|
||||
return !self->inited;
|
||||
}
|
||||
|
||||
void common_hal_busio_i2c_deinit(busio_i2c_obj_t *self) {
|
||||
if (common_hal_busio_i2c_deinited(self)) {
|
||||
if (common_hal_busio_i2c_deinited(self))
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t scl_pin = self->twi->PSEL.SCL;
|
||||
uint8_t sda_pin = self->twi->PSEL.SDA;
|
||||
nrfx_twim_uninit(&self->twim);
|
||||
|
||||
self->twi->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos);
|
||||
self->twi->PSEL.SCL = (TWIM_PSEL_SCL_CONNECT_Disconnected << TWIM_PSEL_SCL_CONNECT_Pos);
|
||||
self->twi->PSEL.SDA = (TWIM_PSEL_SDA_CONNECT_Disconnected << TWIM_PSEL_SDA_CONNECT_Pos);
|
||||
|
||||
reset_pin(scl_pin);
|
||||
reset_pin(sda_pin);
|
||||
self->inited = false;
|
||||
}
|
||||
|
||||
// nrfx_twim_tx doesn't support 0-length data so we fall back to the hal API
|
||||
bool common_hal_busio_i2c_probe(busio_i2c_obj_t *self, uint8_t addr) {
|
||||
// Write no data when just probing
|
||||
return 0 == common_hal_busio_i2c_write(self, addr, NULL, 0, true);
|
||||
NRF_TWIM_Type *reg = self->twim.p_twim;
|
||||
bool found = true;
|
||||
|
||||
nrfx_twim_enable(&self->twim);
|
||||
|
||||
nrf_twim_address_set(reg, addr);
|
||||
nrf_twim_tx_buffer_set(reg, NULL, 0);
|
||||
|
||||
nrf_twim_task_trigger(reg, NRF_TWIM_TASK_RESUME);
|
||||
|
||||
nrf_twim_task_trigger(reg, NRF_TWIM_TASK_STARTTX);
|
||||
while (nrf_twim_event_check(reg, NRF_TWIM_EVENT_TXSTARTED) == 0 &&
|
||||
nrf_twim_event_check(reg, NRF_TWIM_EVENT_ERROR) == 0);
|
||||
nrf_twim_event_clear(reg, NRF_TWIM_EVENT_TXSTARTED);
|
||||
|
||||
nrf_twim_task_trigger(reg, NRF_TWIM_TASK_STOP);
|
||||
while (nrf_twim_event_check(reg, NRF_TWIM_EVENT_STOPPED) == 0);
|
||||
nrf_twim_event_clear(reg, NRF_TWIM_EVENT_STOPPED);
|
||||
|
||||
if (nrf_twim_event_check(reg, NRF_TWIM_EVENT_ERROR)) {
|
||||
nrf_twim_event_clear(reg, NRF_TWIM_EVENT_ERROR);
|
||||
|
||||
nrf_twim_errorsrc_get_and_clear(reg);
|
||||
found = false;
|
||||
}
|
||||
|
||||
nrfx_twim_disable(&self->twim);
|
||||
|
||||
return found;
|
||||
}
|
||||
|
||||
bool common_hal_busio_i2c_try_lock(busio_i2c_obj_t *self) {
|
||||
@ -112,96 +149,23 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) {
|
||||
}
|
||||
|
||||
uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, const uint8_t *data, size_t len, bool stopBit) {
|
||||
NRF_TWIM_Type* twi = self->twi;
|
||||
if(len == 0)
|
||||
return common_hal_busio_i2c_probe(self, addr) ? 0 : MP_ENODEV;
|
||||
|
||||
twi->ADDRESS = addr;
|
||||
twi->TASKS_RESUME = 1;
|
||||
nrfx_twim_enable(&self->twim);
|
||||
const nrfx_err_t err = nrfx_twim_tx(&self->twim, addr, data, len, !stopBit);
|
||||
nrfx_twim_disable(&self->twim);
|
||||
|
||||
twi->TXD.PTR = (uint32_t) data;
|
||||
twi->TXD.MAXCNT = len;
|
||||
|
||||
twi->TASKS_STARTTX = 1;
|
||||
|
||||
// Wait for TX started
|
||||
while(!twi->EVENTS_TXSTARTED && !twi->EVENTS_ERROR) {}
|
||||
twi->EVENTS_TXSTARTED = 0;
|
||||
|
||||
// Wait for TX complete
|
||||
if ( len )
|
||||
{
|
||||
while(!twi->EVENTS_LASTTX && !twi->EVENTS_ERROR) {}
|
||||
twi->EVENTS_LASTTX = 0x0UL;
|
||||
}
|
||||
|
||||
if (stopBit || twi->EVENTS_ERROR)
|
||||
{
|
||||
twi->TASKS_STOP = 0x1UL;
|
||||
while(!twi->EVENTS_STOPPED);
|
||||
twi->EVENTS_STOPPED = 0x0UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
twi->TASKS_SUSPEND = 0x1UL;
|
||||
while(!twi->EVENTS_SUSPENDED);
|
||||
twi->EVENTS_SUSPENDED = 0x0UL;
|
||||
}
|
||||
|
||||
if (twi->EVENTS_ERROR)
|
||||
{
|
||||
twi->EVENTS_ERROR = 0x0UL;
|
||||
uint32_t error = twi->ERRORSRC;
|
||||
twi->ERRORSRC = error;
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return twi_error_to_mp(err);
|
||||
}
|
||||
|
||||
uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, uint8_t *data, size_t len) {
|
||||
NRF_TWIM_Type* twi = self->twi;
|
||||
if(len == 0)
|
||||
return 0;
|
||||
|
||||
if(len == 0) return 0;
|
||||
bool stopBit = true; // should be a parameter
|
||||
nrfx_twim_enable(&self->twim);
|
||||
const nrfx_err_t err = nrfx_twim_rx(&self->twim, addr, data, len);
|
||||
nrfx_twim_disable(&self->twim);
|
||||
|
||||
twi->ADDRESS = addr;
|
||||
twi->TASKS_RESUME = 0x1UL;
|
||||
|
||||
twi->RXD.PTR = (uint32_t) data;
|
||||
twi->RXD.MAXCNT = len;
|
||||
|
||||
twi->TASKS_STARTRX = 0x1UL;
|
||||
|
||||
while(!twi->EVENTS_RXSTARTED && !twi->EVENTS_ERROR);
|
||||
twi->EVENTS_RXSTARTED = 0x0UL;
|
||||
|
||||
while(!twi->EVENTS_LASTRX && !twi->EVENTS_ERROR);
|
||||
twi->EVENTS_LASTRX = 0x0UL;
|
||||
|
||||
if (stopBit || twi->EVENTS_ERROR)
|
||||
{
|
||||
twi->TASKS_STOP = 0x1UL;
|
||||
while(!twi->EVENTS_STOPPED);
|
||||
twi->EVENTS_STOPPED = 0x0UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
twi->TASKS_SUSPEND = 0x1UL;
|
||||
while(!twi->EVENTS_SUSPENDED);
|
||||
twi->EVENTS_SUSPENDED = 0x0UL;
|
||||
}
|
||||
|
||||
if (twi->EVENTS_ERROR)
|
||||
{
|
||||
twi->EVENTS_ERROR = 0x0UL;
|
||||
uint32_t error = twi->ERRORSRC;
|
||||
twi->ERRORSRC = error;
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
// number of byte read
|
||||
// (void) _p_twim->RXD.AMOUNT;
|
||||
|
||||
return 0;
|
||||
return twi_error_to_mp(err);
|
||||
}
|
||||
|
||||
@ -27,16 +27,15 @@
|
||||
#ifndef MICROPY_INCLUDED_NRF_COMMON_HAL_BUSIO_I2C_H
|
||||
#define MICROPY_INCLUDED_NRF_COMMON_HAL_BUSIO_I2C_H
|
||||
|
||||
#include "common-hal/microcontroller/Pin.h"
|
||||
|
||||
//#include "hal/include/hal_i2c_m_sync.h"
|
||||
#include "nrfx_twim.h"
|
||||
|
||||
#include "py/obj.h"
|
||||
|
||||
typedef struct {
|
||||
mp_obj_base_t base;
|
||||
volatile bool has_lock;
|
||||
NRF_TWIM_Type* twi;
|
||||
nrfx_twim_t twim;
|
||||
bool inited;
|
||||
bool has_lock;
|
||||
} busio_i2c_obj_t;
|
||||
|
||||
#endif // MICROPY_INCLUDED_NRF_COMMON_HAL_BUSIO_I2C_H
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
* Copyright (c) 2015 Arduino LLC
|
||||
* Copyright (c) 2016 Sandeep Mistry All right reserved.
|
||||
* Copyright (c) 2017 hathach
|
||||
* Copyright (c) 2018 Artur Pacholec
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
@ -19,94 +20,111 @@
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include "shared-bindings/busio/SPI.h"
|
||||
#include "py/mperrno.h"
|
||||
#include "py/runtime.h"
|
||||
|
||||
#include "nrf.h"
|
||||
#include "pins.h"
|
||||
#include "nrfx_spim.h"
|
||||
#include "nrf_gpio.h"
|
||||
|
||||
// Convert frequency to clock-speed-dependent value. Return 0 if out of range.
|
||||
static uint32_t baudrate_to_reg(const uint32_t baudrate) {
|
||||
uint32_t value;
|
||||
#if NRFX_SPIM3_ENABLED
|
||||
#define INST_NO 3
|
||||
#else
|
||||
#define INST_NO 2
|
||||
#endif
|
||||
|
||||
if (baudrate <= 125000) {
|
||||
value = SPI_FREQUENCY_FREQUENCY_K125;
|
||||
} else if (baudrate <= 250000) {
|
||||
value = SPI_FREQUENCY_FREQUENCY_K250;
|
||||
} else if (baudrate <= 500000) {
|
||||
value = SPI_FREQUENCY_FREQUENCY_K500;
|
||||
} else if (baudrate <= 1000000) {
|
||||
value = SPI_FREQUENCY_FREQUENCY_M1;
|
||||
} else if (baudrate <= 2000000) {
|
||||
value = SPI_FREQUENCY_FREQUENCY_M2;
|
||||
} else if (baudrate <= 4000000) {
|
||||
value = SPI_FREQUENCY_FREQUENCY_M4;
|
||||
} else {
|
||||
value = SPI_FREQUENCY_FREQUENCY_M8;
|
||||
}
|
||||
// Convert frequency to clock-speed-dependent value
|
||||
static nrf_spim_frequency_t baudrate_to_spim_frequency(const uint32_t baudrate) {
|
||||
if (baudrate <= 125000)
|
||||
return NRF_SPIM_FREQ_125K;
|
||||
|
||||
return value;
|
||||
if (baudrate <= 250000)
|
||||
return NRF_SPIM_FREQ_250K;
|
||||
|
||||
if (baudrate <= 500000)
|
||||
return NRF_SPIM_FREQ_500K;
|
||||
|
||||
if (baudrate <= 1000000)
|
||||
return NRF_SPIM_FREQ_1M;
|
||||
|
||||
if (baudrate <= 2000000)
|
||||
return NRF_SPIM_FREQ_2M;
|
||||
|
||||
if (baudrate <= 4000000)
|
||||
return NRF_SPIM_FREQ_4M;
|
||||
|
||||
if (baudrate <= 8000000)
|
||||
return NRF_SPIM_FREQ_8M;
|
||||
|
||||
#ifdef SPIM_FREQUENCY_FREQUENCY_M16
|
||||
if (baudrate <= 16000000)
|
||||
return NRF_SPIM_FREQ_16M;
|
||||
#endif
|
||||
|
||||
#ifdef SPIM_FREQUENCY_FREQUENCY_M32
|
||||
return NRF_SPIM_FREQ_32M;
|
||||
#else
|
||||
return NRF_SPIM_FREQ_8M;
|
||||
#endif
|
||||
}
|
||||
|
||||
void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi, const mcu_pin_obj_t * miso) {
|
||||
const nrfx_spim_t instance = NRFX_SPIM_INSTANCE(INST_NO);
|
||||
self->spim = instance;
|
||||
|
||||
// 1 for I2C, 0 for SPI
|
||||
self->spi = NRF_SPI0;
|
||||
nrfx_spim_config_t config = NRFX_SPIM_DEFAULT_CONFIG;
|
||||
config.frequency = NRF_SPIM_FREQ_8M;
|
||||
|
||||
self->spi->PSELSCK = clock->pin;
|
||||
self->spi->PSELMOSI = mosi->pin;
|
||||
self->spi->PSELMISO = miso->pin;
|
||||
config.sck_pin = NRF_GPIO_PIN_MAP(clock->port, clock->pin);
|
||||
|
||||
if (mosi != (mcu_pin_obj_t*)&mp_const_none_obj)
|
||||
config.mosi_pin = NRF_GPIO_PIN_MAP(mosi->port, mosi->pin);
|
||||
|
||||
#if NRF52840_XXAA
|
||||
self->spi->PSELSCK |= (clock->port << SPI_PSEL_SCK_PORT_Pos);
|
||||
self->spi->PSELMOSI |= (mosi->port << SPI_PSEL_MOSI_PORT_Pos);
|
||||
self->spi->PSELMISO |= (miso->port << SPI_PSEL_MISO_PORT_Pos);
|
||||
#endif
|
||||
if (miso != (mcu_pin_obj_t*)&mp_const_none_obj)
|
||||
config.miso_pin = NRF_GPIO_PIN_MAP(miso->port, miso->pin);
|
||||
|
||||
nrfx_err_t err = nrfx_spim_init(&self->spim, &config, NULL, NULL);
|
||||
|
||||
// A soft reset doesn't uninit the driver so we might end up with a invalid state
|
||||
if (err == NRFX_ERROR_INVALID_STATE) {
|
||||
nrfx_spim_uninit(&self->spim);
|
||||
err = nrfx_spim_init(&self->spim, &config, NULL, NULL);
|
||||
}
|
||||
|
||||
if (err != NRFX_SUCCESS)
|
||||
mp_raise_OSError(MP_EIO);
|
||||
|
||||
self->inited = true;
|
||||
}
|
||||
|
||||
bool common_hal_busio_spi_deinited(busio_spi_obj_t *self) {
|
||||
return self->spi == NULL;
|
||||
return !self->inited;
|
||||
}
|
||||
|
||||
void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
|
||||
if (common_hal_busio_spi_deinited(self)) {
|
||||
if (common_hal_busio_spi_deinited(self))
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef NRF52840_XXAA
|
||||
self->spi->PSEL.SCK = SPI_PSEL_SCK_CONNECT_Disconnected;
|
||||
self->spi->PSEL.MOSI = SPI_PSEL_MOSI_CONNECT_Disconnected;
|
||||
self->spi->PSEL.MISO = SPI_PSEL_MISO_CONNECT_Disconnected;
|
||||
#else
|
||||
self->spi->PSELSCK = SPI_PSEL_SCK_PSELSCK_Disconnected;
|
||||
self->spi->PSELMOSI = SPI_PSEL_MOSI_PSELMOSI_Disconnected;
|
||||
self->spi->PSELMISO = SPI_PSEL_MISO_PSELMISO_Disconnected;
|
||||
#endif
|
||||
// reset_pin(self->clock_pin);
|
||||
// reset_pin(self->MOSI_pin);
|
||||
// reset_pin(self->MISO_pin);
|
||||
nrfx_spim_uninit(&self->spim);
|
||||
|
||||
self->spi = NULL;
|
||||
self->inited = false;
|
||||
}
|
||||
|
||||
bool common_hal_busio_spi_configure(busio_spi_obj_t *self, uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
|
||||
// nrf52 does not support 16 bit
|
||||
if ( bits != 8 ) return false;
|
||||
if (bits != 8)
|
||||
return false;
|
||||
|
||||
self->spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
|
||||
nrf_spim_frequency_set(self->spim.p_reg, baudrate_to_spim_frequency(baudrate));
|
||||
|
||||
uint32_t config = (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos);
|
||||
nrf_spim_mode_t mode = NRF_SPIM_MODE_0;
|
||||
if (polarity) {
|
||||
mode = (phase) ? NRF_SPIM_MODE_3 : NRF_SPIM_MODE_2;
|
||||
} else {
|
||||
mode = (phase) ? NRF_SPIM_MODE_1 : NRF_SPIM_MODE_0;
|
||||
}
|
||||
|
||||
config |= ((polarity ? SPI_CONFIG_CPOL_ActiveLow : SPI_CONFIG_CPOL_ActiveHigh) << SPI_CONFIG_CPOL_Pos);
|
||||
config |= ((phase ? SPI_CONFIG_CPHA_Trailing : SPI_CONFIG_CPHA_Leading ) << SPI_CONFIG_CPHA_Pos);
|
||||
|
||||
self->spi->CONFIG = config;
|
||||
self->spi->FREQUENCY = baudrate_to_reg(baudrate);
|
||||
|
||||
self->spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
|
||||
nrf_spim_configure(self->spim.p_reg, mode, NRF_SPIM_BIT_ORDER_MSB_FIRST);
|
||||
|
||||
return true;
|
||||
}
|
||||
@ -131,87 +149,59 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
|
||||
}
|
||||
|
||||
bool common_hal_busio_spi_write(busio_spi_obj_t *self, const uint8_t *data, size_t len) {
|
||||
if (len == 0) {
|
||||
return true;
|
||||
}
|
||||
if (len == 0)
|
||||
return true;
|
||||
|
||||
while (len)
|
||||
{
|
||||
self->spi->TXD = *data;
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(data, len);
|
||||
const nrfx_err_t err = nrfx_spim_xfer(&self->spim, &xfer, 0);
|
||||
|
||||
while(!self->spi->EVENTS_READY);
|
||||
|
||||
(void) self->spi->RXD;
|
||||
data++;
|
||||
len--;
|
||||
|
||||
self->spi->EVENTS_READY = 0x0UL;
|
||||
}
|
||||
|
||||
return true;
|
||||
return (err == NRFX_SUCCESS);
|
||||
}
|
||||
|
||||
bool common_hal_busio_spi_read(busio_spi_obj_t *self, uint8_t *data, size_t len, uint8_t write_value) {
|
||||
if (len == 0) {
|
||||
return true;
|
||||
}
|
||||
if (len == 0)
|
||||
return true;
|
||||
|
||||
while (len)
|
||||
{
|
||||
self->spi->TXD = write_value;
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_RX(data, len);
|
||||
const nrfx_err_t err = nrfx_spim_xfer(&self->spim, &xfer, 0);
|
||||
|
||||
while(!self->spi->EVENTS_READY);
|
||||
|
||||
*data = self->spi->RXD;
|
||||
|
||||
data++;
|
||||
len--;
|
||||
|
||||
self->spi->EVENTS_READY = 0x0UL;
|
||||
}
|
||||
|
||||
return true;
|
||||
return (err == NRFX_SUCCESS);
|
||||
}
|
||||
|
||||
bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, uint8_t *data_out, uint8_t *data_in, size_t len) {
|
||||
if (len == 0) {
|
||||
return true;
|
||||
}
|
||||
if (len == 0)
|
||||
return true;
|
||||
|
||||
while (len)
|
||||
{
|
||||
self->spi->TXD = *data_out;
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(data_out, len, data_in, len);
|
||||
const nrfx_err_t err = nrfx_spim_xfer(&self->spim, &xfer, 0);
|
||||
|
||||
while(!self->spi->EVENTS_READY);
|
||||
|
||||
*data_in = self->spi->RXD;
|
||||
|
||||
data_out++;
|
||||
data_in++;
|
||||
len--;
|
||||
|
||||
self->spi->EVENTS_READY = 0x0UL;
|
||||
}
|
||||
|
||||
return true;
|
||||
return (err == NRFX_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) {
|
||||
switch (self->spi->FREQUENCY) {
|
||||
case SPI_FREQUENCY_FREQUENCY_K125:
|
||||
switch (self->spim.p_reg->FREQUENCY) {
|
||||
case NRF_SPIM_FREQ_125K:
|
||||
return 125000;
|
||||
case SPI_FREQUENCY_FREQUENCY_K250:
|
||||
case NRF_SPIM_FREQ_250K:
|
||||
return 250000;
|
||||
case SPI_FREQUENCY_FREQUENCY_K500:
|
||||
case NRF_SPIM_FREQ_500K:
|
||||
return 500000;
|
||||
case SPI_FREQUENCY_FREQUENCY_M1:
|
||||
case NRF_SPIM_FREQ_1M:
|
||||
return 1000000;
|
||||
case SPI_FREQUENCY_FREQUENCY_M2:
|
||||
case NRF_SPIM_FREQ_2M:
|
||||
return 2000000;
|
||||
case SPI_FREQUENCY_FREQUENCY_M4:
|
||||
case NRF_SPIM_FREQ_4M:
|
||||
return 4000000;
|
||||
case SPI_FREQUENCY_FREQUENCY_M8:
|
||||
case NRF_SPIM_FREQ_8M:
|
||||
return 8000000;
|
||||
#ifdef SPIM_FREQUENCY_FREQUENCY_M16
|
||||
case NRF_SPIM_FREQ_16M:
|
||||
return 16000000;
|
||||
#endif
|
||||
#ifdef SPIM_FREQUENCY_FREQUENCY_M32
|
||||
case NRF_SPIM_FREQ_32M:
|
||||
return 32000000;
|
||||
#endif
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -27,15 +27,13 @@
|
||||
#ifndef MICROPY_INCLUDED_NRF_COMMON_HAL_BUSIO_SPI_H
|
||||
#define MICROPY_INCLUDED_NRF_COMMON_HAL_BUSIO_SPI_H
|
||||
|
||||
#include "common-hal/microcontroller/Pin.h"
|
||||
|
||||
//#include "hal/include/hal_spi_m_sync.h"
|
||||
|
||||
#include "nrfx_spim.h"
|
||||
#include "py/obj.h"
|
||||
|
||||
typedef struct {
|
||||
mp_obj_base_t base;
|
||||
NRF_SPI_Type *spi;
|
||||
nrfx_spim_t spim;
|
||||
bool inited;
|
||||
bool has_lock;
|
||||
} busio_spi_obj_t;
|
||||
|
||||
|
||||
@ -27,14 +27,15 @@
|
||||
#include "common-hal/microcontroller/Pin.h"
|
||||
#include "common-hal/microcontroller/Processor.h"
|
||||
|
||||
|
||||
#include "shared-bindings/microcontroller/__init__.h"
|
||||
#include "shared-bindings/microcontroller/Pin.h"
|
||||
#include "shared-bindings/microcontroller/Processor.h"
|
||||
|
||||
// TODO porting common_hal_mcu
|
||||
#include "supervisor/filesystem.h"
|
||||
#include "nrfx_glue.h"
|
||||
|
||||
void common_hal_mcu_delay_us(uint32_t delay) {
|
||||
// os_delay_us(delay);
|
||||
NRFX_DELAY_US(delay);
|
||||
}
|
||||
|
||||
void common_hal_mcu_disable_interrupts() {
|
||||
@ -48,7 +49,8 @@ void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) {
|
||||
}
|
||||
|
||||
void common_hal_mcu_reset(void) {
|
||||
// TODO: see atmel-samd for functionality
|
||||
filesystem_flush();
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
// The singleton microcontroller.Processor object, bound to microcontroller.cpu
|
||||
|
||||
@ -28,13 +28,12 @@
|
||||
#include "py/mpconfig.h"
|
||||
#include "py/objstr.h"
|
||||
#include "py/objtuple.h"
|
||||
#include "py/qstr.h"
|
||||
|
||||
#ifdef BLUETOOTH_SD
|
||||
#include "nrf_sdm.h"
|
||||
#endif
|
||||
|
||||
#include "nrf.h"
|
||||
#include "nrf_rng.h"
|
||||
|
||||
STATIC const qstr os_uname_info_fields[] = {
|
||||
MP_QSTR_sysname, MP_QSTR_nodename,
|
||||
@ -47,7 +46,6 @@ STATIC const MP_DEFINE_STR_OBJ(os_uname_info_release_obj, MICROPY_VERSION_STRING
|
||||
STATIC const MP_DEFINE_STR_OBJ(os_uname_info_version_obj, MICROPY_GIT_TAG " on " MICROPY_BUILD_DATE);
|
||||
STATIC const MP_DEFINE_STR_OBJ(os_uname_info_machine_obj, MICROPY_HW_BOARD_NAME " with " MICROPY_HW_MCU_NAME);
|
||||
|
||||
|
||||
STATIC MP_DEFINE_ATTRTUPLE(
|
||||
os_uname_info_obj,
|
||||
os_uname_info_fields,
|
||||
@ -63,28 +61,26 @@ mp_obj_t common_hal_os_uname(void) {
|
||||
return (mp_obj_t)&os_uname_info_obj;
|
||||
}
|
||||
|
||||
bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) {
|
||||
bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) {
|
||||
#ifdef BLUETOOTH_SD
|
||||
uint8_t sd_en = 0;
|
||||
(void) sd_softdevice_is_enabled(&sd_en);
|
||||
|
||||
if (sd_en) {
|
||||
return NRF_SUCCESS == sd_rand_application_vector_get(buffer,length);
|
||||
}
|
||||
if (sd_en)
|
||||
return NRF_SUCCESS == sd_rand_application_vector_get(buffer, length);
|
||||
#endif
|
||||
|
||||
NRF_RNG->EVENTS_VALRDY = 0;
|
||||
NRF_RNG->TASKS_START = 1;
|
||||
nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
|
||||
nrf_rng_task_trigger(NRF_RNG_TASK_START);
|
||||
|
||||
for (uint32_t i = 0; i < length; i++) {
|
||||
while (NRF_RNG->EVENTS_VALRDY == 0) {
|
||||
;
|
||||
}
|
||||
NRF_RNG->EVENTS_VALRDY = 0;
|
||||
buffer[i] = (uint8_t) NRF_RNG->VALUE;
|
||||
while (nrf_rng_event_get(NRF_RNG_EVENT_VALRDY) == 0);
|
||||
nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
|
||||
|
||||
buffer[i] = nrf_rng_random_value_get();
|
||||
}
|
||||
|
||||
NRF_RNG->TASKS_STOP = 1;
|
||||
nrf_rng_task_trigger(NRF_RNG_TASK_STOP);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -28,16 +28,19 @@
|
||||
|
||||
#include "py/mperrno.h"
|
||||
#include "py/runtime.h"
|
||||
#include "shared-bindings/microcontroller/__init__.h"
|
||||
#include "shared-bindings/storage/__init__.h"
|
||||
#include "supervisor/filesystem.h"
|
||||
|
||||
extern volatile bool mp_msc_enabled;
|
||||
|
||||
void common_hal_storage_remount(const char* mount_path, bool readonly) {
|
||||
if (strcmp(mount_path, "/") != 0) {
|
||||
void common_hal_storage_remount(const char *mount_path, bool readonly) {
|
||||
if (strcmp(mount_path, "/") != 0)
|
||||
mp_raise_OSError(MP_EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
void common_hal_storage_erase_filesystem() {
|
||||
mp_raise_NotImplementedError("");
|
||||
void common_hal_storage_erase_filesystem(void) {
|
||||
filesystem_init(false, true); // Force a re-format.
|
||||
common_hal_mcu_reset();
|
||||
// We won't actually get here, since we're resetting.
|
||||
}
|
||||
|
||||
@ -29,10 +29,12 @@
|
||||
#include "shared-bindings/time/__init__.h"
|
||||
#include "tick.h"
|
||||
|
||||
inline uint64_t common_hal_time_monotonic() {
|
||||
return ticks_ms;
|
||||
#include "nrfx_glue.h"
|
||||
|
||||
inline uint64_t common_hal_time_monotonic(void) {
|
||||
return ticks_ms;
|
||||
}
|
||||
|
||||
void common_hal_time_delay_ms(uint32_t delay) {
|
||||
mp_hal_delay_ms(delay);
|
||||
NRFX_DELAY_US(delay);
|
||||
}
|
||||
|
||||
@ -1,144 +0,0 @@
|
||||
/* Copyright (c) 2016, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMPILER_ABSTRACTION_H
|
||||
#define _COMPILER_ABSTRACTION_H
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __align(n)
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
|
||||
#define GET_SP() __current_sp()
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define STRING_PRAGMA(x) _Pragma(#x)
|
||||
#define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
|
||||
#define GET_SP() __get_SP()
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __attribute__((aligned(n)))
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
|
||||
#define GET_SP() gcc_current_sp()
|
||||
|
||||
static inline unsigned int gcc_current_sp(void)
|
||||
{
|
||||
register unsigned sp __ASM("sp");
|
||||
return sp;
|
||||
}
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __align(n)
|
||||
#endif
|
||||
|
||||
/* Not defined for TASKING. */
|
||||
#ifndef __PACKED
|
||||
#define __PACKED
|
||||
#endif
|
||||
|
||||
#define GET_SP() __get_MSP()
|
||||
|
||||
#endif
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif
|
||||
@ -1,77 +0,0 @@
|
||||
/* Copyright (c) 2016, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRF_H
|
||||
#define NRF_H
|
||||
|
||||
/* MDK version */
|
||||
#define MDK_MAJOR_VERSION 8
|
||||
#define MDK_MINOR_VERSION 11
|
||||
#define MDK_MICRO_VERSION 1
|
||||
|
||||
/* Define NRF52_SERIES for common use in nRF52 series devices. */
|
||||
#if defined (NRF52832_XXAA) || defined (NRF52840_XXAA)
|
||||
#define NRF52_SERIES
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(_WIN32)
|
||||
/* Do not include nrf specific files when building for PC host */
|
||||
#elif defined(__unix)
|
||||
/* Do not include nrf specific files when building for PC host */
|
||||
#elif defined(__APPLE__)
|
||||
/* Do not include nrf specific files when building for PC host */
|
||||
#else
|
||||
|
||||
/* Device selection for device includes. */
|
||||
#if defined (NRF51)
|
||||
#include "nrf51.h"
|
||||
#include "nrf51_bitfields.h"
|
||||
#include "nrf51_deprecated.h"
|
||||
#elif defined (NRF52840_XXAA)
|
||||
#include "nrf52840.h"
|
||||
#include "nrf52840_bitfields.h"
|
||||
#include "nrf51_to_nrf52840.h"
|
||||
#include "nrf52_to_nrf52840.h"
|
||||
#elif defined (NRF52832_XXAA)
|
||||
#include "nrf52.h"
|
||||
#include "nrf52_bitfields.h"
|
||||
#include "nrf51_to_nrf52.h"
|
||||
#include "nrf52_name_change.h"
|
||||
#else
|
||||
#error "Device must be defined. See nrf.h."
|
||||
#endif /* NRF51, NRF52832_XXAA, NRF52840_XXAA */
|
||||
|
||||
#include "compiler_abstraction.h"
|
||||
|
||||
#endif /* _WIN32 || __unix || __APPLE__ */
|
||||
|
||||
#endif /* NRF_H */
|
||||
|
||||
@ -1,952 +0,0 @@
|
||||
/* Copyright (c) 2016, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRF51_TO_NRF52_H
|
||||
#define NRF51_TO_NRF52_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices.
|
||||
* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
|
||||
* from the nrf51_deprecated.h file. */
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
|
||||
#define UART0_IRQHandler UARTE0_UART0_IRQHandler
|
||||
#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
#define ADC_IRQHandler SAADC_IRQHandler
|
||||
#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
|
||||
#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
|
||||
#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
|
||||
#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
|
||||
#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
|
||||
#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
|
||||
|
||||
#define UART0_IRQn UARTE0_UART0_IRQn
|
||||
#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
|
||||
#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
|
||||
#define ADC_IRQn SAADC_IRQn
|
||||
#define LPCOMP_IRQn COMP_LPCOMP_IRQn
|
||||
#define SWI0_IRQn SWI0_EGU0_IRQn
|
||||
#define SWI1_IRQn SWI1_EGU1_IRQn
|
||||
#define SWI2_IRQn SWI2_EGU2_IRQn
|
||||
#define SWI3_IRQn SWI3_EGU3_IRQn
|
||||
#define SWI4_IRQn SWI4_EGU4_IRQn
|
||||
#define SWI5_IRQn SWI5_EGU5_IRQn
|
||||
|
||||
|
||||
/* UICR */
|
||||
/* Register RBPCONF was renamed to APPROTECT. */
|
||||
#define RBPCONF APPROTECT
|
||||
|
||||
#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
|
||||
#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
|
||||
#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
|
||||
#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
|
||||
|
||||
|
||||
/* GPIO */
|
||||
/* GPIO port was renamed to P0. */
|
||||
#define NRF_GPIO NRF_P0
|
||||
#define NRF_GPIO_BASE NRF_P0_BASE
|
||||
|
||||
|
||||
/* QDEC */
|
||||
/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
|
||||
#define PSELLED PSEL.LED
|
||||
#define PSELA PSEL.A
|
||||
#define PSELB PSEL.B
|
||||
|
||||
|
||||
/* SPIS */
|
||||
/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
|
||||
#define PSELSCK PSEL.SCK
|
||||
#define PSELMISO PSEL.MISO
|
||||
#define PSELMOSI PSEL.MOSI
|
||||
#define PSELCSN PSEL.CSN
|
||||
|
||||
/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
|
||||
#define RXDPTR RXD.PTR
|
||||
#define MAXRX RXD.MAXCNT
|
||||
#define AMOUNTRX RXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
|
||||
#define TXDPTR TXD.PTR
|
||||
#define MAXTX TXD.MAXCNT
|
||||
#define AMOUNTTX TXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
|
||||
/* MPU */
|
||||
/* Part of MPU module was renamed BPROT, while the rest was eliminated. */
|
||||
#define NRF_MPU NRF_BPROT
|
||||
|
||||
/* Register DISABLEINDEBUG macros were affected. */
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled
|
||||
|
||||
/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */
|
||||
#define PROTENSET0 CONFIG0
|
||||
#define PROTENSET1 CONFIG1
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos
|
||||
#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk
|
||||
#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos
|
||||
#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk
|
||||
#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos
|
||||
#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk
|
||||
#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos
|
||||
#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk
|
||||
#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos
|
||||
#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk
|
||||
#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos
|
||||
#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk
|
||||
#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos
|
||||
#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk
|
||||
#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos
|
||||
#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk
|
||||
#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos
|
||||
#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk
|
||||
#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos
|
||||
#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk
|
||||
#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos
|
||||
#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk
|
||||
#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos
|
||||
#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk
|
||||
#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos
|
||||
#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk
|
||||
#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos
|
||||
#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk
|
||||
#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos
|
||||
#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk
|
||||
#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos
|
||||
#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk
|
||||
#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos
|
||||
#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk
|
||||
#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos
|
||||
#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk
|
||||
#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos
|
||||
#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk
|
||||
#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos
|
||||
#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk
|
||||
#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos
|
||||
#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk
|
||||
#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos
|
||||
#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk
|
||||
#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos
|
||||
#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk
|
||||
#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos
|
||||
#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk
|
||||
#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos
|
||||
#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk
|
||||
#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos
|
||||
#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk
|
||||
#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos
|
||||
#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk
|
||||
#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos
|
||||
#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk
|
||||
#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos
|
||||
#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk
|
||||
#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos
|
||||
#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk
|
||||
#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos
|
||||
#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk
|
||||
#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos
|
||||
#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk
|
||||
#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos
|
||||
#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk
|
||||
#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos
|
||||
#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk
|
||||
#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos
|
||||
#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk
|
||||
#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos
|
||||
#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk
|
||||
#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos
|
||||
#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk
|
||||
#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos
|
||||
#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk
|
||||
#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos
|
||||
#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk
|
||||
#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos
|
||||
#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk
|
||||
#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos
|
||||
#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk
|
||||
#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos
|
||||
#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk
|
||||
#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos
|
||||
#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk
|
||||
#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos
|
||||
#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk
|
||||
#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos
|
||||
#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk
|
||||
#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos
|
||||
#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk
|
||||
#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos
|
||||
#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk
|
||||
#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos
|
||||
#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk
|
||||
#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos
|
||||
#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk
|
||||
#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos
|
||||
#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk
|
||||
#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos
|
||||
#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk
|
||||
#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos
|
||||
#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk
|
||||
#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos
|
||||
#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk
|
||||
#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos
|
||||
#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk
|
||||
#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos
|
||||
#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk
|
||||
#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos
|
||||
#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk
|
||||
#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos
|
||||
#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk
|
||||
#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos
|
||||
#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk
|
||||
#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos
|
||||
#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk
|
||||
#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos
|
||||
#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk
|
||||
#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos
|
||||
#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk
|
||||
#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos
|
||||
#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk
|
||||
#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos
|
||||
#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk
|
||||
#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos
|
||||
#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk
|
||||
#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled
|
||||
|
||||
|
||||
/* From nrf51_deprecated.h */
|
||||
|
||||
/* NVMC */
|
||||
/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
|
||||
#define ERASEPROTECTEDPAGE ERASEPCR0
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* COMP module was eliminated. Adapted to nrf52 headers. */
|
||||
#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
|
||||
|
||||
|
||||
/* REFSEL register redefined enumerated values and added some more. */
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
|
||||
|
||||
|
||||
/* RADIO */
|
||||
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
|
||||
|
||||
|
||||
/* FICR */
|
||||
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
|
||||
#define DEVICEID0 DEVICEID[0]
|
||||
#define DEVICEID1 DEVICEID[1]
|
||||
|
||||
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
|
||||
#define ER0 ER[0]
|
||||
#define ER1 ER[1]
|
||||
#define ER2 ER[2]
|
||||
#define ER3 ER[3]
|
||||
|
||||
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
|
||||
#define IR0 IR[0]
|
||||
#define IR1 IR[1]
|
||||
#define IR2 IR[2]
|
||||
#define IR3 IR[3]
|
||||
|
||||
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
|
||||
#define DEVICEADDR0 DEVICEADDR[0]
|
||||
#define DEVICEADDR1 DEVICEADDR[1]
|
||||
|
||||
|
||||
/* PPI */
|
||||
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
|
||||
#define TASKS_CHG0EN TASKS_CHG[0].EN
|
||||
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
|
||||
#define TASKS_CHG1EN TASKS_CHG[1].EN
|
||||
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
|
||||
#define TASKS_CHG2EN TASKS_CHG[2].EN
|
||||
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
|
||||
#define TASKS_CHG3EN TASKS_CHG[3].EN
|
||||
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
|
||||
|
||||
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
|
||||
#define CH0_EEP CH[0].EEP
|
||||
#define CH0_TEP CH[0].TEP
|
||||
#define CH1_EEP CH[1].EEP
|
||||
#define CH1_TEP CH[1].TEP
|
||||
#define CH2_EEP CH[2].EEP
|
||||
#define CH2_TEP CH[2].TEP
|
||||
#define CH3_EEP CH[3].EEP
|
||||
#define CH3_TEP CH[3].TEP
|
||||
#define CH4_EEP CH[4].EEP
|
||||
#define CH4_TEP CH[4].TEP
|
||||
#define CH5_EEP CH[5].EEP
|
||||
#define CH5_TEP CH[5].TEP
|
||||
#define CH6_EEP CH[6].EEP
|
||||
#define CH6_TEP CH[6].TEP
|
||||
#define CH7_EEP CH[7].EEP
|
||||
#define CH7_TEP CH[7].TEP
|
||||
#define CH8_EEP CH[8].EEP
|
||||
#define CH8_TEP CH[8].TEP
|
||||
#define CH9_EEP CH[9].EEP
|
||||
#define CH9_TEP CH[9].TEP
|
||||
#define CH10_EEP CH[10].EEP
|
||||
#define CH10_TEP CH[10].TEP
|
||||
#define CH11_EEP CH[11].EEP
|
||||
#define CH11_TEP CH[11].TEP
|
||||
#define CH12_EEP CH[12].EEP
|
||||
#define CH12_TEP CH[12].TEP
|
||||
#define CH13_EEP CH[13].EEP
|
||||
#define CH13_TEP CH[13].TEP
|
||||
#define CH14_EEP CH[14].EEP
|
||||
#define CH14_TEP CH[14].TEP
|
||||
#define CH15_EEP CH[15].EEP
|
||||
#define CH15_TEP CH[15].TEP
|
||||
|
||||
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
|
||||
#define CHG0 CHG[0]
|
||||
#define CHG1 CHG[1]
|
||||
#define CHG2 CHG[2]
|
||||
#define CHG3 CHG[3]
|
||||
|
||||
/* All bitfield macros for the CHGx registers therefore changed name. */
|
||||
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52_H */
|
||||
|
||||
@ -1,567 +0,0 @@
|
||||
/* Copyright (c) 2016, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRF51_TO_NRF52840_H
|
||||
#define NRF51_TO_NRF52840_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices.
|
||||
* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
|
||||
* from the nrf51_deprecated.h file. */
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
|
||||
#define UART0_IRQHandler UARTE0_UART0_IRQHandler
|
||||
#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
#define ADC_IRQHandler SAADC_IRQHandler
|
||||
#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
|
||||
#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
|
||||
#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
|
||||
#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
|
||||
#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
|
||||
#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
|
||||
|
||||
#define UART0_IRQn UARTE0_UART0_IRQn
|
||||
#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
|
||||
#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
|
||||
#define ADC_IRQn SAADC_IRQn
|
||||
#define LPCOMP_IRQn COMP_LPCOMP_IRQn
|
||||
#define SWI0_IRQn SWI0_EGU0_IRQn
|
||||
#define SWI1_IRQn SWI1_EGU1_IRQn
|
||||
#define SWI2_IRQn SWI2_EGU2_IRQn
|
||||
#define SWI3_IRQn SWI3_EGU3_IRQn
|
||||
#define SWI4_IRQn SWI4_EGU4_IRQn
|
||||
#define SWI5_IRQn SWI5_EGU5_IRQn
|
||||
|
||||
|
||||
/* UICR */
|
||||
/* Register RBPCONF was renamed to APPROTECT. */
|
||||
#define RBPCONF APPROTECT
|
||||
|
||||
#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
|
||||
#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
|
||||
#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
|
||||
#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
|
||||
|
||||
|
||||
/* GPIO */
|
||||
/* GPIO port was renamed to P0. */
|
||||
#define NRF_GPIO NRF_P0
|
||||
#define NRF_GPIO_BASE NRF_P0_BASE
|
||||
|
||||
|
||||
/* QDEC */
|
||||
/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
|
||||
#define PSELLED PSEL.LED
|
||||
#define PSELA PSEL.A
|
||||
#define PSELB PSEL.B
|
||||
|
||||
|
||||
/* SPIS */
|
||||
/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
|
||||
#define PSELSCK PSEL.SCK
|
||||
#define PSELMISO PSEL.MISO
|
||||
#define PSELMOSI PSEL.MOSI
|
||||
#define PSELCSN PSEL.CSN
|
||||
|
||||
/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
|
||||
#define RXDPTR RXD.PTR
|
||||
#define MAXRX RXD.MAXCNT
|
||||
#define AMOUNTRX RXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
|
||||
#define TXDPTR TXD.PTR
|
||||
#define MAXTX TXD.MAXCNT
|
||||
#define AMOUNTTX TXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
|
||||
/* UART */
|
||||
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
|
||||
#define PSELRTS PSEL.RTS
|
||||
#define PSELTXD PSEL.TXD
|
||||
#define PSELCTS PSEL.CTS
|
||||
#define PSELRXD PSEL.RXD
|
||||
|
||||
/* TWI */
|
||||
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
|
||||
#define PSELSCL PSEL.SCL
|
||||
#define PSELSDA PSEL.SDA
|
||||
|
||||
|
||||
|
||||
/* From nrf51_deprecated.h */
|
||||
|
||||
/* NVMC */
|
||||
/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
|
||||
#define ERASEPROTECTEDPAGE ERASEPCR0
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* COMP module was eliminated. Adapted to nrf52840 headers. */
|
||||
#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
|
||||
|
||||
|
||||
/* REFSEL register redefined enumerated values and added some more. */
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
|
||||
#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
|
||||
|
||||
|
||||
/* RADIO */
|
||||
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
|
||||
|
||||
|
||||
/* FICR */
|
||||
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
|
||||
#define DEVICEID0 DEVICEID[0]
|
||||
#define DEVICEID1 DEVICEID[1]
|
||||
|
||||
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
|
||||
#define ER0 ER[0]
|
||||
#define ER1 ER[1]
|
||||
#define ER2 ER[2]
|
||||
#define ER3 ER[3]
|
||||
|
||||
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
|
||||
#define IR0 IR[0]
|
||||
#define IR1 IR[1]
|
||||
#define IR2 IR[2]
|
||||
#define IR3 IR[3]
|
||||
|
||||
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
|
||||
#define DEVICEADDR0 DEVICEADDR[0]
|
||||
#define DEVICEADDR1 DEVICEADDR[1]
|
||||
|
||||
|
||||
/* PPI */
|
||||
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
|
||||
#define TASKS_CHG0EN TASKS_CHG[0].EN
|
||||
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
|
||||
#define TASKS_CHG1EN TASKS_CHG[1].EN
|
||||
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
|
||||
#define TASKS_CHG2EN TASKS_CHG[2].EN
|
||||
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
|
||||
#define TASKS_CHG3EN TASKS_CHG[3].EN
|
||||
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
|
||||
|
||||
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
|
||||
#define CH0_EEP CH[0].EEP
|
||||
#define CH0_TEP CH[0].TEP
|
||||
#define CH1_EEP CH[1].EEP
|
||||
#define CH1_TEP CH[1].TEP
|
||||
#define CH2_EEP CH[2].EEP
|
||||
#define CH2_TEP CH[2].TEP
|
||||
#define CH3_EEP CH[3].EEP
|
||||
#define CH3_TEP CH[3].TEP
|
||||
#define CH4_EEP CH[4].EEP
|
||||
#define CH4_TEP CH[4].TEP
|
||||
#define CH5_EEP CH[5].EEP
|
||||
#define CH5_TEP CH[5].TEP
|
||||
#define CH6_EEP CH[6].EEP
|
||||
#define CH6_TEP CH[6].TEP
|
||||
#define CH7_EEP CH[7].EEP
|
||||
#define CH7_TEP CH[7].TEP
|
||||
#define CH8_EEP CH[8].EEP
|
||||
#define CH8_TEP CH[8].TEP
|
||||
#define CH9_EEP CH[9].EEP
|
||||
#define CH9_TEP CH[9].TEP
|
||||
#define CH10_EEP CH[10].EEP
|
||||
#define CH10_TEP CH[10].TEP
|
||||
#define CH11_EEP CH[11].EEP
|
||||
#define CH11_TEP CH[11].TEP
|
||||
#define CH12_EEP CH[12].EEP
|
||||
#define CH12_TEP CH[12].TEP
|
||||
#define CH13_EEP CH[13].EEP
|
||||
#define CH13_TEP CH[13].TEP
|
||||
#define CH14_EEP CH[14].EEP
|
||||
#define CH14_TEP CH[14].TEP
|
||||
#define CH15_EEP CH[15].EEP
|
||||
#define CH15_TEP CH[15].TEP
|
||||
|
||||
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
|
||||
#define CHG0 CHG[0]
|
||||
#define CHG1 CHG[1]
|
||||
#define CHG2 CHG[2]
|
||||
#define CHG3 CHG[3]
|
||||
|
||||
/* All bitfield macros for the CHGx registers therefore changed name. */
|
||||
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52840_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
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Load Diff
File diff suppressed because it is too large
Load Diff
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Load Diff
@ -1,70 +0,0 @@
|
||||
/* Copyright (c) 2016, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRF52_NAME_CHANGE_H
|
||||
#define NRF52_NAME_CHANGE_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
|
||||
* nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
|
||||
* macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
|
||||
*/
|
||||
|
||||
/* I2S */
|
||||
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
|
||||
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
|
||||
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
|
||||
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
|
||||
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
|
||||
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
|
||||
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
|
||||
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
|
||||
|
||||
/* LPCOMP */
|
||||
/* Corrected typo in RESULT register. */
|
||||
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF52_NAME_CHANGE_H */
|
||||
|
||||
@ -1,88 +0,0 @@
|
||||
/* Copyright (c) 2016, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRF52_TO_NRF52840_H
|
||||
#define NRF52_TO_NRF52840_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
|
||||
* It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
|
||||
* from the nrf52_namechange.h file. */
|
||||
|
||||
/* Differences between latest nRF52 headers and nRF52840 headers. */
|
||||
|
||||
/* UART */
|
||||
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
|
||||
#define PSELRTS PSEL.RTS
|
||||
#define PSELTXD PSEL.TXD
|
||||
#define PSELCTS PSEL.CTS
|
||||
#define PSELRXD PSEL.RXD
|
||||
|
||||
/* TWI */
|
||||
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
|
||||
#define PSELSCL PSEL.SCL
|
||||
#define PSELSDA PSEL.SDA
|
||||
|
||||
|
||||
/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
|
||||
|
||||
/* I2S */
|
||||
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
|
||||
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
|
||||
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
|
||||
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
|
||||
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
|
||||
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
|
||||
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
|
||||
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
|
||||
|
||||
/* LPCOMP */
|
||||
/* Corrected typo in RESULT register. */
|
||||
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52840_H */
|
||||
|
||||
@ -1,69 +0,0 @@
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of ARM nor the names of its contributors may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_NRF52_H
|
||||
#define SYSTEM_NRF52_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_NRF52_H */
|
||||
@ -1,308 +0,0 @@
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of ARM nor the names of its contributors may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "system_nrf52.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#define __SYSTEM_CLOCK_64M (64000000UL)
|
||||
|
||||
static bool errata_16(void);
|
||||
static bool errata_31(void);
|
||||
static bool errata_32(void);
|
||||
static bool errata_36(void);
|
||||
static bool errata_37(void);
|
||||
static bool errata_57(void);
|
||||
static bool errata_66(void);
|
||||
static bool errata_108(void);
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_16()){
|
||||
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_31()){
|
||||
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_32()){
|
||||
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_36()){
|
||||
NRF_CLOCK->EVENTS_DONE = 0;
|
||||
NRF_CLOCK->EVENTS_CTTO = 0;
|
||||
NRF_CLOCK->CTIV = 0;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_37()){
|
||||
*(volatile uint32_t *)0x400005A0 = 0x3;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_57()){
|
||||
*(volatile uint32_t *)0x40005610 = 0x00000005;
|
||||
*(volatile uint32_t *)0x40005688 = 0x00000001;
|
||||
*(volatile uint32_t *)0x40005618 = 0x00000000;
|
||||
*(volatile uint32_t *)0x40005614 = 0x0000003F;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_66()){
|
||||
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
|
||||
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
|
||||
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
|
||||
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
|
||||
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
|
||||
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
|
||||
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
|
||||
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
|
||||
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
|
||||
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
|
||||
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
|
||||
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
|
||||
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
|
||||
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
|
||||
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
|
||||
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
|
||||
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_108()){
|
||||
*(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
|
||||
}
|
||||
|
||||
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
|
||||
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
|
||||
* operations are not used in your code. */
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= (3UL << 20) | (3UL << 22);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
|
||||
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
|
||||
normal GPIOs. */
|
||||
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
|
||||
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
|
||||
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
|
||||
reserved for PinReset and not available as normal GPIO. */
|
||||
#if defined (CONFIG_GPIO_AS_PINRESET)
|
||||
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
|
||||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[0] = 21;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[1] = 21;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
|
||||
Specification to see which one). */
|
||||
#if defined (ENABLE_SWO)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
|
||||
Specification to see which ones). */
|
||||
#if defined (ENABLE_TRACE)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
|
||||
static bool errata_16(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_31(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_32(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_36(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_37(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_57(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_66(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_108(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
@ -1,209 +0,0 @@
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of ARM nor the names of its contributors may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "system_nrf52840.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#define __SYSTEM_CLOCK_64M (64000000UL)
|
||||
|
||||
static bool errata_36(void);
|
||||
static bool errata_98(void);
|
||||
static bool errata_103(void);
|
||||
static bool errata_115(void);
|
||||
static bool errata_120(void);
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_36()){
|
||||
NRF_CLOCK->EVENTS_DONE = 0;
|
||||
NRF_CLOCK->EVENTS_CTTO = 0;
|
||||
NRF_CLOCK->CTIV = 0;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_98()){
|
||||
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_103()){
|
||||
NRF_CCM->MAXPACKETSIZE = 0xFBul;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_115()){
|
||||
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
|
||||
}
|
||||
|
||||
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_120()){
|
||||
*(volatile uint32_t *)0x40029640ul = 0x200ul;
|
||||
}
|
||||
|
||||
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
|
||||
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
|
||||
* operations are not used in your code. */
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= (3UL << 20) | (3UL << 22);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
|
||||
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
|
||||
normal GPIOs. */
|
||||
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
|
||||
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
|
||||
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
|
||||
reserved for PinReset and not available as normal GPIO. */
|
||||
#if defined (CONFIG_GPIO_AS_PINRESET)
|
||||
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
|
||||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[0] = 18;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[1] = 18;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
|
||||
Specification to see which one). */
|
||||
#if defined (ENABLE_SWO)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
|
||||
Specification to see which ones). */
|
||||
#if defined (ENABLE_TRACE)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
|
||||
static bool errata_36(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_98(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_103(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_115(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_120(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
@ -1,69 +0,0 @@
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of ARM nor the names of its contributors may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_NRF52_H
|
||||
#define SYSTEM_NRF52_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_NRF52_H */
|
||||
@ -1,129 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "mphalport.h"
|
||||
#include "hal_adc.h"
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
|
||||
#define ADC_REF_VOLTAGE_IN_MILLIVOLTS (1200) // Reference voltage (in milli volts) used by ADC while doing conversion.
|
||||
#define ADC_PRE_SCALING_COMPENSATION (3) // The ADC is configured to use VDD with 1/3 prescaling as input. And hence the result of conversion is to be multiplied by 3 to get the actual value of the battery voltage.
|
||||
#define DIODE_FWD_VOLT_DROP_MILLIVOLTS (270) // Typical forward voltage drop of the diode (Part no: SD103ATW-7-F) that is connected in series with the voltage supply. This is the voltage drop when the forward current is 1mA. Source: Data sheet of 'SURFACE MOUNT SCHOTTKY BARRIER DIODE ARRAY' available at www.diodes.com.
|
||||
|
||||
#define ADC_RESULT_IN_MILLI_VOLTS(ADC_VALUE)\
|
||||
((((ADC_VALUE) * ADC_REF_VOLTAGE_IN_MILLIVOLTS) / 255) * ADC_PRE_SCALING_COMPENSATION)
|
||||
|
||||
static const uint32_t hal_adc_input_lookup[] = {
|
||||
ADC_CONFIG_PSEL_AnalogInput0 << ADC_CONFIG_PSEL_Pos,
|
||||
ADC_CONFIG_PSEL_AnalogInput1 << ADC_CONFIG_PSEL_Pos,
|
||||
ADC_CONFIG_PSEL_AnalogInput2 << ADC_CONFIG_PSEL_Pos,
|
||||
ADC_CONFIG_PSEL_AnalogInput3 << ADC_CONFIG_PSEL_Pos,
|
||||
ADC_CONFIG_PSEL_AnalogInput4 << ADC_CONFIG_PSEL_Pos,
|
||||
ADC_CONFIG_PSEL_AnalogInput5 << ADC_CONFIG_PSEL_Pos,
|
||||
ADC_CONFIG_PSEL_AnalogInput6 << ADC_CONFIG_PSEL_Pos,
|
||||
ADC_CONFIG_PSEL_AnalogInput7 << ADC_CONFIG_PSEL_Pos
|
||||
};
|
||||
|
||||
|
||||
static uint8_t battery_level_in_percent(const uint16_t mvolts)
|
||||
{
|
||||
uint8_t battery_level;
|
||||
|
||||
if (mvolts >= 3000) {
|
||||
battery_level = 100;
|
||||
} else if (mvolts > 2900) {
|
||||
battery_level = 100 - ((3000 - mvolts) * 58) / 100;
|
||||
} else if (mvolts > 2740) {
|
||||
battery_level = 42 - ((2900 - mvolts) * 24) / 160;
|
||||
} else if (mvolts > 2440) {
|
||||
battery_level = 18 - ((2740 - mvolts) * 12) / 300;
|
||||
} else if (mvolts > 2100) {
|
||||
battery_level = 6 - ((2440 - mvolts) * 6) / 340;
|
||||
} else {
|
||||
battery_level = 0;
|
||||
}
|
||||
|
||||
return battery_level;
|
||||
}
|
||||
|
||||
uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) {
|
||||
ADC_BASE->INTENSET = ADC_INTENSET_END_Msk;
|
||||
ADC_BASE->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos)
|
||||
| (ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling << ADC_CONFIG_INPSEL_Pos)
|
||||
| (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos)
|
||||
| (hal_adc_input_lookup[p_adc_conf->channel])
|
||||
| (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos);
|
||||
|
||||
ADC_BASE->EVENTS_END = 0;
|
||||
ADC_BASE->ENABLE = ADC_ENABLE_ENABLE_Enabled;
|
||||
|
||||
ADC_BASE->EVENTS_END = 0;
|
||||
ADC_BASE->TASKS_START = 1;
|
||||
|
||||
while (!ADC_BASE->EVENTS_END) {
|
||||
;
|
||||
}
|
||||
|
||||
uint8_t adc_result;
|
||||
|
||||
ADC_BASE->EVENTS_END = 0;
|
||||
adc_result = ADC_BASE->RESULT;
|
||||
ADC_BASE->TASKS_STOP = 1;
|
||||
|
||||
return adc_result;
|
||||
}
|
||||
|
||||
uint16_t hal_adc_battery_level(void) {
|
||||
ADC_BASE->INTENSET = ADC_INTENSET_END_Msk;
|
||||
ADC_BASE->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos)
|
||||
| (ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling << ADC_CONFIG_INPSEL_Pos)
|
||||
| (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos)
|
||||
| (ADC_CONFIG_PSEL_Disabled << ADC_CONFIG_PSEL_Pos)
|
||||
| (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos);
|
||||
|
||||
ADC_BASE->EVENTS_END = 0;
|
||||
ADC_BASE->ENABLE = ADC_ENABLE_ENABLE_Enabled;
|
||||
|
||||
ADC_BASE->EVENTS_END = 0;
|
||||
ADC_BASE->TASKS_START = 1;
|
||||
|
||||
while (!ADC_BASE->EVENTS_END) {
|
||||
;
|
||||
}
|
||||
|
||||
uint8_t adc_result;
|
||||
uint16_t batt_lvl_in_milli_volts;
|
||||
|
||||
ADC_BASE->EVENTS_END = 0;
|
||||
adc_result = ADC_BASE->RESULT;
|
||||
ADC_BASE->TASKS_STOP = 1;
|
||||
|
||||
batt_lvl_in_milli_volts = ADC_RESULT_IN_MILLI_VOLTS(adc_result) + DIODE_FWD_VOLT_DROP_MILLIVOLTS;
|
||||
return battery_level_in_percent(batt_lvl_in_milli_volts);
|
||||
}
|
||||
|
||||
#endif // HAL_ADC_MODULE_ENABLED
|
||||
@ -1,75 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_ADC_H__
|
||||
#define HAL_ADC_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#if NRF51
|
||||
|
||||
#define ADC_IRQ_NUM ADC_IRQn
|
||||
#define ADC_BASE ((NRF_ADC_Type *)NRF_ADC_BASE)
|
||||
#define HAL_ADC_Type NRF_ADC_Type
|
||||
|
||||
#else
|
||||
|
||||
#define ADC_IRQ_NUM SAADC_IRQn
|
||||
#define ADC_BASE ((NRF_SAADC_Type *)NRF_SAADC_BASE)
|
||||
#define HAL_ADC_Type NRF_SAADC_Type
|
||||
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
HAL_ADC_CHANNEL_2 = 2,
|
||||
HAL_ADC_CHANNEL_3,
|
||||
HAL_ADC_CHANNEL_4,
|
||||
HAL_ADC_CHANNEL_5,
|
||||
HAL_ADC_CHANNEL_6,
|
||||
HAL_ADC_CHANNEL_7,
|
||||
} hal_adc_channel_t;
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
hal_adc_channel_t channel;
|
||||
} hal_adc_config_t;
|
||||
|
||||
/**
|
||||
* @brief ADC handle Structure definition
|
||||
*/
|
||||
typedef struct __ADC_HandleTypeDef {
|
||||
hal_adc_config_t config; /* ADC config parameters */
|
||||
} ADC_HandleTypeDef;
|
||||
|
||||
uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf);
|
||||
|
||||
uint16_t hal_adc_battery_level(void);
|
||||
|
||||
#endif // HAL_ADC_H__
|
||||
@ -1,118 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_adc.h"
|
||||
|
||||
#ifdef HAL_ADCE_MODULE_ENABLED
|
||||
|
||||
static const uint32_t hal_adc_input_lookup_pos[] = {
|
||||
SAADC_CH_PSELP_PSELP_AnalogInput0 << SAADC_CH_PSELP_PSELP_Pos,
|
||||
SAADC_CH_PSELP_PSELP_AnalogInput1 << SAADC_CH_PSELP_PSELP_Pos,
|
||||
SAADC_CH_PSELP_PSELP_AnalogInput2 << SAADC_CH_PSELP_PSELP_Pos,
|
||||
SAADC_CH_PSELP_PSELP_AnalogInput3 << SAADC_CH_PSELP_PSELP_Pos,
|
||||
SAADC_CH_PSELP_PSELP_AnalogInput4 << SAADC_CH_PSELP_PSELP_Pos,
|
||||
SAADC_CH_PSELP_PSELP_AnalogInput5 << SAADC_CH_PSELP_PSELP_Pos,
|
||||
SAADC_CH_PSELP_PSELP_AnalogInput6 << SAADC_CH_PSELP_PSELP_Pos,
|
||||
SAADC_CH_PSELP_PSELP_AnalogInput7 << SAADC_CH_PSELP_PSELP_Pos
|
||||
};
|
||||
|
||||
#define HAL_ADCE_PSELP_NOT_CONNECTED (SAADC_CH_PSELP_PSELP_NC << SAADC_CH_PSELP_PSELP_Pos)
|
||||
#define HAL_ADCE_PSELP_VDD (SAADC_CH_PSELP_PSELP_VDD << SAADC_CH_PSELP_PSELP_Pos)
|
||||
|
||||
/*static const uint32_t hal_adc_input_lookup_neg[] = {
|
||||
SAADC_CH_PSELN_PSELN_AnalogInput0 << SAADC_CH_PSELN_PSELN_Pos,
|
||||
SAADC_CH_PSELN_PSELN_AnalogInput1 << SAADC_CH_PSELN_PSELN_Pos,
|
||||
SAADC_CH_PSELN_PSELN_AnalogInput2 << SAADC_CH_PSELN_PSELN_Pos,
|
||||
SAADC_CH_PSELN_PSELN_AnalogInput3 << SAADC_CH_PSELN_PSELN_Pos,
|
||||
SAADC_CH_PSELN_PSELN_AnalogInput4 << SAADC_CH_PSELN_PSELN_Pos,
|
||||
SAADC_CH_PSELN_PSELN_AnalogInput5 << SAADC_CH_PSELN_PSELN_Pos,
|
||||
SAADC_CH_PSELN_PSELN_AnalogInput6 << SAADC_CH_PSELN_PSELN_Pos,
|
||||
SAADC_CH_PSELN_PSELN_AnalogInput7 << SAADC_CH_PSELN_PSELN_Pos
|
||||
};*/
|
||||
|
||||
#define HAL_ADCE_PSELN_NOT_CONNECTED (SAADC_CH_PSELN_PSELN_NC << SAADC_CH_PSELN_PSELN_Pos)
|
||||
#define HAL_ADCE_PSELN_VDD (SAADC_CH_PSELN_PSELN_VDD << SAADC_CH_PSELN_PSELN_Pos)
|
||||
|
||||
uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) {
|
||||
int16_t result = 0;
|
||||
|
||||
// configure to use VDD/4 and gain 1/4
|
||||
ADC_BASE->CH[0].CONFIG = (SAADC_CH_CONFIG_GAIN_Gain1_4 << SAADC_CH_CONFIG_GAIN_Pos)
|
||||
| (SAADC_CH_CONFIG_MODE_SE << SAADC_CH_CONFIG_MODE_Pos)
|
||||
| (SAADC_CH_CONFIG_REFSEL_VDD1_4 << SAADC_CH_CONFIG_REFSEL_Pos)
|
||||
| (SAADC_CH_CONFIG_RESN_Bypass << SAADC_CH_CONFIG_RESN_Pos)
|
||||
| (SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESP_Pos)
|
||||
| (SAADC_CH_CONFIG_TACQ_3us << SAADC_CH_CONFIG_TACQ_Pos);
|
||||
|
||||
// positive input
|
||||
ADC_BASE->CH[0].PSELP = hal_adc_input_lookup_pos[p_adc_conf->channel]; // HAL_ADCE_PSELP_VDD;
|
||||
ADC_BASE->CH[0].PSELN = HAL_ADCE_PSELN_NOT_CONNECTED;
|
||||
|
||||
ADC_BASE->RESOLUTION = SAADC_RESOLUTION_VAL_8bit << SAADC_RESOLUTION_VAL_Pos;
|
||||
ADC_BASE->RESULT.MAXCNT = 1;
|
||||
ADC_BASE->RESULT.PTR = (uint32_t)&result;
|
||||
ADC_BASE->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos;
|
||||
ADC_BASE->ENABLE = SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos;
|
||||
|
||||
// calibrate ADC
|
||||
ADC_BASE->TASKS_CALIBRATEOFFSET = 1;
|
||||
while (ADC_BASE->EVENTS_CALIBRATEDONE == 0) {
|
||||
;
|
||||
}
|
||||
ADC_BASE->EVENTS_CALIBRATEDONE = 0;
|
||||
while (ADC_BASE->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos)) {
|
||||
;
|
||||
}
|
||||
|
||||
// start the ADC
|
||||
ADC_BASE->TASKS_START = 1;
|
||||
while (ADC_BASE->EVENTS_STARTED == 0) {
|
||||
;
|
||||
}
|
||||
ADC_BASE->EVENTS_STARTED = 0;
|
||||
|
||||
// sample ADC
|
||||
ADC_BASE->TASKS_SAMPLE = 1;
|
||||
while (ADC_BASE->EVENTS_END == 0) {
|
||||
;
|
||||
}
|
||||
ADC_BASE->EVENTS_END = 0;
|
||||
|
||||
ADC_BASE->TASKS_STOP = 1;
|
||||
while (ADC_BASE->EVENTS_STOPPED == 0) {
|
||||
;
|
||||
}
|
||||
ADC_BASE->EVENTS_STOPPED = 0;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
uint16_t hal_adc_battery_level(void) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // HAL_ADCE_MODULE_ENABLED
|
||||
@ -1,116 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "hal_gpio.h"
|
||||
#include "mphalport.h"
|
||||
#include "hal_irq.h"
|
||||
|
||||
#define GPIOTE_IRQ_NUM GPIOTE_IRQn
|
||||
#define GPIOTE_BASE ((NRF_GPIOTE_Type *)NRF_GPIOTE_BASE)
|
||||
#define HAL_GPIOTE_Type NRF_GPIOTE_Type
|
||||
|
||||
static hal_gpio_event_callback_t m_callback;
|
||||
|
||||
void hal_gpio_register_callback(hal_gpio_event_callback_t cb) {
|
||||
m_callback = cb;
|
||||
|
||||
#if 0
|
||||
hal_gpio_event_config_t config;
|
||||
config.channel = HAL_GPIO_EVENT_CHANNEL_0;
|
||||
config.event = HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW;
|
||||
config.init_level = 1;
|
||||
config.pin = 13;
|
||||
config.port = 0;
|
||||
|
||||
// start LFCLK if not already started
|
||||
if (NRF_CLOCK->LFCLKSTAT == 0) {
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0);
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
}
|
||||
|
||||
hal_irq_enable(GPIOTE_IRQ_NUM);
|
||||
hal_irq_priority(GPIOTE_IRQ_NUM, 3);
|
||||
|
||||
hal_gpio_event_config(&config);
|
||||
#endif
|
||||
}
|
||||
|
||||
void hal_gpio_event_config(hal_gpio_event_config_t const * p_config) {
|
||||
#if 0
|
||||
hal_gpio_cfg_pin(p_config->port, p_config->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_UP);
|
||||
|
||||
uint8_t channel = (uint8_t)p_config->channel;
|
||||
GPIOTE_BASE->CONFIG[channel] = \
|
||||
GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos \
|
||||
| p_config->pin << GPIOTE_CONFIG_PSEL_Pos \
|
||||
| p_config->event \
|
||||
| p_config->init_level << GPIOTE_CONFIG_OUTINIT_Pos;
|
||||
|
||||
GPIOTE_BASE->INTENSET = 1 << channel;
|
||||
GPIOTE_BASE->EVENTS_IN[channel] = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
||||
void GPIOTE_IRQHandler(void) {
|
||||
if (GPIOTE_BASE->EVENTS_IN[0]) {
|
||||
GPIOTE_BASE->EVENTS_IN[0] = 0;
|
||||
m_callback(HAL_GPIO_EVENT_CHANNEL_0);
|
||||
}
|
||||
if (GPIOTE_BASE->EVENTS_IN[1]) {
|
||||
GPIOTE_BASE->EVENTS_IN[1] = 0;
|
||||
m_callback(HAL_GPIO_EVENT_CHANNEL_1);
|
||||
}
|
||||
if (GPIOTE_BASE->EVENTS_IN[2]) {
|
||||
GPIOTE_BASE->EVENTS_IN[2] = 0;
|
||||
m_callback(HAL_GPIO_EVENT_CHANNEL_2);
|
||||
}
|
||||
if (GPIOTE_BASE->EVENTS_IN[3]) {
|
||||
GPIOTE_BASE->EVENTS_IN[3] = 0;
|
||||
m_callback(HAL_GPIO_EVENT_CHANNEL_3);
|
||||
}
|
||||
|
||||
if (GPIOTE_BASE->EVENTS_IN[4]) {
|
||||
GPIOTE_BASE->EVENTS_IN[4] = 0;
|
||||
m_callback(HAL_GPIO_EVENT_CHANNEL_4);
|
||||
}
|
||||
if (GPIOTE_BASE->EVENTS_IN[5]) {
|
||||
GPIOTE_BASE->EVENTS_IN[5] = 0;
|
||||
m_callback(HAL_GPIO_EVENT_CHANNEL_5);
|
||||
}
|
||||
if (GPIOTE_BASE->EVENTS_IN[6]) {
|
||||
GPIOTE_BASE->EVENTS_IN[6] = 0;
|
||||
m_callback(HAL_GPIO_EVENT_CHANNEL_6);
|
||||
}
|
||||
if (GPIOTE_BASE->EVENTS_IN[7]) {
|
||||
GPIOTE_BASE->EVENTS_IN[7] = 0;
|
||||
m_callback(HAL_GPIO_EVENT_CHANNEL_7);
|
||||
}
|
||||
}
|
||||
|
||||
#endif // if 0
|
||||
@ -1,116 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_IRQ_H__
|
||||
#define HAL_IRQ_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#if BLUETOOTH_SD
|
||||
#include "py/nlr.h"
|
||||
#include "ble_drv.h"
|
||||
|
||||
#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled())
|
||||
|
||||
#define NRF52
|
||||
#include "nrf_nvic.h"
|
||||
#endif // BLUETOOTH_SD
|
||||
|
||||
static inline void hal_irq_clear(uint32_t irq_num) {
|
||||
#if BLUETOOTH_SD
|
||||
if (BLUETOOTH_STACK_ENABLED() == 1) {
|
||||
if (sd_nvic_ClearPendingIRQ(irq_num) != 0) {
|
||||
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
|
||||
"IRQ (%d) clear error", irq_num));
|
||||
}
|
||||
} else
|
||||
#endif // BLUETOOTH_SD
|
||||
{
|
||||
NVIC_ClearPendingIRQ(irq_num);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void hal_irq_enable(uint32_t irq_num) {
|
||||
hal_irq_clear(irq_num);
|
||||
|
||||
#if BLUETOOTH_SD
|
||||
if (BLUETOOTH_STACK_ENABLED() == 1) {
|
||||
if (sd_nvic_EnableIRQ(irq_num) != 0) {
|
||||
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
|
||||
"IRQ (%d) enable error", irq_num));
|
||||
}
|
||||
} else
|
||||
#endif // BLUETOOTH_SD
|
||||
{
|
||||
NVIC_EnableIRQ(irq_num);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void hal_irq_disable(uint32_t irq_num) {
|
||||
#if BLUETOOTH_SD
|
||||
if (BLUETOOTH_STACK_ENABLED() == 1) {
|
||||
if (sd_nvic_DisableIRQ(irq_num) != 0) {
|
||||
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
|
||||
"IRQ (%d) disable error", irq_num));
|
||||
}
|
||||
} else
|
||||
#endif // BLUETOOTH_SD
|
||||
{
|
||||
NVIC_DisableIRQ(irq_num);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void hal_irq_priority(uint32_t irq_num, uint8_t priority) {
|
||||
#if BLUETOOTH_SD
|
||||
if (BLUETOOTH_STACK_ENABLED() == 1) {
|
||||
if (sd_nvic_SetPriority(irq_num, priority) != 0) {
|
||||
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
|
||||
"IRQ (%d) priority error", irq_num, priority));
|
||||
}
|
||||
} else
|
||||
#endif // BLUETOOTH_SD
|
||||
{
|
||||
NVIC_SetPriority(irq_num, priority);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void hal_irq_pending(uint32_t irq_num) {
|
||||
#if BLUETOOTH_SD
|
||||
if (BLUETOOTH_STACK_ENABLED() == 1) {
|
||||
if (sd_nvic_SetPendingIRQ(irq_num) != 0) {
|
||||
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
|
||||
"IRQ (%d) pending error", irq_num));
|
||||
}
|
||||
} else
|
||||
#endif // BLUETOOTH_SD
|
||||
{
|
||||
NVIC_SetPendingIRQ(irq_num);
|
||||
}
|
||||
}
|
||||
|
||||
#endif // HAL_IRQ_H__
|
||||
@ -1,118 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_pwm.h"
|
||||
|
||||
#ifdef HAL_PWM_MODULE_ENABLED
|
||||
|
||||
#define PWM_COUNTER_TOP 16000 // 16MHz divided by 16000-> 1ms
|
||||
|
||||
volatile uint16_t g_pwm_seq[4];
|
||||
volatile uint16_t g_pwm_period;
|
||||
|
||||
static const uint32_t hal_pwm_frequency_lookup[] = {
|
||||
PWM_PRESCALER_PRESCALER_DIV_1, // 16MHz
|
||||
PWM_PRESCALER_PRESCALER_DIV_2, // 8MHz
|
||||
PWM_PRESCALER_PRESCALER_DIV_4, // 4MHz
|
||||
PWM_PRESCALER_PRESCALER_DIV_8, // 2MHz
|
||||
PWM_PRESCALER_PRESCALER_DIV_16, // 1MHz
|
||||
PWM_PRESCALER_PRESCALER_DIV_32, // 500kHz
|
||||
PWM_PRESCALER_PRESCALER_DIV_64, // 250kHz
|
||||
PWM_PRESCALER_PRESCALER_DIV_128 // 125kHz
|
||||
};
|
||||
|
||||
void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) {
|
||||
g_pwm_period = p_pwm_init->period;
|
||||
uint16_t pulse_width = ((g_pwm_period * p_pwm_init->duty)/100);
|
||||
|
||||
if (p_pwm_init->pulse_width > 0) {
|
||||
pulse_width = p_pwm_init->pulse_width;
|
||||
}
|
||||
|
||||
if (p_pwm_init->mode == HAL_PWM_MODE_HIGH_LOW) {
|
||||
g_pwm_seq[0] = g_pwm_period - pulse_width;
|
||||
g_pwm_seq[1] = g_pwm_period - pulse_width;
|
||||
} else {
|
||||
g_pwm_seq[0] = pulse_width;
|
||||
g_pwm_seq[1] = pulse_width;
|
||||
}
|
||||
|
||||
g_pwm_seq[2] = 0;
|
||||
g_pwm_seq[3] = 0;
|
||||
|
||||
p_instance->PSEL.OUT[0] = (p_pwm_init->pwm_pin << PWM_PSEL_OUT_PIN_Pos)
|
||||
| (PWM_PSEL_OUT_CONNECT_Connected << PWM_PSEL_OUT_CONNECT_Pos);
|
||||
|
||||
p_instance->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
|
||||
p_instance->MODE = (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos);
|
||||
p_instance->PRESCALER = (hal_pwm_frequency_lookup[p_pwm_init->freq] << PWM_PRESCALER_PRESCALER_Pos);
|
||||
p_instance->COUNTERTOP = (p_pwm_init->period << PWM_COUNTERTOP_COUNTERTOP_Pos);
|
||||
p_instance->LOOP = (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos);
|
||||
p_instance->DECODER = (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos)
|
||||
| (PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);
|
||||
p_instance->SEQ[0].PTR = ((uint32_t)(g_pwm_seq) << PWM_SEQ_PTR_PTR_Pos);
|
||||
p_instance->SEQ[0].CNT = ((sizeof(g_pwm_seq) / sizeof(uint16_t)) << PWM_SEQ_CNT_CNT_Pos);
|
||||
|
||||
p_instance->SEQ[0].REFRESH = 0;
|
||||
p_instance->SEQ[0].ENDDELAY = 0;
|
||||
}
|
||||
|
||||
void hal_pwm_start(NRF_PWM_Type * p_instance) {
|
||||
p_instance->TASKS_SEQSTART[0] = 1;
|
||||
}
|
||||
|
||||
void hal_pwm_stop(NRF_PWM_Type * p_instance) {
|
||||
p_instance->TASKS_SEQSTART[0] = 0;
|
||||
p_instance->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq) {
|
||||
#if 0
|
||||
p_instance->PRESCALER = (hal_pwm_frequency_lookup[freq] << PWM_PRESCALER_PRESCALER_Pos);
|
||||
#endif
|
||||
}
|
||||
|
||||
void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period) {
|
||||
#if 0
|
||||
g_pwm_period = period;
|
||||
p_instance->COUNTERTOP = (g_pwm_period << PWM_COUNTERTOP_COUNTERTOP_Pos);
|
||||
#endif
|
||||
}
|
||||
|
||||
void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty) {
|
||||
#if 0
|
||||
uint16_t duty_cycle = ((g_pwm_period * duty)/100);
|
||||
|
||||
g_pwm_seq[0] = duty_cycle;
|
||||
g_pwm_seq[1] = duty_cycle;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // HAL_PWM_MODULE_ENABLED
|
||||
@ -1,100 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_PWM_H__
|
||||
#define HAL_PWM_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#define PWM0 ((NRF_PWM_Type *)NRF_PWM0_BASE)
|
||||
#define PWM0_IRQ_NUM PWM1_IRQn
|
||||
#define PWM1 ((NRF_PWM_Type *)NRF_PWM1_BASE)
|
||||
#define PWM1_IRQ_NUM PWM1_IRQn
|
||||
#define PWM2 ((NRF_PWM_Type *)NRF_PWM2_BASE)
|
||||
#define PWM2_IRQ_NUM PWM2_IRQn
|
||||
|
||||
#ifdef NRF52840_XXAA
|
||||
#define PWM3 ((NRF_PWM_Type *)NRF_PWM3_BASE)
|
||||
#define PWM3_IRQ_NUM PWM3_IRQn
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PWM frequency type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_PWM_FREQ_16Mhz = 0,
|
||||
HAL_PWM_FREQ_8Mhz,
|
||||
HAL_PWM_FREQ_4Mhz,
|
||||
HAL_PWM_FREQ_2Mhz,
|
||||
HAL_PWM_FREQ_1Mhz,
|
||||
HAL_PWM_FREQ_500khz,
|
||||
HAL_PWM_FREQ_250khz,
|
||||
HAL_PWM_FREQ_125khz
|
||||
} hal_pwm_freq_t;
|
||||
|
||||
/**
|
||||
* @brief PWM mode type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_PWM_MODE_LOW_HIGH = 0,
|
||||
HAL_PWM_MODE_HIGH_LOW
|
||||
} hal_pwm_mode_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint8_t pwm_pin;
|
||||
hal_pwm_freq_t freq;
|
||||
uint8_t duty;
|
||||
uint16_t pulse_width;
|
||||
uint16_t period;
|
||||
hal_pwm_mode_t mode;
|
||||
} hal_pwm_init_t;
|
||||
|
||||
/**
|
||||
* @brief PWM handle Structure definition
|
||||
*/
|
||||
typedef struct __PWM_HandleTypeDef
|
||||
{
|
||||
NRF_PWM_Type *instance; /* PWM registers base address */
|
||||
hal_pwm_init_t init; /* PWM initialization parameters */
|
||||
} PWM_HandleTypeDef;
|
||||
|
||||
|
||||
void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init);
|
||||
|
||||
void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq);
|
||||
|
||||
void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period);
|
||||
|
||||
void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty);
|
||||
|
||||
void hal_pwm_start(NRF_PWM_Type * p_instance);
|
||||
|
||||
void hal_pwm_stop(NRF_PWM_Type * p_instance);
|
||||
|
||||
#endif // HAL_PWM_H__
|
||||
@ -1,122 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_qspie.h"
|
||||
|
||||
#ifdef HAL_QSPIE_MODULE_ENABLED
|
||||
|
||||
#define QSPI_IRQ_NUM QSPI_IRQn
|
||||
#define QSPI_BASE ((NRF_QSPI_Type *)NRF_QSPI_BASE)
|
||||
|
||||
// frequency, 32 MHz / (SCKFREQ + 1)
|
||||
static const uint32_t hal_qspi_frequency_lookup[] = {
|
||||
(15 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 2 Mbps
|
||||
(7 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 4 Mbps
|
||||
(3 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 8 Mbps
|
||||
(1 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 16 Mbps
|
||||
(0 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps
|
||||
};
|
||||
|
||||
void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init)
|
||||
{
|
||||
// configure SCK
|
||||
p_instance->PSEL.SCK = (p_qspi_init->clk_pin << QSPI_PSEL_SCK_PIN_Pos)
|
||||
| (p_qspi_init->clk_pin_port << QSPI_PSEL_SCK_PORT_Pos)
|
||||
| (QSPI_PSEL_SCK_CONNECT_Connected << QSPI_PSEL_SCK_CONNECT_Pos);
|
||||
|
||||
// configure CS
|
||||
if (p_qspi_init->use_csn) {
|
||||
p_instance->PSEL.CSN = (p_qspi_init->clk_pin << QSPI_PSEL_CSN_PIN_Pos)
|
||||
| (p_qspi_init->clk_pin_port << QSPI_PSEL_CSN_PORT_Pos)
|
||||
| (QSPI_PSEL_CSN_CONNECT_Connected << QSPI_PSEL_CSN_CONNECT_Pos);
|
||||
} else {
|
||||
p_instance->PSEL.CSN = (QSPI_PSEL_CSN_CONNECT_Disconnected << QSPI_PSEL_CSN_CONNECT_Pos);
|
||||
}
|
||||
|
||||
// configure MOSI/IO0, valid for all configurations
|
||||
p_instance->PSEL.IO0 = (p_qspi_init->d0_mosi_pin << QSPI_PSEL_IO0_PIN_Pos)
|
||||
| (p_qspi_init->d0_mosi_pin_port << QSPI_PSEL_IO0_PORT_Pos)
|
||||
| (QSPI_PSEL_IO0_CONNECT_Connected << QSPI_PSEL_IO0_CONNECT_Pos);
|
||||
|
||||
if (p_qspi_init->data_line != HAL_QSPI_DATA_LINE_SINGLE) {
|
||||
// configure MISO/IO1
|
||||
p_instance->PSEL.IO1 = (p_qspi_init->d1_miso_pin << QSPI_PSEL_IO1_PIN_Pos)
|
||||
| (p_qspi_init->d1_miso_pin_port << QSPI_PSEL_IO1_PORT_Pos)
|
||||
| (QSPI_PSEL_IO1_CONNECT_Connected << QSPI_PSEL_IO1_CONNECT_Pos);
|
||||
|
||||
if (p_qspi_init->data_line == HAL_QSPI_DATA_LINE_QUAD) {
|
||||
// configure IO2
|
||||
p_instance->PSEL.IO2 = (p_qspi_init->d2_pin << QSPI_PSEL_IO2_PIN_Pos)
|
||||
| (p_qspi_init->d2_pin_port << QSPI_PSEL_IO2_PORT_Pos)
|
||||
| (QSPI_PSEL_IO2_CONNECT_Connected << QSPI_PSEL_IO2_CONNECT_Pos);
|
||||
|
||||
// configure IO3
|
||||
p_instance->PSEL.IO3 = (p_qspi_init->d3_pin << QSPI_PSEL_IO3_PIN_Pos)
|
||||
| (p_qspi_init->d3_pin_port << QSPI_PSEL_IO3_PORT_Pos)
|
||||
| (QSPI_PSEL_IO3_CONNECT_Connected << QSPI_PSEL_IO3_CONNECT_Pos);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t mode;
|
||||
switch (p_qspi_init->mode) {
|
||||
case HAL_SPI_MODE_CPOL0_CPHA0:
|
||||
mode = (QSPI_IFCONFIG1_SPIMODE_MODE0 << QSPI_IFCONFIG1_SPIMODE_Pos);
|
||||
break;
|
||||
case HAL_SPI_MODE_CPOL1_CPHA1:
|
||||
mode = (QSPI_IFCONFIG1_SPIMODE_MODE3 << QSPI_IFCONFIG1_SPIMODE_Pos);
|
||||
break;
|
||||
default:
|
||||
mode = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
// interface config1
|
||||
p_instance->IFCONFIG1 = hal_qspi_frequency_lookup[p_qspi_init->freq]
|
||||
| mode
|
||||
| (1 << QSPI_IFCONFIG1_SCKDELAY_Pos); // number of 16 MHz periods (62.5 ns)
|
||||
|
||||
p_instance->ENABLE = 1;
|
||||
}
|
||||
|
||||
void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance,
|
||||
uint16_t transfer_size,
|
||||
const uint8_t * tx_data,
|
||||
uint8_t * rx_data)
|
||||
{
|
||||
p_instance->READ.DST = (uint32_t)rx_data;
|
||||
p_instance->READ.CNT = transfer_size;
|
||||
p_instance->READ.SRC = (uint32_t)tx_data;
|
||||
p_instance->READ.CNT = transfer_size;
|
||||
p_instance->TASKS_ACTIVATE = 1;
|
||||
while (p_instance->EVENTS_READY == 0) {
|
||||
;
|
||||
}
|
||||
|
||||
p_instance->TASKS_ACTIVATE = 0;
|
||||
}
|
||||
|
||||
#endif // HAL_QSPIE_MODULE_ENABLED
|
||||
@ -1,110 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_QSPIE_H__
|
||||
#define HAL_QSPIE_H__
|
||||
|
||||
#ifdef HAL_QSPIE_MODULE_ENABLED
|
||||
|
||||
#if NRF52840_XXAA
|
||||
|
||||
#include <nrf.h>
|
||||
|
||||
#else
|
||||
#error "Device not supported."
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Quad SPI clock frequency type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_FREQ_2_Mbps,
|
||||
HAL_FREQ_4_Mbps,
|
||||
HAL_FREQ_8_Mbps,
|
||||
HAL_FREQ_16_Mbps,
|
||||
HAL_FREQ_32_Mbps
|
||||
} hal_qspi_clk_freq_t;
|
||||
|
||||
/**
|
||||
* @brief Quad SPI mode type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge)
|
||||
HAL_SPI_MODE_CPOL1_CPHA1 = 3 // CPOL = 1, CPHA = 1 (data on trailing edge)
|
||||
} hal_qspi_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Quad SPI data line configuration type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_QSPI_DATA_LINE_SINGLE,
|
||||
HAL_QSPI_DATA_LINE_DUAL,
|
||||
HAL_QSPI_DATA_LINE_QUAD
|
||||
} hal_qspi_data_line_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Quad SPI Configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t d0_mosi_pin;
|
||||
uint8_t d1_miso_pin;
|
||||
uint8_t d2_pin;
|
||||
uint8_t d3_pin;
|
||||
uint8_t clk_pin;
|
||||
uint8_t csn_pin;
|
||||
uint8_t d0_mosi_pin_port;
|
||||
uint8_t d1_miso_pin_port;
|
||||
uint8_t d2_pin_port;
|
||||
uint8_t d3_pin_port;
|
||||
uint8_t clk_pin_port;
|
||||
uint8_t csn_pin_port;
|
||||
bool use_csn;
|
||||
hal_qspi_mode_t mode;
|
||||
hal_qspi_data_line_t data_line;
|
||||
hal_qspi_clk_freq_t freq;
|
||||
} hal_qspi_init_t;
|
||||
|
||||
/**
|
||||
* @brief Quad SPI handle Structure definition
|
||||
*/
|
||||
typedef struct __QSPI_HandleTypeDef
|
||||
{
|
||||
NRF_QSPI_Type *instance; /* QSPI registers base address */
|
||||
hal_qspi_init_t init; /* QSPI initialization parameters */
|
||||
} QSPI_HandleTypeDef;
|
||||
|
||||
void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init);
|
||||
|
||||
void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance,
|
||||
uint16_t transfer_size,
|
||||
const uint8_t * tx_data,
|
||||
uint8_t * rx_data);
|
||||
|
||||
#endif // HAL_QSPIE_MODULE_ENABLED
|
||||
|
||||
#endif // HAL_QSPIE_H__
|
||||
@ -1,119 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_rtc.h"
|
||||
#include "hal_irq.h"
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
|
||||
#define HAL_LFCLK_FREQ (32768UL)
|
||||
#define HAL_RTC_FREQ (10UL)
|
||||
#define HAL_RTC_COUNTER_PRESCALER ((HAL_LFCLK_FREQ/HAL_RTC_FREQ)-1)
|
||||
|
||||
static hal_rtc_app_callback m_callback;
|
||||
|
||||
static uint32_t m_period[sizeof(RTC_BASE_POINTERS) / sizeof(uint32_t)];
|
||||
|
||||
void hal_rtc_callback_set(hal_rtc_app_callback callback) {
|
||||
m_callback = callback;
|
||||
}
|
||||
|
||||
void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) {
|
||||
NRF_RTC_Type * p_rtc = RTC_BASE(p_rtc_conf->id);
|
||||
|
||||
// start LFCLK if not already started
|
||||
if (NRF_CLOCK->LFCLKSTAT == 0) {
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0);
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
}
|
||||
|
||||
m_period[p_rtc_conf->id] = p_rtc_conf->period;
|
||||
|
||||
p_rtc->PRESCALER = HAL_RTC_COUNTER_PRESCALER;
|
||||
hal_irq_priority(RTC_IRQ_NUM(p_rtc_conf->id), p_rtc_conf->irq_priority);
|
||||
}
|
||||
|
||||
void hal_rtc_start(uint8_t id) {
|
||||
NRF_RTC_Type * p_rtc = RTC_BASE(id);
|
||||
|
||||
uint32_t period = HAL_RTC_FREQ * m_period[id];
|
||||
uint32_t counter = p_rtc->COUNTER;
|
||||
|
||||
p_rtc->CC[0] = counter + period;
|
||||
|
||||
p_rtc->EVTENSET = RTC_EVTEN_COMPARE0_Msk;
|
||||
p_rtc->INTENSET = RTC_INTENSET_COMPARE0_Msk;
|
||||
|
||||
hal_irq_clear(RTC_IRQ_NUM(id));
|
||||
hal_irq_enable(RTC_IRQ_NUM(id));
|
||||
|
||||
p_rtc->TASKS_START = 1;
|
||||
}
|
||||
|
||||
void hal_rtc_stop(uint8_t id) {
|
||||
NRF_RTC_Type * p_rtc = RTC_BASE(id);
|
||||
|
||||
p_rtc->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
|
||||
p_rtc->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
|
||||
|
||||
hal_irq_disable(RTC_IRQ_NUM(id));
|
||||
|
||||
p_rtc->TASKS_STOP = 1;
|
||||
}
|
||||
|
||||
static void common_irq_handler(uint8_t id) {
|
||||
NRF_RTC_Type * p_rtc = RTC_BASE(id);
|
||||
|
||||
// clear all events
|
||||
p_rtc->EVENTS_COMPARE[0] = 0;
|
||||
p_rtc->EVENTS_COMPARE[1] = 0;
|
||||
p_rtc->EVENTS_COMPARE[2] = 0;
|
||||
p_rtc->EVENTS_COMPARE[3] = 0;
|
||||
p_rtc->EVENTS_TICK = 0;
|
||||
p_rtc->EVENTS_OVRFLW = 0;
|
||||
|
||||
m_callback(id);
|
||||
}
|
||||
|
||||
void RTC0_IRQHandler(void)
|
||||
{
|
||||
common_irq_handler(0);
|
||||
}
|
||||
|
||||
void RTC1_IRQHandler(void)
|
||||
{
|
||||
common_irq_handler(1);
|
||||
}
|
||||
|
||||
void RTC2_IRQHandler(void)
|
||||
{
|
||||
common_irq_handler(2);
|
||||
}
|
||||
|
||||
#endif // HAL_RTC_MODULE_ENABLED
|
||||
|
||||
@ -1,61 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_RTC_H__
|
||||
#define HAL_RTC_H__
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#define RTC_BASE_POINTERS (const uint32_t[]){NRF_RTC0_BASE, \
|
||||
NRF_RTC1_BASE, \
|
||||
NRF_RTC2_BASE}
|
||||
#define RTC_IRQ_VALUES (const uint32_t[]){RTC0_IRQn, \
|
||||
RTC1_IRQn, \
|
||||
RTC2_IRQn}
|
||||
|
||||
#define RTC_BASE(x) ((NRF_RTC_Type *)RTC_BASE_POINTERS[x])
|
||||
#define RTC_IRQ_NUM(x) (RTC_IRQ_VALUES[x])
|
||||
|
||||
typedef void (*hal_rtc_app_callback)(uint8_t id);
|
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t id; /* RTC instance id */
|
||||
uint32_t period; /* RTC period in ms */
|
||||
uint32_t irq_priority; /* RTC IRQ priority */
|
||||
} hal_rtc_conf_t;
|
||||
|
||||
void hal_rtc_callback_set(hal_rtc_app_callback callback);
|
||||
|
||||
void hal_rtc_init(hal_rtc_conf_t const * p_rtc_config);
|
||||
|
||||
void hal_rtc_start(uint8_t id);
|
||||
|
||||
void hal_rtc_stop(uint8_t id);
|
||||
|
||||
#endif // HAL_RTC_H__
|
||||
@ -1,127 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_spi.h"
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
|
||||
static const uint32_t hal_spi_frequency_lookup[] = {
|
||||
SPI_FREQUENCY_FREQUENCY_K125, // 125 kbps
|
||||
SPI_FREQUENCY_FREQUENCY_K250, // 250 kbps
|
||||
SPI_FREQUENCY_FREQUENCY_K500, // 500 kbps
|
||||
SPI_FREQUENCY_FREQUENCY_M1, // 1 Mbps
|
||||
SPI_FREQUENCY_FREQUENCY_M2, // 2 Mbps
|
||||
SPI_FREQUENCY_FREQUENCY_M4, // 4 Mbps
|
||||
SPI_FREQUENCY_FREQUENCY_M8 // 8 Mbps
|
||||
};
|
||||
|
||||
void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) {
|
||||
hal_gpio_cfg_pin(p_spi_init->clk_pin->port, p_spi_init->clk_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
|
||||
hal_gpio_cfg_pin(p_spi_init->mosi_pin->port, p_spi_init->mosi_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
|
||||
hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
|
||||
|
||||
#if NRF51
|
||||
p_instance->PSELSCK = p_spi_init->clk_pin->pin;
|
||||
p_instance->PSELMOSI = p_spi_init->mosi_pin->pin;
|
||||
p_instance->PSELMISO = p_spi_init->miso_pin->pin;
|
||||
#else
|
||||
p_instance->PSEL.SCK = p_spi_init->clk_pin->pin;
|
||||
p_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin;
|
||||
p_instance->PSEL.MISO = p_spi_init->miso_pin->pin;
|
||||
|
||||
#if NRF52840_XXAA
|
||||
p_instance->PSEL.SCK |= (p_spi_init->clk_pin->port << SPI_PSEL_SCK_PORT_Pos);
|
||||
p_instance->PSEL.MOSI |= (p_spi_init->mosi_pin->port << SPI_PSEL_MOSI_PORT_Pos);
|
||||
p_instance->PSEL.MISO |= (p_spi_init->miso_pin->port << SPI_PSEL_MISO_PORT_Pos);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
p_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq];
|
||||
|
||||
uint32_t mode;
|
||||
switch (p_spi_init->mode) {
|
||||
case HAL_SPI_MODE_CPOL0_CPHA0:
|
||||
mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case HAL_SPI_MODE_CPOL0_CPHA1:
|
||||
mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case HAL_SPI_MODE_CPOL1_CPHA0:
|
||||
mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case HAL_SPI_MODE_CPOL1_CPHA1:
|
||||
mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
default:
|
||||
mode = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (p_spi_init->firstbit == HAL_SPI_LSB_FIRST) {
|
||||
p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_LsbFirst << SPI_CONFIG_ORDER_Pos));
|
||||
} else {
|
||||
p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
|
||||
}
|
||||
|
||||
p_instance->EVENTS_READY = 0U;
|
||||
p_instance->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance,
|
||||
uint16_t transfer_size,
|
||||
const uint8_t * tx_data,
|
||||
uint8_t * rx_data) {
|
||||
|
||||
uint16_t number_of_txd_bytes = 0;
|
||||
|
||||
p_instance->EVENTS_READY = 0;
|
||||
|
||||
while (number_of_txd_bytes < transfer_size) {
|
||||
p_instance->TXD = (uint32_t)(tx_data[number_of_txd_bytes]);
|
||||
|
||||
// wait for the transaction complete or timeout (about 10ms - 20 ms)
|
||||
while (p_instance->EVENTS_READY == 0) {
|
||||
;
|
||||
}
|
||||
|
||||
p_instance->EVENTS_READY = 0;
|
||||
|
||||
uint8_t in_byte = (uint8_t)p_instance->RXD;
|
||||
|
||||
if (rx_data != NULL) {
|
||||
rx_data[number_of_txd_bytes] = in_byte;
|
||||
}
|
||||
|
||||
number_of_txd_bytes++;
|
||||
};
|
||||
}
|
||||
|
||||
#endif // HAL_SPI_MODULE_ENABLED
|
||||
@ -1,120 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_SPI_H__
|
||||
#define HAL_SPI_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
|
||||
#ifdef NRF52832_XXAA
|
||||
#define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, \
|
||||
NRF_SPI1_BASE, \
|
||||
NRF_SPI2_BASE}
|
||||
#define SPI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, \
|
||||
SPIM2_SPIS2_SPI2_IRQn}
|
||||
#endif
|
||||
|
||||
#ifdef NRF52840_XXAA
|
||||
#define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, \
|
||||
NRF_SPI1_BASE, \
|
||||
NRF_SPI2_BASE, \
|
||||
NRF_SPIM3_BASE}
|
||||
#define SPI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, \
|
||||
SPIM2_SPIS2_SPI2_IRQn, \
|
||||
SPIM3_IRQn}
|
||||
#endif
|
||||
|
||||
#define SPI_BASE(x) ((NRF_SPI_Type *)SPI_BASE_POINTERS[x])
|
||||
#define SPI_IRQ_NUM(x) (SPI_IRQ_VALUES[x])
|
||||
|
||||
/**
|
||||
* @brief SPI clock frequency type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_SPI_FREQ_125_Kbps = 0,
|
||||
HAL_SPI_FREQ_250_Kbps,
|
||||
HAL_SPI_FREQ_500_Kbps,
|
||||
HAL_SPI_FREQ_1_Mbps,
|
||||
HAL_SPI_FREQ_2_Mbps,
|
||||
HAL_SPI_FREQ_4_Mbps,
|
||||
HAL_SPI_FREQ_8_Mbps,
|
||||
#if NRF52840_XXAA
|
||||
HAL_SPI_FREQ_16_Mbps,
|
||||
HAL_SPI_FREQ_32_Mbps
|
||||
#endif
|
||||
} hal_spi_clk_freq_t;
|
||||
|
||||
/**
|
||||
* @brief SPI mode type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge)
|
||||
HAL_SPI_MODE_CPOL0_CPHA1, // CPOL = 0, CPHA = 1 (data on trailing edge)
|
||||
HAL_SPI_MODE_CPOL1_CPHA0, // CPOL = 1, CPHA = 0 (data on leading edge)
|
||||
HAL_SPI_MODE_CPOL1_CPHA1 // CPOL = 1, CPHA = 1 (data on trailing edge)
|
||||
} hal_spi_mode_t;
|
||||
|
||||
/**
|
||||
* @brief SPI firstbit mode definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_SPI_MSB_FIRST = 0,
|
||||
HAL_SPI_LSB_FIRST
|
||||
} hal_spi_firstbit_t;
|
||||
|
||||
/**
|
||||
* @brief SPI Configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
const pin_obj_t * mosi_pin;
|
||||
const pin_obj_t * miso_pin;
|
||||
const pin_obj_t * clk_pin;
|
||||
hal_spi_firstbit_t firstbit;
|
||||
hal_spi_mode_t mode;
|
||||
uint32_t irq_priority;
|
||||
hal_spi_clk_freq_t freq;
|
||||
} hal_spi_init_t;
|
||||
|
||||
/**
|
||||
* @brief SPI handle Structure definition
|
||||
*/
|
||||
typedef struct __SPI_HandleTypeDef
|
||||
{
|
||||
NRF_SPI_Type *instance; /* SPI registers base address */
|
||||
hal_spi_init_t init; /* SPI initialization parameters */
|
||||
} SPI_HandleTypeDef;
|
||||
|
||||
void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init);
|
||||
|
||||
void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance,
|
||||
uint16_t transfer_size,
|
||||
const uint8_t * tx_data,
|
||||
uint8_t * rx_data);
|
||||
|
||||
#endif // HAL_SPI_H__
|
||||
@ -1,123 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_spi.h"
|
||||
|
||||
#ifdef HAL_SPIE_MODULE_ENABLED
|
||||
|
||||
static const uint32_t hal_spi_frequency_lookup[] = {
|
||||
SPIM_FREQUENCY_FREQUENCY_K125, // 125 kbps
|
||||
SPIM_FREQUENCY_FREQUENCY_K250, // 250 kbps
|
||||
SPIM_FREQUENCY_FREQUENCY_K500, // 500 kbps
|
||||
SPIM_FREQUENCY_FREQUENCY_M1, // 1 Mbps
|
||||
SPIM_FREQUENCY_FREQUENCY_M2, // 2 Mbps
|
||||
SPIM_FREQUENCY_FREQUENCY_M4, // 4 Mbps
|
||||
SPIM_FREQUENCY_FREQUENCY_M8, // 8 Mbps
|
||||
#if NRF52840_XXAA
|
||||
SPIM_FREQUENCY_FREQUENCY_M16, // 16 Mbps
|
||||
SPIM_FREQUENCY_FREQUENCY_M32, // 32 Mbps
|
||||
#endif
|
||||
};
|
||||
|
||||
void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) {
|
||||
// cast to master type
|
||||
NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance;
|
||||
|
||||
hal_gpio_cfg_pin(p_spi_init->clk_pin->port, p_spi_init->clk_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
|
||||
hal_gpio_cfg_pin(p_spi_init->mosi_pin->port, p_spi_init->mosi_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
|
||||
hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
|
||||
|
||||
spim_instance->PSEL.SCK = p_spi_init->clk_pin->pin;
|
||||
spim_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin;
|
||||
spim_instance->PSEL.MISO = p_spi_init->miso_pin->pin;
|
||||
|
||||
#if NRF52840_XXAA
|
||||
spim_instance->PSEL.SCK |= (p_spi_init->clk_pin->port << SPIM_PSEL_SCK_PORT_Pos);
|
||||
spim_instance->PSEL.MOSI |= (p_spi_init->mosi_pin->port << SPIM_PSEL_MOSI_PORT_Pos);
|
||||
spim_instance->PSEL.MISO |= (p_spi_init->miso_pin->port << SPIM_PSEL_MISO_PORT_Pos);
|
||||
#endif
|
||||
|
||||
spim_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq];
|
||||
|
||||
uint32_t mode;
|
||||
switch (p_spi_init->mode) {
|
||||
case HAL_SPI_MODE_CPOL0_CPHA0:
|
||||
mode = (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case HAL_SPI_MODE_CPOL0_CPHA1:
|
||||
mode = (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case HAL_SPI_MODE_CPOL1_CPHA0:
|
||||
mode = (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case HAL_SPI_MODE_CPOL1_CPHA1:
|
||||
mode = (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
default:
|
||||
mode = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (p_spi_init->firstbit == HAL_SPI_LSB_FIRST) {
|
||||
spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_LsbFirst << SPIM_CONFIG_ORDER_Pos));
|
||||
} else {
|
||||
spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos));
|
||||
}
|
||||
|
||||
spim_instance->EVENTS_END = 0;
|
||||
spim_instance->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, uint8_t * rx_data) {
|
||||
|
||||
// cast to master type
|
||||
NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance;
|
||||
|
||||
if (tx_data != NULL) {
|
||||
spim_instance->TXD.PTR = (uint32_t)(tx_data);
|
||||
spim_instance->TXD.MAXCNT = transfer_size;
|
||||
}
|
||||
|
||||
if (rx_data != NULL) {
|
||||
spim_instance->RXD.PTR = (uint32_t)(rx_data);
|
||||
spim_instance->RXD.MAXCNT = transfer_size;
|
||||
}
|
||||
|
||||
spim_instance->TASKS_START = 1;
|
||||
|
||||
while(spim_instance->EVENTS_END != 1) {
|
||||
;
|
||||
}
|
||||
|
||||
spim_instance->EVENTS_END = 0;
|
||||
spim_instance->TASKS_STOP = 1;
|
||||
}
|
||||
|
||||
#endif // HAL_SPIE_MODULE_ENABLED
|
||||
@ -1,76 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Bander F. Ajba
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "mphalport.h"
|
||||
#include "hal_temp.h"
|
||||
|
||||
#if BLUETOOTH_SD
|
||||
#include "py/nlr.h"
|
||||
#include "ble_drv.h"
|
||||
#include "nrf_soc.h"
|
||||
#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled())
|
||||
#endif // BLUETOOTH_SD
|
||||
|
||||
#ifdef HAL_TEMP_MODULE_ENABLED
|
||||
|
||||
void hal_temp_init(void) {
|
||||
// @note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module
|
||||
*(uint32_t *) 0x4000C504 = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int32_t hal_temp_read(void) {
|
||||
#if BLUETOOTH_SD
|
||||
if (BLUETOOTH_STACK_ENABLED() == 1) {
|
||||
int32_t temp;
|
||||
(void)sd_temp_get(&temp);
|
||||
return temp / 4; // resolution of 0.25 degree celsius
|
||||
}
|
||||
#endif // BLUETOOTH_SD
|
||||
|
||||
int32_t volatile temp;
|
||||
hal_temp_init();
|
||||
|
||||
NRF_TEMP->TASKS_START = 1; // Start the temperature measurement.
|
||||
|
||||
while (NRF_TEMP->EVENTS_DATARDY == 0) {
|
||||
// Do nothing.
|
||||
}
|
||||
|
||||
NRF_TEMP->EVENTS_DATARDY = 0;
|
||||
|
||||
// @note Workaround for PAN_028 rev2.0A anomaly 29 - TEMP: Stop task clears the TEMP register.
|
||||
temp = (((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP) / 4);
|
||||
|
||||
// @note Workaround for PAN_028 rev2.0A anomaly 30 - TEMP: Temp module analog front end does not power down when DATARDY event occurs.
|
||||
NRF_TEMP->TASKS_STOP = 1; // Stop the temperature measurement.
|
||||
return temp;
|
||||
}
|
||||
|
||||
#endif // HAL_TEMP_MODULE_ENABLED
|
||||
@ -1,39 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Bander F. Ajba
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_TEMP_H__
|
||||
#define HAL_TEMP_H__
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#define MASK_SIGN (0x00000200UL)
|
||||
#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
|
||||
|
||||
void hal_temp_init(void);
|
||||
|
||||
int32_t hal_temp_read(void);
|
||||
|
||||
#endif
|
||||
@ -1,99 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_timer.h"
|
||||
#include "hal_irq.h"
|
||||
|
||||
#ifdef HAL_TIMER_MODULE_ENABLED
|
||||
|
||||
static hal_timer_app_callback m_callback;
|
||||
|
||||
void hal_timer_callback_set(hal_timer_app_callback callback) {
|
||||
m_callback = callback;
|
||||
}
|
||||
|
||||
void hal_timer_init(hal_timer_conf_t const * p_timer_conf) {
|
||||
NRF_TIMER_Type * p_timer = TIMER_BASE(p_timer_conf->id);
|
||||
|
||||
p_timer->CC[0] = 1000 * p_timer_conf->period;
|
||||
p_timer->MODE = TIMER_MODE_MODE_Timer;
|
||||
p_timer->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;
|
||||
p_timer->PRESCALER = 4; // 1 us
|
||||
p_timer->INTENSET = TIMER_INTENSET_COMPARE0_Msk;
|
||||
p_timer->SHORTS = (TIMER_SHORTS_COMPARE0_CLEAR_Enabled << TIMER_SHORTS_COMPARE0_CLEAR_Pos);
|
||||
p_timer->TASKS_CLEAR = 1;
|
||||
|
||||
hal_irq_priority(TIMER_IRQ_NUM(p_timer_conf->id), p_timer_conf->irq_priority);
|
||||
}
|
||||
|
||||
void hal_timer_start(uint8_t id) {
|
||||
NRF_TIMER_Type * p_timer = TIMER_BASE(id);
|
||||
|
||||
p_timer->TASKS_CLEAR = 1;
|
||||
hal_irq_enable(TIMER_IRQ_NUM(id));
|
||||
p_timer->TASKS_START = 1;
|
||||
}
|
||||
|
||||
void hal_timer_stop(uint8_t id) {
|
||||
NRF_TIMER_Type * p_timer = TIMER_BASE(id);
|
||||
|
||||
hal_irq_disable(TIMER_IRQ_NUM(id));
|
||||
p_timer->TASKS_STOP = 1;
|
||||
}
|
||||
|
||||
static void common_irq_handler(uint8_t id) {
|
||||
NRF_TIMER_Type * p_timer = TIMER_BASE(id);
|
||||
|
||||
if (p_timer->EVENTS_COMPARE[0]) {
|
||||
p_timer->EVENTS_COMPARE[0] = 0;
|
||||
m_callback(id);
|
||||
}
|
||||
}
|
||||
|
||||
void TIMER0_IRQHandler(void) {
|
||||
common_irq_handler(0);
|
||||
}
|
||||
|
||||
#if (MICROPY_PY_MACHINE_SOFT_PWM != 1)
|
||||
void TIMER1_IRQHandler(void) {
|
||||
common_irq_handler(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
void TIMER2_IRQHandler(void) {
|
||||
common_irq_handler(2);
|
||||
}
|
||||
|
||||
void TIMER3_IRQHandler(void) {
|
||||
common_irq_handler(3);
|
||||
}
|
||||
|
||||
void TIMER4_IRQHandler(void) {
|
||||
common_irq_handler(4);
|
||||
}
|
||||
|
||||
#endif // HAL_TIMER_MODULE_ENABLED
|
||||
@ -1,65 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_TIMER_H__
|
||||
#define HAL_TIMER_H__
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#define TIMER_BASE_POINTERS (const uint32_t[]){NRF_TIMER0_BASE, \
|
||||
NRF_TIMER1_BASE, \
|
||||
NRF_TIMER1_BASE, \
|
||||
NRF_TIMER1_BASE, \
|
||||
NRF_TIMER2_BASE}
|
||||
#define TIMER_IRQ_VALUES (const uint32_t[]){TIMER0_IRQn, \
|
||||
TIMER1_IRQn, \
|
||||
TIMER2_IRQn, \
|
||||
TIMER3_IRQn, \
|
||||
TIMER4_IRQn}
|
||||
|
||||
#define TIMER_BASE(x) ((NRF_TIMER_Type *)TIMER_BASE_POINTERS[x])
|
||||
#define TIMER_IRQ_NUM(x) (TIMER_IRQ_VALUES[x])
|
||||
|
||||
typedef void (*hal_timer_app_callback)(uint8_t id);
|
||||
|
||||
/**
|
||||
* @brief Timer Configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t id;
|
||||
uint32_t period;
|
||||
uint8_t irq_priority;
|
||||
} hal_timer_conf_t;
|
||||
|
||||
void hal_timer_callback_set(hal_timer_app_callback callback);
|
||||
|
||||
void hal_timer_init(hal_timer_conf_t const * p_timer_config);
|
||||
|
||||
void hal_timer_start(uint8_t id);
|
||||
|
||||
void hal_timer_stop(uint8_t id);
|
||||
|
||||
#endif // HAL_TIMER_H__
|
||||
@ -1,133 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_twi.h"
|
||||
|
||||
#ifdef HAL_TWI_MODULE_ENABLED
|
||||
|
||||
static const uint32_t hal_twi_frequency_lookup[] = {
|
||||
TWI_FREQUENCY_FREQUENCY_K100, // 100 kbps
|
||||
TWI_FREQUENCY_FREQUENCY_K250, // 250 kbps
|
||||
TWI_FREQUENCY_FREQUENCY_K400, // 400 kbps
|
||||
};
|
||||
|
||||
void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
|
||||
|
||||
#if NRF52840_XXAA
|
||||
p_instance->PSEL.SCL = p_twi_init->scl_pin->pin;
|
||||
p_instance->PSEL.SDA = p_twi_init->sda_pin->pin;
|
||||
p_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWI_PSEL_SCL_PORT_Pos);
|
||||
p_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWI_PSEL_SDA_PORT_Pos);
|
||||
#else
|
||||
p_instance->PSELSCL = p_twi_init->scl_pin->pin;
|
||||
p_instance->PSELSDA = p_twi_init->sda_pin->pin;
|
||||
#endif
|
||||
|
||||
p_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq];
|
||||
p_instance->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
#include <stdio.h>
|
||||
void hal_twi_master_tx(NRF_TWI_Type * p_instance,
|
||||
uint8_t addr,
|
||||
uint16_t transfer_size,
|
||||
const uint8_t * tx_data,
|
||||
bool stop) {
|
||||
|
||||
uint16_t number_of_txd_bytes = 0;
|
||||
|
||||
p_instance->ADDRESS = addr;
|
||||
|
||||
p_instance->EVENTS_TXDSENT = 0;
|
||||
|
||||
p_instance->TXD = tx_data[number_of_txd_bytes];
|
||||
p_instance->TASKS_STARTTX = 1;
|
||||
|
||||
while (number_of_txd_bytes < transfer_size) {
|
||||
// wait for the transaction complete
|
||||
while (p_instance->EVENTS_TXDSENT == 0) {
|
||||
;
|
||||
}
|
||||
|
||||
number_of_txd_bytes++;
|
||||
|
||||
// TODO: This could go one byte out of bound.
|
||||
p_instance->TXD = tx_data[number_of_txd_bytes];
|
||||
p_instance->EVENTS_TXDSENT = 0;
|
||||
}
|
||||
|
||||
|
||||
if (stop) {
|
||||
p_instance->EVENTS_STOPPED = 0;
|
||||
p_instance->TASKS_STOP = 1;
|
||||
|
||||
while (p_instance->EVENTS_STOPPED == 0) {
|
||||
;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void hal_twi_master_rx(NRF_TWI_Type * p_instance,
|
||||
uint8_t addr,
|
||||
uint16_t transfer_size,
|
||||
uint8_t * rx_data,
|
||||
bool stop) {
|
||||
|
||||
uint16_t number_of_rxd_bytes = 0;
|
||||
|
||||
p_instance->ADDRESS = addr;
|
||||
|
||||
p_instance->EVENTS_RXDREADY = 0;
|
||||
|
||||
p_instance->TASKS_STARTRX = 1;
|
||||
|
||||
while (number_of_rxd_bytes < transfer_size) {
|
||||
// wait for the transaction complete
|
||||
while (p_instance->EVENTS_RXDREADY == 0) {
|
||||
;
|
||||
}
|
||||
|
||||
rx_data[number_of_rxd_bytes] = p_instance->RXD;
|
||||
p_instance->EVENTS_RXDREADY = 0;
|
||||
|
||||
number_of_rxd_bytes++;
|
||||
}
|
||||
|
||||
if (stop) {
|
||||
p_instance->EVENTS_STOPPED = 0;
|
||||
p_instance->TASKS_STOP = 1;
|
||||
|
||||
while (p_instance->EVENTS_STOPPED == 0) {
|
||||
;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
|
||||
}
|
||||
|
||||
#endif // HAL_TWI_MODULE_ENABLED
|
||||
|
||||
@ -1,105 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HAL_TWI_H__
|
||||
#define HAL_TWI_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
|
||||
#define TWI_BASE_POINTERS (const uint32_t[]){NRF_TWI0_BASE, NRF_TWI1_BASE}
|
||||
#define TWI_BASE(x) ((NRF_TWI_Type *)TWI_BASE_POINTERS[x])
|
||||
#define TWI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn}
|
||||
|
||||
/**
|
||||
* @brief TWIM Configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
} hal_twim_init_t;
|
||||
|
||||
/**
|
||||
* @brief TWIS Configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
} hal_twis_init_t;
|
||||
|
||||
/**
|
||||
* @brief TWI clock frequency type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_TWI_FREQ_100_Kbps = 0,
|
||||
HAL_TWI_FREQ_250_Kbps,
|
||||
HAL_TWI_FREQ_400_Kbps
|
||||
} hal_twi_clk_freq_t;
|
||||
|
||||
/**
|
||||
* @brief TWI role type definition
|
||||
*/
|
||||
typedef enum {
|
||||
HAL_TWI_MASTER,
|
||||
HAL_TWI_SLAVE
|
||||
} hal_twi_role_t;
|
||||
|
||||
/**
|
||||
* @brief TWI Configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t id; /* TWI instance id */
|
||||
const pin_obj_t * scl_pin; /* TWI SCL pin */
|
||||
const pin_obj_t * sda_pin; /* TWI SDA pin */
|
||||
hal_twi_role_t role; /* TWI master/slave */
|
||||
hal_twi_clk_freq_t freq; /* TWI frequency */
|
||||
} hal_twi_init_t;
|
||||
|
||||
/**
|
||||
* @brief TWI handle Structure definition
|
||||
*/
|
||||
typedef struct __TWI_HandleTypeDef
|
||||
{
|
||||
NRF_TWI_Type *instance; /* TWI register base address */
|
||||
hal_twi_init_t init; /* TWI initialization parameters */
|
||||
} TWI_HandleTypeDef;
|
||||
|
||||
void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init);
|
||||
|
||||
void hal_twi_master_tx(NRF_TWI_Type * p_instance,
|
||||
uint8_t addr,
|
||||
uint16_t transfer_size,
|
||||
const uint8_t * tx_data,
|
||||
bool stop);
|
||||
|
||||
void hal_twi_master_rx(NRF_TWI_Type * p_instance,
|
||||
uint8_t addr,
|
||||
uint16_t transfer_size,
|
||||
uint8_t * rx_data,
|
||||
bool stop);
|
||||
|
||||
|
||||
void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init);
|
||||
|
||||
|
||||
#endif // HAL_TWI_H__
|
||||
@ -1,115 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "mphalport.h"
|
||||
#include "hal_twi.h"
|
||||
|
||||
#ifdef HAL_TWIE_MODULE_ENABLED
|
||||
|
||||
// EasyDMA variants
|
||||
#define TWI_MASTER_BASE(x) ((NRF_TWIM_Type *)TWI_BASE_POINTERS[x])
|
||||
#define TWI_SLAVE_BASE(x) ((NRF_TWIS_Type *)TWI_BASE_POINTERS[x])
|
||||
|
||||
static const uint32_t hal_twi_frequency_lookup[] = {
|
||||
TWIM_FREQUENCY_FREQUENCY_K100, // 100 kbps
|
||||
TWIM_FREQUENCY_FREQUENCY_K250, // 250 kbps
|
||||
TWIM_FREQUENCY_FREQUENCY_K400, // 400 kbps
|
||||
};
|
||||
|
||||
void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
|
||||
// cast to master type
|
||||
NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
|
||||
|
||||
twim_instance->PSEL.SCL = p_twi_init->scl_pin->pin;
|
||||
twim_instance->PSEL.SDA = p_twi_init->sda_pin->pin;
|
||||
|
||||
#if NRF52840_XXAA
|
||||
twim_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWIM_PSEL_SCL_PORT_Pos);
|
||||
twim_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWIM_PSEL_SDA_PORT_Pos);
|
||||
#endif
|
||||
twim_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq];
|
||||
twim_instance->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
void hal_twi_master_tx(NRF_TWI_Type * p_instance,
|
||||
uint8_t addr,
|
||||
uint16_t transfer_size,
|
||||
const uint8_t * tx_data,
|
||||
bool stop) {
|
||||
// cast to master type
|
||||
NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
|
||||
|
||||
twim_instance->ADDRESS = addr;
|
||||
|
||||
printf("Hal I2C transfer size: %u, addr: %x, stop: %u\n", transfer_size, addr, stop);
|
||||
twim_instance->TXD.MAXCNT = transfer_size;
|
||||
twim_instance->TXD.PTR = (uint32_t)tx_data;
|
||||
|
||||
if (stop) {
|
||||
twim_instance->SHORTS = TWIM_SHORTS_LASTTX_STOP_Msk;
|
||||
} else {
|
||||
twim_instance->SHORTS = TWIM_SHORTS_LASTTX_SUSPEND_Msk;
|
||||
}
|
||||
|
||||
if (twim_instance->EVENTS_SUSPENDED == 1) {
|
||||
printf("Resuming\n");
|
||||
twim_instance->EVENTS_SUSPENDED = 0;
|
||||
twim_instance->EVENTS_STOPPED = 0;
|
||||
twim_instance->TASKS_RESUME = 1; // in case of resume
|
||||
} else {
|
||||
printf("Starting\n");
|
||||
twim_instance->EVENTS_SUSPENDED = 0;
|
||||
twim_instance->EVENTS_STOPPED = 0;
|
||||
twim_instance->TASKS_STARTTX = 1;
|
||||
}
|
||||
|
||||
printf("Going into loop\n");
|
||||
while (twim_instance->EVENTS_STOPPED == 0 && twim_instance->EVENTS_SUSPENDED == 0) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void hal_twi_master_rx(NRF_TWI_Type * p_instance,
|
||||
uint8_t addr,
|
||||
uint16_t transfer_size,
|
||||
const uint8_t * rx_data) {
|
||||
// cast to master type
|
||||
NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
|
||||
|
||||
twim_instance->ADDRESS = addr;
|
||||
|
||||
}
|
||||
|
||||
void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
|
||||
// cast to slave type
|
||||
NRF_TWIS_Type * twis_instance = (NRF_TWIS_Type *)p_instance;
|
||||
(void)twis_instance;
|
||||
}
|
||||
|
||||
#endif // HAL_TWIE_MODULE_ENABLED
|
||||
|
||||
@ -1,180 +0,0 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2016 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "mphalport.h"
|
||||
|
||||
#include "hal_uart.h"
|
||||
#include "hal_irq.h"
|
||||
|
||||
#ifdef HAL_UARTE_MODULE_ENABLED
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#ifndef NRF52
|
||||
#error "Device not supported."
|
||||
#endif
|
||||
|
||||
#define UART_BASE(x) ((NRF_UART_Type *)UART_BASE_POINTERS[x])
|
||||
#define UART_IRQ_NUM(x) (UART_IRQ_VALUES[x])
|
||||
|
||||
#define TX_BUF_SIZE 1
|
||||
#define RX_BUF_SIZE 1
|
||||
|
||||
static const uint32_t hal_uart_baudrate_lookup[] = {
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
|
||||
UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud.
|
||||
};
|
||||
|
||||
void nrf_sendchar(NRF_UART_Type * p_instance, int ch) {
|
||||
hal_uart_char_write(p_instance, ch);
|
||||
}
|
||||
|
||||
void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) {
|
||||
|
||||
NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
|
||||
|
||||
hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
|
||||
hal_gpio_pin_set(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin);
|
||||
hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
|
||||
|
||||
uarte_instance->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]);
|
||||
|
||||
uint32_t hwfc = (p_uart_init->flow_control)
|
||||
? (UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos)
|
||||
: (UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos);
|
||||
|
||||
uint32_t parity = (p_uart_init->use_parity)
|
||||
? (UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos)
|
||||
: (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos);
|
||||
|
||||
uarte_instance->CONFIG = (uint32_t)hwfc | (uint32_t)parity;
|
||||
|
||||
uarte_instance->PSEL.RXD = p_uart_init->rx_pin->pin;
|
||||
uarte_instance->PSEL.TXD = p_uart_init->tx_pin->pin;
|
||||
|
||||
#if NRF52840_XXAA
|
||||
uarte_instance->PSEL.RXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos);
|
||||
uarte_instance->PSEL.TXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos);
|
||||
#endif
|
||||
|
||||
if (hwfc) {
|
||||
hal_gpio_cfg_pin(p_uart_init->cts_pin->port, p_uart_init->cts_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
|
||||
hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
|
||||
hal_gpio_pin_set(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin);
|
||||
|
||||
uarte_instance->PSEL.RTS = p_uart_init->rts_pin->pin;
|
||||
uarte_instance->PSEL.CTS = p_uart_init->cts_pin->pin;
|
||||
|
||||
#if NRF52840_XXAA
|
||||
uarte_instance->PSEL.RTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_RTS_PORT_Pos);
|
||||
uarte_instance->PSEL.CTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_CTS_PORT_Pos);
|
||||
#endif
|
||||
}
|
||||
|
||||
hal_irq_priority(p_uart_init->irq_num, p_uart_init->irq_priority);
|
||||
hal_irq_enable(p_uart_init->irq_num);
|
||||
|
||||
uarte_instance->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
|
||||
uarte_instance->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
|
||||
|
||||
uarte_instance->ENABLE = (UARTE_ENABLE_ENABLE_Enabled << UARTE_ENABLE_ENABLE_Pos);
|
||||
|
||||
uarte_instance->EVENTS_ENDTX = 0;
|
||||
uarte_instance->EVENTS_ENDRX = 0;
|
||||
}
|
||||
|
||||
hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch) {
|
||||
|
||||
NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
|
||||
|
||||
uarte_instance->ERRORSRC = 0;
|
||||
|
||||
|
||||
static volatile uint8_t m_tx_buf[TX_BUF_SIZE];
|
||||
(void)m_tx_buf;
|
||||
|
||||
uarte_instance->INTENCLR = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
|
||||
|
||||
m_tx_buf[0] = ch;
|
||||
|
||||
uarte_instance->TXD.PTR = (uint32_t)((uint8_t *)m_tx_buf);
|
||||
uarte_instance->TXD.MAXCNT = (uint32_t)sizeof(m_tx_buf);
|
||||
|
||||
uarte_instance->TASKS_STARTTX = 1;
|
||||
|
||||
while((0 == uarte_instance->EVENTS_ENDTX));
|
||||
|
||||
uarte_instance->EVENTS_ENDTX = 0;
|
||||
uarte_instance->TASKS_STOPTX = 1;
|
||||
|
||||
uarte_instance->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
|
||||
|
||||
return uarte_instance->ERRORSRC;
|
||||
}
|
||||
|
||||
hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch) {
|
||||
|
||||
NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
|
||||
|
||||
uarte_instance->ERRORSRC = 0;
|
||||
|
||||
static volatile uint8_t m_rx_buf[RX_BUF_SIZE];
|
||||
|
||||
uarte_instance->INTENCLR = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
|
||||
|
||||
uarte_instance->RXD.PTR = (uint32_t)((uint8_t *)m_rx_buf);
|
||||
uarte_instance->RXD.MAXCNT = (uint32_t)sizeof(m_rx_buf);
|
||||
|
||||
uarte_instance->TASKS_STARTRX = 1;
|
||||
|
||||
while ((0 == uarte_instance->EVENTS_ENDRX));
|
||||
|
||||
uarte_instance->EVENTS_ENDRX = 0;
|
||||
uarte_instance->TASKS_STOPRX = 1;
|
||||
|
||||
uarte_instance->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
|
||||
*ch = (uint8_t)m_rx_buf[0];
|
||||
|
||||
return uarte_instance->ERRORSRC;
|
||||
}
|
||||
|
||||
#endif // HAL_UARTE_MODULE_ENABLED
|
||||
@ -33,19 +33,6 @@
|
||||
#include "hal_uart.h"
|
||||
|
||||
#define UART_INSTANCE UART_BASE(0)
|
||||
FIL* boot_output_file;
|
||||
|
||||
// this table converts from HAL_StatusTypeDef to POSIX errno
|
||||
const byte mp_hal_status_to_errno_table[4] = {
|
||||
[HAL_OK] = 0,
|
||||
[HAL_ERROR] = MP_EIO,
|
||||
[HAL_BUSY] = MP_EBUSY,
|
||||
[HAL_TIMEOUT] = MP_ETIMEDOUT,
|
||||
};
|
||||
|
||||
NORETURN void mp_hal_raise(HAL_StatusTypeDef status) {
|
||||
nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(mp_hal_status_to_errno_table[status])));
|
||||
}
|
||||
|
||||
#if (MICROPY_PY_BLE_NUS == 0)
|
||||
int mp_hal_stdin_rx_chr(void) {
|
||||
|
||||
24
ports/nrf/nrfx_config.h
Normal file
24
ports/nrf/nrfx_config.h
Normal file
@ -0,0 +1,24 @@
|
||||
#ifndef NRFX_CONFIG_H__
|
||||
#define NRFX_CONFIG_H__
|
||||
|
||||
// SPI
|
||||
#define NRFX_SPIM_ENABLED 1
|
||||
|
||||
#ifdef NRF52840_XXAA
|
||||
#define NRFX_SPIM3_ENABLED 1
|
||||
#else
|
||||
#define NRFX_SPIM2_ENABLED 1
|
||||
#endif
|
||||
|
||||
#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
|
||||
#define NRFX_SPIM_MISO_PULL_CFG 1
|
||||
|
||||
// TWI aka. I2C
|
||||
#define NRFX_TWIM_ENABLED 1
|
||||
#define NRFX_TWIM0_ENABLED 1
|
||||
|
||||
#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
|
||||
#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY NRF_TWIM_FREQ_400K
|
||||
#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
|
||||
|
||||
#endif
|
||||
242
ports/nrf/nrfx_glue.h
Normal file
242
ports/nrf/nrfx_glue.h
Normal file
@ -0,0 +1,242 @@
|
||||
/**
|
||||
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRFX_GLUE_H__
|
||||
#define NRFX_GLUE_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <drivers/nrfx_common.h>
|
||||
|
||||
/**
|
||||
* @defgroup nrfx_glue nrfx_glue.h
|
||||
* @{
|
||||
* @ingroup nrfx
|
||||
*
|
||||
* @brief This file contains macros that should be implemented according to
|
||||
* the needs of the host environment into which @em nrfx is integrated.
|
||||
*/
|
||||
|
||||
#include <soc/nrfx_irqs.h>
|
||||
|
||||
void __assert_func(const char *file, int line, const char *func, const char *expr);
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/**
|
||||
* @brief Macro for placing a runtime assertion.
|
||||
*
|
||||
* @param expression Expression to evaluate.
|
||||
*/
|
||||
|
||||
#ifndef NDEBUG
|
||||
#define NRFX_ASSERT(expr) ((expr) ? (void)0 : __assert_func(__FILE__, __LINE__, __FUNCTION__, #expr))
|
||||
#else
|
||||
#define NRFX_ASSERT(expr)
|
||||
#endif
|
||||
/**
|
||||
* @brief Macro for placing a compile time assertion.
|
||||
*
|
||||
* @param expression Expression to evaluate.
|
||||
*/
|
||||
#define NRFX_STATIC_ASSERT(expression)
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
#define INTERRUPT_PRIORITY_IS_VALID(pri) ((((pri) > 1) && ((pri) < 4)) || \
|
||||
(((pri) > 4) && ((pri) < 8)))
|
||||
#else
|
||||
#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 8)
|
||||
#endif //SOFTDEVICE_PRESENT
|
||||
|
||||
/**
|
||||
* @brief Macro for setting the priority of a specific IRQ.
|
||||
*
|
||||
* @param irq_number IRQ number.
|
||||
* @param priority Priority to set.
|
||||
*/
|
||||
#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) \
|
||||
_NRFX_IRQ_PRIORITY_SET(irq_number, priority)
|
||||
static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number,
|
||||
uint8_t priority)
|
||||
{
|
||||
//ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority));
|
||||
NVIC_SetPriority(irq_number, priority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Macro for enabling a specific IRQ.
|
||||
*
|
||||
* @param irq_number IRQ number.
|
||||
*/
|
||||
#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number)
|
||||
static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(irq_number);
|
||||
NVIC_EnableIRQ(irq_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Macro for checking if a specific IRQ is enabled.
|
||||
*
|
||||
* @param irq_number IRQ number.
|
||||
*
|
||||
* @retval true If the IRQ is enabled.
|
||||
* @retval false Otherwise.
|
||||
*/
|
||||
#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number)
|
||||
static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
|
||||
{
|
||||
return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Macro for disabling a specific IRQ.
|
||||
*
|
||||
* @param irq_number IRQ number.
|
||||
*/
|
||||
#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number)
|
||||
static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
|
||||
{
|
||||
NVIC_DisableIRQ(irq_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Macro for setting a specific IRQ as pending.
|
||||
*
|
||||
* @param irq_number IRQ number.
|
||||
*/
|
||||
#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number)
|
||||
static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number)
|
||||
{
|
||||
NVIC_SetPendingIRQ(irq_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Macro for clearing the pending status of a specific IRQ.
|
||||
*
|
||||
* @param irq_number IRQ number.
|
||||
*/
|
||||
#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number)
|
||||
static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(irq_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Macro for checking the pending status of a specific IRQ.
|
||||
*
|
||||
* @retval true If the IRQ is pending.
|
||||
* @retval false Otherwise.
|
||||
*/
|
||||
#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number)
|
||||
static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number)
|
||||
{
|
||||
return (NVIC_GetPendingIRQ(irq_number) == 1);
|
||||
}
|
||||
|
||||
//#include <nordic_common.h>
|
||||
//#include <app_util_platform.h>
|
||||
/**
|
||||
* @brief Macro for entering into a critical section.
|
||||
*/
|
||||
#define NRFX_CRITICAL_SECTION_ENTER() CRITICAL_REGION_ENTER()
|
||||
|
||||
/**
|
||||
* @brief Macro for exiting from a critical section.
|
||||
*/
|
||||
#define NRFX_CRITICAL_SECTION_EXIT() CRITICAL_REGION_EXIT()
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/**
|
||||
* @brief When set to a non-zero value, this macro specifies that
|
||||
* @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
|
||||
* A compilation error is generated if the DWT unit is not present
|
||||
* in the SoC used.
|
||||
*/
|
||||
#define NRFX_DELAY_DWT_BASED 0
|
||||
|
||||
#include <soc/nrfx_coredep.h>
|
||||
|
||||
#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time)
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/**
|
||||
* @brief When set to a non-zero value, this macro specifies that the
|
||||
* @ref nrfx_error_codes and the @ref ret_code_t type itself are defined
|
||||
* in a customized way and the default definitions from @c <nrfx_error.h>
|
||||
* should not be used.
|
||||
*/
|
||||
#define NRFX_CUSTOM_ERROR_CODES 0
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/**
|
||||
* @brief Bitmask defining PPI channels reserved to be used outside of nrfx.
|
||||
*/
|
||||
#define NRFX_PPI_CHANNELS_USED NRF_PPI_CHANNELS_USED
|
||||
|
||||
/**
|
||||
* @brief Bitmask defining PPI groups reserved to be used outside of nrfx.
|
||||
*/
|
||||
#define NRFX_PPI_GROUPS_USED NRF_PPI_GROUPS_USED
|
||||
|
||||
/**
|
||||
* @brief Bitmask defining SWI instances reserved to be used outside of nrfx.
|
||||
*/
|
||||
#define NRFX_SWI_USED NRF_SWI_USED
|
||||
|
||||
/**
|
||||
* @brief Bitmask defining TIMER instances reserved to be used outside of nrfx.
|
||||
*/
|
||||
#define NRFX_TIMERS_USED NRF_TIMERS_USED
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRFX_GLUE_H__
|
||||
138
ports/nrf/nrfx_log.h
Normal file
138
ports/nrf/nrfx_log.h
Normal file
@ -0,0 +1,138 @@
|
||||
/**
|
||||
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic
|
||||
* Semiconductor ASA integrated circuit in a product or a software update for
|
||||
* such product, must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRFX_LOG_H__
|
||||
#define NRFX_LOG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup nrfx_log nrfx_log.h
|
||||
* @{
|
||||
* @ingroup nrfx
|
||||
*
|
||||
* @brief This file contains macros that should be implemented according to
|
||||
* the needs of the host environment into which @em nrfx is integrated.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro for logging a message with the severity level ERROR.
|
||||
*
|
||||
* @param format printf-style format string, optionally followed by arguments
|
||||
* to be formatted and inserted in the resulting string.
|
||||
*/
|
||||
#define NRFX_LOG_ERROR(format, ...)
|
||||
|
||||
/**
|
||||
* @brief Macro for logging a message with the severity level WARNING.
|
||||
*
|
||||
* @param format printf-style format string, optionally followed by arguments
|
||||
* to be formatted and inserted in the resulting string.
|
||||
*/
|
||||
#define NRFX_LOG_WARNING(format, ...)
|
||||
|
||||
/**
|
||||
* @brief Macro for logging a message with the severity level INFO.
|
||||
*
|
||||
* @param format printf-style format string, optionally followed by arguments
|
||||
* to be formatted and inserted in the resulting string.
|
||||
*/
|
||||
#define NRFX_LOG_INFO(format, ...)
|
||||
|
||||
/**
|
||||
* @brief Macro for logging a message with the severity level DEBUG.
|
||||
*
|
||||
* @param format printf-style format string, optionally followed by arguments
|
||||
* to be formatted and inserted in the resulting string.
|
||||
*/
|
||||
#define NRFX_LOG_DEBUG(format, ...)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro for logging a memory dump with the severity level ERROR.
|
||||
*
|
||||
* @param[in] p_memory Pointer to the memory region to be dumped.
|
||||
* @param[in] length Length of the memory region in bytes.
|
||||
*/
|
||||
#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
|
||||
|
||||
/**
|
||||
* @brief Macro for logging a memory dump with the severity level WARNING.
|
||||
*
|
||||
* @param[in] p_memory Pointer to the memory region to be dumped.
|
||||
* @param[in] length Length of the memory region in bytes.
|
||||
*/
|
||||
#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
|
||||
|
||||
/**
|
||||
* @brief Macro for logging a memory dump with the severity level INFO.
|
||||
*
|
||||
* @param[in] p_memory Pointer to the memory region to be dumped.
|
||||
* @param[in] length Length of the memory region in bytes.
|
||||
*/
|
||||
#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
|
||||
|
||||
/**
|
||||
* @brief Macro for logging a memory dump with the severity level DEBUG.
|
||||
*
|
||||
* @param[in] p_memory Pointer to the memory region to be dumped.
|
||||
* @param[in] length Length of the memory region in bytes.
|
||||
*/
|
||||
#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro for getting the textual representation of a given error code.
|
||||
*
|
||||
* @param[in] error_code Error code.
|
||||
*
|
||||
* @return String containing the textual representation of the error code.
|
||||
*/
|
||||
#define NRFX_LOG_ERROR_STRING_GET(error_code)
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // NRFX_LOG_H__
|
||||
@ -1,139 +1 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2015 Glenn Ruben Bakke
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
// qstrs specific to this port
|
||||
Q(a)
|
||||
Q(a#)
|
||||
Q(a#:1)
|
||||
Q(a#:3)
|
||||
Q(a2)
|
||||
Q(a4)
|
||||
Q(a4:1)
|
||||
Q(a4:3)
|
||||
Q(a:1)
|
||||
Q(a:2)
|
||||
Q(a:4)
|
||||
Q(a:5)
|
||||
Q(b)
|
||||
Q(b2:1)
|
||||
Q(b3)
|
||||
Q(b4)
|
||||
Q(b4:1)
|
||||
Q(b4:2)
|
||||
Q(b5)
|
||||
Q(b5:1)
|
||||
Q(b:1)
|
||||
Q(b:2)
|
||||
Q(c)
|
||||
Q(c#)
|
||||
Q(c#5)
|
||||
Q(c#5:1)
|
||||
Q(c#5:2)
|
||||
Q(c#:1)
|
||||
Q(c#:8)
|
||||
Q(c2:2)
|
||||
Q(c3)
|
||||
Q(c3:3)
|
||||
Q(c3:4)
|
||||
Q(c4)
|
||||
Q(c4:1)
|
||||
Q(c4:3)
|
||||
Q(c4:4)
|
||||
Q(c5)
|
||||
Q(c5:1)
|
||||
Q(c5:2)
|
||||
Q(c5:3)
|
||||
Q(c5:4)
|
||||
Q(c:1)
|
||||
Q(c:2)
|
||||
Q(c:3)
|
||||
Q(c:4)
|
||||
Q(c:8)
|
||||
Q(d)
|
||||
Q(d#)
|
||||
Q(d#5:2)
|
||||
Q(d#:2)
|
||||
Q(d#:3)
|
||||
Q(d3)
|
||||
Q(d4)
|
||||
Q(d4:1)
|
||||
Q(d5)
|
||||
Q(d5:1)
|
||||
Q(d5:2)
|
||||
Q(d:1)
|
||||
Q(d:2)
|
||||
Q(d:3)
|
||||
Q(d:4)
|
||||
Q(d:5)
|
||||
Q(d:6)
|
||||
Q(d:8)
|
||||
Q(e)
|
||||
Q(e3:3)
|
||||
Q(e4)
|
||||
Q(e4:1)
|
||||
Q(e5)
|
||||
Q(e6:3)
|
||||
Q(e:1)
|
||||
Q(e:2)
|
||||
Q(e:3)
|
||||
Q(e:4)
|
||||
Q(e:5)
|
||||
Q(e:6)
|
||||
Q(e:8)
|
||||
Q(eb:8)
|
||||
Q(f)
|
||||
Q(f#)
|
||||
Q(f#5)
|
||||
Q(f#5:2)
|
||||
Q(f#:1)
|
||||
Q(f#:2)
|
||||
Q(f#:8)
|
||||
Q(f2)
|
||||
Q(f:1)
|
||||
Q(f:2)
|
||||
Q(f:3)
|
||||
Q(f:4)
|
||||
Q(f:8)
|
||||
Q(g)
|
||||
Q(g#)
|
||||
Q(g#:1)
|
||||
Q(g#:3)
|
||||
Q(g3:1)
|
||||
Q(g4)
|
||||
Q(g4:1)
|
||||
Q(g4:2)
|
||||
Q(g5)
|
||||
Q(g5:1)
|
||||
Q(g:1)
|
||||
Q(g:2)
|
||||
Q(g:3)
|
||||
Q(g:8)
|
||||
Q(r)
|
||||
Q(r4:2)
|
||||
Q(r:1)
|
||||
Q(r:2)
|
||||
Q(r:3)
|
||||
|
||||
|
||||
@ -65,10 +65,10 @@
|
||||
//| sine_wave[i] = int(math.sin(math.pi * 2 * i / 18) * (2 ** 15) + 2 ** 15)
|
||||
//|
|
||||
//| dac = audioio.AudioOut(board.SPEAKER)
|
||||
//| sine_wave = audioio.RawSample(sine_wave, mono=True, sample_rate=8000)
|
||||
//| sine_wave = audioio.RawSample(sine_wave, sample_rate=8000)
|
||||
//| dac.play(sine_wave, loop=True)
|
||||
//| time.sleep(1)
|
||||
//| sample.stop()
|
||||
//| dac.stop()
|
||||
//|
|
||||
//| Playing a wave file from flash::
|
||||
//|
|
||||
|
||||
@ -70,7 +70,7 @@
|
||||
//| sine_wave = audioio.RawSample(sine_wave)
|
||||
//| dac.play(sine_wave, loop=True)
|
||||
//| time.sleep(1)
|
||||
//| sample.stop()
|
||||
//| dac.stop()
|
||||
//|
|
||||
STATIC mp_obj_t audioio_rawsample_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *pos_args) {
|
||||
mp_arg_check_num(n_args, n_kw, 1, 2, true);
|
||||
|
||||
@ -65,12 +65,15 @@ void common_hal_storage_mount(mp_obj_t vfs_obj, const char* mount_path, bool rea
|
||||
args[1] = mp_const_false; // Don't make the file system automatically when mounting.
|
||||
|
||||
// Check that there's no file or directory with the same name as the mount point.
|
||||
nlr_buf_t nlr;
|
||||
if (nlr_push(&nlr) == 0) {
|
||||
common_hal_os_stat(mount_path);
|
||||
nlr_pop();
|
||||
// Something with the same name exists.
|
||||
mp_raise_OSError(MP_EEXIST);
|
||||
// But it's ok to mount '/' in any case.
|
||||
if (strcmp(vfs->str, "/") != 0) {
|
||||
nlr_buf_t nlr;
|
||||
if (nlr_push(&nlr) == 0) {
|
||||
common_hal_os_stat(mount_path);
|
||||
nlr_pop();
|
||||
// Something with the same name exists.
|
||||
mp_raise_OSError(MP_EEXIST);
|
||||
}
|
||||
}
|
||||
|
||||
// check that the destination mount point is unused
|
||||
|
||||
Loading…
Reference in New Issue
Block a user