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address review comments

This commit is contained in:
Dan Halbert 2019-12-11 15:43:06 -05:00
parent 1e11f2708b
commit ae64a669dd
5 changed files with 17 additions and 26 deletions
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22
ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c
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@ -213,17 +213,17 @@ void frequencyin_samd51_start_dpll() {
// Will also enable the Lock Bypass due to low-frequency sources causing DPLL unlocks // Will also enable the Lock Bypass due to low-frequency sources causing DPLL unlocks
// as outlined in the Errata (1.12.1) // as outlined in the Errata (1.12.1)
OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(2999); OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(2999);
if (BOARD_HAS_CRYSTAL) { // we can use XOSC32K directly as the source #if BOARD_HAS_CRYSTAL
OSC32KCTRL->XOSC32K.bit.EN32K = 1; // we can use XOSC32K directly as the source
OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(1) | OSC32KCTRL->XOSC32K.bit.EN32K = 1;
OSCCTRL_DPLLCTRLB_LBYPASS; OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(1) | OSCCTRL_DPLLCTRLB_LBYPASS;
} else { #else
// can't use OSCULP32K directly; need to setup a GCLK as a reference, // can't use OSCULP32K directly; need to setup a GCLK as a reference,
// which must be done in samd/clocks.c to avoid waiting for sync // which must be done in samd/clocks.c to avoid waiting for sync
return; return;
//OSC32KCTRL->OSCULP32K.bit.EN32K = 1; //OSC32KCTRL->OSCULP32K.bit.EN32K = 1;
//OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(0); //OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(0);
} #endif
OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE; OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
while (!(OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY)) {} while (!(OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY)) {}

12
ports/nrf/README.md
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@ -5,21 +5,13 @@ This is a port of CircuitPython to the Nordic Semiconductor nRF52 series of chip
> **NOTE**: There are board-specific READMEs that may be more up to date than the > **NOTE**: There are board-specific READMEs that may be more up to date than the
generic board-neutral documentation below. generic board-neutral documentation below.
## Compile and Flash ## Flash
Prerequisite steps for building the nrf port:
git clone <URL>.git circuitpython
cd circuitpython
git submodule update --init --recursive
make -C mpy-cross
Some boards have UF2 bootloaders and can simply be flashed in the normal way, by copying Some boards have UF2 bootloaders and can simply be flashed in the normal way, by copying
firmware.uf2 to the BOOT drive. firmware.uf2 to the BOOT drive.
To build and flash issue the following command inside the ports/nrf/ folder: For some boards, you can use the `flash` target:
make BOARD=pca10056
make BOARD=pca10056 flash make BOARD=pca10056 flash
## Segger Targets ## Segger Targets

2
ports/nrf/common-hal/_bleio/Adapter.c
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@ -59,8 +59,8 @@ const nvm_bytearray_obj_t common_hal_bleio_nvm_obj = {
.base = { .base = {
.type = &nvm_bytearray_type, .type = &nvm_bytearray_type,
}, },
.len = CIRCUITPY_BLE_CONFIG_SIZE,
.start_address = (uint8_t*) CIRCUITPY_BLE_CONFIG_START_ADDR, .start_address = (uint8_t*) CIRCUITPY_BLE_CONFIG_START_ADDR,
.len = CIRCUITPY_BLE_CONFIG_SIZE,
}; };
STATIC void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) { STATIC void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) {

5
ports/nrf/mpconfigport.h
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@ -81,12 +81,10 @@
// firmware // firmware
// internal CIRCUITPY flash filesystem (optional) // internal CIRCUITPY flash filesystem (optional)
// BLE config (bonding info, etc.) (optional) // BLE config (bonding info, etc.) (optional)
// microntroller.nvm (optional) // microcontroller.nvm (optional)
// bootloader (note the MBR at 0x0 redirects to the bootloader here, in high flash) // bootloader (note the MBR at 0x0 redirects to the bootloader here, in high flash)
// bootloader settings // bootloader settings
// Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld
// Define these regions starting up from the bottom of flash: // Define these regions starting up from the bottom of flash:
#define MBR_START_ADDR (0x0) #define MBR_START_ADDR (0x0)
@ -101,6 +99,7 @@
// Define these regions starting down from the bootloader: // Define these regions starting down from the bootloader:
// Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld
#define BOOTLOADER_START_ADDR (0x000F4000) #define BOOTLOADER_START_ADDR (0x000F4000)
#define BOOTLOADER_SIZE (0xA000) // 40kiB #define BOOTLOADER_SIZE (0xA000) // 40kiB
#define BOOTLOADER_SETTINGS_START_ADDR (0x000FF000) #define BOOTLOADER_SETTINGS_START_ADDR (0x000FF000)