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Override HAL_Delay and HAL_GetTick

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This commit is contained in:
Lucian Copeland 2020-06-05 11:42:34 -04:00
parent a0977cac7b
commit ad0971fb25
5 changed files with 33 additions and 7 deletions
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2
ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h
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@ -37,7 +37,7 @@
#ifndef CPY_CLK_PLLN #ifndef CPY_CLK_PLLN
#define CPY_CLK_PLLN (336) #define CPY_CLK_PLLN (336)
#endif #endif
#ifndef (CPY_CLK_PLLP #ifndef CPY_CLK_PLLP
#define CPY_CLK_PLLP (RCC_PLLP_DIV4) #define CPY_CLK_PLLP (RCC_PLLP_DIV4)
#endif #endif
#ifndef CPY_CLK_PLLQ #ifndef CPY_CLK_PLLQ

2
ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h
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@ -32,7 +32,7 @@
// Note - the actual maximum frequency is 100MHz, but this requires divisors // Note - the actual maximum frequency is 100MHz, but this requires divisors
// which are incompatible with USB, and there is no additional PLL such as on // which are incompatible with USB, and there is no additional PLL such as on
// the F412. // the F412.
// Defaults: // Defaults:
#ifndef CPY_CLK_VSCALE #ifndef CPY_CLK_VSCALE

2
ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h
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@ -30,7 +30,7 @@
// Line Type: Access Line // Line Type: Access Line
// Speed: 200MHz (MAX) // Speed: 200MHz (MAX)
// Note - uses the I2S PLL for SUSB to enable full 100MHz operation, since USB // Note - uses the I2S PLL for SUSB to enable full 100MHz operation, since USB
// can't get the right divisors from 100MHz PLL settings. // can't get the right divisors from 100MHz PLL settings.
// Defaults: // Defaults:

2
ports/stm/peripherals/stm32h7/clocks.c
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@ -120,4 +120,4 @@ void stm32_peripherals_clocks_init(void) {
if (lse_failure) { if (lse_failure) {
reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT? reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT?
} }
} }

32
ports/stm/supervisor/port.c
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@ -147,9 +147,10 @@ __attribute__((used, naked)) void Reset_Handler(void) {
__enable_irq(); __enable_irq();
main(); main();
} }
#endif //end H7 specific code #endif //end H7 specific code
// Low power clock variables
static volatile uint32_t systick_ms;
static RTC_HandleTypeDef _hrtc; static RTC_HandleTypeDef _hrtc;
#if BOARD_HAS_LOW_SPEED_CRYSTAL #if BOARD_HAS_LOW_SPEED_CRYSTAL
@ -159,7 +160,7 @@ static uint32_t rtc_clock_frequency = LSI_VALUE;
#endif #endif
safe_mode_t port_init(void) { safe_mode_t port_init(void) {
HAL_Init(); HAL_Init(); // Turns on SysTick
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
#if (CPY_STM32F4) #if (CPY_STM32F4)
@ -182,13 +183,38 @@ safe_mode_t port_init(void) {
HAL_RTC_Init(&_hrtc); HAL_RTC_Init(&_hrtc);
HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
// Turn off SysTick
SysTick->CTRL = 0;
return NO_SAFE_MODE; return NO_SAFE_MODE;
} }
void HAL_Delay(uint32_t delay_ms) {
if (SysTick->CTRL != 0) {
// SysTick is on, so use it
uint32_t tickstart = systick_ms;
while (systick_ms - tickstart < delay_ms) {
}
} else {
mp_hal_delay_ms(delay_ms);
}
}
uint32_t HAL_GetTick() {
if (SysTick->CTRL != 0) {
return systick_ms;
} else {
uint8_t subticks;
uint32_t result = (uint32_t)port_get_raw_ticks(&subticks);
return result;
}
}
void SysTick_Handler(void) { void SysTick_Handler(void) {
systick_ms += 1;
// Read the CTRL register to clear the SysTick interrupt. // Read the CTRL register to clear the SysTick interrupt.
SysTick->CTRL; SysTick->CTRL;
HAL_IncTick();
} }
void reset_port(void) { void reset_port(void) {