diff --git a/lib/tinyusb b/lib/tinyusb
index ec9c666107..e3b3229d61 160000
--- a/lib/tinyusb
+++ b/lib/tinyusb
@@ -1 +1 @@
-Subproject commit ec9c666107c0be0f8dc7c2a15e3bdea8c44a50b4
+Subproject commit e3b3229d61676585879c81d5f2e3393a2a1f1b16
diff --git a/ports/mimxrt10xx/Makefile b/ports/mimxrt10xx/Makefile
index 72f4d191ef..b10466bb2d 100644
--- a/ports/mimxrt10xx/Makefile
+++ b/ports/mimxrt10xx/Makefile
@@ -34,10 +34,11 @@ INC += \
 	-I../../lib/tinyusb/src \
 	-I../../supervisor/shared/usb \
 	-I$(BUILD) \
-	-Iboards/ \
+	-Iboards \
 	-Iboards/$(BOARD) \
 	-Iperipherals/ \
 	-Iperipherals/mimxrt10xx/ \
+	-Isdk/CMSIS/Include/ \
 	-Isdk/devices/$(CHIP_FAMILY) \
 	-Isdk/devices/$(CHIP_FAMILY)/drivers \
 	-Isdk/drivers/common
@@ -48,7 +49,7 @@ CFLAGS += -ftree-vrp -DNDEBUG
 
 # TinyUSB defines
 CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX -DCFG_TUD_CDC_RX_BUFSIZE=512 -DCFG_TUD_CDC_TX_BUFSIZE=512
-ifeq ($(CHIP_FAMILY), MIMXRT1011)
+ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),MIMXRT1011 MIMXRT1015))
 CFLAGS += -DCFG_TUD_MIDI_RX_BUFSIZE=64 -DCFG_TUD_MIDI_TX_BUFSIZE=64 -DCFG_TUD_MSC_BUFSIZE=512
 else
 CFLAGS += -DCFG_TUD_MIDI_RX_BUFSIZE=512 -DCFG_TUD_MIDI_TX_BUFSIZE=512 -DCFG_TUD_MSC_BUFSIZE=1024
@@ -75,7 +76,7 @@ CFLAGS += \
 	-mfloat-abi=hard \
 	-mfpu=fpv5-sp-d16 \
 	-DCPU_$(CHIP_VARIANT) \
-	-DIMXRT10XX \
+	-DIMXRT1XXX \
 	-g3 -Wno-unused-parameter \
 	-ffunction-sections -fdata-sections -fstack-usage
 
@@ -100,14 +101,27 @@ ifndef INTERNAL_LIBM
 LIBS += -lm
 endif
 
-LDFLAGS += -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-sp-d16 -mthumb -mapcs
+ifndef CHIP_CORE
+CHIP_CORE = $(CHIP_FAMILY)
+endif
+
+# If not empty, then it is 10xx.
+ifneq ($(findstring MIMXRT10, $(CHIP_FAMILY)),)
+CFLAGS += -DIMXRT10XX=1 -DIMXRT11XX=0
+MIMXRT10xx = $(CHIP_FAMILY)
 BOOTLOADER_SIZE := 0x6000C000
+else
+CFLAGS += -DIMXRT11XX=1 -DIMXRT10XX=0
+MIMXRT11xx = $(CHIP_FAMILY)
+BOOTLOADER_SIZE := 0x3000C000
+endif
+
+LDFLAGS += -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-sp-d16 -mthumb -mapcs
 
 SRC_SDK := \
 	devices/$(CHIP_FAMILY)/drivers/fsl_clock.c \
-	devices/$(CHIP_FAMILY)/system_$(CHIP_FAMILY).c \
+	devices/$(CHIP_FAMILY)/system_$(CHIP_CORE).c \
 	devices/$(CHIP_FAMILY)/xip/fsl_flexspi_nor_boot.c \
-	drivers/adc_12b1msps_sar/fsl_adc.c \
 	drivers/cache/armv7-m7/fsl_cache.c \
 	drivers/common/fsl_common_arm.c \
 	drivers/common/fsl_common.c \
@@ -121,11 +135,23 @@ SRC_SDK := \
 	drivers/sai/fsl_sai.c \
 	drivers/snvs_hp/fsl_snvs_hp.c \
 	drivers/snvs_lp/fsl_snvs_lp.c \
-	drivers/tempmon/fsl_tempmon.c \
 	drivers/trng/fsl_trng.c \
 
+ifeq ($(CIRCUITPY_ANALOGIO), 1)
+SRC_SDK +=	drivers/adc_12b1msps_sar/fsl_adc.c \
+	drivers/tempmon/fsl_tempmon.c
+endif
+
+ifeq ($(CHIP_FAMILY), MIMXRT1176)
+SRC_SDK += devices/$(CHIP_FAMILY)/drivers/fsl_anatop_ai.c \
+	devices/$(CHIP_FAMILY)/drivers/fsl_dcdc.c \
+	devices/$(CHIP_FAMILY)/drivers/fsl_pmu.c
+endif
+
 SRC_SDK := $(addprefix sdk/, $(SRC_SDK))
 
+$(addprefix $(BUILD)/, $(SRC_SDK:.c=.o)): CFLAGS += -Wno-array-bounds
+
 SRC_C += \
 	background.c \
 	boards/$(BOARD)/board.c \
@@ -156,7 +182,7 @@ SRC_SHARED_MODULE_EXPANDED = $(addprefix shared-bindings/, $(SRC_SHARED_MODULE))
                              $(addprefix shared-module/, $(SRC_SHARED_MODULE_INTERNAL))
 
 SRC_S = \
-    sdk/devices/$(CHIP_FAMILY)/gcc/startup_$(CHIP_FAMILY).S \
+    sdk/devices/$(CHIP_FAMILY)/gcc/startup_$(CHIP_CORE).S \
     supervisor/cpu.S
 
 OBJ = $(PY_O) $(SUPERVISOR_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
diff --git a/ports/mimxrt10xx/boards/board.h b/ports/mimxrt10xx/boards/board.h
index e6736806ed..f00fea6be9 100644
--- a/ports/mimxrt10xx/boards/board.h
+++ b/ports/mimxrt10xx/boards/board.h
@@ -27,3 +27,4 @@
 #include "mpconfigboard.h"
 
 #define XIP_BOOT_HEADER_ENABLE (1)
+#define XIP_EXTERNAL_FLASH (1)
diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board.c b/ports/mimxrt10xx/boards/imxrt1010_evk/board.c
index b839ffa666..c5237c8a8e 100644
--- a/ports/mimxrt10xx/boards/imxrt1010_evk/board.c
+++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board.c
@@ -42,8 +42,8 @@ const mcu_pin_obj_t *mimxrt10xx_reset_forbidden_pins[] = {
     &pin_GPIO_SD_07,
     &pin_GPIO_SD_06,
     // USB Pins
-    &pin_GPIO_12,
-    &pin_GPIO_13,
+    &pin_USB_OTG1_DN,
+    &pin_USB_OTG1_DP,
     NULL,                       // Must end in NULL.
 };
 
diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c
index f15a3f3459..383a8ba1d1 100644
--- a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c
+++ b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c
@@ -37,7 +37,7 @@ const flexspi_nor_config_t qspiflash_config = {
         .deviceModeArg = 0x02,
         .deviceType = kFLEXSPIDeviceType_SerialNOR,
         .sflashPadType = kSerialFlash_4Pads,
-        .serialClkFreq = kFLEXSPISerialClk_60MHz,
+        .serialClkFreq = kFLEXSPISerialClk_133MHz,
         .sflashA1Size = FLASH_SIZE,
         .lookupTable =
         {
diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h b/ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h
index 192c265f88..2ae3a8b6f1 100644
--- a/ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h
+++ b/ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h
@@ -17,7 +17,7 @@
 #define DEFAULT_UART_BUS_RX (&pin_GPIO_09)
 #define DEFAULT_UART_BUS_TX (&pin_GPIO_10)
 
-#define CIRCUITPY_CONSOLE_UART_RX (&pin_GPIO_09)
-#define CIRCUITPY_CONSOLE_UART_TX (&pin_GPIO_10)
+// #define CIRCUITPY_CONSOLE_UART_RX (&pin_GPIO_09)
+// #define CIRCUITPY_CONSOLE_UART_TX (&pin_GPIO_10)
 
 #define MICROPY_HW_LED_STATUS (&pin_GPIO_11)
diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/board.c b/ports/mimxrt10xx/boards/imxrt1015_evk/board.c
new file mode 100644
index 0000000000..568945a3eb
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1015_evk/board.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "supervisor/board.h"
+#include "shared-bindings/microcontroller/Pin.h"
+
+// These pins should never ever be reset; doing so could interfere with basic operation.
+// Used in common-hal/microcontroller/Pin.c
+const mcu_pin_obj_t *mimxrt10xx_reset_forbidden_pins[] = {
+    &pin_GPIO_AD_B0_00, // SWDIO
+    &pin_GPIO_AD_B0_01, // SWCLK
+    // FLEX flash
+    &pin_GPIO_SD_B1_06,
+    &pin_GPIO_SD_B1_07,
+    &pin_GPIO_SD_B1_08,
+    &pin_GPIO_SD_B1_09,
+    &pin_GPIO_SD_B1_10,
+    &pin_GPIO_SD_B1_11,
+    // USB Pins
+    &pin_USB_OTG1_DN,
+    &pin_USB_OTG1_DP,
+    NULL,                       // Must end in NULL.
+};
+
+// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.
diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1015_evk/flash_config.c
new file mode 100644
index 0000000000..f15a3f3459
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1015_evk/flash_config.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "boards/flash_config.h"
+
+#include "xip/fsl_flexspi_nor_boot.h"
+
+// Config for AT25SF128A with QSPI routed.
+__attribute__((section(".boot_hdr.conf")))
+const flexspi_nor_config_t qspiflash_config = {
+    .pageSize = 256u,
+    .sectorSize = 4u * 1024u,
+    .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz,
+    .blockSize = 0x00010000,
+    .isUniformBlockSize = false,
+    .memConfig =
+    {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+
+        .busyOffset = 0u,     // Status bit 0 indicates busy.
+        .busyBitPolarity = 0u,     // Busy when the bit is 1.
+
+        .deviceModeCfgEnable = 1u,
+        .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+        .deviceModeSeq = {
+            .seqId = 4u,
+            .seqNum = 1u,
+        },
+        .deviceModeArg = 0x02,
+        .deviceType = kFLEXSPIDeviceType_SerialNOR,
+        .sflashPadType = kSerialFlash_4Pads,
+        .serialClkFreq = kFLEXSPISerialClk_60MHz,
+        .sflashA1Size = FLASH_SIZE,
+        .lookupTable =
+        {
+            // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
+            // The high 16 bits is command 1 and the low are command 0.
+            // Within a command, the top 6 bits are the opcode, the next two are the number
+            // of pads and then last byte is the operand. The operand's meaning changes
+            // per opcode.
+
+            // Indices with ROM should always have the same function because the ROM
+            // bootloader uses it.
+
+            // 0: ROM: Read LUTs
+            // Quad version
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xEB /* the command to send */,
+                RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+                FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+                    READ_SDR,  FLEXSPI_4PAD, 0x04),
+                // Single fast read version, good for debugging.
+                // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x0B /* the command to send */,
+                //                 RADDR_SDR, FLEXSPI_1PAD, 24  /* bits to transmit */),
+                // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+                //                 READ_SDR,  FLEXSPI_1PAD, 0x04),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 1: ROM: Read status
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,  FLEXSPI_1PAD, 0x05 /* the command to send */,
+                READ_SDR, FLEXSPI_1PAD, 0x02),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 2: Empty
+            EMPTY_SEQUENCE,
+
+            // 3: ROM: Write Enable
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+                STOP,    FLEXSPI_1PAD, 0x00),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 4: Config: Write Status
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x31 /* the command to send */,
+                WRITE_SDR, FLEXSPI_1PAD, 0x01),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 5: ROM: Erase Sector
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x20 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 6: Empty
+            EMPTY_SEQUENCE,
+
+            // 7: Empty
+            EMPTY_SEQUENCE,
+
+            // 8: Block Erase
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xD8 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 9: ROM: Page program
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x02 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+                FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+                    STOP,      FLEXSPI_1PAD, 0),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 10: Empty
+            EMPTY_SEQUENCE,
+
+            // 11: ROM: Chip erase
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+                STOP,    FLEXSPI_1PAD, 0),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 12: Empty
+            EMPTY_SEQUENCE,
+
+            // 13: ROM: Read SFDP
+            EMPTY_SEQUENCE,
+
+            // 14: ROM: Restore no cmd
+            EMPTY_SEQUENCE,
+
+            // 15: ROM: Dummy
+            EMPTY_SEQUENCE
+        },
+    },
+};
diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/mpconfigboard.h b/ports/mimxrt10xx/boards/imxrt1015_evk/mpconfigboard.h
new file mode 100644
index 0000000000..ff2fe55319
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1015_evk/mpconfigboard.h
@@ -0,0 +1,24 @@
+#define MICROPY_HW_BOARD_NAME "IMXRT1015-EVK"
+#define MICROPY_HW_MCU_NAME "IMXRT1015DAF5A"
+
+// If you change this, then make sure to update the linker scripts as well to
+// make sure you don't overwrite code
+#define CIRCUITPY_INTERNAL_NVM_SIZE 0
+
+#define BOARD_FLASH_SIZE (16 * 1024 * 1024)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_AD_B0_10)
+#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_AD_B0_12)
+#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_AD_B0_13)
+
+#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_15)
+#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_14)
+
+#define DEFAULT_UART_BUS_RX (&pin_GPIO_EMC_33)
+#define DEFAULT_UART_BUS_TX (&pin_GPIO_EMC_32)
+
+// #define CIRCUITPY_CONSOLE_UART_RX (&pin_GPIO_AD_B0_07)
+// #define CIRCUITPY_CONSOLE_UART_TX (&pin_GPIO_AD_B0_06)
+
+#define MICROPY_HW_LED_STATUS (&pin_GPIO_SD_B1_00)
+#define MICROPY_HW_LED_STATUS_INVERTED (1)
diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/mpconfigboard.mk b/ports/mimxrt10xx/boards/imxrt1015_evk/mpconfigboard.mk
new file mode 100644
index 0000000000..0f446e13bf
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1015_evk/mpconfigboard.mk
@@ -0,0 +1,8 @@
+USB_VID = 0x239A
+USB_PID = 0x8078
+USB_PRODUCT = "IMXRT1015-EVK"
+USB_MANUFACTURER = "NXP"
+
+CHIP_VARIANT = MIMXRT1015DAF5A
+CHIP_FAMILY = MIMXRT1015
+FLASH = AT25SF128A
diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/pins.c b/ports/mimxrt10xx/boards/imxrt1015_evk/pins.c
new file mode 100644
index 0000000000..abe2e8e746
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1015_evk/pins.c
@@ -0,0 +1,76 @@
+#include "shared-bindings/board/__init__.h"
+
+#include "supervisor/board.h"
+
+STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
+    CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_EMC_33) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_EMC_33) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_EMC_32) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_EMC_32) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_EMC_20) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_EMC_26) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_EMC_34) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_EMC_27) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_EMC_21) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_EMC_22) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_SD_B1_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO_SD_B1_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_GPIO_SD_B1_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_GPIO_SD_B1_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_USER_SW), MP_ROM_PTR(&pin_GPIO_EMC_09) },
+
+    // Audio Interface
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_EMC_08) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_SYNC), MP_ROM_PTR(&pin_GPIO_EMC_27) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_BCLK), MP_ROM_PTR(&pin_GPIO_EMC_26) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_EMC_21) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_EMC_25) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_EMC_20) },
+
+    // SPDIF
+    { MP_ROM_QSTR(MP_QSTR_SPDIF_IN), MP_ROM_PTR(&pin_GPIO_EMC_05) },
+    { MP_ROM_QSTR(MP_QSTR_SPDIF_OUT), MP_ROM_PTR(&pin_GPIO_EMC_04) },
+
+    // J29 UART LPUART4
+    { MP_ROM_QSTR(MP_QSTR_J29_TX), MP_ROM_PTR(&pin_GPIO_EMC_32) },
+    { MP_ROM_QSTR(MP_QSTR_J29_RX), MP_ROM_PTR(&pin_GPIO_EMC_33) },
+
+    // J30 UART LPUART3
+    { MP_ROM_QSTR(MP_QSTR_J30_TX), MP_ROM_PTR(&pin_GPIO_EMC_06) },
+    { MP_ROM_QSTR(MP_QSTR_J30_RX), MP_ROM_PTR(&pin_GPIO_EMC_07) },
+
+    // Freelink UART
+    { MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_06) },
+    { MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_07) },
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board.c b/ports/mimxrt10xx/boards/imxrt1020_evk/board.c
index afbc0c58b5..f814afd956 100644
--- a/ports/mimxrt10xx/boards/imxrt1020_evk/board.c
+++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board.c
@@ -44,8 +44,8 @@ const mcu_pin_obj_t *mimxrt10xx_reset_forbidden_pins[] = {
     &pin_GPIO_SD_B1_11,
 
     // USB Pins
-    &pin_GPIO_AD_B1_11,
-    &pin_GPIO_AD_B1_12,
+    &pin_USB_OTG1_DN,
+    &pin_USB_OTG1_DP,
     NULL,                       // Must end in NULL.
 };
 
diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c
index 2ae8ae9b76..47293c22b9 100644
--- a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c
+++ b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c
@@ -21,7 +21,7 @@ const flexspi_nor_config_t qspiflash_config = {
     {
         .tag = FLEXSPI_CFG_BLK_TAG,
         .version = FLEXSPI_CFG_BLK_VERSION,
-        .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad,
+        .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromSckPad,
         .csHoldTime = 3u,
         .csSetupTime = 3u,
 
diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/board.c b/ports/mimxrt10xx/boards/imxrt1040_evk/board.c
new file mode 100644
index 0000000000..0e97d87b60
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1040_evk/board.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "supervisor/board.h"
+#include "shared-bindings/microcontroller/Pin.h"
+
+// These pins should never ever be reset; doing so could interfere with basic operation.
+// Used in common-hal/microcontroller/Pin.c
+const mcu_pin_obj_t *mimxrt10xx_reset_forbidden_pins[] = {
+    // SWD Pins
+    &pin_GPIO_AD_B0_06, // SWDIO
+    &pin_GPIO_AD_B0_07, // SWCLK
+
+    // FLEXSPI QSPI
+    &pin_GPIO_SD_B1_05,
+    &pin_GPIO_SD_B1_06,
+    &pin_GPIO_SD_B1_07,
+    &pin_GPIO_SD_B1_08,
+    &pin_GPIO_SD_B1_09,
+    &pin_GPIO_SD_B1_10,
+    &pin_GPIO_SD_B1_11,
+
+    &pin_USB_OTG1_DN,
+    &pin_USB_OTG1_DP,
+
+    NULL,                       // Must end in NULL.
+};
+
+// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.
diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1040_evk/flash_config.c
new file mode 100644
index 0000000000..e68d9f9312
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1040_evk/flash_config.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "boards/flash_config.h"
+
+#include "xip/fsl_flexspi_nor_boot.h"
+
+// Config for W25Q64JVSSIQ with QSPI routed.
+__attribute__((section(".boot_hdr.conf")))
+const flexspi_nor_config_t qspiflash_config = {
+    .pageSize = 256u,
+    .sectorSize = 4u * 1024u,
+    .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz,
+    .blockSize = 0x00010000,
+    .isUniformBlockSize = false,
+    .memConfig =
+    {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromSckPad,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+
+        .busyOffset = 0u,     // Status bit 0 indicates busy.
+        .busyBitPolarity = 0u,     // Busy when the bit is 1.
+
+        .deviceModeCfgEnable = 1u,
+        .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+        .deviceModeSeq = {
+            .seqId = 4u,
+            .seqNum = 1u,
+        },
+        .deviceModeArg = 0x40,
+        .deviceType = kFLEXSPIDeviceType_SerialNOR,
+        .sflashPadType = kSerialFlash_4Pads,
+        .serialClkFreq = kFLEXSPISerialClk_60MHz,
+        .sflashA1Size = FLASH_SIZE,
+        .lookupTable =
+        {
+            // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
+            // The high 16 bits is command 1 and the low are command 0.
+            // Within a command, the top 6 bits are the opcode, the next two are the number
+            // of pads and then last byte is the operand. The operand's meaning changes
+            // per opcode.
+
+            // Indices with ROM should always have the same function because the ROM
+            // bootloader uses it.
+
+            // 0: ROM: Read LUTs
+            // Quad version
+            SEQUENCE(
+                FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xEB /* the command to send */,
+                    RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+                FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+                    READ_SDR,  FLEXSPI_4PAD, 0x04),
+                // Single fast read version, good for debugging.
+                // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x0B /* the command to send */,
+                //                 RADDR_SDR, FLEXSPI_1PAD, 24  /* bits to transmit */),
+                // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+                //                 READ_SDR,  FLEXSPI_1PAD, 0x04),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 1: ROM: Read status
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,  FLEXSPI_1PAD, 0x05 /* the command to send */,
+                READ_SDR, FLEXSPI_1PAD, 0x02),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 2: Empty
+            EMPTY_SEQUENCE,
+
+            // 3: ROM: Write Enable
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+                STOP,    FLEXSPI_1PAD, 0x00),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 4: Config: Write Status
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x01 /* the command to send */,
+                WRITE_SDR, FLEXSPI_1PAD, 0x01),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 5: ROM: Erase Sector
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x20 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 6: Empty
+            EMPTY_SEQUENCE,
+
+            // 7: Empty
+            EMPTY_SEQUENCE,
+
+            // 8: Block Erase
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xD8 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 9: ROM: Page program
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x02 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+                FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+                    STOP,      FLEXSPI_1PAD, 0),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 10: Empty
+            EMPTY_SEQUENCE,
+
+            // 11: ROM: Chip erase
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+                STOP,    FLEXSPI_1PAD, 0),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 12: Empty
+            EMPTY_SEQUENCE,
+
+            // 13: ROM: Read SFDP
+            EMPTY_SEQUENCE,
+
+            // 14: ROM: Restore no cmd
+            EMPTY_SEQUENCE,
+
+            // 15: ROM: Dummy
+            EMPTY_SEQUENCE
+        },
+    },
+};
diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/mpconfigboard.h b/ports/mimxrt10xx/boards/imxrt1040_evk/mpconfigboard.h
new file mode 100644
index 0000000000..dd1cf9f759
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1040_evk/mpconfigboard.h
@@ -0,0 +1,22 @@
+#define MICROPY_HW_BOARD_NAME "iMX RT 1040 EVK"
+#define MICROPY_HW_MCU_NAME "IMXRT1042XJM5B"
+
+// If you change this, then make sure to update the linker scripts as well to
+// make sure you don't overwrite code
+#define CIRCUITPY_INTERNAL_NVM_SIZE 0
+
+#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
+
+#define MICROPY_HW_LED_STATUS (&pin_GPIO_AD_B0_08)
+#define MICROPY_HW_LED_STATUS_INVERTED (1)
+
+#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_00)
+#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_01)
+
+#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B1_07)
+#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B1_06)
+
+#define CIRCUITPY_CONSOLE_UART_TX (&pin_GPIO_AD_B0_12)
+#define CIRCUITPY_CONSOLE_UART_RX (&pin_GPIO_AD_B0_13)
+
+// If you want to connect over SWD, then make sure J80 is open.
diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/mpconfigboard.mk b/ports/mimxrt10xx/boards/imxrt1040_evk/mpconfigboard.mk
new file mode 100644
index 0000000000..cf351d906e
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1040_evk/mpconfigboard.mk
@@ -0,0 +1,8 @@
+USB_VID = 0x239A
+USB_PID = 0x8084
+USB_PRODUCT = "iMX RT 1040 EVK"
+USB_MANUFACTURER = "NXP"
+
+CHIP_VARIANT = MIMXRT1042XJM5B
+CHIP_FAMILY = MIMXRT1042
+FLASH = W25Q64JV
diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/pins.c b/ports/mimxrt10xx/boards/imxrt1040_evk/pins.c
new file mode 100644
index 0000000000..4cabdddc55
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1040_evk/pins.c
@@ -0,0 +1,123 @@
+#include "shared-bindings/board/__init__.h"
+
+#include "supervisor/board.h"
+
+STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
+    CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_SD_B1_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_SD_B1_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_SD_B1_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_SD_B1_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_B1_14) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_B1_15) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
+
+    // i2c sensor is on I2C1_SCL/SDA
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_08) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_08) },
+
+    // SD Card / Wifi
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_GPIO_B1_12) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_D0), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_D1), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_D2), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_D3), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_PWREN), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
+
+    // LCD Interface
+    { MP_ROM_QSTR(MP_QSTR_LCD_BACKLIGHT), MP_ROM_PTR(&pin_GPIO_B1_15) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_RST), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_ENABLE), MP_ROM_PTR(&pin_GPIO_B0_01) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_VSYNC), MP_ROM_PTR(&pin_GPIO_B0_03) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_HSYNC), MP_ROM_PTR(&pin_GPIO_B0_02) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_CLK), MP_ROM_PTR(&pin_GPIO_B0_00) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D0), MP_ROM_PTR(&pin_GPIO_B0_04) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D1), MP_ROM_PTR(&pin_GPIO_B0_05) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D2), MP_ROM_PTR(&pin_GPIO_B0_06) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D3), MP_ROM_PTR(&pin_GPIO_B0_07) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D4), MP_ROM_PTR(&pin_GPIO_B0_08) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D5), MP_ROM_PTR(&pin_GPIO_B0_09) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D6), MP_ROM_PTR(&pin_GPIO_B0_10) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D7), MP_ROM_PTR(&pin_GPIO_B0_11) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D8), MP_ROM_PTR(&pin_GPIO_B0_12) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D9), MP_ROM_PTR(&pin_GPIO_B0_13) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D10), MP_ROM_PTR(&pin_GPIO_B0_14) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D11), MP_ROM_PTR(&pin_GPIO_B0_15) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D12), MP_ROM_PTR(&pin_GPIO_B1_00) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D13), MP_ROM_PTR(&pin_GPIO_B1_01) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D14), MP_ROM_PTR(&pin_GPIO_B1_02) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D15), MP_ROM_PTR(&pin_GPIO_B1_03) },
+
+    // Touch Interface
+    { MP_ROM_QSTR(MP_QSTR_LCD_TOUCH_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
+
+    // Audio Interface
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_SD_B1_03) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_B0_13) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_RX_SYNC), MP_ROM_PTR(&pin_GPIO_B0_14) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_RX_BCLK), MP_ROM_PTR(&pin_GPIO_B0_15) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_TX_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_TX_SYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
+
+    // SPDIF
+    { MP_ROM_QSTR(MP_QSTR_SPDIF_IN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
+    { MP_ROM_QSTR(MP_QSTR_SPDIF_OUT), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
+
+    // Ethernet
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_MDIO), MP_ROM_PTR(&pin_GPIO_EMC_41) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_MDC), MP_ROM_PTR(&pin_GPIO_EMC_40) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD0), MP_ROM_PTR(&pin_GPIO_B1_04) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD1), MP_ROM_PTR(&pin_GPIO_B1_05) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_CRS_DV), MP_ROM_PTR(&pin_GPIO_B1_06) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD0), MP_ROM_PTR(&pin_GPIO_B1_07) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD1), MP_ROM_PTR(&pin_GPIO_B1_08) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXEN), MP_ROM_PTR(&pin_GPIO_B1_09) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_INT), MP_ROM_PTR(&pin_GPIO_SD_B1_04) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_CLK), MP_ROM_PTR(&pin_GPIO_B1_10) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXER), MP_ROM_PTR(&pin_GPIO_B1_11) },
+
+    // Freelink UART
+    { MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
+    { MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
+
+    // CAN
+    { MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
+    { MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
+    { MP_ROM_QSTR(MP_QSTR_CAN_STBY), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
+
+    // USB
+    { MP_ROM_QSTR(MP_QSTR_USB_HOST_DP), MP_ROM_PTR(&pin_USB_OTG1_DP) },
+    { MP_ROM_QSTR(MP_QSTR_USB_HOST_DM), MP_ROM_PTR(&pin_USB_OTG1_DN) },
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/board.c b/ports/mimxrt10xx/boards/imxrt1050_evkb/board.c
new file mode 100644
index 0000000000..8a34fc4210
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/board.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "supervisor/board.h"
+#include "shared-bindings/microcontroller/Pin.h"
+
+// These pins should never ever be reset; doing so could interfere with basic operation.
+// Used in common-hal/microcontroller/Pin.c
+const mcu_pin_obj_t *mimxrt10xx_reset_forbidden_pins[] = {
+    // SWD Pins
+    &pin_GPIO_AD_B0_06, // SWDIO
+    &pin_GPIO_AD_B0_07, // SWCLK
+
+    // FLEXSPI QSPI
+    &pin_GPIO_SD_B1_05,
+    &pin_GPIO_SD_B1_06,
+    &pin_GPIO_SD_B1_07,
+    &pin_GPIO_SD_B1_08,
+    &pin_GPIO_SD_B1_09,
+    &pin_GPIO_SD_B1_10,
+    &pin_GPIO_SD_B1_11,
+
+    // USB Pins
+    &pin_GPIO_AD_B0_01,
+    &pin_GPIO_AD_B0_03,
+    NULL,                       // Must end in NULL.
+};
+
+// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.
diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/flash_config.c b/ports/mimxrt10xx/boards/imxrt1050_evkb/flash_config.c
new file mode 100644
index 0000000000..110ef465bf
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/flash_config.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "boards/flash_config.h"
+
+#include "xip/fsl_flexspi_nor_boot.h"
+
+// Config for IS25WP064A with QSPI routed.
+__attribute__((section(".boot_hdr.conf")))
+const flexspi_nor_config_t qspiflash_config = {
+    .pageSize = 256u,
+    .sectorSize = 4u * 1024u,
+    .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz,
+    .blockSize = 0x00010000,
+    .isUniformBlockSize = false,
+    .memConfig =
+    {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromSckPad,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+
+        .busyOffset = 0u,     // Status bit 0 indicates busy.
+        .busyBitPolarity = 0u,     // Busy when the bit is 1.
+
+        .deviceModeCfgEnable = 1u,
+        .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+        .deviceModeSeq = {
+            .seqId = 4u,
+            .seqNum = 1u,
+        },
+        .deviceModeArg = 0x40,
+        .deviceType = kFLEXSPIDeviceType_SerialNOR,
+        .sflashPadType = kSerialFlash_4Pads,
+        .serialClkFreq = kFLEXSPISerialClk_60MHz,
+        .sflashA1Size = FLASH_SIZE,
+        .lookupTable =
+        {
+            // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
+            // The high 16 bits is command 1 and the low are command 0.
+            // Within a command, the top 6 bits are the opcode, the next two are the number
+            // of pads and then last byte is the operand. The operand's meaning changes
+            // per opcode.
+
+            // Indices with ROM should always have the same function because the ROM
+            // bootloader uses it.
+
+            // 0: ROM: Read LUTs
+            // Quad version
+            SEQUENCE(
+                FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xEB /* the command to send */,
+                    RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+                FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+                    READ_SDR,  FLEXSPI_4PAD, 0x04),
+                // Single fast read version, good for debugging.
+                // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x0B /* the command to send */,
+                //                 RADDR_SDR, FLEXSPI_1PAD, 24  /* bits to transmit */),
+                // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+                //                 READ_SDR,  FLEXSPI_1PAD, 0x04),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 1: ROM: Read status
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,  FLEXSPI_1PAD, 0x05 /* the command to send */,
+                READ_SDR, FLEXSPI_1PAD, 0x02),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 2: Empty
+            EMPTY_SEQUENCE,
+
+            // 3: ROM: Write Enable
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+                STOP,    FLEXSPI_1PAD, 0x00),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 4: Config: Write Status
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x01 /* the command to send */,
+                WRITE_SDR, FLEXSPI_1PAD, 0x01),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 5: ROM: Erase Sector
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x20 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 6: Empty
+            EMPTY_SEQUENCE,
+
+            // 7: Empty
+            EMPTY_SEQUENCE,
+
+            // 8: Block Erase
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xD8 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 9: ROM: Page program
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x02 /* the command to send */,
+                RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+                FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+                    STOP,      FLEXSPI_1PAD, 0),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 10: Empty
+            EMPTY_SEQUENCE,
+
+            // 11: ROM: Chip erase
+            SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+                STOP,    FLEXSPI_1PAD, 0),
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS,
+                TWO_EMPTY_STEPS),
+
+            // 12: Empty
+            EMPTY_SEQUENCE,
+
+            // 13: ROM: Read SFDP
+            EMPTY_SEQUENCE,
+
+            // 14: ROM: Restore no cmd
+            EMPTY_SEQUENCE,
+
+            // 15: ROM: Dummy
+            EMPTY_SEQUENCE
+        },
+    },
+};
diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/mpconfigboard.h b/ports/mimxrt10xx/boards/imxrt1050_evkb/mpconfigboard.h
new file mode 100644
index 0000000000..44e1dfaf12
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/mpconfigboard.h
@@ -0,0 +1,27 @@
+#define MICROPY_HW_BOARD_NAME "iMX RT 1050 EVKB"
+#define MICROPY_HW_MCU_NAME "IMXRT1052DVL6B"
+
+// If you change this, then make sure to update the linker scripts as well to
+// make sure you don't overwrite code
+#define CIRCUITPY_INTERNAL_NVM_SIZE 0
+
+// This uses the QSPI Flash. You'll need to modify the board to access it. See
+// AN12108 for instructions. https://www.nxp.com/docs/en/application-note/AN12108.pdf
+// JLinkGDBServer -if SWD -device "MIMXRT1052xxx6B?BankAddr=0x60000000&Loader=QSPI"
+#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
+
+#define MICROPY_HW_LED_STATUS (&pin_GPIO_AD_B0_09)
+#define MICROPY_HW_LED_STATUS_INVERTED (1)
+
+#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_00)
+#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_01)
+
+#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B1_07)
+#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B1_06)
+
+#define CIRCUITPY_CONSOLE_UART_TX (&pin_GPIO_AD_B0_12)
+#define CIRCUITPY_CONSOLE_UART_RX (&pin_GPIO_AD_B0_13)
+
+// Put host on the second USB so that the device connection powers the board.
+#define CIRCUITPY_USB_DEVICE_INSTANCE 0
+#define CIRCUITPY_USB_HOST_INSTANCE 1
diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/mpconfigboard.mk b/ports/mimxrt10xx/boards/imxrt1050_evkb/mpconfigboard.mk
new file mode 100644
index 0000000000..6627d46681
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/mpconfigboard.mk
@@ -0,0 +1,10 @@
+USB_VID = 0x239A
+USB_PID = 0x8084
+USB_PRODUCT = "iMX RT 1050 EVKB"
+USB_MANUFACTURER = "NXP"
+
+CHIP_VARIANT = MIMXRT1052DVL6B
+CHIP_FAMILY = MIMXRT1052
+FLASH = IS25WP064A
+
+CIRCUITPY_USB_HOST = 1
diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/pins.c b/ports/mimxrt10xx/boards/imxrt1050_evkb/pins.c
new file mode 100644
index 0000000000..a162463b28
--- /dev/null
+++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/pins.c
@@ -0,0 +1,142 @@
+#include "shared-bindings/board/__init__.h"
+
+#include "supervisor/board.h"
+
+STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
+    CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_AD_B0_09) }, // Connected to audio codec
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_AD_B0_10) }, // Connected to audio codec
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_AD_B0_02) }, // Connected to audio codec
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
+
+    // i2c sensor is on I2C1_SCL/SDA
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
+
+    // Camera Sensor Interface
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_VSYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_PWDN), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_HSYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D9), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D8), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_PIXCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D2), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D5), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D3), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D4), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
+
+    // SD Card
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_GPIO_B1_12) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SD_PWREN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
+
+    // LCD Interface
+    { MP_ROM_QSTR(MP_QSTR_LCD_BACKLIGHT), MP_ROM_PTR(&pin_GPIO_B1_15) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_ENABLE), MP_ROM_PTR(&pin_GPIO_B0_01) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_VSYNC), MP_ROM_PTR(&pin_GPIO_B0_03) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_HSYNC), MP_ROM_PTR(&pin_GPIO_B0_02) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_CLK), MP_ROM_PTR(&pin_GPIO_B0_00) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D0), MP_ROM_PTR(&pin_GPIO_B0_04) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D1), MP_ROM_PTR(&pin_GPIO_B0_05) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D2), MP_ROM_PTR(&pin_GPIO_B0_06) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D3), MP_ROM_PTR(&pin_GPIO_B0_07) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D4), MP_ROM_PTR(&pin_GPIO_B0_08) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D5), MP_ROM_PTR(&pin_GPIO_B0_09) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D6), MP_ROM_PTR(&pin_GPIO_B0_10) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D7), MP_ROM_PTR(&pin_GPIO_B0_11) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D8), MP_ROM_PTR(&pin_GPIO_B0_12) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D9), MP_ROM_PTR(&pin_GPIO_B0_13) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D10), MP_ROM_PTR(&pin_GPIO_B0_14) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D11), MP_ROM_PTR(&pin_GPIO_B0_15) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D12), MP_ROM_PTR(&pin_GPIO_B1_00) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D13), MP_ROM_PTR(&pin_GPIO_B1_01) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D14), MP_ROM_PTR(&pin_GPIO_B1_02) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_D15), MP_ROM_PTR(&pin_GPIO_B1_03) },
+
+    // Touch Interface
+    { MP_ROM_QSTR(MP_QSTR_LCD_TOUCH_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
+
+    // Audio Interface
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_RX_SYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_RX_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_TX_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_TX_SYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
+
+    // SPDIF
+    { MP_ROM_QSTR(MP_QSTR_SPDIF_IN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
+    { MP_ROM_QSTR(MP_QSTR_SPDIF_OUT), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
+
+    // Ethernet
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_MDIO), MP_ROM_PTR(&pin_GPIO_EMC_41) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_MDC), MP_ROM_PTR(&pin_GPIO_EMC_40) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD0), MP_ROM_PTR(&pin_GPIO_B1_04) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD1), MP_ROM_PTR(&pin_GPIO_B1_05) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_CRS_DV), MP_ROM_PTR(&pin_GPIO_B1_06) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD0), MP_ROM_PTR(&pin_GPIO_B1_07) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD1), MP_ROM_PTR(&pin_GPIO_B1_08) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXEN), MP_ROM_PTR(&pin_GPIO_B1_09) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_CLK), MP_ROM_PTR(&pin_GPIO_B1_10) },
+    { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXER), MP_ROM_PTR(&pin_GPIO_B1_11) },
+
+    // Freelink UART
+    { MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
+    { MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
+
+    // CAN
+    { MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
+    { MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
+    { MP_ROM_QSTR(MP_QSTR_CAN_STBY), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
+
+    // USB
+    #if CIRCUITPY_USB_HOST_INSTANCE == 0
+    { MP_ROM_QSTR(MP_QSTR_USB_HOST_DP), MP_ROM_PTR(&pin_USB_OTG1_DP) },
+    { MP_ROM_QSTR(MP_QSTR_USB_HOST_DM), MP_ROM_PTR(&pin_USB_OTG1_DN) },
+    #elif CIRCUITPY_USB_HOST_INSTANCE == 1
+    { MP_ROM_QSTR(MP_QSTR_USB_HOST_DP), MP_ROM_PTR(&pin_USB_OTG2_DP) },
+    { MP_ROM_QSTR(MP_QSTR_USB_HOST_DM), MP_ROM_PTR(&pin_USB_OTG2_DN) },
+    #endif
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c
index e4562c1965..3b47af1d6c 100644
--- a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c
+++ b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c
@@ -14,14 +14,14 @@ __attribute__((section(".boot_hdr.conf")))
 const flexspi_nor_config_t qspiflash_config = {
     .pageSize = 256u,
     .sectorSize = 4u * 1024u,
-    .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz,
+    .ipcmdSerialClkFreq = kFLEXSPISerialClk_133MHz,
     .blockSize = 0x00010000,
     .isUniformBlockSize = false,
     .memConfig =
     {
         .tag = FLEXSPI_CFG_BLK_TAG,
         .version = FLEXSPI_CFG_BLK_VERSION,
-        .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad,
+        .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromSckPad,
         .csHoldTime = 3u,
         .csSetupTime = 3u,
 
@@ -43,7 +43,7 @@ const flexspi_nor_config_t qspiflash_config = {
         },
         .deviceType = kFLEXSPIDeviceType_SerialNOR,
         .sflashPadType = kSerialFlash_4Pads,
-        .serialClkFreq = kFLEXSPISerialClk_60MHz,
+        .serialClkFreq = kFLEXSPISerialClk_133MHz,
         .sflashA1Size = FLASH_SIZE,
         .lookupTable =
         {
diff --git a/ports/mimxrt10xx/common-hal/audiobusio/I2SOut.c b/ports/mimxrt10xx/common-hal/audiobusio/I2SOut.c
index 06765afe02..9ba2762f1c 100644
--- a/ports/mimxrt10xx/common-hal/audiobusio/I2SOut.c
+++ b/ports/mimxrt10xx/common-hal/audiobusio/I2SOut.c
@@ -77,9 +77,9 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t *self,
     const mcu_pin_obj_t *data, bool left_justified) {
 
     int instance = -1;
-    const mcu_periph_obj_t *bclk_periph = find_pin_function(mcu_sai_tx_bclk_list, bit_clock, &instance, MP_QSTR_bit_clock);
-    const mcu_periph_obj_t *sync_periph = find_pin_function(mcu_sai_tx_sync_list, word_select, &instance, MP_QSTR_word_select);
-    const mcu_periph_obj_t *data_periph = find_pin_function(mcu_sai_tx_data0_list, data, &instance, MP_QSTR_data);
+    const mcu_periph_obj_t *bclk_periph = find_pin_function(mcu_i2s_tx_bclk_list, bit_clock, &instance, MP_QSTR_bit_clock);
+    const mcu_periph_obj_t *sync_periph = find_pin_function(mcu_i2s_tx_sync_list, word_select, &instance, MP_QSTR_word_select);
+    const mcu_periph_obj_t *data_periph = find_pin_function(mcu_i2s_tx_data0_list, data, &instance, MP_QSTR_data);
 
     sai_transceiver_t config;
     SAI_GetClassicI2SConfig(&config, 16, kSAI_Stereo, 1);
diff --git a/ports/mimxrt10xx/common-hal/busio/I2C.c b/ports/mimxrt10xx/common-hal/busio/I2C.c
index 6c5bbea416..de1b94e80e 100644
--- a/ports/mimxrt10xx/common-hal/busio/I2C.c
+++ b/ports/mimxrt10xx/common-hal/busio/I2C.c
@@ -37,13 +37,17 @@
 #include "sdk/drivers/lpi2c/fsl_lpi2c.h"
 #include "sdk/drivers/igpio/fsl_gpio.h"
 
+#if IMXRT11XX
+#define I2C_CLOCK_FREQ (24000000)
+#else
 #define I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (1 + CLOCK_GetDiv(kCLOCK_Lpi2cDiv)))
+#endif
+
 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5 5U
 
 // arrays use 0 based numbering: I2C1 is stored at index 0
-#define MAX_I2C 4
-STATIC bool reserved_i2c[MAX_I2C];
-STATIC bool never_reset_i2c[MAX_I2C];
+STATIC bool reserved_i2c[MP_ARRAY_SIZE(mcu_i2c_banks)];
+STATIC bool never_reset_i2c[MP_ARRAY_SIZE(mcu_i2c_banks)];
 
 void i2c_reset(void) {
     for (uint i = 0; i < MP_ARRAY_SIZE(mcu_i2c_banks); i++) {
@@ -63,24 +67,28 @@ static void config_periph_pin(const mcu_periph_obj_t *periph) {
 
     IOMUXC_SetPinConfig(0, 0, 0, 0,
         periph->pin->cfg_reg,
-        IOMUXC_SW_PAD_CTL_PAD_HYS(0)
-        | IOMUXC_SW_PAD_CTL_PAD_PUS(3)
-        | IOMUXC_SW_PAD_CTL_PAD_PUE(0)
+        IOMUXC_SW_PAD_CTL_PAD_PUS(3)
+        #if IMXRT10XX
+        | IOMUXC_SW_PAD_CTL_PAD_HYS(0)
         | IOMUXC_SW_PAD_CTL_PAD_PKE(1)
-        | IOMUXC_SW_PAD_CTL_PAD_ODE(1)
         | IOMUXC_SW_PAD_CTL_PAD_SPEED(2)
+        #endif
+        | IOMUXC_SW_PAD_CTL_PAD_PUE(0)
+        | IOMUXC_SW_PAD_CTL_PAD_ODE(1)
         | IOMUXC_SW_PAD_CTL_PAD_DSE(4)
         | IOMUXC_SW_PAD_CTL_PAD_SRE(0));
 }
 
 static void i2c_check_pin_config(const mcu_pin_obj_t *pin, uint32_t pull) {
     IOMUXC_SetPinConfig(0, 0, 0, 0, pin->cfg_reg,
-        IOMUXC_SW_PAD_CTL_PAD_HYS(1)
-        | IOMUXC_SW_PAD_CTL_PAD_PUS(0)     // Pulldown
-        | IOMUXC_SW_PAD_CTL_PAD_PUE(pull)     // 0=nopull (keeper), 1=pull
+        IOMUXC_SW_PAD_CTL_PAD_PUS(0)     // Pulldown
+        #if IMXRT10XX
+        | IOMUXC_SW_PAD_CTL_PAD_HYS(1)
         | IOMUXC_SW_PAD_CTL_PAD_PKE(1)
-        | IOMUXC_SW_PAD_CTL_PAD_ODE(0)
         | IOMUXC_SW_PAD_CTL_PAD_SPEED(2)
+        #endif
+        | IOMUXC_SW_PAD_CTL_PAD_PUE(pull)     // 0=nopull (keeper), 1=pull
+        | IOMUXC_SW_PAD_CTL_PAD_ODE(0)
         | IOMUXC_SW_PAD_CTL_PAD_DSE(1)
         | IOMUXC_SW_PAD_CTL_PAD_SRE(0));
 }
diff --git a/ports/mimxrt10xx/common-hal/busio/SPI.c b/ports/mimxrt10xx/common-hal/busio/SPI.c
index d88b71a403..641714bcca 100644
--- a/ports/mimxrt10xx/common-hal/busio/SPI.c
+++ b/ports/mimxrt10xx/common-hal/busio/SPI.c
@@ -36,14 +36,21 @@
 
 #include <stdio.h>
 
+#if IMXRT11XX
+#define LPSPI_MASTER_CLK_FREQ (24000000)
+#else
 #define LPSPI_MASTER_CLK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1))
+#endif
 
 #define MAX_SPI_BUSY_RETRIES 100
 
 // arrays use 0 based numbering: SPI1 is stored at index 0
-#define MAX_SPI 4
-STATIC bool reserved_spi[MAX_SPI];
-STATIC bool never_reset_spi[MAX_SPI];
+STATIC bool reserved_spi[MP_ARRAY_SIZE(mcu_spi_banks)];
+STATIC bool never_reset_spi[MP_ARRAY_SIZE(mcu_spi_banks)];
+
+#if IMXRT11XX
+STATIC const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS;
+#endif
 
 STATIC void config_periph_pin(const mcu_periph_obj_t *periph) {
     IOMUXC_SetPinMux(
@@ -54,12 +61,14 @@ STATIC void config_periph_pin(const mcu_periph_obj_t *periph) {
 
     IOMUXC_SetPinConfig(0, 0, 0, 0,
         periph->pin->cfg_reg,
-        IOMUXC_SW_PAD_CTL_PAD_HYS(0)
-        | IOMUXC_SW_PAD_CTL_PAD_PUS(0)
-        | IOMUXC_SW_PAD_CTL_PAD_PUE(0)
+        IOMUXC_SW_PAD_CTL_PAD_PUS(0)
+        #if IMXRT10XX
+        | IOMUXC_SW_PAD_CTL_PAD_HYS(0)
         | IOMUXC_SW_PAD_CTL_PAD_PKE(1)
-        | IOMUXC_SW_PAD_CTL_PAD_ODE(0)
         | IOMUXC_SW_PAD_CTL_PAD_SPEED(2)
+        #endif
+        | IOMUXC_SW_PAD_CTL_PAD_PUE(0)
+        | IOMUXC_SW_PAD_CTL_PAD_ODE(0)
         | IOMUXC_SW_PAD_CTL_PAD_DSE(4)
         | IOMUXC_SW_PAD_CTL_PAD_SRE(0));
 }
@@ -68,6 +77,13 @@ void spi_reset(void) {
     for (uint i = 0; i < MP_ARRAY_SIZE(mcu_spi_banks); i++) {
         if (!never_reset_spi[i]) {
             reserved_spi[i] = false;
+            #if IMXRT11XX
+            // Skip resetting SPIs that aren't clocked. Doing so generates a bus fault.
+            if ((CCM->LPCG[s_lpspiClocks[i + 1]].STATUS0 & CCM_LPCG_STATUS0_ON_MASK) == ((uint32_t)kCLOCK_Off & CCM_LPCG_STATUS0_ON_MASK)) {
+                continue;
+            }
+            #endif
+
             LPSPI_Deinit(mcu_spi_banks[i]);
         }
     }
@@ -78,8 +94,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
     const mcu_pin_obj_t *miso, bool half_duplex) {
 
     const uint32_t sck_count = MP_ARRAY_SIZE(mcu_spi_sck_list);
-    const uint32_t miso_count = MP_ARRAY_SIZE(mcu_spi_miso_list);
-    const uint32_t mosi_count = MP_ARRAY_SIZE(mcu_spi_mosi_list);
+    const uint32_t miso_count = MP_ARRAY_SIZE(mcu_spi_sdi_list);
+    const uint32_t mosi_count = MP_ARRAY_SIZE(mcu_spi_sdo_list);
     bool spi_taken = false;
 
     if (half_duplex) {
@@ -93,13 +109,13 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
         // if both MOSI and MISO exist, loop search normally
         if ((mosi != NULL) && (miso != NULL)) {
             for (uint j = 0; j < mosi_count; j++) {
-                if ((mcu_spi_mosi_list[i].pin != mosi)
-                    || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)) {
+                if ((mcu_spi_sdo_list[i].pin != mosi)
+                    || (mcu_spi_sck_list[i].bank_idx != mcu_spi_sdo_list[j].bank_idx)) {
                     continue;
                 }
                 for (uint k = 0; k < miso_count; k++) {
-                    if ((mcu_spi_miso_list[k].pin != miso) // everything needs the same index
-                        || (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[k].bank_idx)) {
+                    if ((mcu_spi_sdi_list[k].pin != miso) // everything needs the same index
+                        || (mcu_spi_sck_list[i].bank_idx != mcu_spi_sdi_list[k].bank_idx)) {
                         continue;
                     }
                     // if SPI is taken, break (pins never have >1 periph)
@@ -109,8 +125,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
                     }
                     // store pins if not
                     self->clock = &mcu_spi_sck_list[i];
-                    self->mosi = &mcu_spi_mosi_list[j];
-                    self->miso = &mcu_spi_miso_list[k];
+                    self->mosi = &mcu_spi_sdo_list[j];
+                    self->miso = &mcu_spi_sdi_list[k];
                     break;
                 }
                 if (self->clock != NULL || spi_taken) {
@@ -123,8 +139,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
             // if just MISO, reduce search
         } else if (miso != NULL) {
             for (uint j = 0; j < miso_count; j++) {
-                if ((mcu_spi_miso_list[j].pin != miso) // only SCK and MISO need the same index
-                    || (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[j].bank_idx)) {
+                if ((mcu_spi_sdi_list[j].pin != miso) // only SCK and MISO need the same index
+                    || (mcu_spi_sck_list[i].bank_idx != mcu_spi_sdi_list[j].bank_idx)) {
                     continue;
                 }
                 if (reserved_spi[mcu_spi_sck_list[i].bank_idx - 1]) {
@@ -132,7 +148,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
                     break;
                 }
                 self->clock = &mcu_spi_sck_list[i];
-                self->miso = &mcu_spi_miso_list[j];
+                self->miso = &mcu_spi_sdi_list[j];
                 break;
             }
             if (self->clock != NULL || spi_taken) {
@@ -141,8 +157,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
             // if just MOSI, reduce search
         } else if (mosi != NULL) {
             for (uint j = 0; j < mosi_count; j++) {
-                if ((mcu_spi_mosi_list[j].pin != mosi) // only SCK and MOSI need the same index
-                    || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)) {
+                if ((mcu_spi_sdo_list[j].pin != mosi) // only SCK and MOSI need the same index
+                    || (mcu_spi_sck_list[i].bank_idx != mcu_spi_sdo_list[j].bank_idx)) {
                     continue;
                 }
                 if (reserved_spi[mcu_spi_sck_list[i].bank_idx - 1]) {
@@ -150,7 +166,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
                     break;
                 }
                 self->clock = &mcu_spi_sck_list[i];
-                self->mosi = &mcu_spi_mosi_list[j];
+                self->mosi = &mcu_spi_sdo_list[j];
                 break;
             }
             if (self->clock != NULL || spi_taken) {
diff --git a/ports/mimxrt10xx/common-hal/busio/UART.c b/ports/mimxrt10xx/common-hal/busio/UART.c
index 088b2aefc6..e4d5fda6ae 100644
--- a/ports/mimxrt10xx/common-hal/busio/UART.c
+++ b/ports/mimxrt10xx/common-hal/busio/UART.c
@@ -52,11 +52,15 @@
 
 
 // arrays use 0 based numbering: UART1 is stored at index 0
-#define MAX_UART 8
-STATIC bool reserved_uart[MAX_UART];
-STATIC bool never_reset_uart[MAX_UART];
+STATIC bool reserved_uart[MP_ARRAY_SIZE(mcu_uart_banks)];
+STATIC bool never_reset_uart[MP_ARRAY_SIZE(mcu_uart_banks)];
 
+#if IMXRT11XX
+#define UART_CLOCK_FREQ (24000000)
+#else
 #define UART_CLOCK_FREQ (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U)
+#endif
+
 
 static void config_periph_pin(const mcu_periph_obj_t *periph) {
     IOMUXC_SetPinMux(
@@ -67,12 +71,14 @@ static void config_periph_pin(const mcu_periph_obj_t *periph) {
 
     IOMUXC_SetPinConfig(0, 0, 0, 0,
         periph->pin->cfg_reg,
-        IOMUXC_SW_PAD_CTL_PAD_HYS(0)
-        | IOMUXC_SW_PAD_CTL_PAD_PUS(1)
-        | IOMUXC_SW_PAD_CTL_PAD_PUE(1)
+        IOMUXC_SW_PAD_CTL_PAD_PUS(1)
+        #if IMXRT10XX
+        | IOMUXC_SW_PAD_CTL_PAD_HYS(0)
         | IOMUXC_SW_PAD_CTL_PAD_PKE(1)
-        | IOMUXC_SW_PAD_CTL_PAD_ODE(0)
         | IOMUXC_SW_PAD_CTL_PAD_SPEED(1)
+        #endif
+        | IOMUXC_SW_PAD_CTL_PAD_PUE(1)
+        | IOMUXC_SW_PAD_CTL_PAD_ODE(0)
         | IOMUXC_SW_PAD_CTL_PAD_DSE(6)
         | IOMUXC_SW_PAD_CTL_PAD_SRE(0));
 }
@@ -288,12 +294,14 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
         IOMUXC_SetPinMux(rs485_dir->mux_reg, IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5, 0, 0, 0, 0);
         DBGPrintf(&mp_plat_print, "\tAfter IOMUXC_SetPinMux\n");
         IOMUXC_SetPinConfig(0, 0, 0, 0, rs485_dir->cfg_reg,
-            IOMUXC_SW_PAD_CTL_PAD_HYS(1)
-            | IOMUXC_SW_PAD_CTL_PAD_PUS(0)
-            | IOMUXC_SW_PAD_CTL_PAD_PUE(0)
+            IOMUXC_SW_PAD_CTL_PAD_PUS(0)
+            #if IMXRT10XX
+            | IOMUXC_SW_PAD_CTL_PAD_HYS(1)
             | IOMUXC_SW_PAD_CTL_PAD_PKE(1)
-            | IOMUXC_SW_PAD_CTL_PAD_ODE(0)
             | IOMUXC_SW_PAD_CTL_PAD_SPEED(2)
+            #endif
+            | IOMUXC_SW_PAD_CTL_PAD_PUE(0)
+            | IOMUXC_SW_PAD_CTL_PAD_ODE(0)
             | IOMUXC_SW_PAD_CTL_PAD_DSE(1)
             | IOMUXC_SW_PAD_CTL_PAD_SRE(0));
         DBGPrintf(&mp_plat_print, "\tAfter IOMUXC_SetPinConfig\n");
diff --git a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c
index 2b4a78948e..31dac38bdc 100644
--- a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c
+++ b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c
@@ -42,12 +42,14 @@
 
 void pin_config(const mcu_pin_obj_t *pin, bool open_drain, digitalio_pull_t pull) {
     IOMUXC_SetPinConfig(0, 0, 0, 0, pin->cfg_reg,
-        IOMUXC_SW_PAD_CTL_PAD_HYS(1)
-        | IOMUXC_SW_PAD_CTL_PAD_PUS((pull == PULL_UP) ? 2 : 0)
-        | IOMUXC_SW_PAD_CTL_PAD_PUE(pull != PULL_NONE)
+        IOMUXC_SW_PAD_CTL_PAD_PUS((pull == PULL_UP) ? 2 : 0)
+        #if IMXRT10XX
+        | IOMUXC_SW_PAD_CTL_PAD_HYS(1)
         | IOMUXC_SW_PAD_CTL_PAD_PKE(1)
-        | IOMUXC_SW_PAD_CTL_PAD_ODE(open_drain)
         | IOMUXC_SW_PAD_CTL_PAD_SPEED(2)
+        #endif
+        | IOMUXC_SW_PAD_CTL_PAD_PUE(pull != PULL_NONE)
+        | IOMUXC_SW_PAD_CTL_PAD_ODE(open_drain)
         | IOMUXC_SW_PAD_CTL_PAD_DSE(1)
         | IOMUXC_SW_PAD_CTL_PAD_SRE(0));
 }
diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c
index 9277f81d47..bd7d77f4fa 100644
--- a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c
+++ b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c
@@ -33,11 +33,14 @@
 #include "shared-bindings/microcontroller/Processor.h"
 #include "shared-bindings/microcontroller/ResetReason.h"
 
+#if CIRCUITPY_ANALOGIO
 #include "sdk/drivers/tempmon/fsl_tempmon.h"
+#endif
 #include "sdk/drivers/ocotp/fsl_ocotp.h"
 #include "clocks.h"
 
 float common_hal_mcu_processor_get_temperature(void) {
+    #if CIRCUITPY_ANALOGIO
     tempmon_config_t config;
     TEMPMON_GetDefaultConfig(&config);
 
@@ -50,6 +53,9 @@ float common_hal_mcu_processor_get_temperature(void) {
     OCOTP_Deinit(OCOTP);
 
     return temp;
+    #else
+    return 0;
+    #endif
 }
 
 uint32_t common_hal_mcu_processor_set_frequency(mcu_processor_obj_t *self,
@@ -73,7 +79,11 @@ uint32_t common_hal_mcu_processor_get_frequency(void) {
 }
 
 void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) {
+    #if IMXRT11XX
+    OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_Ocotp));
+    #else
     OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk));
+    #endif
 
     // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info)
     // into 8 bit wide destination, avoiding punning.
diff --git a/ports/mimxrt10xx/common-hal/microcontroller/__init__.c b/ports/mimxrt10xx/common-hal/microcontroller/__init__.c
index 1b10b4d4ee..de970fa26a 100644
--- a/ports/mimxrt10xx/common-hal/microcontroller/__init__.c
+++ b/ports/mimxrt10xx/common-hal/microcontroller/__init__.c
@@ -40,6 +40,8 @@
 #include "supervisor/shared/safe_mode.h"
 #include "supervisor/shared/translate/translate.h"
 
+#include "pins.h"
+
 void common_hal_mcu_delay_us(uint32_t delay) {
     mp_hal_delay_us(delay);
 }
@@ -107,188 +109,10 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = {
 
 // This maps MCU pin names to pin objects.
 // NOTE: for all i.MX chips, order MUST match _iomuxc_sw_mux_ctl_pad enum
-STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = {
-    #ifdef MIMXRT1011_SERIES
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_14), MP_ROM_PTR(&pin_GPIO_AD_14) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_13), MP_ROM_PTR(&pin_GPIO_AD_13) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_12), MP_ROM_PTR(&pin_GPIO_AD_12) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_11), MP_ROM_PTR(&pin_GPIO_AD_11) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_10), MP_ROM_PTR(&pin_GPIO_AD_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_09), MP_ROM_PTR(&pin_GPIO_AD_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_08), MP_ROM_PTR(&pin_GPIO_AD_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_07), MP_ROM_PTR(&pin_GPIO_AD_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_06), MP_ROM_PTR(&pin_GPIO_AD_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_05), MP_ROM_PTR(&pin_GPIO_AD_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_04), MP_ROM_PTR(&pin_GPIO_AD_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_03), MP_ROM_PTR(&pin_GPIO_AD_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_02), MP_ROM_PTR(&pin_GPIO_AD_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_01), MP_ROM_PTR(&pin_GPIO_AD_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_00), MP_ROM_PTR(&pin_GPIO_AD_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_14), MP_ROM_PTR(&pin_GPIO_SD_14) }, // spooky ghost pin
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_13), MP_ROM_PTR(&pin_GPIO_SD_13) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_12), MP_ROM_PTR(&pin_GPIO_SD_12) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_11), MP_ROM_PTR(&pin_GPIO_SD_11) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_10), MP_ROM_PTR(&pin_GPIO_SD_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_09), MP_ROM_PTR(&pin_GPIO_SD_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_08), MP_ROM_PTR(&pin_GPIO_SD_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_07), MP_ROM_PTR(&pin_GPIO_SD_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_06), MP_ROM_PTR(&pin_GPIO_SD_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_05), MP_ROM_PTR(&pin_GPIO_SD_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_04), MP_ROM_PTR(&pin_GPIO_SD_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_03), MP_ROM_PTR(&pin_GPIO_SD_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_02), MP_ROM_PTR(&pin_GPIO_SD_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_01), MP_ROM_PTR(&pin_GPIO_SD_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_00), MP_ROM_PTR(&pin_GPIO_SD_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_13), MP_ROM_PTR(&pin_GPIO_13) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_12), MP_ROM_PTR(&pin_GPIO_12) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_11), MP_ROM_PTR(&pin_GPIO_11) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_10), MP_ROM_PTR(&pin_GPIO_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_09), MP_ROM_PTR(&pin_GPIO_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_08), MP_ROM_PTR(&pin_GPIO_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_07), MP_ROM_PTR(&pin_GPIO_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_06), MP_ROM_PTR(&pin_GPIO_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_05), MP_ROM_PTR(&pin_GPIO_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_04), MP_ROM_PTR(&pin_GPIO_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_03), MP_ROM_PTR(&pin_GPIO_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_02), MP_ROM_PTR(&pin_GPIO_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_01), MP_ROM_PTR(&pin_GPIO_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_00), MP_ROM_PTR(&pin_GPIO_00) },
-    #else
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_00), MP_ROM_PTR(&pin_GPIO_EMC_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_01), MP_ROM_PTR(&pin_GPIO_EMC_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_02), MP_ROM_PTR(&pin_GPIO_EMC_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_03), MP_ROM_PTR(&pin_GPIO_EMC_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_04), MP_ROM_PTR(&pin_GPIO_EMC_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_05), MP_ROM_PTR(&pin_GPIO_EMC_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_06), MP_ROM_PTR(&pin_GPIO_EMC_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_07), MP_ROM_PTR(&pin_GPIO_EMC_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_08), MP_ROM_PTR(&pin_GPIO_EMC_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_09), MP_ROM_PTR(&pin_GPIO_EMC_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_10), MP_ROM_PTR(&pin_GPIO_EMC_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_11), MP_ROM_PTR(&pin_GPIO_EMC_11) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_12), MP_ROM_PTR(&pin_GPIO_EMC_12) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_13), MP_ROM_PTR(&pin_GPIO_EMC_13) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_14), MP_ROM_PTR(&pin_GPIO_EMC_14) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_15), MP_ROM_PTR(&pin_GPIO_EMC_15) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_16), MP_ROM_PTR(&pin_GPIO_EMC_16) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_17), MP_ROM_PTR(&pin_GPIO_EMC_17) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_18), MP_ROM_PTR(&pin_GPIO_EMC_18) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_19), MP_ROM_PTR(&pin_GPIO_EMC_19) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_20), MP_ROM_PTR(&pin_GPIO_EMC_20) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_21), MP_ROM_PTR(&pin_GPIO_EMC_21) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_22), MP_ROM_PTR(&pin_GPIO_EMC_22) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_23), MP_ROM_PTR(&pin_GPIO_EMC_23) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_24), MP_ROM_PTR(&pin_GPIO_EMC_24) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_25), MP_ROM_PTR(&pin_GPIO_EMC_25) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_26), MP_ROM_PTR(&pin_GPIO_EMC_26) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_27), MP_ROM_PTR(&pin_GPIO_EMC_27) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_28), MP_ROM_PTR(&pin_GPIO_EMC_28) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_29), MP_ROM_PTR(&pin_GPIO_EMC_29) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_30), MP_ROM_PTR(&pin_GPIO_EMC_30) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_31), MP_ROM_PTR(&pin_GPIO_EMC_31) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_32), MP_ROM_PTR(&pin_GPIO_EMC_32) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_33), MP_ROM_PTR(&pin_GPIO_EMC_33) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_34), MP_ROM_PTR(&pin_GPIO_EMC_34) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_35), MP_ROM_PTR(&pin_GPIO_EMC_35) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_36), MP_ROM_PTR(&pin_GPIO_EMC_36) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_37), MP_ROM_PTR(&pin_GPIO_EMC_37) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_38), MP_ROM_PTR(&pin_GPIO_EMC_38) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_39), MP_ROM_PTR(&pin_GPIO_EMC_39) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_40), MP_ROM_PTR(&pin_GPIO_EMC_40) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_41), MP_ROM_PTR(&pin_GPIO_EMC_41) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_00), MP_ROM_PTR(&pin_GPIO_AD_B0_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_01), MP_ROM_PTR(&pin_GPIO_AD_B0_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_02), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_03), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_04), MP_ROM_PTR(&pin_GPIO_AD_B0_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_05), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_06), MP_ROM_PTR(&pin_GPIO_AD_B0_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_07), MP_ROM_PTR(&pin_GPIO_AD_B0_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_08), MP_ROM_PTR(&pin_GPIO_AD_B0_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_09), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_10), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_11), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_12), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_13), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_14), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B0_15), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_00), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_01), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_02), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_03), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_04), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_05), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_06), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_07), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_08), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_09), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_10), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_11), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_12), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_13), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_14), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_15), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
-    #ifdef MIMXRT1062_SERIES
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_00), MP_ROM_PTR(&pin_GPIO_B0_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_01), MP_ROM_PTR(&pin_GPIO_B0_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_02), MP_ROM_PTR(&pin_GPIO_B0_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_03), MP_ROM_PTR(&pin_GPIO_B0_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_04), MP_ROM_PTR(&pin_GPIO_B0_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_05), MP_ROM_PTR(&pin_GPIO_B0_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_06), MP_ROM_PTR(&pin_GPIO_B0_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_07), MP_ROM_PTR(&pin_GPIO_B0_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_08), MP_ROM_PTR(&pin_GPIO_B0_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_09), MP_ROM_PTR(&pin_GPIO_B0_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_10), MP_ROM_PTR(&pin_GPIO_B0_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_11), MP_ROM_PTR(&pin_GPIO_B0_11) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_12), MP_ROM_PTR(&pin_GPIO_B0_12) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_13), MP_ROM_PTR(&pin_GPIO_B0_13) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_14), MP_ROM_PTR(&pin_GPIO_B0_14) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B0_15), MP_ROM_PTR(&pin_GPIO_B0_15) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_00), MP_ROM_PTR(&pin_GPIO_B1_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_01), MP_ROM_PTR(&pin_GPIO_B1_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_02), MP_ROM_PTR(&pin_GPIO_B1_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_03), MP_ROM_PTR(&pin_GPIO_B1_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_04), MP_ROM_PTR(&pin_GPIO_B1_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_05), MP_ROM_PTR(&pin_GPIO_B1_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_06), MP_ROM_PTR(&pin_GPIO_B1_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_07), MP_ROM_PTR(&pin_GPIO_B1_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_08), MP_ROM_PTR(&pin_GPIO_B1_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_09), MP_ROM_PTR(&pin_GPIO_B1_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_10), MP_ROM_PTR(&pin_GPIO_B1_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_11), MP_ROM_PTR(&pin_GPIO_B1_11) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_12), MP_ROM_PTR(&pin_GPIO_B1_12) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_13), MP_ROM_PTR(&pin_GPIO_B1_13) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_14), MP_ROM_PTR(&pin_GPIO_B1_14) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_B1_15), MP_ROM_PTR(&pin_GPIO_B1_15) },
-    #endif
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_00), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_01), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_02), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_03), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_04), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_05), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
-    #ifdef MIMXRT1021_SERIES
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_06), MP_ROM_PTR(&pin_GPIO_SD_B0_06) },
-    #endif
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_00), MP_ROM_PTR(&pin_GPIO_SD_B1_00) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_01), MP_ROM_PTR(&pin_GPIO_SD_B1_01) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_02), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_03), MP_ROM_PTR(&pin_GPIO_SD_B1_03) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_04), MP_ROM_PTR(&pin_GPIO_SD_B1_04) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_05), MP_ROM_PTR(&pin_GPIO_SD_B1_05) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_06), MP_ROM_PTR(&pin_GPIO_SD_B1_06) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_07), MP_ROM_PTR(&pin_GPIO_SD_B1_07) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_08), MP_ROM_PTR(&pin_GPIO_SD_B1_08) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_09), MP_ROM_PTR(&pin_GPIO_SD_B1_09) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_10), MP_ROM_PTR(&pin_GPIO_SD_B1_10) },
-    { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_11), MP_ROM_PTR(&pin_GPIO_SD_B1_11) },
-    #ifdef MIMXRT1062_SERIES
-    { MP_ROM_QSTR(MP_QSTR_USB_OTG1_DN), MP_ROM_PTR(&pin_USB_OTG1_DN) },
-    { MP_ROM_QSTR(MP_QSTR_USB_OTG1_DP), MP_ROM_PTR(&pin_USB_OTG1_DP) },
-    { MP_ROM_QSTR(MP_QSTR_USB_OTG2_DN), MP_ROM_PTR(&pin_USB_OTG2_DN) },
-    { MP_ROM_QSTR(MP_QSTR_USB_OTG2_DP), MP_ROM_PTR(&pin_USB_OTG2_DP) },
-    #endif
-    #endif
+STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[PIN_COUNT] = {
+
+#define FORMAT_PIN(pin_name) { MP_ROM_QSTR(MP_QSTR_##pin_name), MP_ROM_PTR(&pin_##pin_name) },
+    #include "pin_names.h"
+#undef FORMAT_PIN
 };
 MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_global_dict_table);
diff --git a/ports/mimxrt10xx/common-hal/os/__init__.c b/ports/mimxrt10xx/common-hal/os/__init__.c
index 9219242685..899541bb21 100644
--- a/ports/mimxrt10xx/common-hal/os/__init__.c
+++ b/ports/mimxrt10xx/common-hal/os/__init__.c
@@ -33,7 +33,9 @@
 
 #include "shared-bindings/os/__init__.h"
 
+#if CIRCUITPY_RANDOM
 #include "sdk/drivers/trng/fsl_trng.h"
+#endif
 
 STATIC const qstr os_uname_info_fields[] = {
     MP_QSTR_sysname, MP_QSTR_nodename,
@@ -61,6 +63,7 @@ mp_obj_t common_hal_os_uname(void) {
 }
 
 bool common_hal_os_urandom(uint8_t *buffer, mp_uint_t length) {
+    #if CIRCUITPY_RANDOM
     trng_config_t trngConfig;
 
     TRNG_GetDefaultConfig(&trngConfig);
@@ -71,4 +74,7 @@ bool common_hal_os_urandom(uint8_t *buffer, mp_uint_t length) {
     TRNG_Deinit(TRNG);
 
     return true;
+    #else
+    return false;
+    #endif
 }
diff --git a/ports/mimxrt10xx/linking/chip_family/MIMXRT1011.ld b/ports/mimxrt10xx/linking/chip_family/MIMXRT1011.ld
index 0d0beebaae..55f03cb9c1 100644
--- a/ports/mimxrt10xx/linking/chip_family/MIMXRT1011.ld
+++ b/ports/mimxrt10xx/linking/chip_family/MIMXRT1011.ld
@@ -1,2 +1,4 @@
 ram_size = 128K;
-flash_config_location = 0x60000400;
+flash_base = 0x60000000;
+ocram_base = 0x20200000;
+flash_config_location = flash_base + 0x400;
diff --git a/ports/mimxrt10xx/linking/chip_family/MIMXRT1015.ld b/ports/mimxrt10xx/linking/chip_family/MIMXRT1015.ld
new file mode 100644
index 0000000000..72b2b705b5
--- /dev/null
+++ b/ports/mimxrt10xx/linking/chip_family/MIMXRT1015.ld
@@ -0,0 +1,4 @@
+ram_size = 128K;
+flash_base = 0x60000000;
+ocram_base = 0x20200000;
+flash_config_location = flash_base;
diff --git a/ports/mimxrt10xx/linking/chip_family/MIMXRT1021.ld b/ports/mimxrt10xx/linking/chip_family/MIMXRT1021.ld
index 21f2ea872c..215e58f9b3 100644
--- a/ports/mimxrt10xx/linking/chip_family/MIMXRT1021.ld
+++ b/ports/mimxrt10xx/linking/chip_family/MIMXRT1021.ld
@@ -1,2 +1,4 @@
 ram_size = 256K;
-flash_config_location = 0x60000000;
+flash_base = 0x60000000;
+ocram_base = 0x20200000;
+flash_config_location = flash_base;
diff --git a/ports/mimxrt10xx/linking/chip_family/MIMXRT1042.ld b/ports/mimxrt10xx/linking/chip_family/MIMXRT1042.ld
new file mode 100644
index 0000000000..9af9660087
--- /dev/null
+++ b/ports/mimxrt10xx/linking/chip_family/MIMXRT1042.ld
@@ -0,0 +1,4 @@
+ram_size = 512K;
+flash_base = 0x60000000;
+ocram_base = 0x20200000;
+flash_config_location = flash_base;
diff --git a/ports/mimxrt10xx/linking/chip_family/MIMXRT1052.ld b/ports/mimxrt10xx/linking/chip_family/MIMXRT1052.ld
new file mode 100644
index 0000000000..9af9660087
--- /dev/null
+++ b/ports/mimxrt10xx/linking/chip_family/MIMXRT1052.ld
@@ -0,0 +1,4 @@
+ram_size = 512K;
+flash_base = 0x60000000;
+ocram_base = 0x20200000;
+flash_config_location = flash_base;
diff --git a/ports/mimxrt10xx/linking/chip_family/MIMXRT1062.ld b/ports/mimxrt10xx/linking/chip_family/MIMXRT1062.ld
index e07c5c2c37..1ae8172200 100644
--- a/ports/mimxrt10xx/linking/chip_family/MIMXRT1062.ld
+++ b/ports/mimxrt10xx/linking/chip_family/MIMXRT1062.ld
@@ -1,2 +1,4 @@
 ram_size = 1M;
-flash_config_location = 0x60000000;
+flash_base = 0x60000000;
+ocram_base = 0x20200000;
+flash_config_location = flash_base;
diff --git a/ports/mimxrt10xx/linking/chip_family/MIMXRT1176.ld b/ports/mimxrt10xx/linking/chip_family/MIMXRT1176.ld
new file mode 100644
index 0000000000..a5d18addb7
--- /dev/null
+++ b/ports/mimxrt10xx/linking/chip_family/MIMXRT1176.ld
@@ -0,0 +1,4 @@
+ram_size = 1M;
+flash_base = 0x30000000;
+ocram_base = 0x20240000;
+flash_config_location = flash_base + 0x400;
diff --git a/ports/mimxrt10xx/linking/common.ld b/ports/mimxrt10xx/linking/common.ld
index 76c11c8d6f..a3ed2dbdbf 100644
--- a/ports/mimxrt10xx/linking/common.ld
+++ b/ports/mimxrt10xx/linking/common.ld
@@ -19,13 +19,13 @@ MEMORY
     /* This is the first block and is read so that the bootrom knows the optimal way to interface with the flash chip. */
     FLASH_CONFIG (rx)     : ORIGIN = flash_config_location, LENGTH = 512
     /* This can't move because the bootrom looks at this address. */
-    FLASH_IVT (rx)        : ORIGIN = 0x60001000, LENGTH = 4K
+    FLASH_IVT (rx)        : ORIGIN = flash_base + 0x1000, LENGTH = 4K
     /* Place the ISRs 48k in to leave room for the bootloader when it is available. */
-    FLASH_FIRMWARE (rx)   : ORIGIN = 0x6000C000, LENGTH = code_size - 48K
-    FLASH_FATFS (r)       : ORIGIN = 0x60000000 + code_size, LENGTH = _ld_flash_size - code_size - _ld_reserved_flash_size
+    FLASH_FIRMWARE (rx)   : ORIGIN = flash_base + 0xC000, LENGTH = code_size - 48K
+    FLASH_FATFS (r)       : ORIGIN = flash_base + code_size, LENGTH = _ld_flash_size - code_size - _ld_reserved_flash_size
     /* Teensy uses the last bit of flash for recovery. */
-    RESERVED_FLASH        : ORIGIN = 0x60000000 + code_size + _ld_flash_size - _ld_reserved_flash_size, LENGTH = _ld_reserved_flash_size
-    OCRAM (rwx)           : ORIGIN = 0x20200000, LENGTH = ram_size - 64K
+    RESERVED_FLASH        : ORIGIN = flash_base + code_size + _ld_flash_size - _ld_reserved_flash_size, LENGTH = _ld_reserved_flash_size
+    OCRAM (rwx)           : ORIGIN = ocram_base, LENGTH = ram_size - 64K
     DTCM (x)              : ORIGIN = 0x20000000, LENGTH = 32K
     ITCM (x)              : ORIGIN = 0x00000000, LENGTH = 32K
 }
@@ -135,7 +135,9 @@ SECTIONS
     _ld_ocram_bss_start = ADDR(.bss);
     _ld_ocram_bss_size = SIZEOF(.bss);
     _ld_heap_start = _ld_ocram_bss_start + _ld_ocram_bss_size;
-    _ld_heap_end = ORIGIN(OCRAM) + LENGTH(OCRAM);
+    _ld_ocram_start = ORIGIN(OCRAM);
+    _ld_ocram_end = ORIGIN(OCRAM) + LENGTH(OCRAM);
+    _ld_heap_end = _ld_ocram_end;
 
 
     .itcm : ALIGN(4)
diff --git a/ports/mimxrt10xx/linking/flash/IS25WP128.ld b/ports/mimxrt10xx/linking/flash/IS25WP128.ld
new file mode 100644
index 0000000000..205d9dd839
--- /dev/null
+++ b/ports/mimxrt10xx/linking/flash/IS25WP128.ld
@@ -0,0 +1 @@
+_ld_flash_size = 16M;
diff --git a/ports/mimxrt10xx/mpconfigport.mk b/ports/mimxrt10xx/mpconfigport.mk
index ae22cb69f4..b421b583be 100644
--- a/ports/mimxrt10xx/mpconfigport.mk
+++ b/ports/mimxrt10xx/mpconfigport.mk
@@ -11,13 +11,13 @@ CIRCUITPY_TUSB_MEM_ALIGN = 32
 
 INTERNAL_FLASH_FILESYSTEM = 1
 
-CIRCUITPY_AUDIOBUSIO = 1
+CIRCUITPY_AUDIOBUSIO ?= 1
 CIRCUITPY_AUDIOBUSIO_PDMIN = 0
-CIRCUITPY_AUDIOCORE = 1
+CIRCUITPY_AUDIOCORE ?= 1
 CIRCUITPY_AUDIOIO = 0
 CIRCUITPY_AUDIOMIXER = 1
 CIRCUITPY_AUDIOMP3 = 1
-CIRCUITPY_AUDIOPWMIO = 1
+CIRCUITPY_AUDIOPWMIO ?= 1
 CIRCUITPY_SYNTHIO_MAX_CHANNELS = 12
 CIRCUITPY_BUSDEVICE = 1
 CIRCUITPY_COUNTIO = 0
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c
index e96b55f3e9..69ce673a0e 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c
@@ -35,6 +35,8 @@
 #include "fsl_clock.h"
 #include "fsl_iomuxc.h"
 
+#include "board.h"
+
 #include "clocks.h"
 
 #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c
index b67f7b1179..fd8ef69f7e 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c
@@ -5,6 +5,7 @@
  *
  * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -65,7 +66,7 @@ const mcu_periph_obj_t mcu_spi_sck_list[4] = {
     PERIPH_PIN(2, 1, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 1, &pin_GPIO_SD_11),
 };
 
-const mcu_periph_obj_t mcu_spi_mosi_list[4] = {
+const mcu_periph_obj_t mcu_spi_sdo_list[4] = {
     PERIPH_PIN(1, 0, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 0, &pin_GPIO_AD_04),
     PERIPH_PIN(1, 2, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 1, &pin_GPIO_SD_06),
 
@@ -73,7 +74,7 @@ const mcu_periph_obj_t mcu_spi_mosi_list[4] = {
     PERIPH_PIN(2, 1, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 1, &pin_GPIO_SD_10),
 };
 
-const mcu_periph_obj_t mcu_spi_miso_list[4] = {
+const mcu_periph_obj_t mcu_spi_sdi_list[4] = {
     PERIPH_PIN(1, 0, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 0, &pin_GPIO_AD_03),
     PERIPH_PIN(1, 2, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 1, &pin_GPIO_SD_05),
 
@@ -120,7 +121,7 @@ const mcu_periph_obj_t mcu_uart_rts_list[4] = {
 
     PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_13),
 
-    PERIPH_PIN(4, 3, 0, 0, &pin_GPIO_AD_13)
+    PERIPH_PIN(4, 3, 0, 0, &pin_GPIO_AD_13),
 };
 
 const mcu_periph_obj_t mcu_uart_cts_list[4] = {
@@ -133,67 +134,76 @@ const mcu_periph_obj_t mcu_uart_cts_list[4] = {
     PERIPH_PIN(4, 3, 0, 0, &pin_GPIO_AD_14),
 };
 
-const mcu_pwm_obj_t mcu_pwm_list[20] = {
-    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_02_FLEXPWM1_PWM0_A, &pin_GPIO_02),
-    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A, &pin_GPIO_SD_02),
+I2S_Type *const mcu_i2s_banks[2] = { SAI1, SAI3 };
+
+const mcu_periph_obj_t mcu_i2s_rx_data0_list[2] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_03),
+
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_03),
+};
+
+const mcu_periph_obj_t mcu_i2s_rx_sync_list[2] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_02),
+
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_04),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_bclk_list[2] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_06),
+
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_01),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_data0_list[2] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_04),
+
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_02),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_sync_list[2] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_07),
+
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_00),
+};
+
+const mcu_periph_obj_t mcu_mqs_left_list[1] = {
+    PERIPH_PIN(3, 4, 0, 0, &pin_GPIO_AD_01),
+};
+
+const mcu_periph_obj_t mcu_mqs_right_list[1] = {
+    PERIPH_PIN(3, 4, 0, 0, &pin_GPIO_AD_02),
+};
+
+const mcu_pwm_obj_t mcu_pwm_list[20] = {
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A, &pin_GPIO_SD_02),
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_02_FLEXPWM1_PWM0_A, &pin_GPIO_02),
 
-    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_01_FLEXPWM1_PWM0_B, &pin_GPIO_01),
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_SD_01_FLEXPWM1_PWM0_B, &pin_GPIO_SD_01),
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_01_FLEXPWM1_PWM0_B, &pin_GPIO_01),
 
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_AD_12_FLEXPWM1_PWM0_X, &pin_GPIO_AD_12),
 
-    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_04_FLEXPWM1_PWM1_A, &pin_GPIO_04),
     PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_SD_04_FLEXPWM1_PWM1_A, &pin_GPIO_SD_04),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_04_FLEXPWM1_PWM1_A, &pin_GPIO_04),
 
-    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_03_FLEXPWM1_PWM1_B, &pin_GPIO_03),
     PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_SD_03_FLEXPWM1_PWM1_B, &pin_GPIO_SD_03),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_03_FLEXPWM1_PWM1_B, &pin_GPIO_03),
 
     PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_AD_11_FLEXPWM1_PWM1_X, &pin_GPIO_AD_11),
 
-    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_06_FLEXPWM1_PWM2_A, &pin_GPIO_06),
     PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A, &pin_GPIO_AD_04),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_06_FLEXPWM1_PWM2_A, &pin_GPIO_06),
 
-    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_05_FLEXPWM1_PWM2_B, &pin_GPIO_05),
     PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_AD_03_FLEXPWM1_PWM2_B, &pin_GPIO_AD_03),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_05_FLEXPWM1_PWM2_B, &pin_GPIO_05),
 
     PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_AD_10_FLEXPWM1_PWM2_X, &pin_GPIO_AD_10),
 
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_08_FLEXPWM1_PWM3_A, &pin_GPIO_08),
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_06_FLEXPWM1_PWM3_A, &pin_GPIO_AD_06),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_08_FLEXPWM1_PWM3_A, &pin_GPIO_08),
 
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_07_FLEXPWM1_PWM3_B, &pin_GPIO_07),
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_05_FLEXPWM1_PWM3_B, &pin_GPIO_AD_05),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_07_FLEXPWM1_PWM3_B, &pin_GPIO_07),
 
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X, &pin_GPIO_AD_09),
 };
-
-const mcu_periph_obj_t mcu_sai_rx_bclk_list[] = {
-    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_08),
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_00),
-};
-const mcu_periph_obj_t mcu_sai_rx_data0_list[] = {
-    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_03),
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_03),
-};
-const mcu_periph_obj_t mcu_sai_rx_sync_list[] = {
-    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_02),
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_04),
-};
-const mcu_periph_obj_t mcu_sai_tx_bclk_list[] = {
-    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_06),
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_01),
-};
-const mcu_periph_obj_t mcu_sai_tx_data0_list[] = {
-    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_04),
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_02),
-};
-const mcu_periph_obj_t mcu_sai_tx_sync_list[] = {
-    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_07),
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_SD_00),
-};
-const mcu_periph_obj_t mcu_mqs_left_list[] = {
-    PERIPH_PIN(3, 4, 0, 0, &pin_GPIO_AD_01),
-};
-const mcu_periph_obj_t mcu_mqs_right_list[] = {
-    PERIPH_PIN(3, 4, 0, 0, &pin_GPIO_AD_02),
-};
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h
index 045e33ca0e..e03e2c7967 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h
@@ -3,7 +3,9 @@
  *
  * The MIT License (MIT)
  *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,37 +26,30 @@
  * THE SOFTWARE.
  */
 
-#ifndef MICROPY_INCLUDED_MIMXRT10XX_MIMXRT1011_PERIPHERALS_MIMXRT1011_PERIPH_H
-#define MICROPY_INCLUDED_MIMXRT10XX_MIMXRT1011_PERIPHERALS_MIMXRT1011_PERIPH_H
-
+#pragma once
 extern LPI2C_Type *const mcu_i2c_banks[2];
-
 extern const mcu_periph_obj_t mcu_i2c_sda_list[8];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[8];
 
 extern LPSPI_Type *const mcu_spi_banks[2];
-
 extern const mcu_periph_obj_t mcu_spi_sck_list[4];
-extern const mcu_periph_obj_t mcu_spi_mosi_list[4];
-extern const mcu_periph_obj_t mcu_spi_miso_list[4];
+extern const mcu_periph_obj_t mcu_spi_sdo_list[4];
+extern const mcu_periph_obj_t mcu_spi_sdi_list[4];
 
 extern LPUART_Type *const mcu_uart_banks[4];
-
 extern const mcu_periph_obj_t mcu_uart_rx_list[9];
 extern const mcu_periph_obj_t mcu_uart_tx_list[9];
 extern const mcu_periph_obj_t mcu_uart_rts_list[4];
 extern const mcu_periph_obj_t mcu_uart_cts_list[4];
 
-extern const mcu_pwm_obj_t mcu_pwm_list[20];
-
-extern const mcu_periph_obj_t mcu_sai_rx_bclk_list[2];
-extern const mcu_periph_obj_t mcu_sai_rx_data0_list[2];
-extern const mcu_periph_obj_t mcu_sai_rx_sync_list[2];
-extern const mcu_periph_obj_t mcu_sai_tx_bclk_list[2];
-extern const mcu_periph_obj_t mcu_sai_tx_data0_list[2];
-extern const mcu_periph_obj_t mcu_sai_tx_sync_list[2];
+extern I2S_Type *const mcu_i2s_banks[2];
+extern const mcu_periph_obj_t mcu_i2s_rx_data0_list[2];
+extern const mcu_periph_obj_t mcu_i2s_rx_sync_list[2];
+extern const mcu_periph_obj_t mcu_i2s_tx_bclk_list[2];
+extern const mcu_periph_obj_t mcu_i2s_tx_data0_list[2];
+extern const mcu_periph_obj_t mcu_i2s_tx_sync_list[2];
 
 extern const mcu_periph_obj_t mcu_mqs_left_list[1];
 extern const mcu_periph_obj_t mcu_mqs_right_list[1];
 
-#endif // MICROPY_INCLUDED_MIMXRT10XX_MIMXRT1011_PERIPHERALS_MIMXRT1011_PERIPH_H
+extern const mcu_pwm_obj_t mcu_pwm_list[20];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pin_names.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pin_names.h
new file mode 100644
index 0000000000..b197256a36
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pin_names.h
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+// define FORMAT_PIN(pin_name) and then include this file.
+
+FORMAT_PIN(GPIO_AD_14)
+FORMAT_PIN(GPIO_AD_13)
+FORMAT_PIN(GPIO_AD_12)
+FORMAT_PIN(GPIO_AD_11)
+FORMAT_PIN(GPIO_AD_10)
+FORMAT_PIN(GPIO_AD_09)
+FORMAT_PIN(GPIO_AD_08)
+FORMAT_PIN(GPIO_AD_07)
+FORMAT_PIN(GPIO_AD_06)
+FORMAT_PIN(GPIO_AD_05)
+FORMAT_PIN(GPIO_AD_04)
+FORMAT_PIN(GPIO_AD_03)
+FORMAT_PIN(GPIO_AD_02)
+FORMAT_PIN(GPIO_AD_01)
+FORMAT_PIN(GPIO_AD_00)
+
+FORMAT_PIN(GPIO_SD_13)
+FORMAT_PIN(GPIO_SD_12)
+FORMAT_PIN(GPIO_SD_11)
+FORMAT_PIN(GPIO_SD_10)
+FORMAT_PIN(GPIO_SD_09)
+FORMAT_PIN(GPIO_SD_08)
+FORMAT_PIN(GPIO_SD_07)
+FORMAT_PIN(GPIO_SD_06)
+FORMAT_PIN(GPIO_SD_05)
+FORMAT_PIN(GPIO_SD_04)
+FORMAT_PIN(GPIO_SD_03)
+FORMAT_PIN(GPIO_SD_02)
+FORMAT_PIN(GPIO_SD_01)
+FORMAT_PIN(GPIO_SD_00)
+
+FORMAT_PIN(GPIO_13)
+FORMAT_PIN(GPIO_12)
+FORMAT_PIN(GPIO_11)
+FORMAT_PIN(GPIO_10)
+FORMAT_PIN(GPIO_09)
+FORMAT_PIN(GPIO_08)
+FORMAT_PIN(GPIO_07)
+FORMAT_PIN(GPIO_06)
+FORMAT_PIN(GPIO_05)
+FORMAT_PIN(GPIO_04)
+FORMAT_PIN(GPIO_03)
+FORMAT_PIN(GPIO_02)
+FORMAT_PIN(GPIO_01)
+FORMAT_PIN(GPIO_00)
+FORMAT_PIN(USB_OTG1_DN)
+FORMAT_PIN(USB_OTG1_DP)
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c
index 492d1c6f08..a2b38a8a67 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c
@@ -5,6 +5,7 @@
  *
  * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -29,48 +30,49 @@
 #include "py/mphal.h"
 #include "mimxrt10xx/pins.h"
 
-const mcu_pin_obj_t pin_GPIO_00 = PIN(GPIO1, 0, GPIO_00, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_01 = PIN(GPIO1, 1, GPIO_01, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_02 = PIN(GPIO1, 2, GPIO_02, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_03 = PIN(GPIO1, 3, GPIO_03, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_04 = PIN(GPIO1, 4, GPIO_04, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_05 = PIN(GPIO1, 5, GPIO_05, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_06 = PIN(GPIO1, 6, GPIO_06, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_07 = PIN(GPIO1, 7, GPIO_07, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_08 = PIN(GPIO1, 8, GPIO_08, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_09 = PIN(GPIO1, 9, GPIO_09, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_10 = PIN(GPIO1, 10, GPIO_10, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_11 = PIN(GPIO1, 11, GPIO_11, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_12 = PIN(GPIO1, 12, GPIO_12, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_13 = PIN(GPIO1, 13, GPIO_13, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_00 = PIN(GPIO1, 14, GPIO_AD_00, ADC1, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_01 = PIN(GPIO1, 15, GPIO_AD_01, ADC1, 1, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_02 = PIN(GPIO1, 16, GPIO_AD_02, ADC1, 2, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_03 = PIN(GPIO1, 17, GPIO_AD_03, ADC1, 3, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_04 = PIN(GPIO1, 18, GPIO_AD_04, ADC1, 4, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_05 = PIN(GPIO1, 19, GPIO_AD_05, ADC1, 5, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_06 = PIN(GPIO1, 20, GPIO_AD_06, ADC1, 6, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_07 = PIN(GPIO1, 21, GPIO_AD_07, ADC1, 7, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_AD_08 = PIN(GPIO1, 22, GPIO_AD_08, ADC1, 8, 0x00000007, 0x000070A0);
-const mcu_pin_obj_t pin_GPIO_AD_09 = PIN(GPIO1, 23, GPIO_AD_09, ADC1, 9, 0x00000007, 0x000090B1);
-const mcu_pin_obj_t pin_GPIO_AD_10 = PIN(GPIO1, 24, GPIO_AD_10, ADC1, 10, 0x00000007, 0x000070A0);
-const mcu_pin_obj_t pin_GPIO_AD_11 = PIN(GPIO1, 25, GPIO_AD_11, ADC1, 11, 0x00000007, 0x000030A0);
-const mcu_pin_obj_t pin_GPIO_AD_12 = PIN(GPIO1, 26, GPIO_AD_12, ADC1, 12, 0x00000007, 0x000030A0);
-const mcu_pin_obj_t pin_GPIO_AD_13 = PIN(GPIO1, 27, GPIO_AD_13, ADC1, 13, 0x00000007, 0x000070A0);
 const mcu_pin_obj_t pin_GPIO_AD_14 = PIN(GPIO1, 28, GPIO_AD_14, ADC1, 14, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_00 = PIN(GPIO2, 0, GPIO_SD_00, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_01 = PIN(GPIO2, 1, GPIO_SD_01, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_02 = PIN(GPIO2, 2, GPIO_SD_02, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_03 = PIN(GPIO2, 3, GPIO_SD_03, NO_ADC, 0, 0x00000006, 0x000030A0);
-const mcu_pin_obj_t pin_GPIO_SD_04 = PIN(GPIO2, 4, GPIO_SD_04, NO_ADC, 0, 0x00000006, 0x000030A0);
-const mcu_pin_obj_t pin_GPIO_SD_05 = PIN(GPIO2, 5, GPIO_SD_05, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_06 = PIN(GPIO2, 6, GPIO_SD_06, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_07 = PIN(GPIO2, 7, GPIO_SD_07, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_08 = PIN(GPIO2, 8, GPIO_SD_08, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_09 = PIN(GPIO2, 9, GPIO_SD_09, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_10 = PIN(GPIO2, 10, GPIO_SD_10, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_11 = PIN(GPIO2, 11, GPIO_SD_11, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_12 = PIN(GPIO2, 12, GPIO_SD_12, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_AD_13 = PIN(GPIO1, 27, GPIO_AD_13, ADC1, 13, 0x00000007, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_12 = PIN(GPIO1, 26, GPIO_AD_12, ADC1, 12, 0x00000007, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_AD_11 = PIN(GPIO1, 25, GPIO_AD_11, ADC1, 11, 0x00000007, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_AD_10 = PIN(GPIO1, 24, GPIO_AD_10, ADC1, 10, 0x00000007, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_09 = PIN(GPIO1, 23, GPIO_AD_09, ADC1, 9, 0x00000007, 0x000090B1);
+const mcu_pin_obj_t pin_GPIO_AD_08 = PIN(GPIO1, 22, GPIO_AD_08, ADC1, 8, 0x00000007, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_07 = PIN(GPIO1, 21, GPIO_AD_07, ADC1, 7, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_AD_06 = PIN(GPIO1, 20, GPIO_AD_06, ADC1, 6, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_AD_05 = PIN(GPIO1, 19, GPIO_AD_05, ADC1, 5, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_AD_04 = PIN(GPIO1, 18, GPIO_AD_04, ADC1, 4, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_AD_03 = PIN(GPIO1, 17, GPIO_AD_03, ADC1, 3, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_AD_02 = PIN(GPIO1, 16, GPIO_AD_02, ADC1, 2, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_AD_01 = PIN(GPIO1, 15, GPIO_AD_01, ADC1, 1, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_AD_00 = PIN(GPIO1, 14, GPIO_AD_00, ADC1, 0, 0x00000005, 0x000010A0);
 const mcu_pin_obj_t pin_GPIO_SD_13 = PIN(GPIO2, 13, GPIO_SD_13, NO_ADC, 0, 0x00000005, 0x000010A0);
-const mcu_pin_obj_t pin_GPIO_SD_14 = PIN(GPIO2, 14, GPIO_SD_14, NO_ADC, 0, 0x00000000, 0x000010A0);
-// pin_GPIO_SD_14 isn't actually used as a pad but we include it anyway to make resetting easier
+const mcu_pin_obj_t pin_GPIO_SD_12 = PIN(GPIO2, 12, GPIO_SD_12, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_11 = PIN(GPIO2, 11, GPIO_SD_11, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_10 = PIN(GPIO2, 10, GPIO_SD_10, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_09 = PIN(GPIO2, 9, GPIO_SD_09, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_08 = PIN(GPIO2, 8, GPIO_SD_08, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_07 = PIN(GPIO2, 7, GPIO_SD_07, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_06 = PIN(GPIO2, 6, GPIO_SD_06, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_05 = PIN(GPIO2, 5, GPIO_SD_05, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_04 = PIN(GPIO2, 4, GPIO_SD_04, NO_ADC, 0, 0x00000006, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_SD_03 = PIN(GPIO2, 3, GPIO_SD_03, NO_ADC, 0, 0x00000006, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_SD_02 = PIN(GPIO2, 2, GPIO_SD_02, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_01 = PIN(GPIO2, 1, GPIO_SD_01, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_SD_00 = PIN(GPIO2, 0, GPIO_SD_00, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_13 = PIN(GPIO1, 13, GPIO_13, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_12 = PIN(GPIO1, 12, GPIO_12, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_11 = PIN(GPIO1, 11, GPIO_11, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_10 = PIN(GPIO1, 10, GPIO_10, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_09 = PIN(GPIO1, 9, GPIO_09, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_08 = PIN(GPIO1, 8, GPIO_08, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_07 = PIN(GPIO1, 7, GPIO_07, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_06 = PIN(GPIO1, 6, GPIO_06, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_05 = PIN(GPIO1, 5, GPIO_05, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_04 = PIN(GPIO1, 4, GPIO_04, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_03 = PIN(GPIO1, 3, GPIO_03, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_02 = PIN(GPIO1, 2, GPIO_02, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_01 = PIN(GPIO1, 1, GPIO_01, NO_ADC, 0, 0x00000005, 0x000010A0);
+const mcu_pin_obj_t pin_GPIO_00 = PIN(GPIO1, 0, GPIO_00, NO_ADC, 0, 0x00000005, 0x000010A0);
+
+const mcu_pin_obj_t pin_USB_OTG1_DN = { { &mcu_pin_type }, };
+const mcu_pin_obj_t pin_USB_OTG1_DP = { { &mcu_pin_type }, };
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.h
index 58ef7329e7..118eff9335 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.h
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.h
@@ -3,7 +3,9 @@
  *
  * The MIT License (MIT)
  *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,56 +26,11 @@
  * THE SOFTWARE.
  */
 
-#ifndef MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1011_PINS_H
-#define MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1011_PINS_H
+#pragma once
 
-extern const mcu_pin_obj_t pin_GPIO_00;
-extern const mcu_pin_obj_t pin_GPIO_01;
-extern const mcu_pin_obj_t pin_GPIO_02;
-extern const mcu_pin_obj_t pin_GPIO_03;
-extern const mcu_pin_obj_t pin_GPIO_04;
-extern const mcu_pin_obj_t pin_GPIO_05;
-extern const mcu_pin_obj_t pin_GPIO_06;
-extern const mcu_pin_obj_t pin_GPIO_07;
-extern const mcu_pin_obj_t pin_GPIO_08;
-extern const mcu_pin_obj_t pin_GPIO_09;
-extern const mcu_pin_obj_t pin_GPIO_10;
-extern const mcu_pin_obj_t pin_GPIO_11;
-extern const mcu_pin_obj_t pin_GPIO_12;
-extern const mcu_pin_obj_t pin_GPIO_13;
+#define FORMAT_PIN(pin_name) extern const mcu_pin_obj_t pin_##pin_name;
+#include "pin_names.h"
+#undef FORMAT_PIN
 
-extern const mcu_pin_obj_t pin_GPIO_SD_00;
-extern const mcu_pin_obj_t pin_GPIO_SD_01;
-extern const mcu_pin_obj_t pin_GPIO_SD_02;
-extern const mcu_pin_obj_t pin_GPIO_SD_03;
-extern const mcu_pin_obj_t pin_GPIO_SD_04;
-extern const mcu_pin_obj_t pin_GPIO_SD_05;
-extern const mcu_pin_obj_t pin_GPIO_SD_06;
-extern const mcu_pin_obj_t pin_GPIO_SD_07;
-extern const mcu_pin_obj_t pin_GPIO_SD_08;
-extern const mcu_pin_obj_t pin_GPIO_SD_09;
-extern const mcu_pin_obj_t pin_GPIO_SD_10;
-extern const mcu_pin_obj_t pin_GPIO_SD_11;
-extern const mcu_pin_obj_t pin_GPIO_SD_12;
-extern const mcu_pin_obj_t pin_GPIO_SD_13;
-extern const mcu_pin_obj_t pin_GPIO_SD_14;
-
-extern const mcu_pin_obj_t pin_GPIO_AD_00;
-extern const mcu_pin_obj_t pin_GPIO_AD_01;
-extern const mcu_pin_obj_t pin_GPIO_AD_02;
-extern const mcu_pin_obj_t pin_GPIO_AD_03;
-extern const mcu_pin_obj_t pin_GPIO_AD_04;
-extern const mcu_pin_obj_t pin_GPIO_AD_05;
-extern const mcu_pin_obj_t pin_GPIO_AD_06;
-extern const mcu_pin_obj_t pin_GPIO_AD_07;
-extern const mcu_pin_obj_t pin_GPIO_AD_08;
-extern const mcu_pin_obj_t pin_GPIO_AD_09;
-extern const mcu_pin_obj_t pin_GPIO_AD_10;
-extern const mcu_pin_obj_t pin_GPIO_AD_11;
-extern const mcu_pin_obj_t pin_GPIO_AD_12;
-extern const mcu_pin_obj_t pin_GPIO_AD_13;
-extern const mcu_pin_obj_t pin_GPIO_AD_14;
-
-extern const mcu_pin_obj_t mcu_pin_list[IOMUXC_SW_PAD_CTL_PAD_COUNT];
-
-#endif // MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1011_PINS_H
+#define PIN_COUNT (IOMUXC_SW_PAD_CTL_PAD_COUNT + 2)
+extern const mcu_pin_obj_t mcu_pin_list[PIN_COUNT];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/clocks.c
new file mode 100644
index 0000000000..bef213a7c7
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/clocks.c
@@ -0,0 +1,315 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "mpconfigport.h"
+
+#include "fsl_clock.h"
+#include "fsl_iomuxc.h"
+
+#include "supervisor/linker.h"
+
+#include "board.h"
+
+#include "clocks.h"
+
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           196363636UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             117333333UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                0UL
+
+
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 1,                             /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+    .numerator = 0,                               /* 30 bit numerator of fractional loop divider */
+    .denominator = 1,                             /* 30 bit denominator of fractional loop divider */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 0,                             /* PLL loop divider, Fout = Fin * 20 */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+{
+    .enableClkOutput500M = true,                  /* Enable the PLL providing the ENET 500MHz reference clock */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+
+// Based on the hello_world example in the SDK
+void clocks_init(void) {
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+    #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+    #endif
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 2);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+    #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+    /* Disable Usb1 PLL output for USBPHY1. */
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+    #endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/periph.c
new file mode 100644
index 0000000000..9c56c47dc0
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/periph.c
@@ -0,0 +1,184 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "mimxrt10xx/periph.h"
+
+LPI2C_Type *const mcu_i2c_banks[2] = { LPI2C1, LPI2C2 };
+
+const mcu_periph_obj_t mcu_i2c_sda_list[2] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_B1_15),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_18),
+};
+
+const mcu_periph_obj_t mcu_i2c_scl_list[2] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_B1_14),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_19),
+};
+
+LPSPI_Type *const mcu_spi_banks[2] = { LPSPI1, LPSPI2 };
+
+const mcu_periph_obj_t mcu_spi_sck_list[2] = {
+    PERIPH_PIN(1, 1, 0, 0, &pin_GPIO_AD_B0_10),
+
+    PERIPH_PIN(2, 4, 0, 0, &pin_GPIO_SD_B1_07),
+};
+
+const mcu_periph_obj_t mcu_spi_sdo_list[2] = {
+    PERIPH_PIN(1, 1, 0, 0, &pin_GPIO_AD_B0_12),
+
+    PERIPH_PIN(2, 4, 0, 0, &pin_GPIO_SD_B1_08),
+};
+
+const mcu_periph_obj_t mcu_spi_sdi_list[2] = {
+    PERIPH_PIN(1, 1, 0, 0, &pin_GPIO_AD_B0_13),
+
+    PERIPH_PIN(2, 4, 0, 0, &pin_GPIO_SD_B1_09),
+};
+
+LPUART_Type *const mcu_uart_banks[4] = { LPUART1, LPUART2, LPUART3, LPUART4 };
+
+const mcu_periph_obj_t mcu_uart_rx_list[6] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_07),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_23),
+
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_07),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B0_15),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_33),
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_AD_B1_11),
+};
+
+const mcu_periph_obj_t mcu_uart_tx_list[6] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_06),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_22),
+
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_06),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B0_14),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_32),
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_AD_B1_10),
+};
+
+const mcu_periph_obj_t mcu_uart_rts_list[3] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_09),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_21),
+
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B0_13),
+};
+
+const mcu_periph_obj_t mcu_uart_cts_list[3] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_08),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_20),
+
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B0_12),
+};
+
+I2S_Type *const mcu_i2s_banks[3] = { SAI1, SAI2, SAI3 };
+
+const mcu_periph_obj_t mcu_i2s_rx_data0_list[3] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_21),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_08),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_11),
+};
+
+const mcu_periph_obj_t mcu_i2s_rx_sync_list[3] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_18),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_07),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_10),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_bclk_list[4] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_26),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_04),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_33),
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_06),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_data0_list[4] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_25),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_06),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_32),
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_08),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_sync_list[4] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_27),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_05),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_34),
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_07),
+};
+
+const mcu_periph_obj_t mcu_mqs_left_list[2] = {
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_17),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_07),
+};
+
+const mcu_periph_obj_t mcu_mqs_right_list[2] = {
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_16),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_06),
+};
+
+const mcu_pwm_obj_t mcu_pwm_list[12] = {
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00, &pin_GPIO_EMC_26),
+
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00, &pin_GPIO_EMC_27),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01, &pin_GPIO_EMC_24),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01, &pin_GPIO_EMC_25),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02, &pin_GPIO_EMC_22),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02, &pin_GPIO_AD_B1_10),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02, &pin_GPIO_EMC_23),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02, &pin_GPIO_AD_B1_11),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03, &pin_GPIO_EMC_20),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03, &pin_GPIO_AD_B1_12),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03, &pin_GPIO_EMC_21),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03, &pin_GPIO_AD_B1_13),
+};
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/periph.h
new file mode 100644
index 0000000000..af53706d6f
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/periph.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+extern LPI2C_Type *const mcu_i2c_banks[2];
+extern const mcu_periph_obj_t mcu_i2c_sda_list[2];
+extern const mcu_periph_obj_t mcu_i2c_scl_list[2];
+
+extern LPSPI_Type *const mcu_spi_banks[2];
+extern const mcu_periph_obj_t mcu_spi_sck_list[2];
+extern const mcu_periph_obj_t mcu_spi_sdo_list[2];
+extern const mcu_periph_obj_t mcu_spi_sdi_list[2];
+
+extern LPUART_Type *const mcu_uart_banks[4];
+extern const mcu_periph_obj_t mcu_uart_rx_list[6];
+extern const mcu_periph_obj_t mcu_uart_tx_list[6];
+extern const mcu_periph_obj_t mcu_uart_rts_list[3];
+extern const mcu_periph_obj_t mcu_uart_cts_list[3];
+
+extern I2S_Type *const mcu_i2s_banks[3];
+extern const mcu_periph_obj_t mcu_i2s_rx_data0_list[3];
+extern const mcu_periph_obj_t mcu_i2s_rx_sync_list[3];
+extern const mcu_periph_obj_t mcu_i2s_tx_bclk_list[4];
+extern const mcu_periph_obj_t mcu_i2s_tx_data0_list[4];
+extern const mcu_periph_obj_t mcu_i2s_tx_sync_list[4];
+
+extern const mcu_periph_obj_t mcu_mqs_left_list[2];
+extern const mcu_periph_obj_t mcu_mqs_right_list[2];
+
+extern const mcu_pwm_obj_t mcu_pwm_list[12];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pin_names.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pin_names.h
new file mode 100644
index 0000000000..0416e2ee65
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pin_names.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+// define FORMAT_PIN(pin_name) and then include this file.
+
+FORMAT_PIN(GPIO_EMC_04)
+FORMAT_PIN(GPIO_EMC_05)
+FORMAT_PIN(GPIO_EMC_06)
+FORMAT_PIN(GPIO_EMC_07)
+FORMAT_PIN(GPIO_EMC_08)
+FORMAT_PIN(GPIO_EMC_09)
+FORMAT_PIN(GPIO_EMC_16)
+FORMAT_PIN(GPIO_EMC_17)
+FORMAT_PIN(GPIO_EMC_18)
+FORMAT_PIN(GPIO_EMC_19)
+FORMAT_PIN(GPIO_EMC_20)
+FORMAT_PIN(GPIO_EMC_21)
+FORMAT_PIN(GPIO_EMC_22)
+FORMAT_PIN(GPIO_EMC_23)
+FORMAT_PIN(GPIO_EMC_24)
+FORMAT_PIN(GPIO_EMC_25)
+FORMAT_PIN(GPIO_EMC_26)
+FORMAT_PIN(GPIO_EMC_27)
+FORMAT_PIN(GPIO_EMC_32)
+FORMAT_PIN(GPIO_EMC_33)
+FORMAT_PIN(GPIO_EMC_34)
+FORMAT_PIN(GPIO_EMC_35)
+
+FORMAT_PIN(GPIO_AD_B0_00)
+FORMAT_PIN(GPIO_AD_B0_01)
+FORMAT_PIN(GPIO_AD_B0_02)
+FORMAT_PIN(GPIO_AD_B0_03)
+FORMAT_PIN(GPIO_AD_B0_04)
+FORMAT_PIN(GPIO_AD_B0_05)
+FORMAT_PIN(GPIO_AD_B0_06)
+FORMAT_PIN(GPIO_AD_B0_07)
+FORMAT_PIN(GPIO_AD_B0_08)
+FORMAT_PIN(GPIO_AD_B0_09)
+FORMAT_PIN(GPIO_AD_B0_10)
+FORMAT_PIN(GPIO_AD_B0_11)
+FORMAT_PIN(GPIO_AD_B0_12)
+FORMAT_PIN(GPIO_AD_B0_13)
+FORMAT_PIN(GPIO_AD_B0_14)
+FORMAT_PIN(GPIO_AD_B0_15)
+
+FORMAT_PIN(GPIO_AD_B1_10)
+FORMAT_PIN(GPIO_AD_B1_11)
+FORMAT_PIN(GPIO_AD_B1_12)
+FORMAT_PIN(GPIO_AD_B1_13)
+FORMAT_PIN(GPIO_AD_B1_14)
+FORMAT_PIN(GPIO_AD_B1_15)
+
+FORMAT_PIN(GPIO_SD_B1_00)
+FORMAT_PIN(GPIO_SD_B1_01)
+FORMAT_PIN(GPIO_SD_B1_02)
+FORMAT_PIN(GPIO_SD_B1_03)
+FORMAT_PIN(GPIO_SD_B1_04)
+FORMAT_PIN(GPIO_SD_B1_05)
+FORMAT_PIN(GPIO_SD_B1_06)
+FORMAT_PIN(GPIO_SD_B1_07)
+FORMAT_PIN(GPIO_SD_B1_08)
+FORMAT_PIN(GPIO_SD_B1_09)
+FORMAT_PIN(GPIO_SD_B1_10)
+FORMAT_PIN(GPIO_SD_B1_11)
+FORMAT_PIN(USB_OTG1_DN)
+FORMAT_PIN(USB_OTG1_DP)
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pins.c
new file mode 100644
index 0000000000..efa7abcedf
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pins.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "mimxrt10xx/pins.h"
+
+const mcu_pin_obj_t pin_GPIO_EMC_04 = PIN(GPIO2, 4, GPIO_EMC_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_05 = PIN(GPIO2, 5, GPIO_EMC_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_06 = PIN(GPIO2, 6, GPIO_EMC_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_07 = PIN(GPIO2, 7, GPIO_EMC_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_08 = PIN(GPIO2, 8, GPIO_EMC_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_09 = PIN(GPIO2, 9, GPIO_EMC_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_16 = PIN(GPIO2, 16, GPIO_EMC_16, NO_ADC, 0, 0x00000006, 0x000030B0);
+const mcu_pin_obj_t pin_GPIO_EMC_17 = PIN(GPIO2, 17, GPIO_EMC_17, NO_ADC, 0, 0x00000006, 0x000030B0);
+const mcu_pin_obj_t pin_GPIO_EMC_18 = PIN(GPIO2, 18, GPIO_EMC_18, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_19 = PIN(GPIO2, 19, GPIO_EMC_19, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_20 = PIN(GPIO2, 20, GPIO_EMC_20, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_21 = PIN(GPIO2, 21, GPIO_EMC_21, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_22 = PIN(GPIO2, 22, GPIO_EMC_22, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_23 = PIN(GPIO2, 23, GPIO_EMC_23, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_24 = PIN(GPIO2, 24, GPIO_EMC_24, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_25 = PIN(GPIO2, 25, GPIO_EMC_25, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_26 = PIN(GPIO2, 26, GPIO_EMC_26, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_27 = PIN(GPIO2, 27, GPIO_EMC_27, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_32 = PIN(GPIO3, 0, GPIO_EMC_32, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_33 = PIN(GPIO3, 1, GPIO_EMC_33, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_34 = PIN(GPIO3, 2, GPIO_EMC_34, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_35 = PIN(GPIO3, 3, GPIO_EMC_35, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_00 = PIN(GPIO1, 0, GPIO_AD_B0_00, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_01 = PIN(GPIO1, 1, GPIO_AD_B0_01, NO_ADC, 0, 0x00000000, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_02 = PIN(GPIO1, 2, GPIO_AD_B0_02, NO_ADC, 0, 0x00000000, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_03 = PIN(GPIO1, 3, GPIO_AD_B0_03, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_04 = PIN(GPIO1, 4, GPIO_AD_B0_04, NO_ADC, 0, 0x00000000, 0x000090B1);
+const mcu_pin_obj_t pin_GPIO_AD_B0_05 = PIN(GPIO1, 5, GPIO_AD_B0_05, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_06 = PIN(GPIO1, 6, GPIO_AD_B0_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_07 = PIN(GPIO1, 7, GPIO_AD_B0_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_08 = PIN(GPIO1, 8, GPIO_AD_B0_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_09 = PIN(GPIO1, 9, GPIO_AD_B0_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_10 = PIN(GPIO1, 10, GPIO_AD_B0_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_11 = PIN(GPIO1, 11, GPIO_AD_B0_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_12 = PIN(GPIO1, 12, GPIO_AD_B0_12, ADC1, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_13 = PIN(GPIO1, 13, GPIO_AD_B0_13, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_14 = PIN(GPIO1, 14, GPIO_AD_B0_14, ADC1, 1, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_15 = PIN(GPIO1, 15, GPIO_AD_B0_15, ADC1, 2, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_10 = PIN(GPIO1, 26, GPIO_AD_B1_10, ADC1, 10, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_11 = PIN(GPIO1, 27, GPIO_AD_B1_11, ADC1, 11, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_12 = PIN(GPIO1, 28, GPIO_AD_B1_12, ADC1, 12, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_13 = PIN(GPIO1, 29, GPIO_AD_B1_13, ADC1, 13, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_14 = PIN(GPIO1, 30, GPIO_AD_B1_14, ADC1, 14, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_15 = PIN(GPIO1, 31, GPIO_AD_B1_15, ADC1, 15, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_00 = PIN(GPIO3, 20, GPIO_SD_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_01 = PIN(GPIO3, 21, GPIO_SD_B1_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_02 = PIN(GPIO3, 22, GPIO_SD_B1_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_03 = PIN(GPIO3, 23, GPIO_SD_B1_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_04 = PIN(GPIO3, 24, GPIO_SD_B1_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_05 = PIN(GPIO3, 25, GPIO_SD_B1_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_06 = PIN(GPIO3, 26, GPIO_SD_B1_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_07 = PIN(GPIO3, 27, GPIO_SD_B1_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_08 = PIN(GPIO3, 28, GPIO_SD_B1_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_09 = PIN(GPIO3, 29, GPIO_SD_B1_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_10 = PIN(GPIO3, 30, GPIO_SD_B1_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_11 = PIN(GPIO3, 31, GPIO_SD_B1_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+
+const mcu_pin_obj_t pin_USB_OTG1_DN = { { &mcu_pin_type }, };
+const mcu_pin_obj_t pin_USB_OTG1_DP = { { &mcu_pin_type }, };
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pins.h
new file mode 100644
index 0000000000..118eff9335
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1015/pins.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+
+#define FORMAT_PIN(pin_name) extern const mcu_pin_obj_t pin_##pin_name;
+#include "pin_names.h"
+#undef FORMAT_PIN
+
+#define PIN_COUNT (IOMUXC_SW_PAD_CTL_PAD_COUNT + 2)
+extern const mcu_pin_obj_t mcu_pin_list[PIN_COUNT];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c
index 198f85110e..eab7f4eacc 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c
@@ -36,6 +36,8 @@
 #include "fsl_clock.h"
 #include "fsl_iomuxc.h"
 
+#include "board.h"
+
 #include "clocks.h"
 
 // These values are pulled from the SDK's devices/MIMXRT1021/project_template/clock_config.* files.
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c
index 59bd3cc105..8615e6cfc5 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c
@@ -5,7 +5,7 @@
  *
  * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
- * Copyright (c) 2020 Scott Shawcroft
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -70,13 +70,13 @@ const mcu_periph_obj_t mcu_spi_sck_list[8] = {
     PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 1, &pin_GPIO_EMC_10),
     PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 2, &pin_GPIO_SD_B1_07),
 
-    PERIPH_PIN(3, 2, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B1_12),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_12),
 
-    PERIPH_PIN(4, 2, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B1_02),
-    PERIPH_PIN(4, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 1, &pin_GPIO_EMC_32),
+    PERIPH_PIN(4, 2, kIOMUXC_LPSPI4_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B1_02),
+    PERIPH_PIN(4, 4, kIOMUXC_LPSPI4_SCK_SELECT_INPUT, 1, &pin_GPIO_EMC_32),
 };
 
-const mcu_periph_obj_t mcu_spi_mosi_list[8] = {
+const mcu_periph_obj_t mcu_spi_sdo_list[8] = {
     PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 0, &pin_GPIO_SD_B0_04),
     PERIPH_PIN(1, 1, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 1, &pin_GPIO_AD_B0_12),
 
@@ -84,13 +84,13 @@ const mcu_periph_obj_t mcu_spi_mosi_list[8] = {
     PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 1, &pin_GPIO_EMC_12),
     PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 2, &pin_GPIO_SD_B1_08),
 
-    PERIPH_PIN(3, 2, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 0, &pin_GPIO_AD_B1_14),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_14),
 
-    PERIPH_PIN(4, 2, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 0, &pin_GPIO_AD_B1_04),
-    PERIPH_PIN(4, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 1, &pin_GPIO_EMC_34),
+    PERIPH_PIN(4, 2, kIOMUXC_LPSPI4_SDO_SELECT_INPUT, 0, &pin_GPIO_AD_B1_04),
+    PERIPH_PIN(4, 4, kIOMUXC_LPSPI4_SDO_SELECT_INPUT, 1, &pin_GPIO_EMC_34),
 };
 
-const mcu_periph_obj_t mcu_spi_miso_list[8] = {
+const mcu_periph_obj_t mcu_spi_sdi_list[8] = {
     PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 0, &pin_GPIO_SD_B0_05),
     PERIPH_PIN(1, 1, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 1, &pin_GPIO_AD_B0_13),
 
@@ -98,10 +98,10 @@ const mcu_periph_obj_t mcu_spi_miso_list[8] = {
     PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 1, &pin_GPIO_EMC_13),
     PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 2, &pin_GPIO_SD_B1_09),
 
-    PERIPH_PIN(3, 2, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 0, &pin_GPIO_AD_B1_15),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_15),
 
-    PERIPH_PIN(4, 2, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 0, &pin_GPIO_AD_B1_05),
-    PERIPH_PIN(4, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 1, &pin_GPIO_EMC_35),
+    PERIPH_PIN(4, 2, kIOMUXC_LPSPI4_SDI_SELECT_INPUT, 0, &pin_GPIO_AD_B1_05),
+    PERIPH_PIN(4, 4, kIOMUXC_LPSPI4_SDI_SELECT_INPUT, 1, &pin_GPIO_EMC_35),
 };
 
 LPUART_Type *const mcu_uart_banks[8] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 };
@@ -162,18 +162,18 @@ const mcu_periph_obj_t mcu_uart_rts_list[10] = {
     PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_09),
 
     PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_21),
-    PERIPH_PIN(2, 2, 0, 1, &pin_GPIO_AD_B1_07),
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_07),
 
-    PERIPH_PIN(3, 2, 0, 1, &pin_GPIO_AD_B0_13),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B0_13),
 
     PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_01),
-    PERIPH_PIN(4, 2, 0, 1, &pin_GPIO_EMC_31),
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_31),
 
     PERIPH_PIN(5, 2, 0, 0, &pin_GPIO_EMC_37),
 
     PERIPH_PIN(6, 2, 0, 0, &pin_GPIO_EMC_15),
 
-    PERIPH_PIN(7, 2, 0, 1, &pin_GPIO_SD_B0_03),
+    PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_SD_B0_03),
 
     PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_EMC_25),
 };
@@ -184,10 +184,10 @@ const mcu_periph_obj_t mcu_uart_cts_list[10] = {
     PERIPH_PIN(2, 2, kIOMUXC_LPUART2_CTS_B_SELECT_INPUT, 0, &pin_GPIO_AD_B1_06),
     PERIPH_PIN(2, 2, kIOMUXC_LPUART2_CTS_B_SELECT_INPUT, 1, &pin_GPIO_EMC_20),
 
-    PERIPH_PIN(3, 2, 0, 1, &pin_GPIO_AD_B0_12),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B0_12),
 
     PERIPH_PIN(4, 2, kIOMUXC_LPUART4_CTS_B_SELECT_INPUT, 0, &pin_GPIO_EMC_00),
-    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_CTS_B_SELECT_INPUT, 0, &pin_GPIO_EMC_30),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_CTS_B_SELECT_INPUT, 1, &pin_GPIO_EMC_30),
 
     PERIPH_PIN(5, 2, 0, 0, &pin_GPIO_EMC_36),
 
@@ -198,126 +198,142 @@ const mcu_periph_obj_t mcu_uart_cts_list[10] = {
     PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_EMC_24),
 };
 
-const mcu_pwm_obj_t mcu_pwm_list[39] = {
+I2S_Type *const mcu_i2s_banks[3] = { SAI1, SAI2, SAI3 };
+
+const mcu_periph_obj_t mcu_i2s_rx_data0_list[7] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_EMC_13),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 1, &pin_GPIO_AD_B1_05),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 2, &pin_GPIO_EMC_21),
+
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_SD_B0_03),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT, 1, &pin_GPIO_EMC_08),
+
+    PERIPH_PIN(3, 3, kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_SD_B1_11),
+    PERIPH_PIN(3, 3, kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT, 1, &pin_GPIO_EMC_31),
+};
+
+const mcu_periph_obj_t mcu_i2s_rx_sync_list[7] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_AD_B1_04),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 1, &pin_GPIO_EMC_15),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 2, &pin_GPIO_EMC_18),
+
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B0_01),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT, 1, &pin_GPIO_EMC_07),
+
+    PERIPH_PIN(3, 3, kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B1_10),
+    PERIPH_PIN(3, 3, kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT, 1, &pin_GPIO_EMC_30),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_bclk_list[7] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_EMC_11),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 1, &pin_GPIO_AD_B1_01),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 2, &pin_GPIO_EMC_26),
+
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_SD_B0_05),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT, 1, &pin_GPIO_EMC_04),
+
+    PERIPH_PIN(3, 3, kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_SD_B1_06),
+    PERIPH_PIN(3, 3, kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT, 1, &pin_GPIO_EMC_33),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_data0_list[7] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_12),
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_25),
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_03),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_06),
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_SD_B0_04),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_32),
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_08),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_sync_list[7] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_EMC_10),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B1_02),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 2, &pin_GPIO_EMC_27),
+
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B0_06),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT, 1, &pin_GPIO_EMC_05),
+
+    PERIPH_PIN(3, 3, kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B1_07),
+    PERIPH_PIN(3, 3, kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT, 1, &pin_GPIO_EMC_34),
+};
+
+const mcu_periph_obj_t mcu_mqs_left_list[3] = {
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_17),
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_38),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_07),
+};
+
+const mcu_periph_obj_t mcu_mqs_right_list[3] = {
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_16),
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_37),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_06),
+};
+
+const mcu_pwm_obj_t mcu_pwm_list[40] = {
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00, &pin_GPIO_EMC_26),
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00, &pin_GPIO_AD_B1_06),
 
-    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01, &pin_GPIO_EMC_24),
-    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01, &pin_GPIO_AD_B1_08),
-
-    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02, &pin_GPIO_EMC_22),
-    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02, &pin_GPIO_AD_B1_10),
-
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03, &pin_GPIO_EMC_20),
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03, &pin_GPIO_AD_B1_12),
-
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00, &pin_GPIO_EMC_27),
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00, &pin_GPIO_AD_B1_07),
 
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00, &pin_GPIO_EMC_28),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01, &pin_GPIO_EMC_24),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01, &pin_GPIO_AD_B1_08),
+
     PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01, &pin_GPIO_EMC_25),
     PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01, &pin_GPIO_AD_B1_09),
 
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01, &pin_GPIO_EMC_29),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02, &pin_GPIO_EMC_22),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02, &pin_GPIO_AD_B1_10),
+
     PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02, &pin_GPIO_EMC_23),
     PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02, &pin_GPIO_AD_B1_11),
 
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02, &pin_GPIO_EMC_30),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03, &pin_GPIO_EMC_20),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03, &pin_GPIO_AD_B1_12),
+
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03, &pin_GPIO_EMC_21),
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03, &pin_GPIO_AD_B1_13),
 
-    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00, &pin_GPIO_EMC_28),
-    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01, &pin_GPIO_EMC_29),
-    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02, &pin_GPIO_EMC_30),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03, &pin_GPIO_EMC_31),
 
     PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00, &pin_GPIO_EMC_38),
     PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00, &pin_GPIO_AD_B0_14),
 
-    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01, &pin_GPIO_EMC_36),
-    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01, &pin_GPIO_AD_B0_12),
-
-    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02, &pin_GPIO_EMC_30),
-    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02, &pin_GPIO_AD_B0_10),
-
-    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03, &pin_GPIO_EMC_28),
-    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03, &pin_GPIO_AD_B0_06),
-
     PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00, &pin_GPIO_EMC_39),
     PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00, &pin_GPIO_AD_B0_15),
 
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00, &pin_GPIO_EMC_10),
+
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01, &pin_GPIO_EMC_36),
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01, &pin_GPIO_AD_B0_12),
+
     PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01, &pin_GPIO_EMC_37),
     PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01, &pin_GPIO_AD_B0_13),
 
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01, &pin_GPIO_EMC_11),
+
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02, &pin_GPIO_EMC_30),
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02, &pin_GPIO_AD_B0_10),
+
     PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02, &pin_GPIO_EMC_31),
     PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02, &pin_GPIO_AD_B0_11),
 
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02, &pin_GPIO_EMC_12),
+
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03, &pin_GPIO_EMC_28),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03, &pin_GPIO_AD_B0_06),
+
     PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03, &pin_GPIO_EMC_29),
     PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03, &pin_GPIO_AD_B0_07),
 
-    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00, &pin_GPIO_EMC_10),
-    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01, &pin_GPIO_EMC_11),
-    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02, &pin_GPIO_EMC_12),
     PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03, &pin_GPIO_EMC_13),
 };
-
-const mcu_periph_obj_t mcu_sai_rx_bclk_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_14),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_19),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_06),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_09),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_SD_B0_02),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_29),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_09),
-};
-const mcu_periph_obj_t mcu_sai_rx_data0_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_13),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_21),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_05),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_08),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_SD_B0_03),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_30),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_11),
-};
-const mcu_periph_obj_t mcu_sai_rx_sync_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_15),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_28),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_04),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_07),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_SD_B0_01),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_30),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_10),
-};
-const mcu_periph_obj_t mcu_sai_tx_bclk_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_11),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_26),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_01),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_04),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_SD_B0_04),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_33),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B0_06),
-};
-const mcu_periph_obj_t mcu_sai_tx_data0_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_12),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_25),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_03),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_06),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_SD_B0_04),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_32),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_08),
-};
-const mcu_periph_obj_t mcu_sai_tx_sync_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_10),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_27),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_02),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_05),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_SD_B0_06),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_34),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B1_07),
-};
-const mcu_periph_obj_t mcu_mqs_left_list[] = {
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_07),
-    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_17),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_38),
-};
-const mcu_periph_obj_t mcu_mqs_right_list[] = {
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_06),
-    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_16),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_37),
-};
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.h
index 51c97b3eef..496e0ab153 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.h
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.h
@@ -3,8 +3,9 @@
  *
  * The MIT License (MIT)
  *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
- * Copyright (c) 2020 Scott Shawcroft
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -26,33 +27,29 @@
  */
 
 #pragma once
-
 extern LPI2C_Type *const mcu_i2c_banks[4];
-
 extern const mcu_periph_obj_t mcu_i2c_sda_list[8];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[8];
 
 extern LPSPI_Type *const mcu_spi_banks[4];
-
 extern const mcu_periph_obj_t mcu_spi_sck_list[8];
-extern const mcu_periph_obj_t mcu_spi_mosi_list[8];
-extern const mcu_periph_obj_t mcu_spi_miso_list[8];
+extern const mcu_periph_obj_t mcu_spi_sdo_list[8];
+extern const mcu_periph_obj_t mcu_spi_sdi_list[8];
 
 extern LPUART_Type *const mcu_uart_banks[8];
-
 extern const mcu_periph_obj_t mcu_uart_rx_list[16];
 extern const mcu_periph_obj_t mcu_uart_tx_list[16];
 extern const mcu_periph_obj_t mcu_uart_rts_list[10];
 extern const mcu_periph_obj_t mcu_uart_cts_list[10];
 
-extern const mcu_pwm_obj_t mcu_pwm_list[39];
-
-extern const mcu_periph_obj_t mcu_sai_rx_bclk_list[7];
-extern const mcu_periph_obj_t mcu_sai_rx_data0_list[7];
-extern const mcu_periph_obj_t mcu_sai_rx_sync_list[7];
-extern const mcu_periph_obj_t mcu_sai_tx_bclk_list[7];
-extern const mcu_periph_obj_t mcu_sai_tx_data0_list[7];
-extern const mcu_periph_obj_t mcu_sai_tx_sync_list[7];
+extern I2S_Type *const mcu_i2s_banks[3];
+extern const mcu_periph_obj_t mcu_i2s_rx_data0_list[7];
+extern const mcu_periph_obj_t mcu_i2s_rx_sync_list[7];
+extern const mcu_periph_obj_t mcu_i2s_tx_bclk_list[7];
+extern const mcu_periph_obj_t mcu_i2s_tx_data0_list[7];
+extern const mcu_periph_obj_t mcu_i2s_tx_sync_list[7];
 
 extern const mcu_periph_obj_t mcu_mqs_left_list[3];
 extern const mcu_periph_obj_t mcu_mqs_right_list[3];
+
+extern const mcu_pwm_obj_t mcu_pwm_list[40];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pin_names.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pin_names.h
new file mode 100644
index 0000000000..1f159afe53
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pin_names.h
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+// define FORMAT_PIN(pin_name) and then include this file.
+
+FORMAT_PIN(GPIO_EMC_00)
+FORMAT_PIN(GPIO_EMC_01)
+FORMAT_PIN(GPIO_EMC_02)
+FORMAT_PIN(GPIO_EMC_03)
+FORMAT_PIN(GPIO_EMC_04)
+FORMAT_PIN(GPIO_EMC_05)
+FORMAT_PIN(GPIO_EMC_06)
+FORMAT_PIN(GPIO_EMC_07)
+FORMAT_PIN(GPIO_EMC_08)
+FORMAT_PIN(GPIO_EMC_09)
+FORMAT_PIN(GPIO_EMC_10)
+FORMAT_PIN(GPIO_EMC_11)
+FORMAT_PIN(GPIO_EMC_12)
+FORMAT_PIN(GPIO_EMC_13)
+FORMAT_PIN(GPIO_EMC_14)
+FORMAT_PIN(GPIO_EMC_15)
+FORMAT_PIN(GPIO_EMC_16)
+FORMAT_PIN(GPIO_EMC_17)
+FORMAT_PIN(GPIO_EMC_18)
+FORMAT_PIN(GPIO_EMC_19)
+FORMAT_PIN(GPIO_EMC_20)
+FORMAT_PIN(GPIO_EMC_21)
+FORMAT_PIN(GPIO_EMC_22)
+FORMAT_PIN(GPIO_EMC_23)
+FORMAT_PIN(GPIO_EMC_24)
+FORMAT_PIN(GPIO_EMC_25)
+FORMAT_PIN(GPIO_EMC_26)
+FORMAT_PIN(GPIO_EMC_27)
+FORMAT_PIN(GPIO_EMC_28)
+FORMAT_PIN(GPIO_EMC_29)
+FORMAT_PIN(GPIO_EMC_30)
+FORMAT_PIN(GPIO_EMC_31)
+FORMAT_PIN(GPIO_EMC_32)
+FORMAT_PIN(GPIO_EMC_33)
+FORMAT_PIN(GPIO_EMC_34)
+FORMAT_PIN(GPIO_EMC_35)
+FORMAT_PIN(GPIO_EMC_36)
+FORMAT_PIN(GPIO_EMC_37)
+FORMAT_PIN(GPIO_EMC_38)
+FORMAT_PIN(GPIO_EMC_39)
+FORMAT_PIN(GPIO_EMC_40)
+FORMAT_PIN(GPIO_EMC_41)
+
+FORMAT_PIN(GPIO_AD_B0_00)
+FORMAT_PIN(GPIO_AD_B0_01)
+FORMAT_PIN(GPIO_AD_B0_02)
+FORMAT_PIN(GPIO_AD_B0_03)
+FORMAT_PIN(GPIO_AD_B0_04)
+FORMAT_PIN(GPIO_AD_B0_05)
+FORMAT_PIN(GPIO_AD_B0_06)
+FORMAT_PIN(GPIO_AD_B0_07)
+FORMAT_PIN(GPIO_AD_B0_08)
+FORMAT_PIN(GPIO_AD_B0_09)
+FORMAT_PIN(GPIO_AD_B0_10)
+FORMAT_PIN(GPIO_AD_B0_11)
+FORMAT_PIN(GPIO_AD_B0_12)
+FORMAT_PIN(GPIO_AD_B0_13)
+FORMAT_PIN(GPIO_AD_B0_14)
+FORMAT_PIN(GPIO_AD_B0_15)
+
+FORMAT_PIN(GPIO_AD_B1_00)
+FORMAT_PIN(GPIO_AD_B1_01)
+FORMAT_PIN(GPIO_AD_B1_02)
+FORMAT_PIN(GPIO_AD_B1_03)
+FORMAT_PIN(GPIO_AD_B1_04)
+FORMAT_PIN(GPIO_AD_B1_05)
+FORMAT_PIN(GPIO_AD_B1_06)
+FORMAT_PIN(GPIO_AD_B1_07)
+FORMAT_PIN(GPIO_AD_B1_08)
+FORMAT_PIN(GPIO_AD_B1_09)
+FORMAT_PIN(GPIO_AD_B1_10)
+FORMAT_PIN(GPIO_AD_B1_11)
+FORMAT_PIN(GPIO_AD_B1_12)
+FORMAT_PIN(GPIO_AD_B1_13)
+FORMAT_PIN(GPIO_AD_B1_14)
+FORMAT_PIN(GPIO_AD_B1_15)
+
+FORMAT_PIN(GPIO_SD_B0_00)
+FORMAT_PIN(GPIO_SD_B0_01)
+FORMAT_PIN(GPIO_SD_B0_02)
+FORMAT_PIN(GPIO_SD_B0_03)
+FORMAT_PIN(GPIO_SD_B0_04)
+FORMAT_PIN(GPIO_SD_B0_05)
+FORMAT_PIN(GPIO_SD_B0_06)
+
+FORMAT_PIN(GPIO_SD_B1_00)
+FORMAT_PIN(GPIO_SD_B1_01)
+FORMAT_PIN(GPIO_SD_B1_02)
+FORMAT_PIN(GPIO_SD_B1_03)
+FORMAT_PIN(GPIO_SD_B1_04)
+FORMAT_PIN(GPIO_SD_B1_05)
+FORMAT_PIN(GPIO_SD_B1_06)
+FORMAT_PIN(GPIO_SD_B1_07)
+FORMAT_PIN(GPIO_SD_B1_08)
+FORMAT_PIN(GPIO_SD_B1_09)
+FORMAT_PIN(GPIO_SD_B1_10)
+FORMAT_PIN(GPIO_SD_B1_11)
+FORMAT_PIN(USB_OTG1_DN)
+FORMAT_PIN(USB_OTG1_DP)
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c
index fe39f7e19d..e349f43542 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c
@@ -5,6 +5,7 @@
  *
  * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -29,38 +30,6 @@
 #include "py/mphal.h"
 #include "mimxrt10xx/pins.h"
 
-const mcu_pin_obj_t pin_GPIO_AD_B0_00 = PIN(GPIO1, 0, GPIO_AD_B0_00, NO_ADC, 0, 0x00000000, 0x000070A0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_01 = PIN(GPIO1, 1, GPIO_AD_B0_01, NO_ADC, 0, 0x00000000, 0x000030A0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_02 = PIN(GPIO1, 2, GPIO_AD_B0_02, NO_ADC, 0, 0x00000000, 0x000030A0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_03 = PIN(GPIO1, 3, GPIO_AD_B0_03, NO_ADC, 0, 0x00000000, 0x000070A0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_04 = PIN(GPIO1, 4, GPIO_AD_B0_04, NO_ADC, 0, 0x00000000, 0x000090B1);
-const mcu_pin_obj_t pin_GPIO_AD_B0_05 = PIN(GPIO1, 5, GPIO_AD_B0_05, NO_ADC, 0, 0x00000000, 0x000070A0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_06 = PIN(GPIO1, 6, GPIO_AD_B0_06, NO_ADC, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_07 = PIN(GPIO1, 7, GPIO_AD_B0_07, NO_ADC, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_08 = PIN(GPIO1, 8, GPIO_AD_B0_08, NO_ADC, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_09 = PIN(GPIO1, 9, GPIO_AD_B0_09, NO_ADC, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_10 = PIN(GPIO1, 10, GPIO_AD_B0_10, NO_ADC, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_11 = PIN(GPIO1, 11, GPIO_AD_B0_11, NO_ADC, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_12 = PIN(GPIO1, 12, GPIO_AD_B0_12, ADC1, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_13 = PIN(GPIO1, 13, GPIO_AD_B0_13, ADC2, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_14 = PIN(GPIO1, 14, GPIO_AD_B0_14, ADC2, 1, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B0_15 = PIN(GPIO1, 15, GPIO_AD_B0_15, ADC1, 2, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_00 = PIN(GPIO1, 16, GPIO_AD_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_01 = PIN(GPIO1, 17, GPIO_AD_B1_01, ADC1, 3, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_02 = PIN(GPIO1, 18, GPIO_AD_B1_02, ADC2, 3, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_03 = PIN(GPIO1, 19, GPIO_AD_B1_03, ADC1, 4, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_04 = PIN(GPIO1, 20, GPIO_AD_B1_04, ADC2, 4, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_05 = PIN(GPIO1, 21, GPIO_AD_B1_05, ADC2, 5, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_06 = PIN(GPIO1, 22, GPIO_AD_B1_06, ADC2, 6, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_07 = PIN(GPIO1, 23, GPIO_AD_B1_07, ADC2, 7, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_08 = PIN(GPIO1, 24, GPIO_AD_B1_08, ADC2, 8, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_09 = PIN(GPIO1, 25, GPIO_AD_B1_09, ADC2, 9, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_10 = PIN(GPIO1, 26, GPIO_AD_B1_10, ADC2, 10, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_11 = PIN(GPIO1, 27, GPIO_AD_B1_11, ADC2, 11, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_12 = PIN(GPIO1, 28, GPIO_AD_B1_12, ADC2, 12, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_13 = PIN(GPIO1, 29, GPIO_AD_B1_13, ADC2, 13, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_14 = PIN(GPIO1, 30, GPIO_AD_B1_14, ADC2, 14, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_15 = PIN(GPIO1, 31, GPIO_AD_B1_15, ADC2, 15, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_00 = PIN(GPIO2, 0, GPIO_EMC_00, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_01 = PIN(GPIO2, 1, GPIO_EMC_01, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_02 = PIN(GPIO2, 2, GPIO_EMC_02, NO_ADC, 0, 0x00000005, 0x000010B0);
@@ -103,6 +72,38 @@ const mcu_pin_obj_t pin_GPIO_EMC_38 = PIN(GPIO3, 6, GPIO_EMC_38, NO_ADC, 0, 0x00
 const mcu_pin_obj_t pin_GPIO_EMC_39 = PIN(GPIO3, 7, GPIO_EMC_39, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_40 = PIN(GPIO3, 8, GPIO_EMC_40, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_41 = PIN(GPIO3, 9, GPIO_EMC_41, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_00 = PIN(GPIO1, 0, GPIO_AD_B0_00, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_01 = PIN(GPIO1, 1, GPIO_AD_B0_01, NO_ADC, 0, 0x00000000, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_02 = PIN(GPIO1, 2, GPIO_AD_B0_02, NO_ADC, 0, 0x00000000, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_03 = PIN(GPIO1, 3, GPIO_AD_B0_03, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_04 = PIN(GPIO1, 4, GPIO_AD_B0_04, NO_ADC, 0, 0x00000000, 0x000090B1);
+const mcu_pin_obj_t pin_GPIO_AD_B0_05 = PIN(GPIO1, 5, GPIO_AD_B0_05, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_06 = PIN(GPIO1, 6, GPIO_AD_B0_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_07 = PIN(GPIO1, 7, GPIO_AD_B0_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_08 = PIN(GPIO1, 8, GPIO_AD_B0_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_09 = PIN(GPIO1, 9, GPIO_AD_B0_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_10 = PIN(GPIO1, 10, GPIO_AD_B0_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_11 = PIN(GPIO1, 11, GPIO_AD_B0_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_12 = PIN(GPIO1, 12, GPIO_AD_B0_12, ADC1, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_13 = PIN(GPIO1, 13, GPIO_AD_B0_13, ADC2, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_14 = PIN(GPIO1, 14, GPIO_AD_B0_14, ADC2, 1, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_15 = PIN(GPIO1, 15, GPIO_AD_B0_15, ADC2, 2, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_00 = PIN(GPIO1, 16, GPIO_AD_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_01 = PIN(GPIO1, 17, GPIO_AD_B1_01, ADC1, 3, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_02 = PIN(GPIO1, 18, GPIO_AD_B1_02, ADC2, 3, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_03 = PIN(GPIO1, 19, GPIO_AD_B1_03, ADC1, 4, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_04 = PIN(GPIO1, 20, GPIO_AD_B1_04, ADC2, 4, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_05 = PIN(GPIO1, 21, GPIO_AD_B1_05, ADC2, 5, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_06 = PIN(GPIO1, 22, GPIO_AD_B1_06, ADC2, 6, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_07 = PIN(GPIO1, 23, GPIO_AD_B1_07, ADC2, 7, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_08 = PIN(GPIO1, 24, GPIO_AD_B1_08, ADC2, 8, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_09 = PIN(GPIO1, 25, GPIO_AD_B1_09, ADC2, 9, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_10 = PIN(GPIO1, 26, GPIO_AD_B1_10, ADC2, 10, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_11 = PIN(GPIO1, 27, GPIO_AD_B1_11, ADC2, 11, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_12 = PIN(GPIO1, 28, GPIO_AD_B1_12, ADC2, 12, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_13 = PIN(GPIO1, 29, GPIO_AD_B1_13, ADC2, 13, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_14 = PIN(GPIO1, 30, GPIO_AD_B1_14, ADC2, 14, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_15 = PIN(GPIO1, 31, GPIO_AD_B1_15, ADC2, 15, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_SD_B0_00 = PIN(GPIO3, 13, GPIO_SD_B0_00, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_SD_B0_01 = PIN(GPIO3, 14, GPIO_SD_B0_01, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_SD_B0_02 = PIN(GPIO3, 15, GPIO_SD_B0_02, NO_ADC, 0, 0x00000005, 0x000010B0);
@@ -122,3 +123,6 @@ const mcu_pin_obj_t pin_GPIO_SD_B1_08 = PIN(GPIO3, 28, GPIO_SD_B1_08, NO_ADC, 0,
 const mcu_pin_obj_t pin_GPIO_SD_B1_09 = PIN(GPIO3, 29, GPIO_SD_B1_09, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_SD_B1_10 = PIN(GPIO3, 30, GPIO_SD_B1_10, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_SD_B1_11 = PIN(GPIO3, 31, GPIO_SD_B1_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+
+const mcu_pin_obj_t pin_USB_OTG1_DN = { { &mcu_pin_type }, };
+const mcu_pin_obj_t pin_USB_OTG1_DP = { { &mcu_pin_type }, };
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.h
index 4485b6e152..118eff9335 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.h
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.h
@@ -3,8 +3,9 @@
  *
  * The MIT License (MIT)
  *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
- * Copyright (c) 2020 Scott Shawcroft
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -25,107 +26,11 @@
  * THE SOFTWARE.
  */
 
-#ifndef MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PINS_H
-#define MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PINS_H
+#pragma once
 
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_00;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_01;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_02;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_03;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_04;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_05;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_06;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_07;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_08;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_09;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_10;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_11;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_12;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_13;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_14;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_15;
+#define FORMAT_PIN(pin_name) extern const mcu_pin_obj_t pin_##pin_name;
+#include "pin_names.h"
+#undef FORMAT_PIN
 
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_00;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_01;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_02;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_03;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_04;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_05;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_06;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_07;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_08;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_09;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_10;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_11;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_12;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_13;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_14;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_15;
-
-extern const mcu_pin_obj_t pin_GPIO_EMC_00;
-extern const mcu_pin_obj_t pin_GPIO_EMC_01;
-extern const mcu_pin_obj_t pin_GPIO_EMC_02;
-extern const mcu_pin_obj_t pin_GPIO_EMC_03;
-extern const mcu_pin_obj_t pin_GPIO_EMC_04;
-extern const mcu_pin_obj_t pin_GPIO_EMC_05;
-extern const mcu_pin_obj_t pin_GPIO_EMC_06;
-extern const mcu_pin_obj_t pin_GPIO_EMC_07;
-extern const mcu_pin_obj_t pin_GPIO_EMC_08;
-extern const mcu_pin_obj_t pin_GPIO_EMC_09;
-extern const mcu_pin_obj_t pin_GPIO_EMC_10;
-extern const mcu_pin_obj_t pin_GPIO_EMC_11;
-extern const mcu_pin_obj_t pin_GPIO_EMC_12;
-extern const mcu_pin_obj_t pin_GPIO_EMC_13;
-extern const mcu_pin_obj_t pin_GPIO_EMC_14;
-extern const mcu_pin_obj_t pin_GPIO_EMC_15;
-extern const mcu_pin_obj_t pin_GPIO_EMC_16;
-extern const mcu_pin_obj_t pin_GPIO_EMC_17;
-extern const mcu_pin_obj_t pin_GPIO_EMC_18;
-extern const mcu_pin_obj_t pin_GPIO_EMC_19;
-extern const mcu_pin_obj_t pin_GPIO_EMC_20;
-extern const mcu_pin_obj_t pin_GPIO_EMC_21;
-extern const mcu_pin_obj_t pin_GPIO_EMC_22;
-extern const mcu_pin_obj_t pin_GPIO_EMC_23;
-extern const mcu_pin_obj_t pin_GPIO_EMC_24;
-extern const mcu_pin_obj_t pin_GPIO_EMC_25;
-extern const mcu_pin_obj_t pin_GPIO_EMC_26;
-extern const mcu_pin_obj_t pin_GPIO_EMC_27;
-extern const mcu_pin_obj_t pin_GPIO_EMC_28;
-extern const mcu_pin_obj_t pin_GPIO_EMC_29;
-extern const mcu_pin_obj_t pin_GPIO_EMC_30;
-extern const mcu_pin_obj_t pin_GPIO_EMC_31;
-extern const mcu_pin_obj_t pin_GPIO_EMC_32;
-extern const mcu_pin_obj_t pin_GPIO_EMC_33;
-extern const mcu_pin_obj_t pin_GPIO_EMC_34;
-extern const mcu_pin_obj_t pin_GPIO_EMC_35;
-extern const mcu_pin_obj_t pin_GPIO_EMC_36;
-extern const mcu_pin_obj_t pin_GPIO_EMC_37;
-extern const mcu_pin_obj_t pin_GPIO_EMC_38;
-extern const mcu_pin_obj_t pin_GPIO_EMC_39;
-extern const mcu_pin_obj_t pin_GPIO_EMC_40;
-extern const mcu_pin_obj_t pin_GPIO_EMC_41;
-
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_00;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_01;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_02;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_03;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_04;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_05;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_06;
-
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_00;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_01;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_02;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_03;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_04;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_05;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_06;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_07;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_08;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_09;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_10;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_11;
-
-extern const mcu_pin_obj_t mcu_pin_list[IOMUXC_SW_PAD_CTL_PAD_COUNT];
-
-#endif // MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PINS_H
+#define PIN_COUNT (IOMUXC_SW_PAD_CTL_PAD_COUNT + 2)
+extern const mcu_pin_obj_t mcu_pin_list[PIN_COUNT];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/clocks.c
new file mode 100644
index 0000000000..f62f974bdd
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/clocks.c
@@ -0,0 +1,382 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "mpconfigport.h"
+
+#include "fsl_clock.h"
+#include "fsl_iomuxc.h"
+#include "fsl_device_registers.h"
+
+#include "board.h"
+
+#include "clocks.h"
+
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             528000000U  /*!< Core clock frequency: 528000000Hz */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 100,                           /* PLL loop divider, Fout = Fin * 50 */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 1,                             /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+    .numerator = 0,                               /* 30 bit numerator of fractional loop divider */
+    .denominator = 1,                             /* 30 bit denominator of fractional loop divider */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 0,                             /* PLL loop divider, Fout = Fin * 20 */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 31,                            /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .postDivider = 8,                             /* Divider after PLL */
+    .numerator = 0,                               /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .denominator = 1,                             /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void clocks_init(void) {
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+    #ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+    #endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+    #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+    #endif
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+    #ifndef SKIP_SYSCLK_INIT
+    #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+    #endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+    #endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+    #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+    /* Disable Usb1 PLL output for USBPHY1. */
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+    #endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+        CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+        CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 0);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/periph.c
new file mode 100644
index 0000000000..bbd41e7007
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/periph.c
@@ -0,0 +1,356 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "mimxrt10xx/periph.h"
+
+LPI2C_Type *const mcu_i2c_banks[4] = { LPI2C1, LPI2C2, LPI2C3, LPI2C4 };
+
+const mcu_periph_obj_t mcu_i2c_sda_list[9] = {
+    PERIPH_PIN(1, 2, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 0, &pin_GPIO_SD_B1_05),
+    PERIPH_PIN(1, 3, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 1, &pin_GPIO_AD_B1_01),
+
+    PERIPH_PIN(2, 3, kIOMUXC_LPI2C2_SDA_SELECT_INPUT, 0, &pin_GPIO_SD_B1_10),
+    PERIPH_PIN(2, 2, kIOMUXC_LPI2C2_SDA_SELECT_INPUT, 1, &pin_GPIO_B0_05),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPI2C3_SDA_SELECT_INPUT, 0, &pin_GPIO_EMC_21),
+    PERIPH_PIN(3, 2, kIOMUXC_LPI2C3_SDA_SELECT_INPUT, 1, &pin_GPIO_SD_B0_01),
+    PERIPH_PIN(3, 1, kIOMUXC_LPI2C3_SDA_SELECT_INPUT, 2, &pin_GPIO_AD_B1_06),
+
+    PERIPH_PIN(4, 2, kIOMUXC_LPI2C4_SDA_SELECT_INPUT, 0, &pin_GPIO_EMC_11),
+    PERIPH_PIN(4, 0, kIOMUXC_LPI2C4_SDA_SELECT_INPUT, 1, &pin_GPIO_AD_B0_13),
+};
+
+const mcu_periph_obj_t mcu_i2c_scl_list[9] = {
+    PERIPH_PIN(1, 2, kIOMUXC_LPI2C1_SCL_SELECT_INPUT, 0, &pin_GPIO_SD_B1_04),
+    PERIPH_PIN(1, 3, kIOMUXC_LPI2C1_SCL_SELECT_INPUT, 1, &pin_GPIO_AD_B1_00),
+
+    PERIPH_PIN(2, 3, kIOMUXC_LPI2C2_SCL_SELECT_INPUT, 0, &pin_GPIO_SD_B1_11),
+    PERIPH_PIN(2, 2, kIOMUXC_LPI2C2_SCL_SELECT_INPUT, 1, &pin_GPIO_B0_04),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPI2C3_SCL_SELECT_INPUT, 0, &pin_GPIO_EMC_22),
+    PERIPH_PIN(3, 2, kIOMUXC_LPI2C3_SCL_SELECT_INPUT, 1, &pin_GPIO_SD_B0_00),
+    PERIPH_PIN(3, 1, kIOMUXC_LPI2C3_SCL_SELECT_INPUT, 2, &pin_GPIO_AD_B1_07),
+
+    PERIPH_PIN(4, 2, kIOMUXC_LPI2C4_SCL_SELECT_INPUT, 0, &pin_GPIO_EMC_12),
+    PERIPH_PIN(4, 0, kIOMUXC_LPI2C4_SCL_SELECT_INPUT, 1, &pin_GPIO_AD_B0_12),
+};
+
+LPSPI_Type *const mcu_spi_banks[3] = { LPSPI1, LPSPI2, LPSPI3 };
+
+const mcu_periph_obj_t mcu_spi_sck_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 0, &pin_GPIO_EMC_27),
+    PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 1, &pin_GPIO_SD_B0_00),
+
+    PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 0, &pin_GPIO_SD_B1_07),
+    PERIPH_PIN(2, 2, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 1, &pin_GPIO_EMC_00),
+
+    PERIPH_PIN(3, 3, kIOMUXC_LPSPI3_SCK_SELECT_INPUT, 0, &pin_GPIO_B0_03),
+    PERIPH_PIN(3, 1, kIOMUXC_LPSPI3_SCK_SELECT_INPUT, 1, &pin_GPIO_B1_07),
+};
+
+const mcu_periph_obj_t mcu_spi_sdo_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 0, &pin_GPIO_EMC_28),
+    PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 1, &pin_GPIO_SD_B0_02),
+
+    PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 0, &pin_GPIO_SD_B1_08),
+    PERIPH_PIN(2, 2, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 1, &pin_GPIO_EMC_02),
+
+    PERIPH_PIN(3, 3, kIOMUXC_LPSPI3_SDO_SELECT_INPUT, 0, &pin_GPIO_B0_02),
+    PERIPH_PIN(3, 1, kIOMUXC_LPSPI3_SDO_SELECT_INPUT, 1, &pin_GPIO_B1_06),
+};
+
+const mcu_periph_obj_t mcu_spi_sdi_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 0, &pin_GPIO_EMC_29),
+    PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 1, &pin_GPIO_SD_B0_03),
+
+    PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 0, &pin_GPIO_SD_B1_09),
+    PERIPH_PIN(2, 2, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 1, &pin_GPIO_EMC_03),
+
+    PERIPH_PIN(3, 3, kIOMUXC_LPSPI3_SDI_SELECT_INPUT, 0, &pin_GPIO_B0_01),
+    PERIPH_PIN(3, 1, kIOMUXC_LPSPI3_SDI_SELECT_INPUT, 1, &pin_GPIO_B1_05),
+};
+
+LPUART_Type *const mcu_uart_banks[8] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 };
+
+const mcu_periph_obj_t mcu_uart_rx_list[16] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_13),
+
+    PERIPH_PIN(2, 2, kIOMUXC_LPUART2_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_10),
+    PERIPH_PIN(2, 2, kIOMUXC_LPUART2_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_03),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_RX_SELECT_INPUT, 0, &pin_GPIO_AD_B1_07),
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_14),
+    PERIPH_PIN(3, 3, kIOMUXC_LPUART3_RX_SELECT_INPUT, 2, &pin_GPIO_B0_09),
+
+    PERIPH_PIN(4, 4, kIOMUXC_LPUART4_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_01),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_20),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_RX_SELECT_INPUT, 2, &pin_GPIO_B1_01),
+
+    PERIPH_PIN(5, 2, kIOMUXC_LPUART5_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_24),
+    PERIPH_PIN(5, 1, kIOMUXC_LPUART5_RX_SELECT_INPUT, 1, &pin_GPIO_B1_13),
+
+    PERIPH_PIN(6, 2, kIOMUXC_LPUART6_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_26),
+
+    PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_09),
+    PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_32),
+
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B0_05),
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 2, &pin_GPIO_EMC_39),
+};
+
+const mcu_periph_obj_t mcu_uart_tx_list[16] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_12),
+
+    PERIPH_PIN(2, 2, kIOMUXC_LPUART2_TX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_11),
+    PERIPH_PIN(2, 2, kIOMUXC_LPUART2_TX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_02),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_TX_SELECT_INPUT, 0, &pin_GPIO_AD_B1_06),
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_TX_SELECT_INPUT, 1, &pin_GPIO_EMC_13),
+    PERIPH_PIN(3, 3, kIOMUXC_LPUART3_TX_SELECT_INPUT, 2, &pin_GPIO_B0_08),
+
+    PERIPH_PIN(4, 4, kIOMUXC_LPUART4_TX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_00),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_TX_SELECT_INPUT, 1, &pin_GPIO_EMC_19),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_TX_SELECT_INPUT, 2, &pin_GPIO_B1_00),
+
+    PERIPH_PIN(5, 2, kIOMUXC_LPUART5_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_23),
+    PERIPH_PIN(5, 1, kIOMUXC_LPUART5_TX_SELECT_INPUT, 1, &pin_GPIO_B1_12),
+
+    PERIPH_PIN(6, 2, kIOMUXC_LPUART6_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_25),
+
+    PERIPH_PIN(7, 2, kIOMUXC_LPUART7_TX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_08),
+    PERIPH_PIN(7, 2, kIOMUXC_LPUART7_TX_SELECT_INPUT, 1, &pin_GPIO_EMC_31),
+
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_TX_SELECT_INPUT, 0, &pin_GPIO_SD_B0_04),
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_TX_SELECT_INPUT, 2, &pin_GPIO_EMC_38),
+};
+
+const mcu_periph_obj_t mcu_uart_rts_list[9] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_15),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_01),
+
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_16),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_05),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_18),
+
+    PERIPH_PIN(5, 2, 0, 0, &pin_GPIO_EMC_27),
+
+    PERIPH_PIN(6, 2, 0, 0, &pin_GPIO_EMC_29),
+
+    PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_SD_B1_07),
+
+    PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_SD_B0_03),
+};
+
+const mcu_periph_obj_t mcu_uart_cts_list[9] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_14),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_00),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 0, &pin_GPIO_EMC_15),
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 1, &pin_GPIO_AD_B1_04),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_17),
+
+    PERIPH_PIN(5, 2, 0, 0, &pin_GPIO_EMC_28),
+
+    PERIPH_PIN(6, 2, 0, 0, &pin_GPIO_EMC_30),
+
+    PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_SD_B1_06),
+
+    PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_SD_B0_02),
+};
+
+I2S_Type *const mcu_i2s_banks[3] = { SAI1, SAI2, SAI3 };
+
+const mcu_periph_obj_t mcu_i2s_rx_data0_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_SD_B1_06),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 2, &pin_GPIO_B1_00),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_EMC_08),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT, 1, &pin_GPIO_AD_B0_08),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_33),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_00),
+};
+
+const mcu_periph_obj_t mcu_i2s_rx_sync_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B1_04),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 2, &pin_GPIO_B0_14),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_EMC_09),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B0_07),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_34),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_05),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_bclk_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_SD_B1_08),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 2, &pin_GPIO_B1_02),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_EMC_06),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT, 1, &pin_GPIO_AD_B0_05),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_38),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_03),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_data0_list[6] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B1_01),
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_SD_B1_07),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_04),
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_B0_09),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_36),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_01),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_sync_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B1_09),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 2, &pin_GPIO_B1_03),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_EMC_05),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B0_04),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_39),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_02),
+};
+
+const mcu_periph_obj_t mcu_mqs_left_list[3] = {
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_14),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_05),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_01),
+};
+
+const mcu_periph_obj_t mcu_mqs_right_list[3] = {
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_13),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_04),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_00),
+};
+
+const mcu_pwm_obj_t mcu_pwm_list[61] = {
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00, &pin_GPIO_EMC_23),
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00, &pin_GPIO_SD_B0_00),
+
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00, &pin_GPIO_EMC_24),
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00, &pin_GPIO_SD_B0_01),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01, &pin_GPIO_EMC_25),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01, &pin_GPIO_SD_B0_02),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01, &pin_GPIO_EMC_26),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01, &pin_GPIO_SD_B0_03),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02, &pin_GPIO_EMC_27),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02, &pin_GPIO_SD_B0_04),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02, &pin_GPIO_EMC_28),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02, &pin_GPIO_SD_B0_05),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02, &pin_GPIO_AD_B0_12),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03, &pin_GPIO_EMC_12),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03, &pin_GPIO_EMC_38),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03, &pin_GPIO_AD_B0_10),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03, &pin_GPIO_B1_00),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03, &pin_GPIO_SD_B1_00),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03, &pin_GPIO_EMC_13),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03, &pin_GPIO_EMC_39),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03, &pin_GPIO_AD_B0_11),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03, &pin_GPIO_B1_01),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03, &pin_GPIO_SD_B1_01),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03, &pin_GPIO_AD_B0_13),
+
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00, &pin_GPIO_EMC_06),
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00, &pin_GPIO_B0_06),
+
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00, &pin_GPIO_EMC_07),
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00, &pin_GPIO_B0_07),
+
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01, &pin_GPIO_EMC_08),
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01, &pin_GPIO_B0_08),
+
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01, &pin_GPIO_EMC_09),
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01, &pin_GPIO_B0_09),
+
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02, &pin_GPIO_EMC_10),
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02, &pin_GPIO_B0_10),
+
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02, &pin_GPIO_EMC_11),
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02, &pin_GPIO_B0_11),
+
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03, &pin_GPIO_EMC_19),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03, &pin_GPIO_AD_B0_09),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03, &pin_GPIO_B1_02),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03, &pin_GPIO_SD_B1_02),
+
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03, &pin_GPIO_EMC_20),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03, &pin_GPIO_B1_03),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03, &pin_GPIO_SD_B1_03),
+
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00, &pin_GPIO_EMC_29),
+
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00, &pin_GPIO_EMC_30),
+
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01, &pin_GPIO_EMC_31),
+
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01, &pin_GPIO_EMC_32),
+
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02, &pin_GPIO_EMC_33),
+
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02, &pin_GPIO_EMC_34),
+
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03, &pin_GPIO_EMC_21),
+
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03, &pin_GPIO_EMC_22),
+
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00, &pin_GPIO_EMC_00),
+
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00, &pin_GPIO_EMC_01),
+
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01, &pin_GPIO_EMC_02),
+
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01, &pin_GPIO_EMC_03),
+
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02, &pin_GPIO_EMC_04),
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02, &pin_GPIO_B1_14),
+
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02, &pin_GPIO_EMC_05),
+
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03, &pin_GPIO_EMC_17),
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03, &pin_GPIO_B1_15),
+
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03, &pin_GPIO_EMC_18),
+};
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/periph.h
new file mode 100644
index 0000000000..69a15dc50c
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/periph.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+extern LPI2C_Type *const mcu_i2c_banks[4];
+extern const mcu_periph_obj_t mcu_i2c_sda_list[9];
+extern const mcu_periph_obj_t mcu_i2c_scl_list[9];
+
+extern LPSPI_Type *const mcu_spi_banks[3];
+extern const mcu_periph_obj_t mcu_spi_sck_list[6];
+extern const mcu_periph_obj_t mcu_spi_sdo_list[6];
+extern const mcu_periph_obj_t mcu_spi_sdi_list[6];
+
+extern LPUART_Type *const mcu_uart_banks[8];
+extern const mcu_periph_obj_t mcu_uart_rx_list[16];
+extern const mcu_periph_obj_t mcu_uart_tx_list[16];
+extern const mcu_periph_obj_t mcu_uart_rts_list[9];
+extern const mcu_periph_obj_t mcu_uart_cts_list[9];
+
+extern I2S_Type *const mcu_i2s_banks[3];
+extern const mcu_periph_obj_t mcu_i2s_rx_data0_list[6];
+extern const mcu_periph_obj_t mcu_i2s_rx_sync_list[6];
+extern const mcu_periph_obj_t mcu_i2s_tx_bclk_list[6];
+extern const mcu_periph_obj_t mcu_i2s_tx_data0_list[6];
+extern const mcu_periph_obj_t mcu_i2s_tx_sync_list[6];
+
+extern const mcu_periph_obj_t mcu_mqs_left_list[3];
+extern const mcu_periph_obj_t mcu_mqs_right_list[3];
+
+extern const mcu_pwm_obj_t mcu_pwm_list[61];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pin_names.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pin_names.h
new file mode 100644
index 0000000000..05b3110bf3
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pin_names.h
@@ -0,0 +1,151 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+// define FORMAT_PIN(pin_name) and then include this file.
+
+FORMAT_PIN(GPIO_EMC_00)
+FORMAT_PIN(GPIO_EMC_01)
+FORMAT_PIN(GPIO_EMC_02)
+FORMAT_PIN(GPIO_EMC_03)
+FORMAT_PIN(GPIO_EMC_04)
+FORMAT_PIN(GPIO_EMC_05)
+FORMAT_PIN(GPIO_EMC_06)
+FORMAT_PIN(GPIO_EMC_07)
+FORMAT_PIN(GPIO_EMC_08)
+FORMAT_PIN(GPIO_EMC_09)
+FORMAT_PIN(GPIO_EMC_10)
+FORMAT_PIN(GPIO_EMC_11)
+FORMAT_PIN(GPIO_EMC_12)
+FORMAT_PIN(GPIO_EMC_13)
+FORMAT_PIN(GPIO_EMC_14)
+FORMAT_PIN(GPIO_EMC_15)
+FORMAT_PIN(GPIO_EMC_16)
+FORMAT_PIN(GPIO_EMC_17)
+FORMAT_PIN(GPIO_EMC_18)
+FORMAT_PIN(GPIO_EMC_19)
+FORMAT_PIN(GPIO_EMC_20)
+FORMAT_PIN(GPIO_EMC_21)
+FORMAT_PIN(GPIO_EMC_22)
+FORMAT_PIN(GPIO_EMC_23)
+FORMAT_PIN(GPIO_EMC_24)
+FORMAT_PIN(GPIO_EMC_25)
+FORMAT_PIN(GPIO_EMC_26)
+FORMAT_PIN(GPIO_EMC_27)
+FORMAT_PIN(GPIO_EMC_28)
+FORMAT_PIN(GPIO_EMC_29)
+FORMAT_PIN(GPIO_EMC_30)
+FORMAT_PIN(GPIO_EMC_31)
+FORMAT_PIN(GPIO_EMC_32)
+FORMAT_PIN(GPIO_EMC_33)
+FORMAT_PIN(GPIO_EMC_34)
+FORMAT_PIN(GPIO_EMC_35)
+FORMAT_PIN(GPIO_EMC_36)
+FORMAT_PIN(GPIO_EMC_37)
+FORMAT_PIN(GPIO_EMC_38)
+FORMAT_PIN(GPIO_EMC_39)
+FORMAT_PIN(GPIO_EMC_40)
+FORMAT_PIN(GPIO_EMC_41)
+
+FORMAT_PIN(GPIO_AD_B0_04)
+FORMAT_PIN(GPIO_AD_B0_05)
+FORMAT_PIN(GPIO_AD_B0_06)
+FORMAT_PIN(GPIO_AD_B0_07)
+FORMAT_PIN(GPIO_AD_B0_08)
+FORMAT_PIN(GPIO_AD_B0_09)
+FORMAT_PIN(GPIO_AD_B0_10)
+FORMAT_PIN(GPIO_AD_B0_11)
+FORMAT_PIN(GPIO_AD_B0_12)
+FORMAT_PIN(GPIO_AD_B0_13)
+FORMAT_PIN(GPIO_AD_B0_14)
+FORMAT_PIN(GPIO_AD_B0_15)
+
+FORMAT_PIN(GPIO_AD_B1_00)
+FORMAT_PIN(GPIO_AD_B1_01)
+FORMAT_PIN(GPIO_AD_B1_02)
+FORMAT_PIN(GPIO_AD_B1_03)
+FORMAT_PIN(GPIO_AD_B1_04)
+FORMAT_PIN(GPIO_AD_B1_05)
+FORMAT_PIN(GPIO_AD_B1_06)
+FORMAT_PIN(GPIO_AD_B1_07)
+
+FORMAT_PIN(GPIO_B0_00)
+FORMAT_PIN(GPIO_B0_01)
+FORMAT_PIN(GPIO_B0_02)
+FORMAT_PIN(GPIO_B0_03)
+FORMAT_PIN(GPIO_B0_04)
+FORMAT_PIN(GPIO_B0_05)
+FORMAT_PIN(GPIO_B0_06)
+FORMAT_PIN(GPIO_B0_07)
+FORMAT_PIN(GPIO_B0_08)
+FORMAT_PIN(GPIO_B0_09)
+FORMAT_PIN(GPIO_B0_10)
+FORMAT_PIN(GPIO_B0_11)
+FORMAT_PIN(GPIO_B0_12)
+FORMAT_PIN(GPIO_B0_13)
+FORMAT_PIN(GPIO_B0_14)
+FORMAT_PIN(GPIO_B0_15)
+
+FORMAT_PIN(GPIO_B1_00)
+FORMAT_PIN(GPIO_B1_01)
+FORMAT_PIN(GPIO_B1_02)
+FORMAT_PIN(GPIO_B1_03)
+FORMAT_PIN(GPIO_B1_04)
+FORMAT_PIN(GPIO_B1_05)
+FORMAT_PIN(GPIO_B1_06)
+FORMAT_PIN(GPIO_B1_07)
+FORMAT_PIN(GPIO_B1_08)
+FORMAT_PIN(GPIO_B1_09)
+FORMAT_PIN(GPIO_B1_10)
+FORMAT_PIN(GPIO_B1_11)
+FORMAT_PIN(GPIO_B1_12)
+FORMAT_PIN(GPIO_B1_13)
+FORMAT_PIN(GPIO_B1_14)
+FORMAT_PIN(GPIO_B1_15)
+
+FORMAT_PIN(GPIO_SD_B0_00)
+FORMAT_PIN(GPIO_SD_B0_01)
+FORMAT_PIN(GPIO_SD_B0_02)
+FORMAT_PIN(GPIO_SD_B0_03)
+FORMAT_PIN(GPIO_SD_B0_04)
+FORMAT_PIN(GPIO_SD_B0_05)
+
+FORMAT_PIN(GPIO_SD_B1_00)
+FORMAT_PIN(GPIO_SD_B1_01)
+FORMAT_PIN(GPIO_SD_B1_02)
+FORMAT_PIN(GPIO_SD_B1_03)
+FORMAT_PIN(GPIO_SD_B1_04)
+FORMAT_PIN(GPIO_SD_B1_05)
+FORMAT_PIN(GPIO_SD_B1_06)
+FORMAT_PIN(GPIO_SD_B1_07)
+FORMAT_PIN(GPIO_SD_B1_08)
+FORMAT_PIN(GPIO_SD_B1_09)
+FORMAT_PIN(GPIO_SD_B1_10)
+FORMAT_PIN(GPIO_SD_B1_11)
+FORMAT_PIN(USB_OTG1_DN)
+FORMAT_PIN(USB_OTG1_DP)
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pins.c
new file mode 100644
index 0000000000..64d35c2d67
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pins.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "mimxrt10xx/pins.h"
+
+const mcu_pin_obj_t pin_GPIO_EMC_00 = PIN(GPIO4, 0, GPIO_EMC_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_01 = PIN(GPIO4, 1, GPIO_EMC_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_02 = PIN(GPIO4, 2, GPIO_EMC_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_03 = PIN(GPIO4, 3, GPIO_EMC_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_04 = PIN(GPIO4, 4, GPIO_EMC_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_05 = PIN(GPIO4, 5, GPIO_EMC_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_06 = PIN(GPIO4, 6, GPIO_EMC_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_07 = PIN(GPIO4, 7, GPIO_EMC_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_08 = PIN(GPIO4, 8, GPIO_EMC_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_09 = PIN(GPIO4, 9, GPIO_EMC_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_10 = PIN(GPIO4, 10, GPIO_EMC_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_11 = PIN(GPIO4, 11, GPIO_EMC_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_12 = PIN(GPIO4, 12, GPIO_EMC_12, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_13 = PIN(GPIO4, 13, GPIO_EMC_13, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_14 = PIN(GPIO4, 14, GPIO_EMC_14, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_15 = PIN(GPIO4, 15, GPIO_EMC_15, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_16 = PIN(GPIO4, 16, GPIO_EMC_16, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_17 = PIN(GPIO4, 17, GPIO_EMC_17, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_18 = PIN(GPIO4, 18, GPIO_EMC_18, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_19 = PIN(GPIO4, 19, GPIO_EMC_19, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_20 = PIN(GPIO4, 20, GPIO_EMC_20, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_21 = PIN(GPIO4, 21, GPIO_EMC_21, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_22 = PIN(GPIO4, 22, GPIO_EMC_22, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_23 = PIN(GPIO4, 23, GPIO_EMC_23, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_24 = PIN(GPIO4, 24, GPIO_EMC_24, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_25 = PIN(GPIO4, 25, GPIO_EMC_25, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_26 = PIN(GPIO4, 26, GPIO_EMC_26, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_27 = PIN(GPIO4, 27, GPIO_EMC_27, NO_ADC, 0, 0x00000005, 0x000030B0);
+const mcu_pin_obj_t pin_GPIO_EMC_28 = PIN(GPIO4, 28, GPIO_EMC_28, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_29 = PIN(GPIO4, 29, GPIO_EMC_29, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_30 = PIN(GPIO4, 30, GPIO_EMC_30, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_31 = PIN(GPIO4, 31, GPIO_EMC_31, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_32 = PIN(GPIO3, 18, GPIO_EMC_32, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_33 = PIN(GPIO3, 19, GPIO_EMC_33, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_34 = PIN(GPIO3, 20, GPIO_EMC_34, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_35 = PIN(GPIO3, 21, GPIO_EMC_35, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_36 = PIN(GPIO3, 22, GPIO_EMC_36, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_37 = PIN(GPIO3, 23, GPIO_EMC_37, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_38 = PIN(GPIO3, 24, GPIO_EMC_38, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_39 = PIN(GPIO3, 25, GPIO_EMC_39, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_40 = PIN(GPIO3, 26, GPIO_EMC_40, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_41 = PIN(GPIO3, 27, GPIO_EMC_41, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_04 = PIN(GPIO1, 4, GPIO_AD_B0_04, NO_ADC, 0, 0x00000000, 0x000030B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_05 = PIN(GPIO1, 5, GPIO_AD_B0_05, NO_ADC, 0, 0x00000000, 0x000030B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_06 = PIN(GPIO1, 6, GPIO_AD_B0_06, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_07 = PIN(GPIO1, 7, GPIO_AD_B0_07, NO_ADC, 0, 0x00000000, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_08 = PIN(GPIO1, 8, GPIO_AD_B0_08, NO_ADC, 0, 0x00000000, 0x000030A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_09 = PIN(GPIO1, 9, GPIO_AD_B0_09, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_10 = PIN(GPIO1, 10, GPIO_AD_B0_10, NO_ADC, 0, 0x00000000, 0x000090B1);
+const mcu_pin_obj_t pin_GPIO_AD_B0_11 = PIN(GPIO1, 11, GPIO_AD_B0_11, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_12 = PIN(GPIO1, 12, GPIO_AD_B0_12, ADC1, 1, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_13 = PIN(GPIO1, 13, GPIO_AD_B0_13, ADC1, 2, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_14 = PIN(GPIO1, 14, GPIO_AD_B0_14, ADC1, 3, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_15 = PIN(GPIO1, 15, GPIO_AD_B0_15, ADC1, 4, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_00 = PIN(GPIO1, 16, GPIO_AD_B1_00, ADC2, 5, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_01 = PIN(GPIO1, 17, GPIO_AD_B1_01, ADC2, 6, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_02 = PIN(GPIO1, 18, GPIO_AD_B1_02, ADC2, 7, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_03 = PIN(GPIO1, 19, GPIO_AD_B1_03, ADC2, 8, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_04 = PIN(GPIO1, 20, GPIO_AD_B1_04, ADC2, 9, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_05 = PIN(GPIO1, 21, GPIO_AD_B1_05, ADC2, 10, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_06 = PIN(GPIO1, 22, GPIO_AD_B1_06, ADC2, 11, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_07 = PIN(GPIO1, 23, GPIO_AD_B1_07, ADC2, 12, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_00 = PIN(GPIO2, 0, GPIO_B0_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_01 = PIN(GPIO2, 1, GPIO_B0_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_02 = PIN(GPIO2, 2, GPIO_B0_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_03 = PIN(GPIO2, 3, GPIO_B0_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_04 = PIN(GPIO2, 4, GPIO_B0_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_05 = PIN(GPIO2, 5, GPIO_B0_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_06 = PIN(GPIO2, 6, GPIO_B0_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_07 = PIN(GPIO2, 7, GPIO_B0_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_08 = PIN(GPIO2, 8, GPIO_B0_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_09 = PIN(GPIO2, 9, GPIO_B0_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_10 = PIN(GPIO2, 10, GPIO_B0_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_11 = PIN(GPIO2, 11, GPIO_B0_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_12 = PIN(GPIO2, 12, GPIO_B0_12, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_13 = PIN(GPIO2, 13, GPIO_B0_13, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_14 = PIN(GPIO2, 14, GPIO_B0_14, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_15 = PIN(GPIO2, 15, GPIO_B0_15, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_00 = PIN(GPIO2, 16, GPIO_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_01 = PIN(GPIO2, 17, GPIO_B1_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_02 = PIN(GPIO2, 18, GPIO_B1_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_03 = PIN(GPIO2, 19, GPIO_B1_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_04 = PIN(GPIO2, 20, GPIO_B1_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_05 = PIN(GPIO2, 21, GPIO_B1_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_06 = PIN(GPIO2, 22, GPIO_B1_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_07 = PIN(GPIO2, 23, GPIO_B1_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_08 = PIN(GPIO2, 24, GPIO_B1_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_09 = PIN(GPIO2, 25, GPIO_B1_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_10 = PIN(GPIO2, 26, GPIO_B1_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_11 = PIN(GPIO2, 27, GPIO_B1_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_12 = PIN(GPIO2, 28, GPIO_B1_12, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_13 = PIN(GPIO2, 29, GPIO_B1_13, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_14 = PIN(GPIO2, 30, GPIO_B1_14, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_15 = PIN(GPIO2, 31, GPIO_B1_15, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_00 = PIN(GPIO3, 12, GPIO_SD_B0_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_01 = PIN(GPIO3, 13, GPIO_SD_B0_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_02 = PIN(GPIO3, 14, GPIO_SD_B0_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_03 = PIN(GPIO3, 15, GPIO_SD_B0_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_04 = PIN(GPIO3, 16, GPIO_SD_B0_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_05 = PIN(GPIO3, 17, GPIO_SD_B0_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_00 = PIN(GPIO3, 0, GPIO_SD_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_01 = PIN(GPIO3, 1, GPIO_SD_B1_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_02 = PIN(GPIO3, 2, GPIO_SD_B1_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_03 = PIN(GPIO3, 3, GPIO_SD_B1_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_04 = PIN(GPIO3, 4, GPIO_SD_B1_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_05 = PIN(GPIO3, 5, GPIO_SD_B1_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_06 = PIN(GPIO3, 6, GPIO_SD_B1_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_07 = PIN(GPIO3, 7, GPIO_SD_B1_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_08 = PIN(GPIO3, 8, GPIO_SD_B1_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_09 = PIN(GPIO3, 9, GPIO_SD_B1_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_10 = PIN(GPIO3, 10, GPIO_SD_B1_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_11 = PIN(GPIO3, 11, GPIO_SD_B1_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+
+const mcu_pin_obj_t pin_USB_OTG1_DN = { { &mcu_pin_type }, };
+const mcu_pin_obj_t pin_USB_OTG1_DP = { { &mcu_pin_type }, };
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pins.h
new file mode 100644
index 0000000000..118eff9335
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1042/pins.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+
+#define FORMAT_PIN(pin_name) extern const mcu_pin_obj_t pin_##pin_name;
+#include "pin_names.h"
+#undef FORMAT_PIN
+
+#define PIN_COUNT (IOMUXC_SW_PAD_CTL_PAD_COUNT + 2)
+extern const mcu_pin_obj_t mcu_pin_list[PIN_COUNT];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/clocks.c
new file mode 100644
index 0000000000..832ad9afac
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/clocks.c
@@ -0,0 +1,402 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "mpconfigport.h"
+
+#include "fsl_clock.h"
+#include "fsl_iomuxc.h"
+#include "fsl_device_registers.h"
+
+#include "board.h"
+
+#include "clocks.h"
+
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 100,                           /* PLL loop divider, Fout = Fin * 50 */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 1,                             /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+    .numerator = 0,                               /* 30 bit numerator of fractional loop divider */
+    .denominator = 1,                             /* 30 bit denominator of fractional loop divider */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 0,                             /* PLL loop divider, Fout = Fin * 20 */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 31,                            /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .postDivider = 8,                             /* Divider after PLL */
+    .numerator = 0,                               /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .denominator = 1,                             /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void clocks_init(void) {
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+    #ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+    #endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+    #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    #error "whoops"
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
+    #endif
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+    #ifndef SKIP_SYSCLK_INIT
+    #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+    #endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+    #endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+    #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+    /* Disable Usb1 PLL output for USBPHY1. */
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+    #endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+        CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+        CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* DeInit Usb2 PLL. */
+    CLOCK_DeinitUsb2Pll();
+    /* Bypass Usb2 PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
+    /* Enable Usb2 PLL output. */
+    CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    #if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+    #elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+    /* Backward compatibility for original bitfield name */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    #else
+    #error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+    #endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/periph.c
new file mode 100644
index 0000000000..35b097f675
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/periph.c
@@ -0,0 +1,377 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "mimxrt10xx/periph.h"
+
+LPI2C_Type *const mcu_i2c_banks[4] = { LPI2C1, LPI2C2, LPI2C3, LPI2C4 };
+
+const mcu_periph_obj_t mcu_i2c_sda_list[9] = {
+    PERIPH_PIN(1, 2, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 0, &pin_GPIO_SD_B1_05),
+    PERIPH_PIN(1, 3, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 1, &pin_GPIO_AD_B1_01),
+
+    PERIPH_PIN(2, 3, kIOMUXC_LPI2C2_SDA_SELECT_INPUT, 0, &pin_GPIO_SD_B1_10),
+    PERIPH_PIN(2, 2, kIOMUXC_LPI2C2_SDA_SELECT_INPUT, 1, &pin_GPIO_B0_05),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPI2C3_SDA_SELECT_INPUT, 0, &pin_GPIO_EMC_21),
+    PERIPH_PIN(3, 2, kIOMUXC_LPI2C3_SDA_SELECT_INPUT, 1, &pin_GPIO_SD_B0_01),
+    PERIPH_PIN(3, 1, kIOMUXC_LPI2C3_SDA_SELECT_INPUT, 2, &pin_GPIO_AD_B1_06),
+
+    PERIPH_PIN(4, 2, kIOMUXC_LPI2C4_SDA_SELECT_INPUT, 0, &pin_GPIO_EMC_11),
+    PERIPH_PIN(4, 0, kIOMUXC_LPI2C4_SDA_SELECT_INPUT, 1, &pin_GPIO_AD_B0_13),
+};
+
+const mcu_periph_obj_t mcu_i2c_scl_list[9] = {
+    PERIPH_PIN(1, 2, kIOMUXC_LPI2C1_SCL_SELECT_INPUT, 0, &pin_GPIO_SD_B1_04),
+    PERIPH_PIN(1, 3, kIOMUXC_LPI2C1_SCL_SELECT_INPUT, 1, &pin_GPIO_AD_B1_00),
+
+    PERIPH_PIN(2, 3, kIOMUXC_LPI2C2_SCL_SELECT_INPUT, 0, &pin_GPIO_SD_B1_11),
+    PERIPH_PIN(2, 2, kIOMUXC_LPI2C2_SCL_SELECT_INPUT, 1, &pin_GPIO_B0_04),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPI2C3_SCL_SELECT_INPUT, 0, &pin_GPIO_EMC_22),
+    PERIPH_PIN(3, 2, kIOMUXC_LPI2C3_SCL_SELECT_INPUT, 1, &pin_GPIO_SD_B0_00),
+    PERIPH_PIN(3, 1, kIOMUXC_LPI2C3_SCL_SELECT_INPUT, 2, &pin_GPIO_AD_B1_07),
+
+    PERIPH_PIN(4, 2, kIOMUXC_LPI2C4_SCL_SELECT_INPUT, 0, &pin_GPIO_EMC_12),
+    PERIPH_PIN(4, 0, kIOMUXC_LPI2C4_SCL_SELECT_INPUT, 1, &pin_GPIO_AD_B0_12),
+};
+
+LPSPI_Type *const mcu_spi_banks[4] = { LPSPI1, LPSPI2, LPSPI3, LPSPI4 };
+
+const mcu_periph_obj_t mcu_spi_sck_list[8] = {
+    PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 0, &pin_GPIO_EMC_27),
+    PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 1, &pin_GPIO_SD_B0_00),
+
+    PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 0, &pin_GPIO_SD_B1_07),
+    PERIPH_PIN(2, 2, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 1, &pin_GPIO_EMC_00),
+
+    PERIPH_PIN(3, 7, kIOMUXC_LPSPI3_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B0_00),
+    PERIPH_PIN(3, 2, kIOMUXC_LPSPI3_SCK_SELECT_INPUT, 1, &pin_GPIO_AD_B1_15),
+
+    PERIPH_PIN(4, 3, kIOMUXC_LPSPI4_SCK_SELECT_INPUT, 0, &pin_GPIO_B0_03),
+    PERIPH_PIN(4, 1, kIOMUXC_LPSPI4_SCK_SELECT_INPUT, 1, &pin_GPIO_B1_07),
+};
+
+const mcu_periph_obj_t mcu_spi_sdo_list[8] = {
+    PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 0, &pin_GPIO_EMC_28),
+    PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 1, &pin_GPIO_SD_B0_02),
+
+    PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 0, &pin_GPIO_SD_B1_08),
+    PERIPH_PIN(2, 2, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 1, &pin_GPIO_EMC_02),
+
+    PERIPH_PIN(3, 7, kIOMUXC_LPSPI3_SDO_SELECT_INPUT, 0, &pin_GPIO_AD_B0_01),
+    PERIPH_PIN(3, 2, kIOMUXC_LPSPI3_SDO_SELECT_INPUT, 1, &pin_GPIO_AD_B1_14),
+
+    PERIPH_PIN(4, 3, kIOMUXC_LPSPI4_SDO_SELECT_INPUT, 0, &pin_GPIO_B0_02),
+    PERIPH_PIN(4, 1, kIOMUXC_LPSPI4_SDO_SELECT_INPUT, 1, &pin_GPIO_B1_06),
+};
+
+const mcu_periph_obj_t mcu_spi_sdi_list[8] = {
+    PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 0, &pin_GPIO_EMC_29),
+    PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 1, &pin_GPIO_SD_B0_03),
+
+    PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 0, &pin_GPIO_SD_B1_09),
+    PERIPH_PIN(2, 2, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 1, &pin_GPIO_EMC_03),
+
+    PERIPH_PIN(3, 7, kIOMUXC_LPSPI3_SDI_SELECT_INPUT, 0, &pin_GPIO_AD_B0_02),
+    PERIPH_PIN(3, 2, kIOMUXC_LPSPI3_SDI_SELECT_INPUT, 1, &pin_GPIO_AD_B1_13),
+
+    PERIPH_PIN(4, 3, kIOMUXC_LPSPI4_SDI_SELECT_INPUT, 0, &pin_GPIO_B0_01),
+    PERIPH_PIN(4, 1, kIOMUXC_LPSPI4_SDI_SELECT_INPUT, 1, &pin_GPIO_B1_05),
+};
+
+LPUART_Type *const mcu_uart_banks[8] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 };
+
+const mcu_periph_obj_t mcu_uart_rx_list[18] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_13),
+
+    PERIPH_PIN(2, 2, kIOMUXC_LPUART2_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_10),
+    PERIPH_PIN(2, 2, kIOMUXC_LPUART2_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_03),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_RX_SELECT_INPUT, 0, &pin_GPIO_AD_B1_07),
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_14),
+    PERIPH_PIN(3, 3, kIOMUXC_LPUART3_RX_SELECT_INPUT, 2, &pin_GPIO_B0_09),
+
+    PERIPH_PIN(4, 4, kIOMUXC_LPUART4_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_01),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_20),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_RX_SELECT_INPUT, 2, &pin_GPIO_B1_01),
+
+    PERIPH_PIN(5, 2, kIOMUXC_LPUART5_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_24),
+    PERIPH_PIN(5, 1, kIOMUXC_LPUART5_RX_SELECT_INPUT, 1, &pin_GPIO_B1_13),
+
+    PERIPH_PIN(6, 2, kIOMUXC_LPUART6_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_26),
+    PERIPH_PIN(6, 2, kIOMUXC_LPUART6_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B0_03),
+
+    PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_09),
+    PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_32),
+
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B0_05),
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_11),
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 2, &pin_GPIO_EMC_39),
+};
+
+const mcu_periph_obj_t mcu_uart_tx_list[18] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_12),
+
+    PERIPH_PIN(2, 2, kIOMUXC_LPUART2_TX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_11),
+    PERIPH_PIN(2, 2, kIOMUXC_LPUART2_TX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_02),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_TX_SELECT_INPUT, 0, &pin_GPIO_AD_B1_06),
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_TX_SELECT_INPUT, 1, &pin_GPIO_EMC_13),
+    PERIPH_PIN(3, 3, kIOMUXC_LPUART3_TX_SELECT_INPUT, 2, &pin_GPIO_B0_08),
+
+    PERIPH_PIN(4, 4, kIOMUXC_LPUART4_TX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_00),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_TX_SELECT_INPUT, 1, &pin_GPIO_EMC_19),
+    PERIPH_PIN(4, 2, kIOMUXC_LPUART4_TX_SELECT_INPUT, 2, &pin_GPIO_B1_00),
+
+    PERIPH_PIN(5, 2, kIOMUXC_LPUART5_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_23),
+    PERIPH_PIN(5, 1, kIOMUXC_LPUART5_TX_SELECT_INPUT, 1, &pin_GPIO_B1_12),
+
+    PERIPH_PIN(6, 2, kIOMUXC_LPUART6_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_25),
+    PERIPH_PIN(6, 2, kIOMUXC_LPUART6_TX_SELECT_INPUT, 1, &pin_GPIO_AD_B0_02),
+
+    PERIPH_PIN(7, 2, kIOMUXC_LPUART7_TX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_08),
+    PERIPH_PIN(7, 2, kIOMUXC_LPUART7_TX_SELECT_INPUT, 1, &pin_GPIO_EMC_31),
+
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_TX_SELECT_INPUT, 0, &pin_GPIO_SD_B0_04),
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_TX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_10),
+    PERIPH_PIN(8, 2, kIOMUXC_LPUART8_TX_SELECT_INPUT, 2, &pin_GPIO_EMC_38),
+};
+
+const mcu_periph_obj_t mcu_uart_rts_list[9] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_15),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_01),
+
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_16),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_05),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_18),
+
+    PERIPH_PIN(5, 2, 0, 0, &pin_GPIO_EMC_27),
+
+    PERIPH_PIN(6, 2, 0, 0, &pin_GPIO_EMC_29),
+
+    PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_SD_B1_07),
+
+    PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_SD_B0_03),
+};
+
+const mcu_periph_obj_t mcu_uart_cts_list[9] = {
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_14),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_00),
+
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 0, &pin_GPIO_EMC_15),
+    PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 1, &pin_GPIO_AD_B1_04),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_17),
+
+    PERIPH_PIN(5, 2, 0, 0, &pin_GPIO_EMC_28),
+
+    PERIPH_PIN(6, 2, 0, 0, &pin_GPIO_EMC_30),
+
+    PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_SD_B1_06),
+
+    PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_SD_B0_02),
+};
+
+I2S_Type *const mcu_i2s_banks[3] = { SAI1, SAI2, SAI3 };
+
+const mcu_periph_obj_t mcu_i2s_rx_data0_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_SD_B1_06),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 1, &pin_GPIO_AD_B1_12),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 2, &pin_GPIO_B1_00),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_EMC_08),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT, 1, &pin_GPIO_AD_B0_08),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_33),
+};
+
+const mcu_periph_obj_t mcu_i2s_rx_sync_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B1_04),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B1_10),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 2, &pin_GPIO_B0_14),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_EMC_09),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B0_07),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_34),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_bclk_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_SD_B1_08),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 1, &pin_GPIO_AD_B1_14),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 2, &pin_GPIO_B1_02),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_EMC_06),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT, 1, &pin_GPIO_AD_B0_05),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_38),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_data0_list[6] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_13),
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B1_01),
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_SD_B1_07),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_04),
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_B0_09),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_36),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_sync_list[6] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B1_09),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B1_15),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 2, &pin_GPIO_B1_03),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_EMC_05),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B0_04),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_39),
+};
+
+const mcu_periph_obj_t mcu_mqs_left_list[3] = {
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_14),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_05),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_01),
+};
+
+const mcu_periph_obj_t mcu_mqs_right_list[3] = {
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_13),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_04),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_00),
+};
+
+const mcu_pwm_obj_t mcu_pwm_list[67] = {
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A, &pin_GPIO_EMC_23),
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A, &pin_GPIO_SD_B0_00),
+
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B, &pin_GPIO_EMC_24),
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B, &pin_GPIO_SD_B0_01),
+
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X, &pin_GPIO_AD_B0_02),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A, &pin_GPIO_EMC_25),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A, &pin_GPIO_SD_B0_02),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B, &pin_GPIO_EMC_26),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B, &pin_GPIO_SD_B0_03),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X, &pin_GPIO_AD_B0_03),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A, &pin_GPIO_EMC_27),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A, &pin_GPIO_SD_B0_04),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B, &pin_GPIO_EMC_28),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B, &pin_GPIO_SD_B0_05),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X, &pin_GPIO_AD_B0_12),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A, &pin_GPIO_EMC_12),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A, &pin_GPIO_EMC_38),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A, &pin_GPIO_AD_B0_10),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A, &pin_GPIO_B1_00),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A, &pin_GPIO_SD_B1_00),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B, &pin_GPIO_EMC_13),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B, &pin_GPIO_EMC_39),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B, &pin_GPIO_AD_B0_11),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B, &pin_GPIO_B1_01),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B, &pin_GPIO_SD_B1_01),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X, &pin_GPIO_AD_B0_13),
+
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A, &pin_GPIO_EMC_06),
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A, &pin_GPIO_B0_06),
+
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B, &pin_GPIO_EMC_07),
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B, &pin_GPIO_B0_07),
+
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A, &pin_GPIO_EMC_08),
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A, &pin_GPIO_B0_08),
+
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B, &pin_GPIO_EMC_09),
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B, &pin_GPIO_B0_09),
+
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A, &pin_GPIO_EMC_10),
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A, &pin_GPIO_B0_10),
+
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B, &pin_GPIO_EMC_11),
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B, &pin_GPIO_B0_11),
+
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A, &pin_GPIO_EMC_19),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A, &pin_GPIO_AD_B0_00),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A, &pin_GPIO_AD_B0_09),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A, &pin_GPIO_B1_02),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A, &pin_GPIO_SD_B1_02),
+
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B, &pin_GPIO_EMC_20),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B, &pin_GPIO_AD_B0_01),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B, &pin_GPIO_B1_03),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B, &pin_GPIO_SD_B1_03),
+
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A, &pin_GPIO_EMC_29),
+
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B, &pin_GPIO_EMC_30),
+
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A, &pin_GPIO_EMC_31),
+
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B, &pin_GPIO_EMC_32),
+
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A, &pin_GPIO_EMC_33),
+
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B, &pin_GPIO_EMC_34),
+
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A, &pin_GPIO_EMC_21),
+
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B, &pin_GPIO_EMC_22),
+
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A, &pin_GPIO_EMC_00),
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A, &pin_GPIO_AD_B1_08),
+
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B, &pin_GPIO_EMC_01),
+
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A, &pin_GPIO_EMC_02),
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A, &pin_GPIO_AD_B1_09),
+
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B, &pin_GPIO_EMC_03),
+
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A, &pin_GPIO_EMC_04),
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A, &pin_GPIO_B1_14),
+
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B, &pin_GPIO_EMC_05),
+
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A, &pin_GPIO_EMC_17),
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A, &pin_GPIO_B1_15),
+
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B, &pin_GPIO_EMC_18),
+};
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/periph.h
new file mode 100644
index 0000000000..ae6566f974
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/periph.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+extern LPI2C_Type *const mcu_i2c_banks[4];
+extern const mcu_periph_obj_t mcu_i2c_sda_list[9];
+extern const mcu_periph_obj_t mcu_i2c_scl_list[9];
+
+extern LPSPI_Type *const mcu_spi_banks[4];
+extern const mcu_periph_obj_t mcu_spi_sck_list[8];
+extern const mcu_periph_obj_t mcu_spi_sdo_list[8];
+extern const mcu_periph_obj_t mcu_spi_sdi_list[8];
+
+extern LPUART_Type *const mcu_uart_banks[8];
+extern const mcu_periph_obj_t mcu_uart_rx_list[18];
+extern const mcu_periph_obj_t mcu_uart_tx_list[18];
+extern const mcu_periph_obj_t mcu_uart_rts_list[9];
+extern const mcu_periph_obj_t mcu_uart_cts_list[9];
+
+extern I2S_Type *const mcu_i2s_banks[3];
+extern const mcu_periph_obj_t mcu_i2s_rx_data0_list[6];
+extern const mcu_periph_obj_t mcu_i2s_rx_sync_list[6];
+extern const mcu_periph_obj_t mcu_i2s_tx_bclk_list[6];
+extern const mcu_periph_obj_t mcu_i2s_tx_data0_list[6];
+extern const mcu_periph_obj_t mcu_i2s_tx_sync_list[6];
+
+extern const mcu_periph_obj_t mcu_mqs_left_list[3];
+extern const mcu_periph_obj_t mcu_mqs_right_list[3];
+
+extern const mcu_pwm_obj_t mcu_pwm_list[67];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pin_names.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pin_names.h
new file mode 100644
index 0000000000..4b9df709cf
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pin_names.h
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+// define FORMAT_PIN(pin_name) and then include this file.
+
+FORMAT_PIN(GPIO_EMC_00)
+FORMAT_PIN(GPIO_EMC_01)
+FORMAT_PIN(GPIO_EMC_02)
+FORMAT_PIN(GPIO_EMC_03)
+FORMAT_PIN(GPIO_EMC_04)
+FORMAT_PIN(GPIO_EMC_05)
+FORMAT_PIN(GPIO_EMC_06)
+FORMAT_PIN(GPIO_EMC_07)
+FORMAT_PIN(GPIO_EMC_08)
+FORMAT_PIN(GPIO_EMC_09)
+FORMAT_PIN(GPIO_EMC_10)
+FORMAT_PIN(GPIO_EMC_11)
+FORMAT_PIN(GPIO_EMC_12)
+FORMAT_PIN(GPIO_EMC_13)
+FORMAT_PIN(GPIO_EMC_14)
+FORMAT_PIN(GPIO_EMC_15)
+FORMAT_PIN(GPIO_EMC_16)
+FORMAT_PIN(GPIO_EMC_17)
+FORMAT_PIN(GPIO_EMC_18)
+FORMAT_PIN(GPIO_EMC_19)
+FORMAT_PIN(GPIO_EMC_20)
+FORMAT_PIN(GPIO_EMC_21)
+FORMAT_PIN(GPIO_EMC_22)
+FORMAT_PIN(GPIO_EMC_23)
+FORMAT_PIN(GPIO_EMC_24)
+FORMAT_PIN(GPIO_EMC_25)
+FORMAT_PIN(GPIO_EMC_26)
+FORMAT_PIN(GPIO_EMC_27)
+FORMAT_PIN(GPIO_EMC_28)
+FORMAT_PIN(GPIO_EMC_29)
+FORMAT_PIN(GPIO_EMC_30)
+FORMAT_PIN(GPIO_EMC_31)
+FORMAT_PIN(GPIO_EMC_32)
+FORMAT_PIN(GPIO_EMC_33)
+FORMAT_PIN(GPIO_EMC_34)
+FORMAT_PIN(GPIO_EMC_35)
+FORMAT_PIN(GPIO_EMC_36)
+FORMAT_PIN(GPIO_EMC_37)
+FORMAT_PIN(GPIO_EMC_38)
+FORMAT_PIN(GPIO_EMC_39)
+FORMAT_PIN(GPIO_EMC_40)
+FORMAT_PIN(GPIO_EMC_41)
+
+FORMAT_PIN(GPIO_AD_B0_00)
+FORMAT_PIN(GPIO_AD_B0_01)
+FORMAT_PIN(GPIO_AD_B0_02)
+FORMAT_PIN(GPIO_AD_B0_03)
+FORMAT_PIN(GPIO_AD_B0_04)
+FORMAT_PIN(GPIO_AD_B0_05)
+FORMAT_PIN(GPIO_AD_B0_06)
+FORMAT_PIN(GPIO_AD_B0_07)
+FORMAT_PIN(GPIO_AD_B0_08)
+FORMAT_PIN(GPIO_AD_B0_09)
+FORMAT_PIN(GPIO_AD_B0_10)
+FORMAT_PIN(GPIO_AD_B0_11)
+FORMAT_PIN(GPIO_AD_B0_12)
+FORMAT_PIN(GPIO_AD_B0_13)
+FORMAT_PIN(GPIO_AD_B0_14)
+FORMAT_PIN(GPIO_AD_B0_15)
+
+FORMAT_PIN(GPIO_AD_B1_00)
+FORMAT_PIN(GPIO_AD_B1_01)
+FORMAT_PIN(GPIO_AD_B1_02)
+FORMAT_PIN(GPIO_AD_B1_03)
+FORMAT_PIN(GPIO_AD_B1_04)
+FORMAT_PIN(GPIO_AD_B1_05)
+FORMAT_PIN(GPIO_AD_B1_06)
+FORMAT_PIN(GPIO_AD_B1_07)
+FORMAT_PIN(GPIO_AD_B1_08)
+FORMAT_PIN(GPIO_AD_B1_09)
+FORMAT_PIN(GPIO_AD_B1_10)
+FORMAT_PIN(GPIO_AD_B1_11)
+FORMAT_PIN(GPIO_AD_B1_12)
+FORMAT_PIN(GPIO_AD_B1_13)
+FORMAT_PIN(GPIO_AD_B1_14)
+FORMAT_PIN(GPIO_AD_B1_15)
+
+FORMAT_PIN(GPIO_B0_00)
+FORMAT_PIN(GPIO_B0_01)
+FORMAT_PIN(GPIO_B0_02)
+FORMAT_PIN(GPIO_B0_03)
+FORMAT_PIN(GPIO_B0_04)
+FORMAT_PIN(GPIO_B0_05)
+FORMAT_PIN(GPIO_B0_06)
+FORMAT_PIN(GPIO_B0_07)
+FORMAT_PIN(GPIO_B0_08)
+FORMAT_PIN(GPIO_B0_09)
+FORMAT_PIN(GPIO_B0_10)
+FORMAT_PIN(GPIO_B0_11)
+FORMAT_PIN(GPIO_B0_12)
+FORMAT_PIN(GPIO_B0_13)
+FORMAT_PIN(GPIO_B0_14)
+FORMAT_PIN(GPIO_B0_15)
+
+FORMAT_PIN(GPIO_B1_00)
+FORMAT_PIN(GPIO_B1_01)
+FORMAT_PIN(GPIO_B1_02)
+FORMAT_PIN(GPIO_B1_03)
+FORMAT_PIN(GPIO_B1_04)
+FORMAT_PIN(GPIO_B1_05)
+FORMAT_PIN(GPIO_B1_06)
+FORMAT_PIN(GPIO_B1_07)
+FORMAT_PIN(GPIO_B1_08)
+FORMAT_PIN(GPIO_B1_09)
+FORMAT_PIN(GPIO_B1_10)
+FORMAT_PIN(GPIO_B1_11)
+FORMAT_PIN(GPIO_B1_12)
+FORMAT_PIN(GPIO_B1_13)
+FORMAT_PIN(GPIO_B1_14)
+FORMAT_PIN(GPIO_B1_15)
+
+FORMAT_PIN(GPIO_SD_B0_00)
+FORMAT_PIN(GPIO_SD_B0_01)
+FORMAT_PIN(GPIO_SD_B0_02)
+FORMAT_PIN(GPIO_SD_B0_03)
+FORMAT_PIN(GPIO_SD_B0_04)
+FORMAT_PIN(GPIO_SD_B0_05)
+
+FORMAT_PIN(GPIO_SD_B1_00)
+FORMAT_PIN(GPIO_SD_B1_01)
+FORMAT_PIN(GPIO_SD_B1_02)
+FORMAT_PIN(GPIO_SD_B1_03)
+FORMAT_PIN(GPIO_SD_B1_04)
+FORMAT_PIN(GPIO_SD_B1_05)
+FORMAT_PIN(GPIO_SD_B1_06)
+FORMAT_PIN(GPIO_SD_B1_07)
+FORMAT_PIN(GPIO_SD_B1_08)
+FORMAT_PIN(GPIO_SD_B1_09)
+FORMAT_PIN(GPIO_SD_B1_10)
+FORMAT_PIN(GPIO_SD_B1_11)
+FORMAT_PIN(USB_OTG1_DN)
+FORMAT_PIN(USB_OTG1_DP)
+FORMAT_PIN(USB_OTG2_DN)
+FORMAT_PIN(USB_OTG2_DP)
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pins.c
new file mode 100644
index 0000000000..83bbe18e42
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pins.c
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "mimxrt10xx/pins.h"
+
+const mcu_pin_obj_t pin_GPIO_EMC_00 = PIN(GPIO4, 0, GPIO_EMC_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_01 = PIN(GPIO4, 1, GPIO_EMC_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_02 = PIN(GPIO4, 2, GPIO_EMC_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_03 = PIN(GPIO4, 3, GPIO_EMC_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_04 = PIN(GPIO4, 4, GPIO_EMC_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_05 = PIN(GPIO4, 5, GPIO_EMC_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_06 = PIN(GPIO4, 6, GPIO_EMC_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_07 = PIN(GPIO4, 7, GPIO_EMC_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_08 = PIN(GPIO4, 8, GPIO_EMC_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_09 = PIN(GPIO4, 9, GPIO_EMC_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_10 = PIN(GPIO4, 10, GPIO_EMC_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_11 = PIN(GPIO4, 11, GPIO_EMC_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_12 = PIN(GPIO4, 12, GPIO_EMC_12, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_13 = PIN(GPIO4, 13, GPIO_EMC_13, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_14 = PIN(GPIO4, 14, GPIO_EMC_14, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_15 = PIN(GPIO4, 15, GPIO_EMC_15, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_16 = PIN(GPIO4, 16, GPIO_EMC_16, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_17 = PIN(GPIO4, 17, GPIO_EMC_17, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_18 = PIN(GPIO4, 18, GPIO_EMC_18, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_19 = PIN(GPIO4, 19, GPIO_EMC_19, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_20 = PIN(GPIO4, 20, GPIO_EMC_20, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_21 = PIN(GPIO4, 21, GPIO_EMC_21, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_22 = PIN(GPIO4, 22, GPIO_EMC_22, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_23 = PIN(GPIO4, 23, GPIO_EMC_23, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_24 = PIN(GPIO4, 24, GPIO_EMC_24, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_25 = PIN(GPIO4, 25, GPIO_EMC_25, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_26 = PIN(GPIO4, 26, GPIO_EMC_26, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_27 = PIN(GPIO4, 27, GPIO_EMC_27, NO_ADC, 0, 0x00000005, 0x000030B0);
+const mcu_pin_obj_t pin_GPIO_EMC_28 = PIN(GPIO4, 28, GPIO_EMC_28, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_29 = PIN(GPIO4, 29, GPIO_EMC_29, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_30 = PIN(GPIO4, 30, GPIO_EMC_30, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_31 = PIN(GPIO4, 31, GPIO_EMC_31, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_32 = PIN(GPIO3, 18, GPIO_EMC_32, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_33 = PIN(GPIO3, 19, GPIO_EMC_33, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_34 = PIN(GPIO3, 20, GPIO_EMC_34, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_35 = PIN(GPIO3, 21, GPIO_EMC_35, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_36 = PIN(GPIO3, 22, GPIO_EMC_36, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_37 = PIN(GPIO3, 23, GPIO_EMC_37, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_38 = PIN(GPIO3, 24, GPIO_EMC_38, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_39 = PIN(GPIO3, 25, GPIO_EMC_39, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_40 = PIN(GPIO3, 26, GPIO_EMC_40, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_41 = PIN(GPIO3, 27, GPIO_EMC_41, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_00 = PIN(GPIO1, 0, GPIO_AD_B0_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_01 = PIN(GPIO1, 1, GPIO_AD_B0_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_02 = PIN(GPIO1, 2, GPIO_AD_B0_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_03 = PIN(GPIO1, 3, GPIO_AD_B0_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_04 = PIN(GPIO1, 4, GPIO_AD_B0_04, NO_ADC, 0, 0x00000000, 0x000030B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_05 = PIN(GPIO1, 5, GPIO_AD_B0_05, NO_ADC, 0, 0x00000000, 0x000030B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_06 = PIN(GPIO1, 6, GPIO_AD_B0_06, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_07 = PIN(GPIO1, 7, GPIO_AD_B0_07, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_08 = PIN(GPIO1, 8, GPIO_AD_B0_08, NO_ADC, 0, 0x00000000, 0x0000B0A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_09 = PIN(GPIO1, 9, GPIO_AD_B0_09, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_10 = PIN(GPIO1, 10, GPIO_AD_B0_10, NO_ADC, 0, 0x00000000, 0x000090B1);
+const mcu_pin_obj_t pin_GPIO_AD_B0_11 = PIN(GPIO1, 11, GPIO_AD_B0_11, NO_ADC, 0, 0x00000000, 0x000070A0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_12 = PIN(GPIO1, 12, GPIO_AD_B0_12, ADC1, 1, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_13 = PIN(GPIO1, 13, GPIO_AD_B0_13, ADC1, 2, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_14 = PIN(GPIO1, 14, GPIO_AD_B0_14, ADC1, 3, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B0_15 = PIN(GPIO1, 15, GPIO_AD_B0_15, ADC1, 4, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_00 = PIN(GPIO1, 16, GPIO_AD_B1_00, ADC2, 5, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_01 = PIN(GPIO1, 17, GPIO_AD_B1_01, ADC2, 6, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_02 = PIN(GPIO1, 18, GPIO_AD_B1_02, ADC2, 7, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_03 = PIN(GPIO1, 19, GPIO_AD_B1_03, ADC2, 8, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_04 = PIN(GPIO1, 20, GPIO_AD_B1_04, ADC2, 9, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_05 = PIN(GPIO1, 21, GPIO_AD_B1_05, ADC2, 10, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_06 = PIN(GPIO1, 22, GPIO_AD_B1_06, ADC2, 11, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_07 = PIN(GPIO1, 23, GPIO_AD_B1_07, ADC2, 12, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_08 = PIN(GPIO1, 24, GPIO_AD_B1_08, ADC2, 13, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_09 = PIN(GPIO1, 25, GPIO_AD_B1_09, ADC2, 14, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_10 = PIN(GPIO1, 26, GPIO_AD_B1_10, ADC2, 15, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_11 = PIN(GPIO1, 27, GPIO_AD_B1_11, ADC2, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_12 = PIN(GPIO1, 28, GPIO_AD_B1_12, ADC2, 1, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_13 = PIN(GPIO1, 29, GPIO_AD_B1_13, ADC2, 2, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_14 = PIN(GPIO1, 30, GPIO_AD_B1_14, ADC2, 3, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_15 = PIN(GPIO1, 31, GPIO_AD_B1_15, ADC2, 4, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_00 = PIN(GPIO2, 0, GPIO_B0_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_01 = PIN(GPIO2, 1, GPIO_B0_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_02 = PIN(GPIO2, 2, GPIO_B0_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_03 = PIN(GPIO2, 3, GPIO_B0_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_04 = PIN(GPIO2, 4, GPIO_B0_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_05 = PIN(GPIO2, 5, GPIO_B0_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_06 = PIN(GPIO2, 6, GPIO_B0_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_07 = PIN(GPIO2, 7, GPIO_B0_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_08 = PIN(GPIO2, 8, GPIO_B0_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_09 = PIN(GPIO2, 9, GPIO_B0_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_10 = PIN(GPIO2, 10, GPIO_B0_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_11 = PIN(GPIO2, 11, GPIO_B0_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_12 = PIN(GPIO2, 12, GPIO_B0_12, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_13 = PIN(GPIO2, 13, GPIO_B0_13, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_14 = PIN(GPIO2, 14, GPIO_B0_14, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B0_15 = PIN(GPIO2, 15, GPIO_B0_15, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_00 = PIN(GPIO2, 16, GPIO_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_01 = PIN(GPIO2, 17, GPIO_B1_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_02 = PIN(GPIO2, 18, GPIO_B1_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_03 = PIN(GPIO2, 19, GPIO_B1_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_04 = PIN(GPIO2, 20, GPIO_B1_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_05 = PIN(GPIO2, 21, GPIO_B1_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_06 = PIN(GPIO2, 22, GPIO_B1_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_07 = PIN(GPIO2, 23, GPIO_B1_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_08 = PIN(GPIO2, 24, GPIO_B1_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_09 = PIN(GPIO2, 25, GPIO_B1_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_10 = PIN(GPIO2, 26, GPIO_B1_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_11 = PIN(GPIO2, 27, GPIO_B1_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_12 = PIN(GPIO2, 28, GPIO_B1_12, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_13 = PIN(GPIO2, 29, GPIO_B1_13, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_14 = PIN(GPIO2, 30, GPIO_B1_14, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_B1_15 = PIN(GPIO2, 31, GPIO_B1_15, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_00 = PIN(GPIO3, 12, GPIO_SD_B0_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_01 = PIN(GPIO3, 13, GPIO_SD_B0_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_02 = PIN(GPIO3, 14, GPIO_SD_B0_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_03 = PIN(GPIO3, 15, GPIO_SD_B0_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_04 = PIN(GPIO3, 16, GPIO_SD_B0_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B0_05 = PIN(GPIO3, 17, GPIO_SD_B0_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_00 = PIN(GPIO3, 0, GPIO_SD_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_01 = PIN(GPIO3, 1, GPIO_SD_B1_01, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_02 = PIN(GPIO3, 2, GPIO_SD_B1_02, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_03 = PIN(GPIO3, 3, GPIO_SD_B1_03, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_04 = PIN(GPIO3, 4, GPIO_SD_B1_04, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_05 = PIN(GPIO3, 5, GPIO_SD_B1_05, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_06 = PIN(GPIO3, 6, GPIO_SD_B1_06, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_07 = PIN(GPIO3, 7, GPIO_SD_B1_07, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_08 = PIN(GPIO3, 8, GPIO_SD_B1_08, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_09 = PIN(GPIO3, 9, GPIO_SD_B1_09, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_10 = PIN(GPIO3, 10, GPIO_SD_B1_10, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_SD_B1_11 = PIN(GPIO3, 11, GPIO_SD_B1_11, NO_ADC, 0, 0x00000005, 0x000010B0);
+
+const mcu_pin_obj_t pin_USB_OTG1_DN = { { &mcu_pin_type }, };
+const mcu_pin_obj_t pin_USB_OTG1_DP = { { &mcu_pin_type }, };
+const mcu_pin_obj_t pin_USB_OTG2_DN = { { &mcu_pin_type }, };
+const mcu_pin_obj_t pin_USB_OTG2_DP = { { &mcu_pin_type }, };
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pins.h
new file mode 100644
index 0000000000..6e40d30c2b
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1052/pins.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+
+#define FORMAT_PIN(pin_name) extern const mcu_pin_obj_t pin_##pin_name;
+#include "pin_names.h"
+#undef FORMAT_PIN
+
+#define PIN_COUNT (IOMUXC_SW_PAD_CTL_PAD_COUNT + 4)
+extern const mcu_pin_obj_t mcu_pin_list[PIN_COUNT];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c
index c43f4eb96b..12c9a09621 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c
@@ -5,6 +5,7 @@
  *
  * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -19,7 +20,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS  R COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
@@ -77,7 +78,7 @@ const mcu_periph_obj_t mcu_spi_sck_list[8] = {
     PERIPH_PIN(4, 1, kIOMUXC_LPSPI4_SCK_SELECT_INPUT, 1, &pin_GPIO_B1_07),
 };
 
-const mcu_periph_obj_t mcu_spi_mosi_list[8] = {
+const mcu_periph_obj_t mcu_spi_sdo_list[8] = {
     PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 0, &pin_GPIO_EMC_28),
     PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 1, &pin_GPIO_SD_B0_02),
 
@@ -91,7 +92,7 @@ const mcu_periph_obj_t mcu_spi_mosi_list[8] = {
     PERIPH_PIN(4, 1, kIOMUXC_LPSPI4_SDO_SELECT_INPUT, 1, &pin_GPIO_B1_06),
 };
 
-const mcu_periph_obj_t mcu_spi_miso_list[8] = {
+const mcu_periph_obj_t mcu_spi_sdi_list[8] = {
     PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 0, &pin_GPIO_EMC_29),
     PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 1, &pin_GPIO_SD_B0_03),
 
@@ -168,8 +169,8 @@ const mcu_periph_obj_t mcu_uart_rts_list[9] = {
 
     PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_01),
 
-    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_05),
     PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_16),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_05),
 
     PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_18),
 
@@ -201,6 +202,80 @@ const mcu_periph_obj_t mcu_uart_cts_list[9] = {
     PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_SD_B0_02),
 };
 
+I2S_Type *const mcu_i2s_banks[3] = { SAI1, SAI2, SAI3 };
+
+const mcu_periph_obj_t mcu_i2s_rx_data0_list[7] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_SD_B1_06),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 1, &pin_GPIO_AD_B1_12),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT, 2, &pin_GPIO_B1_00),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT, 0, &pin_GPIO_EMC_08),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT, 1, &pin_GPIO_AD_B0_08),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_33),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_00),
+};
+
+const mcu_periph_obj_t mcu_i2s_rx_sync_list[7] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B1_04),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B1_10),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT, 2, &pin_GPIO_B0_14),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT, 0, &pin_GPIO_EMC_09),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B0_07),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_34),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_05),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_bclk_list[7] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_SD_B1_08),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 1, &pin_GPIO_AD_B1_14),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT, 2, &pin_GPIO_B1_02),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT, 0, &pin_GPIO_EMC_06),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT, 1, &pin_GPIO_AD_B0_05),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_38),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_03),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_data0_list[7] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_13),
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B1_01),
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_SD_B1_07),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_04),
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_B0_09),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_36),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_01),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_sync_list[7] = {
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_SD_B1_09),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B1_15),
+    PERIPH_PIN(1, 3, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT, 2, &pin_GPIO_B1_03),
+
+    PERIPH_PIN(2, 2, kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT, 0, &pin_GPIO_EMC_05),
+    PERIPH_PIN(2, 3, kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT, 1, &pin_GPIO_AD_B0_04),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_39),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_02),
+};
+
+const mcu_periph_obj_t mcu_mqs_left_list[3] = {
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_14),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_05),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_01),
+};
+
+const mcu_periph_obj_t mcu_mqs_right_list[3] = {
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_13),
+    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_04),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_00),
+};
+
 const mcu_pwm_obj_t mcu_pwm_list[67] = {
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00, &pin_GPIO_EMC_23),
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00, &pin_GPIO_SD_B0_00),
@@ -226,17 +301,17 @@ const mcu_pwm_obj_t mcu_pwm_list[67] = {
 
     PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02, &pin_GPIO_AD_B0_12),
 
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03, &pin_GPIO_AD_B0_10),
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03, &pin_GPIO_EMC_38),
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03, &pin_GPIO_SD_B1_00),
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03, &pin_GPIO_EMC_12),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03, &pin_GPIO_EMC_38),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03, &pin_GPIO_AD_B0_10),
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03, &pin_GPIO_B1_00),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03, &pin_GPIO_SD_B1_00),
 
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03, &pin_GPIO_AD_B0_11),
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03, &pin_GPIO_EMC_39),
-    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03, &pin_GPIO_SD_B1_01),
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03, &pin_GPIO_EMC_13),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03, &pin_GPIO_EMC_39),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03, &pin_GPIO_AD_B0_11),
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03, &pin_GPIO_B1_01),
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03, &pin_GPIO_SD_B1_01),
 
     PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03, &pin_GPIO_AD_B0_13),
 
@@ -258,16 +333,16 @@ const mcu_pwm_obj_t mcu_pwm_list[67] = {
     PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02, &pin_GPIO_EMC_11),
     PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02, &pin_GPIO_B0_11),
 
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03, &pin_GPIO_EMC_19),
     PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03, &pin_GPIO_AD_B0_00),
     PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03, &pin_GPIO_AD_B0_09),
-    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03, &pin_GPIO_EMC_19),
-    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03, &pin_GPIO_SD_B1_02),
     PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03, &pin_GPIO_B1_02),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03, &pin_GPIO_SD_B1_02),
 
-    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03, &pin_GPIO_AD_B0_01),
     PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03, &pin_GPIO_EMC_20),
-    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03, &pin_GPIO_SD_B1_03),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03, &pin_GPIO_AD_B0_01),
     PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03, &pin_GPIO_B1_03),
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03, &pin_GPIO_SD_B1_03),
 
     PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00, &pin_GPIO_EMC_29),
 
@@ -285,90 +360,23 @@ const mcu_pwm_obj_t mcu_pwm_list[67] = {
 
     PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03, &pin_GPIO_EMC_22),
 
-    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00, &pin_GPIO_AD_B1_08),
     PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00, &pin_GPIO_EMC_00),
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00, &pin_GPIO_AD_B1_08),
 
     PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00, &pin_GPIO_EMC_01),
 
-    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01, &pin_GPIO_AD_B1_09),
     PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01, &pin_GPIO_EMC_02),
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01, &pin_GPIO_AD_B1_09),
 
     PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01, &pin_GPIO_EMC_03),
 
-    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02, &pin_GPIO_B1_14),
     PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02, &pin_GPIO_EMC_04),
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02, &pin_GPIO_B1_14),
 
     PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02, &pin_GPIO_EMC_05),
 
-    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03, &pin_GPIO_B1_15),
     PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03, &pin_GPIO_EMC_17),
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03, &pin_GPIO_B1_15),
 
     PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03, &pin_GPIO_EMC_18),
-
-};
-
-const mcu_periph_obj_t mcu_sai_rx_bclk_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_11),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B0_15),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_SD_B1_05),
-    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_10),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_B0_06),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_35),
-    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_00),
-};
-
-const mcu_periph_obj_t mcu_sai_rx_data0_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B1_00),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_12),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_06),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_B0_08),
-    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_08),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_33),
-    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_00),
-};
-const mcu_periph_obj_t mcu_sai_rx_sync_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_11),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B0_15),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_SD_B1_05),
-    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_09),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_B0_06),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_34),
-    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_05),
-};
-const mcu_periph_obj_t mcu_sai_tx_bclk_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_SD_B1_08),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B1_02),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_14),
-    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B0_05),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_06),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_38),
-    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_03),
-};
-const mcu_periph_obj_t mcu_sai_tx_data0_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_13),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B1_01),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_SD_B1_07),
-    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_04),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_B0_09),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_36),
-    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_01),
-};
-const mcu_periph_obj_t mcu_sai_tx_sync_list[] = {
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_AD_B1_15),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_B1_03),
-    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_SD_B1_09),
-    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B0_04),
-    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_05),
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_39),
-    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_SD_B1_02),
-};
-const mcu_periph_obj_t mcu_mqs_left_list[] = {
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_14),
-    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_01),
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_05),
-};
-const mcu_periph_obj_t mcu_mqs_right_list[] = {
-    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_13),
-    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_00),
-    PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_B0_04),
 };
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h
index 28ea8e3742..7917a2ebdb 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h
@@ -3,7 +3,9 @@
  *
  * The MIT License (MIT)
  *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,37 +26,30 @@
  * THE SOFTWARE.
  */
 
-#ifndef MICROPY_INCLUDED_MIMXRT10XX_MIMXRT1062_PERIPHERALS_MIMXRT1011_PERIPH_H
-#define MICROPY_INCLUDED_MIMXRT10XX_MIMXRT1062_PERIPHERALS_MIMXRT1011_PERIPH_H
-
+#pragma once
 extern LPI2C_Type *const mcu_i2c_banks[4];
-
 extern const mcu_periph_obj_t mcu_i2c_sda_list[9];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[9];
 
 extern LPSPI_Type *const mcu_spi_banks[4];
-
 extern const mcu_periph_obj_t mcu_spi_sck_list[8];
-extern const mcu_periph_obj_t mcu_spi_mosi_list[8];
-extern const mcu_periph_obj_t mcu_spi_miso_list[8];
+extern const mcu_periph_obj_t mcu_spi_sdo_list[8];
+extern const mcu_periph_obj_t mcu_spi_sdi_list[8];
 
 extern LPUART_Type *const mcu_uart_banks[8];
-
 extern const mcu_periph_obj_t mcu_uart_rx_list[18];
 extern const mcu_periph_obj_t mcu_uart_tx_list[18];
 extern const mcu_periph_obj_t mcu_uart_rts_list[9];
 extern const mcu_periph_obj_t mcu_uart_cts_list[9];
 
-extern const mcu_pwm_obj_t mcu_pwm_list[67];
-
-extern const mcu_periph_obj_t mcu_sai_rx_bclk_list[7];
-extern const mcu_periph_obj_t mcu_sai_rx_data0_list[7];
-extern const mcu_periph_obj_t mcu_sai_rx_sync_list[7];
-extern const mcu_periph_obj_t mcu_sai_tx_bclk_list[7];
-extern const mcu_periph_obj_t mcu_sai_tx_data0_list[7];
-extern const mcu_periph_obj_t mcu_sai_tx_sync_list[7];
+extern I2S_Type *const mcu_i2s_banks[3];
+extern const mcu_periph_obj_t mcu_i2s_rx_data0_list[7];
+extern const mcu_periph_obj_t mcu_i2s_rx_sync_list[7];
+extern const mcu_periph_obj_t mcu_i2s_tx_bclk_list[7];
+extern const mcu_periph_obj_t mcu_i2s_tx_data0_list[7];
+extern const mcu_periph_obj_t mcu_i2s_tx_sync_list[7];
 
 extern const mcu_periph_obj_t mcu_mqs_left_list[3];
 extern const mcu_periph_obj_t mcu_mqs_right_list[3];
 
-#endif // MICROPY_INCLUDED_MIMXRT10XX_MIMXRT1062_PERIPHERALS_MIMXRT1011_PERIPH_H
+extern const mcu_pwm_obj_t mcu_pwm_list[67];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pin_names.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pin_names.h
new file mode 100644
index 0000000000..4b9df709cf
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pin_names.h
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+// define FORMAT_PIN(pin_name) and then include this file.
+
+FORMAT_PIN(GPIO_EMC_00)
+FORMAT_PIN(GPIO_EMC_01)
+FORMAT_PIN(GPIO_EMC_02)
+FORMAT_PIN(GPIO_EMC_03)
+FORMAT_PIN(GPIO_EMC_04)
+FORMAT_PIN(GPIO_EMC_05)
+FORMAT_PIN(GPIO_EMC_06)
+FORMAT_PIN(GPIO_EMC_07)
+FORMAT_PIN(GPIO_EMC_08)
+FORMAT_PIN(GPIO_EMC_09)
+FORMAT_PIN(GPIO_EMC_10)
+FORMAT_PIN(GPIO_EMC_11)
+FORMAT_PIN(GPIO_EMC_12)
+FORMAT_PIN(GPIO_EMC_13)
+FORMAT_PIN(GPIO_EMC_14)
+FORMAT_PIN(GPIO_EMC_15)
+FORMAT_PIN(GPIO_EMC_16)
+FORMAT_PIN(GPIO_EMC_17)
+FORMAT_PIN(GPIO_EMC_18)
+FORMAT_PIN(GPIO_EMC_19)
+FORMAT_PIN(GPIO_EMC_20)
+FORMAT_PIN(GPIO_EMC_21)
+FORMAT_PIN(GPIO_EMC_22)
+FORMAT_PIN(GPIO_EMC_23)
+FORMAT_PIN(GPIO_EMC_24)
+FORMAT_PIN(GPIO_EMC_25)
+FORMAT_PIN(GPIO_EMC_26)
+FORMAT_PIN(GPIO_EMC_27)
+FORMAT_PIN(GPIO_EMC_28)
+FORMAT_PIN(GPIO_EMC_29)
+FORMAT_PIN(GPIO_EMC_30)
+FORMAT_PIN(GPIO_EMC_31)
+FORMAT_PIN(GPIO_EMC_32)
+FORMAT_PIN(GPIO_EMC_33)
+FORMAT_PIN(GPIO_EMC_34)
+FORMAT_PIN(GPIO_EMC_35)
+FORMAT_PIN(GPIO_EMC_36)
+FORMAT_PIN(GPIO_EMC_37)
+FORMAT_PIN(GPIO_EMC_38)
+FORMAT_PIN(GPIO_EMC_39)
+FORMAT_PIN(GPIO_EMC_40)
+FORMAT_PIN(GPIO_EMC_41)
+
+FORMAT_PIN(GPIO_AD_B0_00)
+FORMAT_PIN(GPIO_AD_B0_01)
+FORMAT_PIN(GPIO_AD_B0_02)
+FORMAT_PIN(GPIO_AD_B0_03)
+FORMAT_PIN(GPIO_AD_B0_04)
+FORMAT_PIN(GPIO_AD_B0_05)
+FORMAT_PIN(GPIO_AD_B0_06)
+FORMAT_PIN(GPIO_AD_B0_07)
+FORMAT_PIN(GPIO_AD_B0_08)
+FORMAT_PIN(GPIO_AD_B0_09)
+FORMAT_PIN(GPIO_AD_B0_10)
+FORMAT_PIN(GPIO_AD_B0_11)
+FORMAT_PIN(GPIO_AD_B0_12)
+FORMAT_PIN(GPIO_AD_B0_13)
+FORMAT_PIN(GPIO_AD_B0_14)
+FORMAT_PIN(GPIO_AD_B0_15)
+
+FORMAT_PIN(GPIO_AD_B1_00)
+FORMAT_PIN(GPIO_AD_B1_01)
+FORMAT_PIN(GPIO_AD_B1_02)
+FORMAT_PIN(GPIO_AD_B1_03)
+FORMAT_PIN(GPIO_AD_B1_04)
+FORMAT_PIN(GPIO_AD_B1_05)
+FORMAT_PIN(GPIO_AD_B1_06)
+FORMAT_PIN(GPIO_AD_B1_07)
+FORMAT_PIN(GPIO_AD_B1_08)
+FORMAT_PIN(GPIO_AD_B1_09)
+FORMAT_PIN(GPIO_AD_B1_10)
+FORMAT_PIN(GPIO_AD_B1_11)
+FORMAT_PIN(GPIO_AD_B1_12)
+FORMAT_PIN(GPIO_AD_B1_13)
+FORMAT_PIN(GPIO_AD_B1_14)
+FORMAT_PIN(GPIO_AD_B1_15)
+
+FORMAT_PIN(GPIO_B0_00)
+FORMAT_PIN(GPIO_B0_01)
+FORMAT_PIN(GPIO_B0_02)
+FORMAT_PIN(GPIO_B0_03)
+FORMAT_PIN(GPIO_B0_04)
+FORMAT_PIN(GPIO_B0_05)
+FORMAT_PIN(GPIO_B0_06)
+FORMAT_PIN(GPIO_B0_07)
+FORMAT_PIN(GPIO_B0_08)
+FORMAT_PIN(GPIO_B0_09)
+FORMAT_PIN(GPIO_B0_10)
+FORMAT_PIN(GPIO_B0_11)
+FORMAT_PIN(GPIO_B0_12)
+FORMAT_PIN(GPIO_B0_13)
+FORMAT_PIN(GPIO_B0_14)
+FORMAT_PIN(GPIO_B0_15)
+
+FORMAT_PIN(GPIO_B1_00)
+FORMAT_PIN(GPIO_B1_01)
+FORMAT_PIN(GPIO_B1_02)
+FORMAT_PIN(GPIO_B1_03)
+FORMAT_PIN(GPIO_B1_04)
+FORMAT_PIN(GPIO_B1_05)
+FORMAT_PIN(GPIO_B1_06)
+FORMAT_PIN(GPIO_B1_07)
+FORMAT_PIN(GPIO_B1_08)
+FORMAT_PIN(GPIO_B1_09)
+FORMAT_PIN(GPIO_B1_10)
+FORMAT_PIN(GPIO_B1_11)
+FORMAT_PIN(GPIO_B1_12)
+FORMAT_PIN(GPIO_B1_13)
+FORMAT_PIN(GPIO_B1_14)
+FORMAT_PIN(GPIO_B1_15)
+
+FORMAT_PIN(GPIO_SD_B0_00)
+FORMAT_PIN(GPIO_SD_B0_01)
+FORMAT_PIN(GPIO_SD_B0_02)
+FORMAT_PIN(GPIO_SD_B0_03)
+FORMAT_PIN(GPIO_SD_B0_04)
+FORMAT_PIN(GPIO_SD_B0_05)
+
+FORMAT_PIN(GPIO_SD_B1_00)
+FORMAT_PIN(GPIO_SD_B1_01)
+FORMAT_PIN(GPIO_SD_B1_02)
+FORMAT_PIN(GPIO_SD_B1_03)
+FORMAT_PIN(GPIO_SD_B1_04)
+FORMAT_PIN(GPIO_SD_B1_05)
+FORMAT_PIN(GPIO_SD_B1_06)
+FORMAT_PIN(GPIO_SD_B1_07)
+FORMAT_PIN(GPIO_SD_B1_08)
+FORMAT_PIN(GPIO_SD_B1_09)
+FORMAT_PIN(GPIO_SD_B1_10)
+FORMAT_PIN(GPIO_SD_B1_11)
+FORMAT_PIN(USB_OTG1_DN)
+FORMAT_PIN(USB_OTG1_DP)
+FORMAT_PIN(USB_OTG2_DN)
+FORMAT_PIN(USB_OTG2_DP)
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c
index 7fb5e7a9be..472677ff24 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c
@@ -5,6 +5,7 @@
  *
  * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -56,7 +57,7 @@ const mcu_pin_obj_t pin_GPIO_EMC_23 = PIN(GPIO4, 23, GPIO_EMC_23, NO_ADC, 0, 0x0
 const mcu_pin_obj_t pin_GPIO_EMC_24 = PIN(GPIO4, 24, GPIO_EMC_24, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_25 = PIN(GPIO4, 25, GPIO_EMC_25, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_26 = PIN(GPIO4, 26, GPIO_EMC_26, NO_ADC, 0, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_EMC_27 = PIN(GPIO4, 27, GPIO_EMC_27, NO_ADC, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_EMC_27 = PIN(GPIO4, 27, GPIO_EMC_27, NO_ADC, 0, 0x00000005, 0x000030B0);
 const mcu_pin_obj_t pin_GPIO_EMC_28 = PIN(GPIO4, 28, GPIO_EMC_28, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_29 = PIN(GPIO4, 29, GPIO_EMC_29, NO_ADC, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_EMC_30 = PIN(GPIO4, 30, GPIO_EMC_30, NO_ADC, 0, 0x00000005, 0x000010B0);
@@ -87,18 +88,18 @@ const mcu_pin_obj_t pin_GPIO_AD_B0_12 = PIN(GPIO1, 12, GPIO_AD_B0_12, ADC1, 1, 0
 const mcu_pin_obj_t pin_GPIO_AD_B0_13 = PIN(GPIO1, 13, GPIO_AD_B0_13, ADC1, 2, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_AD_B0_14 = PIN(GPIO1, 14, GPIO_AD_B0_14, ADC1, 3, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_AD_B0_15 = PIN(GPIO1, 15, GPIO_AD_B0_15, ADC1, 4, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_00 = PIN(GPIO1, 16, GPIO_AD_B1_00, ADC1, 5, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_01 = PIN(GPIO1, 17, GPIO_AD_B1_01, ADC1, 6, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_02 = PIN(GPIO1, 18, GPIO_AD_B1_02, ADC1, 7, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_03 = PIN(GPIO1, 19, GPIO_AD_B1_03, ADC1, 8, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_04 = PIN(GPIO1, 20, GPIO_AD_B1_04, ADC1, 9, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_05 = PIN(GPIO1, 21, GPIO_AD_B1_05, ADC1, 10, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_06 = PIN(GPIO1, 22, GPIO_AD_B1_06, ADC1, 11, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_07 = PIN(GPIO1, 23, GPIO_AD_B1_07, ADC1, 12, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_08 = PIN(GPIO1, 24, GPIO_AD_B1_08, ADC1, 13, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_09 = PIN(GPIO1, 25, GPIO_AD_B1_09, ADC1, 14, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_10 = PIN(GPIO1, 26, GPIO_AD_B1_10, ADC1, 15, 0x00000005, 0x000010B0);
-const mcu_pin_obj_t pin_GPIO_AD_B1_11 = PIN(GPIO1, 27, GPIO_AD_B1_11, ADC1, 0, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_00 = PIN(GPIO1, 16, GPIO_AD_B1_00, ADC2, 5, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_01 = PIN(GPIO1, 17, GPIO_AD_B1_01, ADC2, 6, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_02 = PIN(GPIO1, 18, GPIO_AD_B1_02, ADC2, 7, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_03 = PIN(GPIO1, 19, GPIO_AD_B1_03, ADC2, 8, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_04 = PIN(GPIO1, 20, GPIO_AD_B1_04, ADC2, 9, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_05 = PIN(GPIO1, 21, GPIO_AD_B1_05, ADC2, 10, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_06 = PIN(GPIO1, 22, GPIO_AD_B1_06, ADC2, 11, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_07 = PIN(GPIO1, 23, GPIO_AD_B1_07, ADC2, 12, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_08 = PIN(GPIO1, 24, GPIO_AD_B1_08, ADC2, 13, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_09 = PIN(GPIO1, 25, GPIO_AD_B1_09, ADC2, 14, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_10 = PIN(GPIO1, 26, GPIO_AD_B1_10, ADC2, 15, 0x00000005, 0x000010B0);
+const mcu_pin_obj_t pin_GPIO_AD_B1_11 = PIN(GPIO1, 27, GPIO_AD_B1_11, ADC2, 0, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_AD_B1_12 = PIN(GPIO1, 28, GPIO_AD_B1_12, ADC2, 1, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_AD_B1_13 = PIN(GPIO1, 29, GPIO_AD_B1_13, ADC2, 2, 0x00000005, 0x000010B0);
 const mcu_pin_obj_t pin_GPIO_AD_B1_14 = PIN(GPIO1, 30, GPIO_AD_B1_14, ADC2, 3, 0x00000005, 0x000010B0);
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.h
index 109882df93..6e40d30c2b 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.h
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.h
@@ -3,7 +3,9 @@
  *
  * The MIT License (MIT)
  *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
  * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,145 +26,11 @@
  * THE SOFTWARE.
  */
 
-#ifndef MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1062_PINS_H
-#define MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1062_PINS_H
+#pragma once
 
-extern const mcu_pin_obj_t pin_GPIO_EMC_00;
-extern const mcu_pin_obj_t pin_GPIO_EMC_01;
-extern const mcu_pin_obj_t pin_GPIO_EMC_02;
-extern const mcu_pin_obj_t pin_GPIO_EMC_03;
-extern const mcu_pin_obj_t pin_GPIO_EMC_04;
-extern const mcu_pin_obj_t pin_GPIO_EMC_05;
-extern const mcu_pin_obj_t pin_GPIO_EMC_06;
-extern const mcu_pin_obj_t pin_GPIO_EMC_07;
-extern const mcu_pin_obj_t pin_GPIO_EMC_08;
-extern const mcu_pin_obj_t pin_GPIO_EMC_09;
-extern const mcu_pin_obj_t pin_GPIO_EMC_10;
-extern const mcu_pin_obj_t pin_GPIO_EMC_11;
-extern const mcu_pin_obj_t pin_GPIO_EMC_12;
-extern const mcu_pin_obj_t pin_GPIO_EMC_13;
-extern const mcu_pin_obj_t pin_GPIO_EMC_14;
-extern const mcu_pin_obj_t pin_GPIO_EMC_15;
-extern const mcu_pin_obj_t pin_GPIO_EMC_16;
-extern const mcu_pin_obj_t pin_GPIO_EMC_17;
-extern const mcu_pin_obj_t pin_GPIO_EMC_18;
-extern const mcu_pin_obj_t pin_GPIO_EMC_19;
-extern const mcu_pin_obj_t pin_GPIO_EMC_20;
-extern const mcu_pin_obj_t pin_GPIO_EMC_21;
-extern const mcu_pin_obj_t pin_GPIO_EMC_22;
-extern const mcu_pin_obj_t pin_GPIO_EMC_23;
-extern const mcu_pin_obj_t pin_GPIO_EMC_24;
-extern const mcu_pin_obj_t pin_GPIO_EMC_25;
-extern const mcu_pin_obj_t pin_GPIO_EMC_26;
-extern const mcu_pin_obj_t pin_GPIO_EMC_27;
-extern const mcu_pin_obj_t pin_GPIO_EMC_28;
-extern const mcu_pin_obj_t pin_GPIO_EMC_29;
-extern const mcu_pin_obj_t pin_GPIO_EMC_30;
-extern const mcu_pin_obj_t pin_GPIO_EMC_31;
-extern const mcu_pin_obj_t pin_GPIO_EMC_32;
-extern const mcu_pin_obj_t pin_GPIO_EMC_33;
-extern const mcu_pin_obj_t pin_GPIO_EMC_34;
-extern const mcu_pin_obj_t pin_GPIO_EMC_35;
-extern const mcu_pin_obj_t pin_GPIO_EMC_36;
-extern const mcu_pin_obj_t pin_GPIO_EMC_37;
-extern const mcu_pin_obj_t pin_GPIO_EMC_38;
-extern const mcu_pin_obj_t pin_GPIO_EMC_39;
-extern const mcu_pin_obj_t pin_GPIO_EMC_40;
-extern const mcu_pin_obj_t pin_GPIO_EMC_41;
+#define FORMAT_PIN(pin_name) extern const mcu_pin_obj_t pin_##pin_name;
+#include "pin_names.h"
+#undef FORMAT_PIN
 
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_00;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_01;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_02;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_03;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_04;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_05;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_06;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_07;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_08;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_09;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_10;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_11;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_12;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_13;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_14;
-extern const mcu_pin_obj_t pin_GPIO_AD_B0_15;
-
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_00;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_01;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_02;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_03;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_04;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_05;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_06;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_07;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_08;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_09;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_10;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_11;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_12;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_13;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_14;
-extern const mcu_pin_obj_t pin_GPIO_AD_B1_15;
-
-extern const mcu_pin_obj_t pin_GPIO_B0_00;
-extern const mcu_pin_obj_t pin_GPIO_B0_01;
-extern const mcu_pin_obj_t pin_GPIO_B0_02;
-extern const mcu_pin_obj_t pin_GPIO_B0_03;
-extern const mcu_pin_obj_t pin_GPIO_B0_04;
-extern const mcu_pin_obj_t pin_GPIO_B0_05;
-extern const mcu_pin_obj_t pin_GPIO_B0_06;
-extern const mcu_pin_obj_t pin_GPIO_B0_07;
-extern const mcu_pin_obj_t pin_GPIO_B0_08;
-extern const mcu_pin_obj_t pin_GPIO_B0_09;
-extern const mcu_pin_obj_t pin_GPIO_B0_10;
-extern const mcu_pin_obj_t pin_GPIO_B0_11;
-extern const mcu_pin_obj_t pin_GPIO_B0_12;
-extern const mcu_pin_obj_t pin_GPIO_B0_13;
-extern const mcu_pin_obj_t pin_GPIO_B0_14;
-extern const mcu_pin_obj_t pin_GPIO_B0_15;
-
-extern const mcu_pin_obj_t pin_GPIO_B1_00;
-extern const mcu_pin_obj_t pin_GPIO_B1_01;
-extern const mcu_pin_obj_t pin_GPIO_B1_02;
-extern const mcu_pin_obj_t pin_GPIO_B1_03;
-extern const mcu_pin_obj_t pin_GPIO_B1_04;
-extern const mcu_pin_obj_t pin_GPIO_B1_05;
-extern const mcu_pin_obj_t pin_GPIO_B1_06;
-extern const mcu_pin_obj_t pin_GPIO_B1_07;
-extern const mcu_pin_obj_t pin_GPIO_B1_08;
-extern const mcu_pin_obj_t pin_GPIO_B1_09;
-extern const mcu_pin_obj_t pin_GPIO_B1_10;
-extern const mcu_pin_obj_t pin_GPIO_B1_11;
-extern const mcu_pin_obj_t pin_GPIO_B1_12;
-extern const mcu_pin_obj_t pin_GPIO_B1_13;
-extern const mcu_pin_obj_t pin_GPIO_B1_14;
-extern const mcu_pin_obj_t pin_GPIO_B1_15;
-
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_00;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_01;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_02;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_03;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_04;
-extern const mcu_pin_obj_t pin_GPIO_SD_B0_05;
-
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_00;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_01;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_02;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_03;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_04;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_05;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_06;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_07;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_08;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_09;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_10;
-extern const mcu_pin_obj_t pin_GPIO_SD_B1_11;
-
-extern const mcu_pin_obj_t pin_USB_OTG1_DN;
-extern const mcu_pin_obj_t pin_USB_OTG1_DP;
-extern const mcu_pin_obj_t pin_USB_OTG2_DN;
-extern const mcu_pin_obj_t pin_USB_OTG2_DP;
-
-extern const mcu_pin_obj_t mcu_pin_list[IOMUXC_SW_PAD_CTL_PAD_COUNT];
-
-#endif // MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1062_PINS_H
+#define PIN_COUNT (IOMUXC_SW_PAD_CTL_PAD_COUNT + 4)
+extern const mcu_pin_obj_t mcu_pin_list[PIN_COUNT];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/clocks.c
new file mode 100644
index 0000000000..1252d48135
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/clocks.c
@@ -0,0 +1,672 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "mpconfigport.h"
+
+#include "fsl_clock.h"
+#include "fsl_iomuxc.h"
+#include "fsl_dcdc.h"
+#include "fsl_device_registers.h"
+#include "fsl_pmu.h"
+
+#include "clocks.h"
+
+#ifndef SKIP_POWER_ADJUSTMENT
+#if __CORTEX_M == 7
+#define BYPASS_LDO_LPSR 1
+#define SKIP_LDO_ADJUSTMENT 1
+#elif __CORTEX_M == 4
+#define SKIP_DCDC_ADJUSTMENT 1
+#define SKIP_FBB_ENABLE 1
+#endif
+#endif
+
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+{
+    .postDivider = kCLOCK_PllPostDiv2,            /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
+    .loopDivider = 166,                           /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
+};
+
+const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
+{
+    .mfd = 268435455,                             /* Denominator of spread spectrum */
+    .ss = NULL,                                   /* Spread spectrum parameter */
+    .ssEnable = false,                            /* Enable spread spectrum or not */
+};
+
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 41,                            /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
+    .postDivider = 0,                             /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
+    .numerator = 1,                               /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .denominator = 960000,                        /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .ss = NULL,                                   /* Spread spectrum parameter */
+    .ssEnable = false,                            /* Enable spread spectrum or not */
+};
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void clocks_init(void) {
+    clock_root_config_t rootCfg = {0};
+
+    /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
+    DCDC_BootIntoDCM(DCDC);
+
+    #if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
+    if ((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU)) {
+        DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
+    } else {
+        /* Set 1.125V for production samples to align with data sheet requirement */
+        DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
+    }
+    #endif
+
+    #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
+    /* Check if FBB need to be enabled in OverDrive(OD) mode */
+    if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) {
+        PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
+    } else {
+        PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
+    }
+    #endif
+
+    #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
+    PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
+    PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
+    #endif
+
+    #if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
+    pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
+    pmu_static_lpsr_dig_config_t lpsrDigConfig;
+
+    if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) {
+        PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
+        PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
+    }
+
+    if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) {
+        PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
+        lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
+        PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
+    }
+    #endif
+
+    /* Config CLK_1M */
+    CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
+
+    /* Init OSC RC 16M */
+    ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
+
+    /* Init OSC RC 400M */
+    CLOCK_OSC_EnableOscRc400M();
+    CLOCK_OSC_GateOscRc400M(true);
+
+    /* Init OSC RC 48M */
+    CLOCK_OSC_EnableOsc48M(true);
+    CLOCK_OSC_EnableOsc48MDiv2(true);
+
+    /* Config OSC 24M */
+    ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
+    /* Wait for 24M OSC to be stable. */
+    while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
+           (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {
+    }
+
+    /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
+    #if __CORTEX_M == 7
+    rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+
+    rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+    #endif
+
+    #if __CORTEX_M == 4
+    rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
+
+    rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+    #endif
+
+    /*
+    * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
+    */
+    /* Init Arm Pll. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+
+    /* Bypass Sys Pll1. */
+    CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
+
+    /* DeInit Sys Pll1. */
+    CLOCK_DeinitSysPll1();
+
+    /* Init Sys Pll2. */
+    CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
+
+    /* Init System Pll2 pfd0. */
+    CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
+
+    /* Init System Pll2 pfd1. */
+    CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
+
+    /* Init System Pll2 pfd2. */
+    CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
+
+    /* Init System Pll2 pfd3. */
+    CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
+
+    /* Init Sys Pll3. */
+    CLOCK_InitSysPll3();
+
+    /* Init System Pll3 pfd0. */
+    CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
+
+    /* Init System Pll3 pfd1. */
+    CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
+
+    /* Init System Pll3 pfd2. */
+    CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
+
+    /* Init System Pll3 pfd3. */
+    CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
+
+    /* Bypass Audio Pll. */
+    CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
+
+    /* DeInit Audio Pll. */
+    CLOCK_DeinitAudioPll();
+
+    /* Init Video Pll. */
+    CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
+
+    /* Module clock root configurations. */
+    /* Configure M7 using ARM_PLL_CLK */
+    #if __CORTEX_M == 7
+    rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+    #endif
+
+    /* Configure M4 using SYS_PLL3_PFD3_CLK */
+    #if __CORTEX_M == 4
+    rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
+    #endif
+
+    /* Configure BUS using SYS_PLL3_CLK */
+    rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
+    rootCfg.div = 2;
+    CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
+
+    /* Configure BUS_LPSR using SYS_PLL3_CLK */
+    rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
+    rootCfg.div = 3;
+    CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+
+    /* Configure SEMC using SYS_PLL2_PFD1_CLK */
+    #ifndef SKIP_SEMC_INIT
+    rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
+    rootCfg.div = 3;
+    CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
+    #endif
+
+    #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+    #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    UpdateSemcClock();
+    #endif
+    #endif
+
+    /* Configure CSSYS using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
+
+    /* Configure CSTRACE using SYS_PLL2_CLK */
+    rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
+    rootCfg.div = 4;
+    CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
+
+    /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
+    #if __CORTEX_M == 4
+    rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
+    #endif
+
+    /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
+    #if __CORTEX_M == 7
+    rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 240;
+    CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+    #endif
+
+    /* Configure ADC1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
+
+    /* Configure ADC2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
+
+    /* Configure ACMP using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
+
+    /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
+
+    /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
+
+    /* Configure GPT1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
+
+    /* Configure GPT2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
+
+    /* Configure GPT3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
+
+    /* Configure GPT4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
+
+    /* Configure GPT5 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
+
+    /* Configure GPT6 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
+
+    /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
+    #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
+    rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
+    #endif
+
+    /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
+
+    /* Configure CAN1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
+
+    /* Configure CAN2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
+
+    /* Configure CAN3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
+
+    /* Configure LPUART1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
+
+    /* Configure LPUART2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
+
+    /* Configure LPUART3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
+
+    /* Configure LPUART4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
+
+    /* Configure LPUART5 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
+
+    /* Configure LPUART6 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
+
+    /* Configure LPUART7 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
+
+    /* Configure LPUART8 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
+
+    /* Configure LPUART9 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
+
+    /* Configure LPUART10 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
+
+    /* Configure LPUART11 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
+
+    /* Configure LPUART12 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
+
+    /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
+
+    /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
+
+    /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
+
+    /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
+
+    /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
+
+    /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
+
+    /* Configure LPSPI1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
+
+    /* Configure LPSPI2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
+
+    /* Configure LPSPI3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
+
+    /* Configure LPSPI4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
+
+    /* Configure LPSPI5 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
+
+    /* Configure LPSPI6 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
+
+    /* Configure EMV1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
+
+    /* Configure EMV2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
+
+    /* Configure ENET1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
+
+    /* Configure ENET2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
+
+    /* Configure ENET_QOS using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
+
+    /* Configure ENET_25M using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
+
+    /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
+
+    /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
+
+    /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
+
+    /* Configure USDHC1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
+
+    /* Configure USDHC2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
+
+    /* Configure ASRC using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
+
+    /* Configure MQS using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
+
+    /* Configure MIC using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
+
+    /* Configure SPDIF using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
+
+    /* Configure SAI1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
+
+    /* Configure SAI2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
+
+    /* Configure SAI3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
+
+    /* Configure SAI4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
+
+    /* Configure GC355 using PLL_VIDEO_CLK */
+    rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
+    rootCfg.div = 2;
+    CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
+
+    /* Configure LCDIF using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
+
+    /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
+
+    /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
+
+    /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
+
+    /* Configure CSI2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
+
+    /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
+
+    /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
+
+    /* Configure CSI using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
+
+    /* Configure CKO1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
+
+    /* Configure CKO2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
+
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
+    /* Set ENET_1G Tx clock source. */
+    IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
+    /* Set ENET_1G Ref clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
+    /* Set ENET_QOS Tx clock source. */
+    IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
+    /* Set ENET_QOS Ref clock source. */
+    IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
+    /* Set GPT3 High frequency reference clock source. */
+    IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
+    /* Set GPT4 High frequency reference clock source. */
+    IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
+    /* Set GPT5 High frequency reference clock source. */
+    IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
+    /* Set GPT6 High frequency reference clock source. */
+    IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
+
+    #if __CORTEX_M == 7
+    SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
+    #else
+    SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
+    #endif
+}
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/periph.c
new file mode 100644
index 0000000000..3263bdea09
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/periph.c
@@ -0,0 +1,358 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "mimxrt10xx/periph.h"
+
+LPI2C_Type *const mcu_i2c_banks[6] = { LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6 };
+
+const mcu_periph_obj_t mcu_i2c_sda_list[8] = {
+    PERIPH_PIN(1, 1, 0, 0, &pin_GPIO_AD_09),
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_33),
+
+    PERIPH_PIN(2, 9, 0, 0, &pin_GPIO_EMC_B2_01),
+    PERIPH_PIN(2, 9, 0, 0, &pin_GPIO_AD_19),
+
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_DISP_B1_03),
+    PERIPH_PIN(3, 6, 0, 0, &pin_GPIO_DISP_B2_11),
+
+    PERIPH_PIN(4, 9, 0, 0, &pin_GPIO_AD_25),
+    PERIPH_PIN(4, 6, 0, 0, &pin_GPIO_DISP_B2_13),
+};
+
+const mcu_periph_obj_t mcu_i2c_scl_list[8] = {
+    PERIPH_PIN(1, 1, 0, 0, &pin_GPIO_AD_08),
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_32),
+
+    PERIPH_PIN(2, 9, 0, 0, &pin_GPIO_EMC_B2_00),
+    PERIPH_PIN(2, 9, 0, 0, &pin_GPIO_AD_18),
+
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_DISP_B1_02),
+    PERIPH_PIN(3, 6, 0, 0, &pin_GPIO_DISP_B2_10),
+
+    PERIPH_PIN(4, 9, 0, 0, &pin_GPIO_AD_24),
+    PERIPH_PIN(4, 6, 0, 0, &pin_GPIO_DISP_B2_12),
+};
+
+LPSPI_Type *const mcu_spi_banks[6] = { LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6 };
+
+const mcu_periph_obj_t mcu_spi_sck_list[8] = {
+    PERIPH_PIN(1, 8, 0, 0, &pin_GPIO_EMC_B2_00),
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_28),
+
+    PERIPH_PIN(2, 1, 0, 0, &pin_GPIO_AD_24),
+    PERIPH_PIN(2, 6, 0, 0, &pin_GPIO_SD_B2_07),
+
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_EMC_B2_04),
+    PERIPH_PIN(3, 9, 0, 0, &pin_GPIO_DISP_B1_04),
+
+    PERIPH_PIN(4, 4, 0, 0, &pin_GPIO_SD_B2_00),
+    PERIPH_PIN(4, 9, 0, 0, &pin_GPIO_DISP_B2_12),
+};
+
+const mcu_periph_obj_t mcu_spi_sdo_list[0] = {
+};
+
+const mcu_periph_obj_t mcu_spi_sdi_list[0] = {
+};
+
+LPUART_Type *const mcu_uart_banks[12] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 };
+
+const mcu_periph_obj_t mcu_uart_rx_list[15] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_25),
+    PERIPH_PIN(1, 9, 0, 0, &pin_GPIO_DISP_B1_03),
+    PERIPH_PIN(1, 9, 0, 0, &pin_GPIO_DISP_B2_09),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_DISP_B2_11),
+
+    PERIPH_PIN(3, 4, 0, 0, &pin_GPIO_AD_31),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_DISP_B1_04),
+
+    PERIPH_PIN(5, 1, 0, 0, &pin_GPIO_AD_29),
+
+    PERIPH_PIN(6, 3, 0, 0, &pin_GPIO_EMC_B1_41),
+
+    PERIPH_PIN(7, 6, 0, 0, &pin_GPIO_AD_01),
+    PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_DISP_B2_07),
+
+    PERIPH_PIN(8, 6, 0, 0, &pin_GPIO_AD_03),
+    PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_DISP_B2_09),
+
+    PERIPH_PIN(9, 3, 0, 0, &pin_GPIO_SD_B2_01),
+
+    PERIPH_PIN(10, 1, 0, 0, &pin_GPIO_AD_16),
+    PERIPH_PIN(10, 8, 0, 0, &pin_GPIO_AD_33),
+};
+
+const mcu_periph_obj_t mcu_uart_tx_list[15] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_24),
+    PERIPH_PIN(1, 9, 0, 0, &pin_GPIO_DISP_B1_02),
+    PERIPH_PIN(1, 9, 0, 0, &pin_GPIO_DISP_B2_08),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_DISP_B2_10),
+
+    PERIPH_PIN(3, 4, 0, 0, &pin_GPIO_AD_30),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_DISP_B1_06),
+
+    PERIPH_PIN(5, 1, 0, 0, &pin_GPIO_AD_28),
+
+    PERIPH_PIN(6, 3, 0, 0, &pin_GPIO_EMC_B1_40),
+
+    PERIPH_PIN(7, 6, 0, 0, &pin_GPIO_AD_00),
+    PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_DISP_B2_06),
+
+    PERIPH_PIN(8, 6, 0, 0, &pin_GPIO_AD_02),
+    PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_DISP_B2_08),
+
+    PERIPH_PIN(9, 3, 0, 0, &pin_GPIO_SD_B2_00),
+
+    PERIPH_PIN(10, 1, 0, 0, &pin_GPIO_AD_15),
+    PERIPH_PIN(10, 8, 0, 0, &pin_GPIO_AD_32),
+};
+
+const mcu_periph_obj_t mcu_uart_rts_list[10] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_27),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_DISP_B2_13),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B2_08),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_DISP_B1_07),
+
+    PERIPH_PIN(5, 3, 0, 0, &pin_GPIO_SD_B2_10),
+
+    PERIPH_PIN(6, 3, 0, 0, &pin_GPIO_EMC_B2_01),
+
+    PERIPH_PIN(7, 1, 0, 0, &pin_GPIO_AD_03),
+
+    PERIPH_PIN(8, 1, 0, 0, &pin_GPIO_AD_05),
+
+    PERIPH_PIN(9, 3, 0, 0, &pin_GPIO_SD_B2_03),
+
+    PERIPH_PIN(10, 8, 0, 0, &pin_GPIO_AD_35),
+};
+
+const mcu_periph_obj_t mcu_uart_cts_list[10] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_26),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_DISP_B2_12),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_SD_B2_07),
+
+    PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_DISP_B1_05),
+
+    PERIPH_PIN(5, 3, 0, 0, &pin_GPIO_SD_B2_09),
+
+    PERIPH_PIN(6, 3, 0, 0, &pin_GPIO_EMC_B2_00),
+
+    PERIPH_PIN(7, 1, 0, 0, &pin_GPIO_AD_02),
+
+    PERIPH_PIN(8, 1, 0, 0, &pin_GPIO_AD_04),
+
+    PERIPH_PIN(9, 3, 0, 0, &pin_GPIO_SD_B2_02),
+
+    PERIPH_PIN(10, 8, 0, 0, &pin_GPIO_AD_34),
+};
+
+I2S_Type *const mcu_i2s_banks[4] = { SAI1, SAI2, SAI3, SAI4 };
+
+const mcu_periph_obj_t mcu_i2s_rx_data0_list[4] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_20),
+    PERIPH_PIN(1, 4, 0, 0, &pin_GPIO_DISP_B2_06),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_B2_07),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_B2_13),
+};
+
+const mcu_periph_obj_t mcu_i2s_rx_sync_list[4] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_18),
+    PERIPH_PIN(1, 4, 0, 0, &pin_GPIO_DISP_B2_04),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_B2_05),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_B2_11),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_bclk_list[4] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_22),
+    PERIPH_PIN(1, 4, 0, 0, &pin_GPIO_DISP_B2_08),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_B2_09),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_B2_15),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_data0_list[4] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_21),
+    PERIPH_PIN(1, 4, 0, 0, &pin_GPIO_DISP_B2_07),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_B2_08),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_B2_14),
+};
+
+const mcu_periph_obj_t mcu_i2s_tx_sync_list[4] = {
+    PERIPH_PIN(1, 0, 0, 0, &pin_GPIO_AD_23),
+    PERIPH_PIN(1, 4, 0, 0, &pin_GPIO_DISP_B2_09),
+
+    PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_B2_10),
+
+    PERIPH_PIN(3, 3, 0, 0, &pin_GPIO_EMC_B2_16),
+};
+
+const mcu_periph_obj_t mcu_mqs_left_list[2] = {
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_B1_41),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_DISP_B2_01),
+};
+
+const mcu_periph_obj_t mcu_mqs_right_list[2] = {
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_B1_40),
+    PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_DISP_B2_00),
+};
+
+const mcu_pwm_obj_t mcu_pwm_list[68] = {
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A, &pin_GPIO_EMC_B1_23),
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A, &pin_GPIO_AD_00),
+
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B, &pin_GPIO_EMC_B1_24),
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B, &pin_GPIO_AD_01),
+
+    PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X, &pin_GPIO_AD_06),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A, &pin_GPIO_EMC_B1_25),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A, &pin_GPIO_AD_02),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B, &pin_GPIO_EMC_B1_26),
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B, &pin_GPIO_AD_03),
+
+    PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X, &pin_GPIO_AD_07),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A, &pin_GPIO_EMC_B1_27),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A, &pin_GPIO_AD_04),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B, &pin_GPIO_EMC_B1_28),
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B, &pin_GPIO_AD_05),
+
+    PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X, &pin_GPIO_AD_08),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A, &pin_GPIO_EMC_B1_38),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B, &pin_GPIO_EMC_B1_39),
+
+    PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X, &pin_GPIO_AD_09),
+
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A, &pin_GPIO_EMC_B1_06),
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A, &pin_GPIO_AD_24),
+
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B, &pin_GPIO_EMC_B1_07),
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B, &pin_GPIO_AD_25),
+
+    PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X, &pin_GPIO_AD_10),
+
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A, &pin_GPIO_EMC_B1_08),
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A, &pin_GPIO_AD_26),
+
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B, &pin_GPIO_EMC_B1_09),
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B, &pin_GPIO_AD_27),
+
+    PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X, &pin_GPIO_AD_11),
+
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A, &pin_GPIO_EMC_B1_10),
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A, &pin_GPIO_AD_28),
+
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B, &pin_GPIO_EMC_B1_11),
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B, &pin_GPIO_AD_29),
+
+    PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X, &pin_GPIO_AD_12),
+
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A, &pin_GPIO_EMC_B1_19),
+
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B, &pin_GPIO_EMC_B1_20),
+
+    PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X, &pin_GPIO_AD_13),
+
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A, &pin_GPIO_EMC_B1_29),
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A, &pin_GPIO_EMC_B2_00),
+
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B, &pin_GPIO_EMC_B1_30),
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B, &pin_GPIO_EMC_B2_01),
+
+    PWM_PIN(PWM3, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X, &pin_GPIO_AD_14),
+
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A, &pin_GPIO_EMC_B1_31),
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A, &pin_GPIO_EMC_B2_02),
+
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B, &pin_GPIO_EMC_B1_32),
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B, &pin_GPIO_EMC_B2_03),
+
+    PWM_PIN(PWM3, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X, &pin_GPIO_AD_15),
+
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A, &pin_GPIO_EMC_B1_33),
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A, &pin_GPIO_EMC_B2_04),
+
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B, &pin_GPIO_EMC_B1_34),
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B, &pin_GPIO_EMC_B2_05),
+
+    PWM_PIN(PWM3, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X, &pin_GPIO_AD_16),
+
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A, &pin_GPIO_EMC_B1_21),
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A, &pin_GPIO_EMC_B2_06),
+
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B, &pin_GPIO_EMC_B1_22),
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B, &pin_GPIO_EMC_B2_07),
+
+    PWM_PIN(PWM3, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X, &pin_GPIO_AD_17),
+
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A, &pin_GPIO_EMC_B1_00),
+
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B, &pin_GPIO_EMC_B1_01),
+
+    PWM_PIN(PWM4, kPWM_Module_0, kPWM_PwmX, IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X, &pin_GPIO_AD_18),
+
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A, &pin_GPIO_EMC_B1_02),
+
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B, &pin_GPIO_EMC_B1_03),
+
+    PWM_PIN(PWM4, kPWM_Module_1, kPWM_PwmX, IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X, &pin_GPIO_AD_19),
+
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A, &pin_GPIO_EMC_B1_04),
+
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B, &pin_GPIO_EMC_B1_05),
+
+    PWM_PIN(PWM4, kPWM_Module_2, kPWM_PwmX, IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X, &pin_GPIO_AD_20),
+
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmA, IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A, &pin_GPIO_EMC_B1_17),
+
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmB, IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B, &pin_GPIO_EMC_B1_18),
+
+    PWM_PIN(PWM4, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X, &pin_GPIO_AD_21),
+};
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/periph.h
new file mode 100644
index 0000000000..41695d655b
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/periph.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+extern LPI2C_Type *const mcu_i2c_banks[6];
+extern const mcu_periph_obj_t mcu_i2c_sda_list[8];
+extern const mcu_periph_obj_t mcu_i2c_scl_list[8];
+
+extern LPSPI_Type *const mcu_spi_banks[6];
+extern const mcu_periph_obj_t mcu_spi_sck_list[8];
+extern const mcu_periph_obj_t mcu_spi_sdo_list[0];
+extern const mcu_periph_obj_t mcu_spi_sdi_list[0];
+
+extern LPUART_Type *const mcu_uart_banks[12];
+extern const mcu_periph_obj_t mcu_uart_rx_list[15];
+extern const mcu_periph_obj_t mcu_uart_tx_list[15];
+extern const mcu_periph_obj_t mcu_uart_rts_list[10];
+extern const mcu_periph_obj_t mcu_uart_cts_list[10];
+
+extern I2S_Type *const mcu_i2s_banks[4];
+extern const mcu_periph_obj_t mcu_i2s_rx_data0_list[4];
+extern const mcu_periph_obj_t mcu_i2s_rx_sync_list[4];
+extern const mcu_periph_obj_t mcu_i2s_tx_bclk_list[4];
+extern const mcu_periph_obj_t mcu_i2s_tx_data0_list[4];
+extern const mcu_periph_obj_t mcu_i2s_tx_sync_list[4];
+
+extern const mcu_periph_obj_t mcu_mqs_left_list[2];
+extern const mcu_periph_obj_t mcu_mqs_right_list[2];
+
+extern const mcu_pwm_obj_t mcu_pwm_list[68];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pin_names.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pin_names.h
new file mode 100644
index 0000000000..6dcd77a6a2
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pin_names.h
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+// define FORMAT_PIN(pin_name) and then include this file.
+
+FORMAT_PIN(GPIO_EMC_B1_00)
+FORMAT_PIN(GPIO_EMC_B1_01)
+FORMAT_PIN(GPIO_EMC_B1_02)
+FORMAT_PIN(GPIO_EMC_B1_03)
+FORMAT_PIN(GPIO_EMC_B1_04)
+FORMAT_PIN(GPIO_EMC_B1_05)
+FORMAT_PIN(GPIO_EMC_B1_06)
+FORMAT_PIN(GPIO_EMC_B1_07)
+FORMAT_PIN(GPIO_EMC_B1_08)
+FORMAT_PIN(GPIO_EMC_B1_09)
+FORMAT_PIN(GPIO_EMC_B1_10)
+FORMAT_PIN(GPIO_EMC_B1_11)
+FORMAT_PIN(GPIO_EMC_B1_12)
+FORMAT_PIN(GPIO_EMC_B1_13)
+FORMAT_PIN(GPIO_EMC_B1_14)
+FORMAT_PIN(GPIO_EMC_B1_15)
+FORMAT_PIN(GPIO_EMC_B1_16)
+FORMAT_PIN(GPIO_EMC_B1_17)
+FORMAT_PIN(GPIO_EMC_B1_18)
+FORMAT_PIN(GPIO_EMC_B1_19)
+FORMAT_PIN(GPIO_EMC_B1_20)
+FORMAT_PIN(GPIO_EMC_B1_21)
+FORMAT_PIN(GPIO_EMC_B1_22)
+FORMAT_PIN(GPIO_EMC_B1_23)
+FORMAT_PIN(GPIO_EMC_B1_24)
+FORMAT_PIN(GPIO_EMC_B1_25)
+FORMAT_PIN(GPIO_EMC_B1_26)
+FORMAT_PIN(GPIO_EMC_B1_27)
+FORMAT_PIN(GPIO_EMC_B1_28)
+FORMAT_PIN(GPIO_EMC_B1_29)
+FORMAT_PIN(GPIO_EMC_B1_30)
+FORMAT_PIN(GPIO_EMC_B1_31)
+FORMAT_PIN(GPIO_EMC_B1_32)
+FORMAT_PIN(GPIO_EMC_B1_33)
+FORMAT_PIN(GPIO_EMC_B1_34)
+FORMAT_PIN(GPIO_EMC_B1_35)
+FORMAT_PIN(GPIO_EMC_B1_36)
+FORMAT_PIN(GPIO_EMC_B1_37)
+FORMAT_PIN(GPIO_EMC_B1_38)
+FORMAT_PIN(GPIO_EMC_B1_39)
+FORMAT_PIN(GPIO_EMC_B1_40)
+FORMAT_PIN(GPIO_EMC_B1_41)
+
+FORMAT_PIN(GPIO_EMC_B2_00)
+FORMAT_PIN(GPIO_EMC_B2_01)
+FORMAT_PIN(GPIO_EMC_B2_02)
+FORMAT_PIN(GPIO_EMC_B2_03)
+FORMAT_PIN(GPIO_EMC_B2_04)
+FORMAT_PIN(GPIO_EMC_B2_05)
+FORMAT_PIN(GPIO_EMC_B2_06)
+FORMAT_PIN(GPIO_EMC_B2_07)
+FORMAT_PIN(GPIO_EMC_B2_08)
+FORMAT_PIN(GPIO_EMC_B2_09)
+FORMAT_PIN(GPIO_EMC_B2_10)
+FORMAT_PIN(GPIO_EMC_B2_11)
+FORMAT_PIN(GPIO_EMC_B2_12)
+FORMAT_PIN(GPIO_EMC_B2_13)
+FORMAT_PIN(GPIO_EMC_B2_14)
+FORMAT_PIN(GPIO_EMC_B2_15)
+FORMAT_PIN(GPIO_EMC_B2_16)
+FORMAT_PIN(GPIO_EMC_B2_17)
+FORMAT_PIN(GPIO_EMC_B2_18)
+FORMAT_PIN(GPIO_EMC_B2_19)
+FORMAT_PIN(GPIO_EMC_B2_20)
+
+FORMAT_PIN(GPIO_AD_00)
+FORMAT_PIN(GPIO_AD_01)
+FORMAT_PIN(GPIO_AD_02)
+FORMAT_PIN(GPIO_AD_03)
+FORMAT_PIN(GPIO_AD_04)
+FORMAT_PIN(GPIO_AD_05)
+FORMAT_PIN(GPIO_AD_06)
+FORMAT_PIN(GPIO_AD_07)
+FORMAT_PIN(GPIO_AD_08)
+FORMAT_PIN(GPIO_AD_09)
+FORMAT_PIN(GPIO_AD_10)
+FORMAT_PIN(GPIO_AD_11)
+FORMAT_PIN(GPIO_AD_12)
+FORMAT_PIN(GPIO_AD_13)
+FORMAT_PIN(GPIO_AD_14)
+FORMAT_PIN(GPIO_AD_15)
+FORMAT_PIN(GPIO_AD_16)
+FORMAT_PIN(GPIO_AD_17)
+FORMAT_PIN(GPIO_AD_18)
+FORMAT_PIN(GPIO_AD_19)
+FORMAT_PIN(GPIO_AD_20)
+FORMAT_PIN(GPIO_AD_21)
+FORMAT_PIN(GPIO_AD_22)
+FORMAT_PIN(GPIO_AD_23)
+FORMAT_PIN(GPIO_AD_24)
+FORMAT_PIN(GPIO_AD_25)
+FORMAT_PIN(GPIO_AD_26)
+FORMAT_PIN(GPIO_AD_27)
+FORMAT_PIN(GPIO_AD_28)
+FORMAT_PIN(GPIO_AD_29)
+FORMAT_PIN(GPIO_AD_30)
+FORMAT_PIN(GPIO_AD_31)
+FORMAT_PIN(GPIO_AD_32)
+FORMAT_PIN(GPIO_AD_33)
+FORMAT_PIN(GPIO_AD_34)
+FORMAT_PIN(GPIO_AD_35)
+
+FORMAT_PIN(GPIO_SD_B1_00)
+FORMAT_PIN(GPIO_SD_B1_01)
+FORMAT_PIN(GPIO_SD_B1_02)
+FORMAT_PIN(GPIO_SD_B1_03)
+FORMAT_PIN(GPIO_SD_B1_04)
+FORMAT_PIN(GPIO_SD_B1_05)
+
+FORMAT_PIN(GPIO_SD_B2_00)
+FORMAT_PIN(GPIO_SD_B2_01)
+FORMAT_PIN(GPIO_SD_B2_02)
+FORMAT_PIN(GPIO_SD_B2_03)
+FORMAT_PIN(GPIO_SD_B2_04)
+FORMAT_PIN(GPIO_SD_B2_05)
+FORMAT_PIN(GPIO_SD_B2_06)
+FORMAT_PIN(GPIO_SD_B2_07)
+FORMAT_PIN(GPIO_SD_B2_08)
+FORMAT_PIN(GPIO_SD_B2_09)
+FORMAT_PIN(GPIO_SD_B2_10)
+FORMAT_PIN(GPIO_SD_B2_11)
+
+FORMAT_PIN(GPIO_DISP_B1_00)
+FORMAT_PIN(GPIO_DISP_B1_01)
+FORMAT_PIN(GPIO_DISP_B1_02)
+FORMAT_PIN(GPIO_DISP_B1_03)
+FORMAT_PIN(GPIO_DISP_B1_04)
+FORMAT_PIN(GPIO_DISP_B1_05)
+FORMAT_PIN(GPIO_DISP_B1_06)
+FORMAT_PIN(GPIO_DISP_B1_07)
+FORMAT_PIN(GPIO_DISP_B1_08)
+FORMAT_PIN(GPIO_DISP_B1_09)
+FORMAT_PIN(GPIO_DISP_B1_10)
+FORMAT_PIN(GPIO_DISP_B1_11)
+
+FORMAT_PIN(GPIO_DISP_B2_00)
+FORMAT_PIN(GPIO_DISP_B2_01)
+FORMAT_PIN(GPIO_DISP_B2_02)
+FORMAT_PIN(GPIO_DISP_B2_03)
+FORMAT_PIN(GPIO_DISP_B2_04)
+FORMAT_PIN(GPIO_DISP_B2_05)
+FORMAT_PIN(GPIO_DISP_B2_06)
+FORMAT_PIN(GPIO_DISP_B2_07)
+FORMAT_PIN(GPIO_DISP_B2_08)
+FORMAT_PIN(GPIO_DISP_B2_09)
+FORMAT_PIN(GPIO_DISP_B2_10)
+FORMAT_PIN(GPIO_DISP_B2_11)
+FORMAT_PIN(GPIO_DISP_B2_12)
+FORMAT_PIN(GPIO_DISP_B2_13)
+FORMAT_PIN(GPIO_DISP_B2_14)
+FORMAT_PIN(GPIO_DISP_B2_15)
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pins.c
new file mode 100644
index 0000000000..71562462e6
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pins.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "mimxrt10xx/pins.h"
+
+const mcu_pin_obj_t pin_GPIO_EMC_B1_00 = PIN(GPIO7, 0, GPIO_EMC_B1_00, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_01 = PIN(GPIO7, 1, GPIO_EMC_B1_01, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_02 = PIN(GPIO7, 2, GPIO_EMC_B1_02, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_03 = PIN(GPIO7, 3, GPIO_EMC_B1_03, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_04 = PIN(GPIO7, 4, GPIO_EMC_B1_04, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_05 = PIN(GPIO7, 5, GPIO_EMC_B1_05, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_06 = PIN(GPIO7, 6, GPIO_EMC_B1_06, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_07 = PIN(GPIO7, 7, GPIO_EMC_B1_07, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_08 = PIN(GPIO7, 8, GPIO_EMC_B1_08, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_09 = PIN(GPIO7, 9, GPIO_EMC_B1_09, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_10 = PIN(GPIO7, 10, GPIO_EMC_B1_10, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_11 = PIN(GPIO7, 11, GPIO_EMC_B1_11, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_12 = PIN(GPIO7, 12, GPIO_EMC_B1_12, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_13 = PIN(GPIO7, 13, GPIO_EMC_B1_13, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_14 = PIN(GPIO7, 14, GPIO_EMC_B1_14, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_15 = PIN(GPIO7, 15, GPIO_EMC_B1_15, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_16 = PIN(GPIO7, 16, GPIO_EMC_B1_16, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_17 = PIN(GPIO7, 17, GPIO_EMC_B1_17, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_18 = PIN(GPIO7, 18, GPIO_EMC_B1_18, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_19 = PIN(GPIO7, 19, GPIO_EMC_B1_19, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_20 = PIN(GPIO7, 20, GPIO_EMC_B1_20, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_21 = PIN(GPIO7, 21, GPIO_EMC_B1_21, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_22 = PIN(GPIO7, 22, GPIO_EMC_B1_22, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_23 = PIN(GPIO7, 23, GPIO_EMC_B1_23, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_24 = PIN(GPIO7, 24, GPIO_EMC_B1_24, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_25 = PIN(GPIO7, 25, GPIO_EMC_B1_25, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_26 = PIN(GPIO7, 26, GPIO_EMC_B1_26, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_27 = PIN(GPIO7, 27, GPIO_EMC_B1_27, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_28 = PIN(GPIO7, 28, GPIO_EMC_B1_28, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_29 = PIN(GPIO7, 29, GPIO_EMC_B1_29, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_30 = PIN(GPIO7, 30, GPIO_EMC_B1_30, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_31 = PIN(GPIO7, 31, GPIO_EMC_B1_31, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_32 = PIN(GPIO8, 0, GPIO_EMC_B1_32, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_33 = PIN(GPIO8, 1, GPIO_EMC_B1_33, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_34 = PIN(GPIO8, 2, GPIO_EMC_B1_34, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_35 = PIN(GPIO8, 3, GPIO_EMC_B1_35, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_36 = PIN(GPIO8, 4, GPIO_EMC_B1_36, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_37 = PIN(GPIO8, 5, GPIO_EMC_B1_37, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_38 = PIN(GPIO8, 6, GPIO_EMC_B1_38, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_39 = PIN(GPIO8, 7, GPIO_EMC_B1_39, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_40 = PIN(GPIO8, 8, GPIO_EMC_B1_40, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B1_41 = PIN(GPIO8, 9, GPIO_EMC_B1_41, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_00 = PIN(GPIO8, 10, GPIO_EMC_B2_00, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_01 = PIN(GPIO8, 11, GPIO_EMC_B2_01, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_02 = PIN(GPIO8, 12, GPIO_EMC_B2_02, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_03 = PIN(GPIO8, 13, GPIO_EMC_B2_03, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_04 = PIN(GPIO8, 14, GPIO_EMC_B2_04, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_05 = PIN(GPIO8, 15, GPIO_EMC_B2_05, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_06 = PIN(GPIO8, 16, GPIO_EMC_B2_06, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_07 = PIN(GPIO8, 17, GPIO_EMC_B2_07, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_08 = PIN(GPIO8, 18, GPIO_EMC_B2_08, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_09 = PIN(GPIO8, 19, GPIO_EMC_B2_09, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_10 = PIN(GPIO8, 20, GPIO_EMC_B2_10, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_11 = PIN(GPIO8, 21, GPIO_EMC_B2_11, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_12 = PIN(GPIO8, 22, GPIO_EMC_B2_12, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_13 = PIN(GPIO8, 23, GPIO_EMC_B2_13, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_14 = PIN(GPIO8, 24, GPIO_EMC_B2_14, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_15 = PIN(GPIO8, 25, GPIO_EMC_B2_15, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_16 = PIN(GPIO8, 26, GPIO_EMC_B2_16, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_17 = PIN(GPIO8, 27, GPIO_EMC_B2_17, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_18 = PIN(GPIO8, 28, GPIO_EMC_B2_18, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_19 = PIN(GPIO8, 29, GPIO_EMC_B2_19, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_EMC_B2_20 = PIN(GPIO8, 30, GPIO_EMC_B2_20, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_AD_00 = PIN(GPIO8, 31, GPIO_AD_00, NO_ADC, 0, 0x00000005, 0x0000000E);
+const mcu_pin_obj_t pin_GPIO_AD_01 = PIN(GPIO9, 0, GPIO_AD_01, NO_ADC, 0, 0x00000005, 0x0000000E);
+const mcu_pin_obj_t pin_GPIO_AD_02 = PIN(GPIO9, 1, GPIO_AD_02, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_03 = PIN(GPIO9, 2, GPIO_AD_03, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_04 = PIN(GPIO9, 3, GPIO_AD_04, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_05 = PIN(GPIO9, 4, GPIO_AD_05, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_06 = PIN(GPIO9, 5, GPIO_AD_06, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_07 = PIN(GPIO9, 6, GPIO_AD_07, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_08 = PIN(GPIO9, 7, GPIO_AD_08, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_09 = PIN(GPIO9, 8, GPIO_AD_09, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_10 = PIN(GPIO9, 9, GPIO_AD_10, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_11 = PIN(GPIO9, 10, GPIO_AD_11, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_12 = PIN(GPIO9, 11, GPIO_AD_12, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_13 = PIN(GPIO9, 12, GPIO_AD_13, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_14 = PIN(GPIO9, 13, GPIO_AD_14, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_15 = PIN(GPIO9, 14, GPIO_AD_15, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_16 = PIN(GPIO9, 15, GPIO_AD_16, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_17 = PIN(GPIO9, 16, GPIO_AD_17, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_18 = PIN(GPIO9, 17, GPIO_AD_18, NO_ADC, 0, 0x00000005, 0x0000000E);
+const mcu_pin_obj_t pin_GPIO_AD_19 = PIN(GPIO9, 18, GPIO_AD_19, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_20 = PIN(GPIO9, 19, GPIO_AD_20, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_21 = PIN(GPIO9, 20, GPIO_AD_21, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_22 = PIN(GPIO9, 21, GPIO_AD_22, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_23 = PIN(GPIO9, 22, GPIO_AD_23, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_24 = PIN(GPIO9, 23, GPIO_AD_24, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_25 = PIN(GPIO9, 24, GPIO_AD_25, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_26 = PIN(GPIO9, 25, GPIO_AD_26, NO_ADC, 0, 0x00000005, 0x0000000E);
+const mcu_pin_obj_t pin_GPIO_AD_27 = PIN(GPIO9, 26, GPIO_AD_27, NO_ADC, 0, 0x00000005, 0x0000000E);
+const mcu_pin_obj_t pin_GPIO_AD_28 = PIN(GPIO9, 27, GPIO_AD_28, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_29 = PIN(GPIO9, 28, GPIO_AD_29, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_30 = PIN(GPIO9, 29, GPIO_AD_30, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_31 = PIN(GPIO9, 30, GPIO_AD_31, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_32 = PIN(GPIO9, 31, GPIO_AD_32, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_33 = PIN(GPIO10, 0, GPIO_AD_33, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_34 = PIN(GPIO10, 1, GPIO_AD_34, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_AD_35 = PIN(GPIO10, 2, GPIO_AD_35, NO_ADC, 0, 0x00000005, 0x0000000E);
+const mcu_pin_obj_t pin_GPIO_SD_B1_00 = PIN(GPIO10, 3, GPIO_SD_B1_00, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_SD_B1_01 = PIN(GPIO10, 4, GPIO_SD_B1_01, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B1_02 = PIN(GPIO10, 5, GPIO_SD_B1_02, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_SD_B1_03 = PIN(GPIO10, 6, GPIO_SD_B1_03, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_SD_B1_04 = PIN(GPIO10, 7, GPIO_SD_B1_04, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_SD_B1_05 = PIN(GPIO10, 8, GPIO_SD_B1_05, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_00 = PIN(GPIO10, 9, GPIO_SD_B2_00, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_01 = PIN(GPIO10, 10, GPIO_SD_B2_01, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_02 = PIN(GPIO10, 11, GPIO_SD_B2_02, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_03 = PIN(GPIO10, 12, GPIO_SD_B2_03, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_04 = PIN(GPIO10, 13, GPIO_SD_B2_04, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_SD_B2_05 = PIN(GPIO10, 14, GPIO_SD_B2_05, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_SD_B2_06 = PIN(GPIO10, 15, GPIO_SD_B2_06, NO_ADC, 0, 0x00000005, 0x00000004);
+const mcu_pin_obj_t pin_GPIO_SD_B2_07 = PIN(GPIO10, 16, GPIO_SD_B2_07, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_08 = PIN(GPIO10, 17, GPIO_SD_B2_08, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_09 = PIN(GPIO10, 18, GPIO_SD_B2_09, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_10 = PIN(GPIO10, 19, GPIO_SD_B2_10, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_SD_B2_11 = PIN(GPIO10, 20, GPIO_SD_B2_11, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_00 = PIN(GPIO10, 21, GPIO_DISP_B1_00, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_01 = PIN(GPIO10, 22, GPIO_DISP_B1_01, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_02 = PIN(GPIO10, 23, GPIO_DISP_B1_02, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_03 = PIN(GPIO10, 24, GPIO_DISP_B1_03, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_04 = PIN(GPIO10, 25, GPIO_DISP_B1_04, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_05 = PIN(GPIO10, 26, GPIO_DISP_B1_05, NO_ADC, 0, 0x00000005, 0x00000008);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_06 = PIN(GPIO10, 27, GPIO_DISP_B1_06, NO_ADC, 0, 0x00000005, 0x0000000C);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_07 = PIN(GPIO10, 28, GPIO_DISP_B1_07, NO_ADC, 0, 0x00000005, 0x0000000C);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_08 = PIN(GPIO10, 29, GPIO_DISP_B1_08, NO_ADC, 0, 0x00000005, 0x0000000C);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_09 = PIN(GPIO10, 30, GPIO_DISP_B1_09, NO_ADC, 0, 0x00000005, 0x0000000C);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_10 = PIN(GPIO10, 31, GPIO_DISP_B1_10, NO_ADC, 0, 0x00000005, 0x0000000C);
+const mcu_pin_obj_t pin_GPIO_DISP_B1_11 = PIN(GPIO11, 0, GPIO_DISP_B1_11, NO_ADC, 0, 0x00000005, 0x0000000C);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_00 = PIN(GPIO11, 1, GPIO_DISP_B2_00, NO_ADC, 0, 0x00000005, 0x00000002);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_01 = PIN(GPIO11, 2, GPIO_DISP_B2_01, NO_ADC, 0, 0x00000005, 0x00000002);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_02 = PIN(GPIO11, 3, GPIO_DISP_B2_02, NO_ADC, 0, 0x00000005, 0x00000002);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_03 = PIN(GPIO11, 4, GPIO_DISP_B2_03, NO_ADC, 0, 0x00000005, 0x00000002);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_04 = PIN(GPIO11, 5, GPIO_DISP_B2_04, NO_ADC, 0, 0x00000005, 0x00000002);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_05 = PIN(GPIO11, 6, GPIO_DISP_B2_05, NO_ADC, 0, 0x00000005, 0x00000002);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_06 = PIN(GPIO11, 7, GPIO_DISP_B2_06, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_07 = PIN(GPIO11, 8, GPIO_DISP_B2_07, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_08 = PIN(GPIO11, 9, GPIO_DISP_B2_08, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_09 = PIN(GPIO11, 10, GPIO_DISP_B2_09, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_10 = PIN(GPIO11, 11, GPIO_DISP_B2_10, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_11 = PIN(GPIO11, 12, GPIO_DISP_B2_11, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_12 = PIN(GPIO11, 13, GPIO_DISP_B2_12, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_13 = PIN(GPIO11, 14, GPIO_DISP_B2_13, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_14 = PIN(GPIO11, 15, GPIO_DISP_B2_14, NO_ADC, 0, 0x00000005, 0x00000006);
+const mcu_pin_obj_t pin_GPIO_DISP_B2_15 = PIN(GPIO11, 16, GPIO_DISP_B2_15, NO_ADC, 0, 0x00000005, 0x0000000E);
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pins.h
new file mode 100644
index 0000000000..0d99219c8a
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1176/pins.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+
+#define FORMAT_PIN(pin_name) extern const mcu_pin_obj_t pin_##pin_name;
+#include "pin_names.h"
+#undef FORMAT_PIN
+
+#define PIN_COUNT (IOMUXC_SW_PAD_CTL_PAD_COUNT + 0)
+extern const mcu_pin_obj_t mcu_pin_list[PIN_COUNT];
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h
index 8184d5b135..ffbd72339e 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h
@@ -78,10 +78,18 @@ extern LPUART_Type *const mcu_uart_banks[];
 
 #ifdef MIMXRT1011_SERIES
 #include "MIMXRT1011/periph.h"
+#elif defined(MIMXRT1015_SERIES)
+#include "MIMXRT1015/periph.h"
 #elif defined(MIMXRT1021_SERIES)
 #include "MIMXRT1021/periph.h"
+#elif defined(MIMXRT1042_SERIES)
+#include "MIMXRT1042/periph.h"
+#elif defined(MIMXRT1052_SERIES)
+#include "MIMXRT1052/periph.h"
 #elif defined(MIMXRT1062_SERIES)
 #include "MIMXRT1062/periph.h"
+#elif defined(MIMXRT1176_cm7_SERIES)
+#include "MIMXRT1176/periph.h"
 #endif
 
 #endif // MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_PERIPH_H
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/pin_names.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/pin_names.h
new file mode 100644
index 0000000000..37db5c2261
--- /dev/null
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/pin_names.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// OK to include more than once because FORMAT_PIN may be different.
+
+#ifdef MIMXRT1011_SERIES
+#include "MIMXRT1011/pin_names.h"
+#elif defined(MIMXRT1021_SERIES)
+#include "MIMXRT1021/pin_names.h"
+#elif defined(MIMXRT1042_SERIES)
+#include "MIMXRT1042/pin_names.h"
+#elif defined(MIMXRT1052_SERIES)
+#include "MIMXRT1052/pin_names.h"
+#elif defined(MIMXRT1062_SERIES)
+#include "MIMXRT1062/pin_names.h"
+#elif defined(MIMXRT1176_cm7_SERIES)
+#include "MIMXRT1176/pin_names.h"
+#endif
diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h
index 0457a09a1a..8ffc17ba07 100644
--- a/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h
+++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h
@@ -78,10 +78,18 @@ void enable_pin_change_interrupt(const mcu_pin_obj_t *pin, gpio_change_interrupt
 
 #ifdef MIMXRT1011_SERIES
 #include "MIMXRT1011/pins.h"
+#elif defined(MIMXRT1015_SERIES)
+#include "MIMXRT1015/pins.h"
 #elif defined(MIMXRT1021_SERIES)
 #include "MIMXRT1021/pins.h"
+#elif defined(MIMXRT1042_SERIES)
+#include "MIMXRT1042/pins.h"
+#elif defined(MIMXRT1052_SERIES)
+#include "MIMXRT1052/pins.h"
 #elif defined(MIMXRT1062_SERIES)
 #include "MIMXRT1062/pins.h"
+#elif defined(MIMXRT1176_cm7_SERIES)
+#include "MIMXRT1176/pins.h"
 #endif
 
 #endif // MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_PINS_H
diff --git a/ports/mimxrt10xx/sdk b/ports/mimxrt10xx/sdk
index 2b9354539e..9990f264f9 160000
--- a/ports/mimxrt10xx/sdk
+++ b/ports/mimxrt10xx/sdk
@@ -1 +1 @@
-Subproject commit 2b9354539e6e4f722749e87b0bdc22966dc080d9
+Subproject commit 9990f264f98430f6d885041ab0f24224d68f4958
diff --git a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c
index e32eaf8832..3ccd67096a 100644
--- a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c
+++ b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c
@@ -137,7 +137,7 @@ status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type * base, uint
     status = flexspi_nor_wait_bus_busy(base);
 
     /* Do software reset. */
-    #if defined(FSL_FEATURE_SOC_OTFAD_COUNT)
+    #if defined(FSL_FEATURE_SOC_OTFAD_COUNT) && FSL_FEATURE_SOC_OTFAD_COUNT == 1
     base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK;
     base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK);
     #else
diff --git a/ports/mimxrt10xx/supervisor/internal_flash.c b/ports/mimxrt10xx/supervisor/internal_flash.c
index bacb62854a..cd4dd33ba0 100644
--- a/ports/mimxrt10xx/supervisor/internal_flash.c
+++ b/ports/mimxrt10xx/supervisor/internal_flash.c
@@ -52,6 +52,11 @@ extern uint32_t __fatfs_flash_length[];
 uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4)));
 uint32_t _flash_page_addr = NO_CACHE;
 
+#ifndef FLEXSPI
+#define FLEXSPI FLEXSPI1
+#define FlexSPI_AMBA_BASE FlexSPI1_AMBA_BASE
+#endif
+
 void PLACE_IN_ITCM(supervisor_flash_init)(void) {
     // Update the LUT to make sure all entries are available. Copy the values to
     // memory first so that we don't read from the flash as we update the LUT.
@@ -62,6 +67,41 @@ void PLACE_IN_ITCM(supervisor_flash_init)(void) {
     __DSB();
     __ISB();
     flexspi_nor_init();
+
+    #if IMXRT10XX
+    // Disable interrupts of priority 8+. They likely use code in flash
+    // itself. Higher priority interrupts (<8) should ensure all of their
+    // code is in RAM.
+    __set_BASEPRI(8 << (8 - __NVIC_PRIO_BITS));
+
+    // Increase clock speed to 120 MHz
+    // Wait for bus idle before change flash configuration.
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+    FLEXSPI_Enable(FLEXSPI, false);
+
+    // Disable FlexSPI clock
+    CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
+
+    // Changing the clock is OK now.
+
+    // The PFD is 480 * 18 / PFD0_FRAC. We do / 18 which outputs 480 MHz.
+    CCM_ANALOG->PFD_480 = (CCM_ANALOG->PFD_480 & ~CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) | CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(18);
+
+    // This divides down the 480 Mhz by PODF + 1. So 480 / (3 + 1) = 120 MHz.
+    CCM->CSCMR1 = (CCM->CSCMR1 & ~CCM_CSCMR1_FLEXSPI_PODF_MASK) | CCM_CSCMR1_FLEXSPI_PODF(3);
+
+    // Re-enable FlexSPI
+    CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
+
+    FLEXSPI_Enable(FLEXSPI, true);
+
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+    __set_BASEPRI(0U);
+    #endif
 }
 
 static inline uint32_t lba2addr(uint32_t block) {
diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c
index feb8566aad..997a97ba49 100644
--- a/ports/mimxrt10xx/supervisor/port.c
+++ b/ports/mimxrt10xx/supervisor/port.c
@@ -89,11 +89,13 @@ extern uint32_t _ld_stack_top;
 
 extern uint32_t __isr_vector[];
 
+extern uint32_t _ld_ocram_start;
 extern uint32_t _ld_ocram_bss_start;
 extern uint32_t _ld_ocram_bss_size;
 extern uint32_t _ld_ocram_data_destination;
 extern uint32_t _ld_ocram_data_size;
 extern uint32_t _ld_ocram_data_flash_copy;
+extern uint32_t _ld_ocram_end;
 extern uint32_t _ld_dtcm_bss_start;
 extern uint32_t _ld_dtcm_bss_size;
 extern uint32_t _ld_dtcm_data_destination;
@@ -106,36 +108,6 @@ extern uint32_t _ld_isr_destination;
 extern uint32_t _ld_isr_size;
 extern uint32_t _ld_isr_flash_copy;
 
-// Remove these once the SDK re-includes them.
-// https://github.com/nxp-mcuxpresso/mcux-sdk/issues/110
-/*! @name GPR14 - GPR14 General Purpose Register */
-/*! @{ */
-#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK      (0xF0000U)
-#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT     (16U)
-/*! CM7_CFGITCMSZ
- *  0b0000..0 KB (No ITCM)
- *  0b0011..4 KB
- *  0b0100..8 KB
- *  0b0101..16 KB
- *  0b0110..32 KB
- *  0b0111..64 KB
- *  0b1000..128 KB
- */
-#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
-#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK      (0xF00000U)
-#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT     (20U)
-/*! CM7_CFGDTCMSZ
- *  0b0000..0 KB (No DTCM)
- *  0b0011..4 KB
- *  0b0100..8 KB
- *  0b0101..16 KB
- *  0b0110..32 KB
- *  0b0111..64 KB
- *  0b1000..128 KB
- */
-#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
-/*! @} */
-
 extern void main(void);
 
 // This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c.
@@ -159,18 +131,27 @@ __attribute__((used, naked, no_instrument_function, optimize("no-tree-loop-distr
     // then the return will jump to an invalid address.
     // Configure FlexRAM. The e is one block of ITCM (0b11) and DTCM (0b10). The rest is two OCRAM
     // (0b01). We shift in zeroes for all unimplemented banks.
-    IOMUXC_GPR->GPR17 = (0xe5555555) >> (32 - 2 * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
+    uint32_t flexram_config = (0xe5555555) >> (32 - 2 * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
+    // imxrt1176 splits the config across two registers.
+    #ifdef IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK
+    IOMUXC_GPR->GPR17 = flexram_config & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK;
+    IOMUXC_GPR->GPR18 = (flexram_config >> 16) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK;
+    #else
+    IOMUXC_GPR->GPR17 = flexram_config;
+    #endif
 
     // Switch from FlexRAM fuse config to the IOMUXC values.
     IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(1);
 
     // Let the core know the TCM sizes changed.
+    #ifdef IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK
     uint32_t current_gpr14 = IOMUXC_GPR->GPR14;
     current_gpr14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK;
     current_gpr14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(0x6);
     current_gpr14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK;
     current_gpr14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(0x6);
     IOMUXC_GPR->GPR14 = current_gpr14;
+    #endif
 
     // Enable FlexRAM interrupts on invalid access.
     FLEXRAM->INT_STAT_EN = FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(1) |
@@ -182,6 +163,7 @@ __attribute__((used, naked, no_instrument_function, optimize("no-tree-loop-distr
     #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
 
     /* Disable Watchdog Power Down Counter */
+    #if defined(RTWDOG)
     WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
     WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
 
@@ -191,6 +173,32 @@ __attribute__((used, naked, no_instrument_function, optimize("no-tree-loop-distr
     RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
     RTWDOG->TOVAL = 0xFFFF;
     RTWDOG->CS = (uint32_t)((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
+    #endif
+
+    #if defined(RTWDOG3)
+    if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U) {
+        WDOG1->WCR &= ~(uint16_t)WDOG_WCR_WDE_MASK;
+    }
+    if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U) {
+        WDOG2->WCR &= ~(uint16_t)WDOG_WCR_WDE_MASK;
+    }
+    if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) {
+        RTWDOG3->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
+    } else {
+        RTWDOG3->CNT = 0xC520U;
+        RTWDOG3->CNT = 0xD928U;
+    }
+    RTWDOG3->TOVAL = 0xFFFF;
+    RTWDOG3->CS = (uint32_t)((RTWDOG3->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
+    if ((RTWDOG4->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) {
+        RTWDOG4->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
+    } else {
+        RTWDOG4->CNT = 0xC520U;
+        RTWDOG4->CNT = 0xD928U;
+    }
+    RTWDOG4->TOVAL = 0xFFFF;
+    RTWDOG4->CS = (uint32_t)((RTWDOG4->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
+    #endif
 
     /* Disable Systick which might be enabled by bootrom */
     if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) {
@@ -227,6 +235,9 @@ __attribute__((used, naked, no_instrument_function, optimize("no-tree-loop-distr
     // FlexSPI2 is 0x70000000
 
     // This the first portion (1MB, 2MB or 4MB) of flash is the bootloader and CircuitPython read-only data.
+    #if !defined(FlexSPI_AMBA_BASE)
+    #define FlexSPI_AMBA_BASE FlexSPI1_AMBA_BASE
+    #endif
     MPU->RBAR = ARM_MPU_RBAR(10, FlexSPI_AMBA_BASE);
     uint32_t region_size = ARM_MPU_REGION_SIZE_32B;
     uint32_t code_size = ((uint32_t)&_ld_filesystem_start) - FlexSPI_AMBA_BASE;
@@ -265,13 +276,18 @@ __attribute__((used, naked, no_instrument_function, optimize("no-tree-loop-distr
     // This is OCRAM. We mark it as shareable so that it isn't cached. This makes USB work at the
     // cost of 1/4 speed OCRAM accesses. It will leave more room for caching data from the flash
     // too which might be a net win.
-    MPU->RBAR = ARM_MPU_RBAR(14, 0x20200000U);
+    MPU->RBAR = ARM_MPU_RBAR(14, ((uint32_t)&_ld_ocram_start));
     MPU->RASR = ARM_MPU_RASR(NO_EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB);
 
+    #if IMXRT10XX
     // We steal 64k from FlexRAM for ITCM and DTCM so disable those memory regions here.
     // We use 64k from FlexRAM for ITCM and DTCM so disable those memory regions here.
-    MPU->RBAR = ARM_MPU_RBAR(15, 0x20280000U);
+    MPU->RBAR = ARM_MPU_RBAR(15, ((uint32_t)&_ld_ocram_end));
     MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, 0x80, ARM_MPU_REGION_SIZE_512KB);
+    #else
+    // On the iMX RT 11xx OCRAM is not flexram (for now). So no need to mask it off.
+    #endif
+
 
     /* Enable MPU */
     ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
@@ -330,7 +346,9 @@ void __attribute__((no_instrument_function,section(".itcm.profile_exit"),long_ca
 }
 
 safe_mode_t port_init(void) {
+    #if IMXRT10XX
     CLOCK_SetMode(kCLOCK_ModeRun);
+    #endif
 
     clocks_init();
 
@@ -380,6 +398,9 @@ safe_mode_t port_init(void) {
     for (uint16_t i = 0; i < NUMBER_OF_INT_VECTORS; i++) {
         NVIC_SetPriority(i, (1UL << __NVIC_PRIO_BITS) - 1UL);
     }
+    #ifdef MIMXRT1042_SERIES
+    #define USB_OTG1_IRQn USB_OTG_IRQn
+    #endif
     NVIC_SetPriority(USB_OTG1_IRQn, 1);
     #ifdef USBPHY2
     NVIC_SetPriority(USB_OTG2_IRQn, 1);
@@ -398,7 +419,21 @@ safe_mode_t port_init(void) {
 
     // Always enable the SNVS interrupt. The GPC won't wake us up unless at least one interrupt is
     // enabled. It won't occur very often so it'll be low overhead.
+    #if IMXRT11XX
+    NVIC_EnableIRQ(SNVS_HP_NON_TZ_IRQn);
+    #else
     NVIC_EnableIRQ(SNVS_HP_WRAPPER_IRQn);
+    #endif
+
+    #if IMXRT11XX
+    /* Save SRSR to another register so we can read it later. */
+    SRC->GPR[11] = SRC->SRSR;
+    SRC->SRSR = 0xFFFFFFFFU;
+
+    if ((SRC->GPR[11] & SRC_SRSR_M7_LOCKUP_M7_MASK) != 0) {
+        return SAFE_MODE_HARD_FAULT;
+    }
+    #endif
 
     // Note that `reset_port` CANNOT GO HERE, unlike other ports, because `board_init` hasn't been
     // run yet, which uses `never_reset` to protect critical pins from being reset by  `reset_port`.
@@ -411,7 +446,9 @@ safe_mode_t port_init(void) {
 }
 
 void reset_port(void) {
+    #if CIRCUITPY_BUSIO
     spi_reset();
+    #endif
 
     #if CIRCUITPY_AUDIOIO
     audio_dma_reset();
@@ -497,9 +534,15 @@ uint64_t port_get_raw_ticks(uint8_t *subticks) {
     return ticks / 32;
 }
 
+#if IMXRT10XX
 void SNVS_HP_WRAPPER_IRQHandler(void);
 __attribute__((used))
 void PLACE_IN_ITCM(SNVS_HP_WRAPPER_IRQHandler)(void) {
+#else
+void SNVS_HP_NON_TZ_IRQHandler(void);
+__attribute__((used))
+void PLACE_IN_ITCM(SNVS_HP_NON_TZ_IRQHandler)(void) {
+    #endif
     if ((SNVS->HPSR & SNVS_HPSR_PI_MASK) != 0) {
         supervisor_tick();
         SNVS->HPSR = SNVS_HPSR_PI_MASK;
@@ -552,7 +595,11 @@ void port_idle_until_interrupt(void) {
 
     common_hal_mcu_disable_interrupts();
     if (!background_callback_pending()) {
+        #if IMXRT11XX
+        NVIC_ClearPendingIRQ(SNVS_HP_NON_TZ_IRQn);
+        #else
         NVIC_ClearPendingIRQ(SNVS_HP_WRAPPER_IRQn);
+        #endif
         __WFI();
     }
     common_hal_mcu_enable_interrupts();
diff --git a/ports/mimxrt10xx/supervisor/usb.c b/ports/mimxrt10xx/supervisor/usb.c
index bc6bc5f0cd..64a2639c16 100644
--- a/ports/mimxrt10xx/supervisor/usb.c
+++ b/ports/mimxrt10xx/supervisor/usb.c
@@ -79,8 +79,13 @@ STATIC void init_usb_instance(mp_int_t instance) {
 
 // Provide the prototypes for the interrupt handlers. The iMX RT SDK doesn't.
 // The SDK only links to them from assembly.
+    #ifdef MIMXRT1042_SERIES
+    void USB_OTG_IRQHandler(void);
+    void PLACE_IN_ITCM(USB_OTG_IRQHandler)(void) {
+    #else
     void USB_OTG1_IRQHandler(void);
     void PLACE_IN_ITCM(USB_OTG1_IRQHandler)(void) {
+        #endif
         usb_irq_handler(0);
     }
 
diff --git a/ports/mimxrt10xx/tools/gen_peripherals_data.py b/ports/mimxrt10xx/tools/gen_peripherals_data.py
new file mode 100644
index 0000000000..0b4f215279
--- /dev/null
+++ b/ports/mimxrt10xx/tools/gen_peripherals_data.py
@@ -0,0 +1,356 @@
+import sys
+import pathlib
+import xml.etree.ElementTree as ET
+
+SIGNALS = {
+    "LPI2C": ["SDA", "SCL"],
+    "LPSPI": ["SCK", "SDO", "SDI"],
+    "LPUART": ["RX", "TX", "RTS", "CTS"],
+    "I2S": ["RX_DATA0", "RX_SYNC", "TX_BCLK", "TX_DATA0", "TX_SYNC"],
+    "MQS": ["LEFT", "RIGHT"],
+}
+
+SIGNAL_RENAME = {
+    "CTS_B": "CTS",
+    "RTS_B": "RTS",
+    "RXD": "RX",
+    "TXD": "TX",
+    "TX_DATA00": "TX_DATA0",
+    "RX_DATA00": "RX_DATA0",
+    "TX_DATA": "TX_DATA0",
+    "RX_DATA": "RX_DATA0",
+}
+
+SKIP_LPSR = True
+
+svd_folder = pathlib.Path(sys.argv[1])
+
+# Download and extract config tools data from https://mcuxpresso.nxp.com/en/select_config_tools_data
+config_data_folder = pathlib.Path(sys.argv[2])
+devices = sys.argv[3:]
+
+peripherals_dir = pathlib.Path("peripherals/mimxrt10xx")
+
+copyright = """/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Lucian Copeland for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+"""
+
+for device in devices:
+    print(device)
+    svd_fn = svd_folder / device / (device + ".xml")
+    if not svd_fn.exists():
+        svd_fn = svd_folder / device / (device + "_cm7.xml")
+
+    pin_to_analog = {}
+    out_dir = peripherals_dir / device
+    largest_signals = None
+    for signal_file in config_data_folder.glob(
+        f"{device}*ConfigTools_data*/**/signal_configuration.xml"
+    ):
+        if largest_signals is None or signal_file.stat().st_size > largest_signals.stat().st_size:
+            largest_signals = signal_file
+
+    # Use the signal file to find analog connections
+    signal_tree = ET.parse(largest_signals)
+    signal_root = signal_tree.getroot()
+    for connection in signal_root.iter("connections"):
+        if "name_part" not in connection.attrib or not connection.attrib["name_part"].startswith(
+            "ADC"
+        ):
+            continue
+        name_part = connection.attrib["name_part"]
+        try:
+            assign = next(connection.iter("assign"))
+        except StopIteration:
+            continue
+        split_pin = assign.attrib["register"].split("_")
+        pin_name = "_".join(split_pin[split_pin.index("GPIO") :])
+        adc_instance, adc_channel = name_part.split("_")
+
+        try:
+            adc_channel = int(adc_channel[2:])
+        except ValueError:
+            continue
+        pin_to_analog[pin_name] = (adc_instance, adc_channel)
+
+    # Find USB pins
+    usb_pins = []
+    all_pins = set()
+    for pin in signal_root.iter("pin"):
+        pin_name = pin.get("name")
+        if SKIP_LPSR and "LPSR" in pin_name:
+            continue
+        all_pins.add(pin_name)
+        if not pin_name.startswith("USB_OTG"):
+            continue
+        if not pin_name.endswith(("DN", "DP")):
+            continue
+        usb_pins.append(pin_name)
+
+    # Find peripherals
+    all_peripherals = {}
+    for peripheral in signal_root.iter("peripheral"):
+        ptype = peripheral.get("peripheral_type")
+        if ptype not in all_peripherals:
+            all_peripherals[ptype] = []
+        all_peripherals[ptype].append(peripheral.get("id"))
+
+    print(svd_fn)
+    tree = ET.parse(svd_fn)
+    root = tree.getroot()
+    pin_number = 0
+    last_gpio_base = None
+    mux_register_base = None
+
+    pins_h = [
+        copyright,
+        "#pragma once",
+        "",
+        "#define FORMAT_PIN(pin_name) extern const mcu_pin_obj_t pin_##pin_name;",
+        '#include "pin_names.h"',
+        "#undef FORMAT_PIN",
+    ]
+    pins_c = [
+        copyright,
+        '#include "py/obj.h"',
+        '#include "py/mphal.h"',
+        '#include "mimxrt10xx/pins.h"',
+        "",
+    ]
+    pin_names_h = [copyright, "", "// define FORMAT_PIN(pin_name) and then include this file."]
+    mux_registers_by_pin = {}
+    peripheral_inputs = {}
+    pwm_outputs = []
+    for register in root.iter("register"):
+        name = register.find("name").text
+        if name.endswith("SELECT_INPUT"):
+            name_split = name.split("_")
+            instance = name_split[0]
+            signal = "_".join(name_split[1:-2])
+            signal = SIGNAL_RENAME.get(signal, signal)
+            if instance not in peripheral_inputs:
+                peripheral_inputs[instance] = {}
+            if signal not in peripheral_inputs[instance]:
+                peripheral_inputs[instance][signal] = {}
+            for evalue in register.iter("enumeratedValue"):
+                ename = evalue.find("name").text.strip("_")
+                if "_ALT" in ename:
+                    pin_name, alt = ename.rsplit("_", maxsplit=1)
+                else:
+                    pin_name = ename
+                    alt = evalue.find("description").text.rsplit(maxsplit=1)[1]
+                if SKIP_LPSR and "LPSR" in pin_name:
+                    continue
+                alt = int(alt[3:])
+                value = int(evalue.find("value").text, 0)
+                peripheral_inputs[instance][signal][pin_name] = [alt, name, value]
+        # Mux registers come before PAD registers.
+        elif name.startswith("SW_MUX_CTL_PAD_GPIO"):
+            address_offset = int(register.find("addressOffset").text, 16)
+            if mux_register_base is None:
+                mux_register_base = address_offset
+
+            split_pin = name.split("_")
+            pin_name = "_".join(split_pin[4:])
+            if pin_name not in all_pins:
+                continue
+            gpio_base = "_".join(split_pin[4:-1])
+
+            mux_registers_by_pin[pin_name] = register
+
+            if last_gpio_base != gpio_base:
+                pin_names_h.append("")
+            last_gpio_base = gpio_base
+
+            pin_number += 1
+
+            pin_names_h.append(f"FORMAT_PIN({pin_name})")
+        elif name.startswith("SW_PAD_CTL_PAD_GPIO"):
+            split_pin = name.split("_")
+            pin_name = "_".join(split_pin[4:])
+            if pin_name not in all_pins:
+                continue
+            mux_register = mux_registers_by_pin[pin_name]
+            mux_reset = int(mux_register.find("resetValue").text, 16)
+
+            pad_reset = int(register.find("resetValue").text, 16)
+
+            # Look through alt modes to find GPIO.
+            mux_field = mux_register.find("fields").find("field")
+            assert mux_field.find("name").text == "MUX_MODE"
+            for alt in mux_field.iter("enumeratedValue"):
+                desc = alt.find("description").text
+                if "FLEXPWM" in desc:
+                    desc_split = desc.split()
+                    alt = desc_split[3]
+                    connection = desc_split[6]
+                    pwm_instance = int(connection[7:8])
+                    if connection.count("_") == 1:
+                        # Form: FLEXPWM#_PWMC##
+                        channel = connection[-3:-2]
+                        module = int(connection[-2:])
+                    else:  # two _
+                        # Form: FLEXPWM#_PWM#_C
+                        channel = connection[-1:]
+                        module = int(connection[-3:-2])
+                    pwm_outputs.append((pwm_instance, module, channel, connection, pin_name))
+                elif "GPIO" in desc:
+                    alt_name = desc.split()[-4]
+                    # The 117x has a GPIO mux between GPIOn and CM7_GPIOn. For now,
+                    # we use the the slow, default GPIOn.
+                    if alt_name.startswith("GPIO_MUX"):
+                        alt_name = alt_name.replace("GPIO_MUX", "GPIO")
+                    gpio_instance, gpio_number = alt_name.split("_")
+                    if gpio_instance == "GPIOMUX":
+                        gpio_instance = "GPIO1"
+                    gpio_number = int(gpio_number[2:])
+                else:
+                    desc_split = desc.split()
+                    alt = desc_split[3]
+                    connection = desc_split[6]
+                    alt = int(alt[3:])
+                    if "_" not in connection:
+                        print("skipping", pin_name, connection)
+                        continue
+                    instance, signal = connection.split("_", maxsplit=1)
+                    signal = SIGNAL_RENAME.get(signal, signal)
+                    if instance not in peripheral_inputs:
+                        peripheral_inputs[instance] = {}
+                    if signal not in peripheral_inputs[instance]:
+                        peripheral_inputs[instance][signal] = {}
+                    peripheral_inputs[instance][signal][pin_name] = [alt, None, 0]
+
+            if pin_name in pin_to_analog:
+                adc_instance, adc_channel = pin_to_analog[pin_name]
+            else:
+                adc_instance = "NO_ADC"
+                adc_channel = 0
+
+            pins_c.append(
+                f"const mcu_pin_obj_t pin_{pin_name} = PIN({gpio_instance}, {gpio_number}, {pin_name}, {adc_instance}, {adc_channel}, 0x{mux_reset:08X}, 0x{pad_reset:08X});"
+            )
+
+    pins_c.append("")
+
+    for pin_name in sorted(usb_pins):
+        pin_names_h.append(f"FORMAT_PIN({pin_name})")
+        pins_c.append(f"const mcu_pin_obj_t pin_{pin_name} = {{ {{ &mcu_pin_type }}, }};")
+
+    pin_names_h.append("")
+    pins_c.append("")
+
+    pins_h.append("")
+    pins_h.append(f"#define PIN_COUNT (IOMUXC_SW_PAD_CTL_PAD_COUNT + {len(usb_pins)})")
+    pins_h.append(f"extern const mcu_pin_obj_t mcu_pin_list[PIN_COUNT];")
+    pins_h.append("")
+
+    out_dir.mkdir(exist_ok=True)
+
+    (out_dir / "pin_names.h").write_text("\n".join(pin_names_h))
+    (out_dir / "pins.h").write_text("\n".join(pins_h))
+    (out_dir / "pins.c").write_text("\n".join(pins_c))
+
+    periph_h = [copyright, "#pragma once"]
+    periph_c = [
+        copyright,
+        '#include "py/obj.h"',
+        '#include "py/mphal.h"',
+        '#include "mimxrt10xx/periph.h"',
+        "",
+    ]
+
+    for ptype in SIGNALS:
+        instances = all_peripherals[ptype]
+        short_name = ptype.lower()
+        if short_name.startswith("lp"):
+            short_name = short_name[2:]
+        # Only one MQS exists and it is related to SAI3
+        if ptype != "MQS":
+            periph_h.append(
+                f"extern {ptype}_Type *const mcu_{short_name}_banks[{len(instances)}];"
+            )
+            joined_instances = ", ".join(instances)
+            periph_c.append(
+                f"{ptype}_Type *const mcu_{short_name}_banks[{len(instances)}] = {{ {joined_instances} }};"
+            )
+            periph_c.append("")
+        for signal in SIGNALS[ptype]:
+            pin_count = 0
+            for instance in instances:
+                if instance not in peripheral_inputs or signal not in peripheral_inputs[instance]:
+                    continue
+                pin_count += len(peripheral_inputs[instance][signal])
+            periph_h.append(
+                f"extern const mcu_periph_obj_t mcu_{short_name}_{signal.lower()}_list[{pin_count}];"
+            )
+            periph_c.append(
+                f"const mcu_periph_obj_t mcu_{short_name}_{signal.lower()}_list[{pin_count}] = {{"
+            )
+            for instance in instances:
+                if instance not in peripheral_inputs or signal not in peripheral_inputs[instance]:
+                    continue
+                # MQS is tied to SAI3
+                if instance == "MQS":
+                    instance_number = 3
+                else:
+                    instance_number = int(instance[len(ptype) :])
+                    if instance_number > 1:
+                        periph_c.append("")
+                pins = peripheral_inputs[instance][signal]
+                pin_names = list(pins.keys())
+                pin_names.sort(key=lambda x: pins[x][-1])
+                for pin_name in pin_names:
+                    alt, select_input, input_value = pins[pin_name]
+                    if select_input:
+                        select_input = f"kIOMUXC_{select_input}"
+                    else:
+                        select_input = "0"
+                    periph_c.append(
+                        f"    PERIPH_PIN({instance_number}, {alt}, {select_input}, {input_value}, &pin_{pin_name}),"
+                    )
+            periph_c.append(f"}};")
+            periph_c.append(f"")
+        periph_h.append("")
+
+    pwm_outputs.sort(key=lambda x: x[:3])
+    periph_c.append(f"const mcu_pwm_obj_t mcu_pwm_list[{len(pwm_outputs)}] = {{")
+    periph_h.append(f"extern const mcu_pwm_obj_t mcu_pwm_list[{len(pwm_outputs)}];")
+    last_channel = None
+    for pwm_instance, module, channel, connection, pin_name in pwm_outputs:
+        this_channel = (pwm_instance, module, channel)
+        if last_channel is not None and last_channel != this_channel:
+            periph_c.append("")
+        last_channel = this_channel
+        periph_c.append(
+            f"    PWM_PIN(PWM{pwm_instance}, kPWM_Module_{module}, kPWM_Pwm{channel}, IOMUXC_{pin_name}_{connection}, &pin_{pin_name}),"
+        )
+    periph_c.append(f"}};")
+    periph_c.append("")
+
+    (out_dir / "periph.h").write_text("\n".join(periph_h))
+    (out_dir / "periph.c").write_text("\n".join(periph_c))
diff --git a/py/stackctrl.c b/py/stackctrl.c
index 546987f04d..e534a2f5f9 100644
--- a/py/stackctrl.c
+++ b/py/stackctrl.c
@@ -30,8 +30,11 @@
 void mp_stack_ctrl_init(void) {
     // Force routine to not be inlined. Better guarantee than MP_NOINLINE for -flto.
     __asm volatile ("");
+    #pragma GCC diagnostic push
+    #pragma GCC diagnostic ignored "-Wdangling-pointer"
     volatile int stack_dummy;
     MP_STATE_THREAD(stack_top) = (char *)&stack_dummy;
+    #pragma GCC diagnostic pop
 }
 
 void mp_stack_set_top(void *top) {
diff --git a/supervisor/linker.h b/supervisor/linker.h
index 9666c4ca12..2d88812da4 100644
--- a/supervisor/linker.h
+++ b/supervisor/linker.h
@@ -29,7 +29,7 @@
 #ifndef MICROPY_INCLUDED_SUPERVISOR_LINKER_H
 #define MICROPY_INCLUDED_SUPERVISOR_LINKER_H
 
-#if defined(IMXRT10XX) || defined(FOMU) || defined(STM32H7) || defined(RASPBERRYPI)
+#if defined(IMXRT1XXX) || defined(FOMU) || defined(STM32H7) || defined(RASPBERRYPI)
 #define PLACE_IN_DTCM_DATA(name) name __attribute__((section(".dtcm_data." #name)))
 #define PLACE_IN_DTCM_BSS(name) name __attribute__((section(".dtcm_bss." #name)))
 // Don't inline ITCM functions because that may pull them out of ITCM into other sections.
diff --git a/tools/cortex-m-fault-gdb.py b/tools/cortex-m-fault-gdb.py
index 2ed2d13909..54a921e91f 100644
--- a/tools/cortex-m-fault-gdb.py
+++ b/tools/cortex-m-fault-gdb.py
@@ -74,12 +74,19 @@ class CortexMFault(gdb.Command):
             print("No preempted exceptions")
         else:
             print("Another exception was preempted")
+        print("icsr", hex(icsr))
         vectactive = icsr & 0x1FF
         if vectactive != 0:
             if vectactive in EXCEPTIONS:
                 print(EXCEPTIONS[vectactive])
             else:
                 print(vectactive - 16)
+        vectpending = (icsr >> 12) & 0x1FF
+        if vectpending != 0:
+            if vectpending in EXCEPTIONS:
+                print(EXCEPTIONS[vectpending])
+            else:
+                print(vectpending - 16)
 
         vtor = self._read(VTOR)
         print("vtor", hex(vtor))