py: Support arm and thumb ARM ISAs, in addition to thumb2.
These changes were tested with QEMU, and by few people of real hardware.
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py/nlr.h
2
py/nlr.h
@ -45,7 +45,7 @@ struct _nlr_buf_t {
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#else
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void *regs[8];
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#endif
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#elif defined(__thumb2__)
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#elif defined(__thumb2__) || defined(__thumb__) || defined(__arm__)
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void *regs[10];
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#else
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#define MICROPY_NLR_SETJMP (1)
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@ -24,19 +24,21 @@
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* THE SOFTWARE.
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*/
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#if defined(__thumb2__) && !MICROPY_NLR_SETJMP
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/* thumb callee save: bx, bp, sp, r12, r14, r14, r15 */
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#if !MICROPY_NLR_SETJMP && (defined(__thumb2__) || defined(__thumb__) || defined(__arm__))
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/* arm callee save: bx, bp, sp, r12, r14, r14, r15 */
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.syntax unified
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/*.cpu cortex-m4*/
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.thumb
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/*.thumb*/
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.text
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.align 2
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/* uint nlr_push(r0=nlr_buf_t *nlr) */
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.global nlr_push
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#if defined(__thumb2__)
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.thumb
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.thumb_func
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#endif
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.type nlr_push, %function
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nlr_push:
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str lr, [r0, #8] @ store lr into nlr_buf
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@ -64,8 +66,10 @@ nlr_push:
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@ void nlr_pop()
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.global nlr_pop
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#if defined(__thumb2__)
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.thumb
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.thumb_func
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#endif
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.type nlr_pop, %function
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nlr_pop:
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ldr r3, .L5 @ load addr of nlr_top
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@ -80,8 +84,10 @@ nlr_pop:
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/* void nlr_jump(r0=uint val) */
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.global nlr_jump
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#if defined(__thumb2__)
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.thumb
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.thumb_func
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#endif
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.type nlr_jump, %function
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nlr_jump:
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ldr r3, .L2 @ load addr of nlr_top
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@ -97,7 +97,7 @@ void gc_helper_get_regs(regs_t arr) {
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}
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#endif
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#ifdef __thumb2__
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#if defined(__thumb2__) || defined(__thumb__) || defined(__arm__)
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typedef machine_uint_t regs_t[10];
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void gc_helper_get_regs(regs_t arr) {
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