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atmel-samd: Save a little space by tweaking error messages.

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This commit is contained in:
Scott Shawcroft 2017-02-19 17:24:15 +01:00
parent 8584f5fece
commit a5a41d7163
4 changed files with 8 additions and 8 deletions
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2
atmel-samd/common-hal/nativeio/AnalogIn.c
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@ -46,7 +46,7 @@ void common_hal_nativeio_analogin_construct(nativeio_analogin_obj_t* self,
const mcu_pin_obj_t *pin) {
if (!pin->has_adc) {
// No ADC function on that pin
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "pin %q does not have ADC capabilities", pin->name));
nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "Pin does not have ADC capabilities"));
}
self->pin = pin;

8
atmel-samd/common-hal/nativeio/PWMOut.c
View File

@ -80,12 +80,12 @@ void common_hal_nativeio_pwmout_construct(nativeio_pwmout_obj_t* self,
if (pin->primary_timer.tc == 0 && pin->secondary_timer.tc == 0) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"Invalid pin."));
"Invalid pin"));
}
if (frequency == 0 || frequency > 6000000) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"Invalid PWM frequency."));
"Invalid PWM frequency"));
}
uint16_t primary_timer_index = 0xff;
@ -136,7 +136,7 @@ void common_hal_nativeio_pwmout_construct(nativeio_pwmout_obj_t* self,
index = primary_timer_index;
}
if (t == NULL) {
nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "All timers in use."));
nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "All timers in use"));
return;
}
uint8_t resolution = 0;
@ -266,7 +266,7 @@ void common_hal_nativeio_pwmout_set_frequency(nativeio_pwmout_obj_t* self,
uint32_t frequency) {
if (frequency == 0 || frequency > 6000000) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"Invalid PWM frequency."));
"Invalid PWM frequency"));
}
const pin_timer_t* t = self->timer;
uint8_t resolution;

4
atmel-samd/common-hal/nativeio/SPI.c
View File

@ -92,7 +92,7 @@ void common_hal_nativeio_spi_construct(nativeio_spi_obj_t *self,
}
}
if (sercom == NULL) {
nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "Invalid pins."));
nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "Invalid pins"));
}
// Depends on where MOSI and CLK are.
@ -111,7 +111,7 @@ void common_hal_nativeio_spi_construct(nativeio_spi_obj_t *self,
}
}
if (dopo == 8) {
nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "SPI MOSI and clock pins incompatible."));
nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "SPI MOSI and clock pins incompatible"));
}
config_spi_master.mux_setting = (dopo << SERCOM_SPI_CTRLA_DOPO_Pos) |

2
atmel-samd/common-hal/nativeio/UART.c
View File

@ -162,7 +162,7 @@ void common_hal_nativeio_uart_construct(nativeio_uart_obj_t *self,
}
}
if (sercom == NULL) {
nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "Invalid pins."));
nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "Invalid pins"));
}
if (tx == NULL) {
tx_pad = 0;