update idf to v5.0

This commit is contained in:
MicroDev 2023-01-06 12:15:06 +05:30 committed by Scott Shawcroft
parent 3032d4e7d5
commit a18e015888
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GPG Key ID: 0DFD512649C052DA
57 changed files with 261 additions and 2332 deletions

15
.gitmodules vendored
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@ -143,7 +143,16 @@
[submodule "ports/espressif/esp-idf"]
path = ports/espressif/esp-idf
url = https://github.com/adafruit/esp-idf.git
branch = release/v4.4-circuitpython
[submodule "ports/espressif/esp-protocols"]
path = ports/espressif/esp-protocols
url = https://github.com/espressif/esp-protocols.git
[submodule "ports/espressif/esp-iot-solution"]
path = ports/espressif/esp-iot-solution
url = https://github.com/espressif/esp-iot-solution.git
[submodule "ports/espressif/esp-camera"]
path = ports/espressif/esp-camera
url = https://github.com/espressif/esp32-camera.git
branch = circuitpython
[submodule "frozen/Adafruit_CircuitPython_ST7789"]
path = frozen/Adafruit_CircuitPython_ST7789
url = https://github.com/adafruit/Adafruit_CircuitPython_ST7789
@ -297,10 +306,6 @@
[submodule "frozen/circuitpython_picoed"]
path = frozen/circuitpython_picoed
url = https://github.com/elecfreaks/circuitpython_picoed.git
[submodule "ports/espressif/esp32-camera"]
path = ports/espressif/esp32-camera
url = https://github.com/adafruit/esp32-camera/
branch = circuitpython
[submodule "ports/raspberrypi/lib/cyw43-driver"]
path = ports/raspberrypi/lib/cyw43-driver
url = https://github.com/georgerobotics/cyw43-driver.git

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@ -1,12 +1,12 @@
# The following five lines of boilerplate have to be in your project's
# CMakeLists in this exact order for cmake to work correctly
cmake_minimum_required(VERSION 3.13)
cmake_minimum_required(VERSION 3.16)
set(ENV{IDF_PATH} ${CMAKE_SOURCE_DIR}/esp-idf)
# The component list here determines what options we get in menuconfig and what the ninja file
# can build.
set(COMPONENTS esptool_py soc driver log main esp-tls mbedtls mdns esp_event esp_adc_cal esp_netif esp_wifi lwip ulp wpa_supplicant freertos bt usb esp32-camera esp_lcd)
# The component list here determines what options we get in menuconfig and what the ninja file can build.
set(COMPONENTS bt driver esp-tls esp_adc_cal esp_event esp_netif esp_psram esp_wifi esptool_py freertos log lwip main mbedtls mdns soc ulp usb wpa_supplicant esp_lcd)
set(EXTRA_COMPONENT_DIRS esp-protocols/components/mdns)
list(APPEND EXTRA_COMPONENT_DIRS "esp32-camera")

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@ -51,6 +51,7 @@ INC += \
-isystem esp-idf \
-isystem esp-idf/components/app_update/include \
-isystem esp-idf/components/bootloader_support/include \
-isystem esp-idf/components/bootloader_support/bootloader_flash/include \
-isystem esp-idf/components/bt/include/$(IDF_TARGET)/include \
-isystem esp-idf/components/bt/host/nimble/esp-hci/include \
-isystem esp-idf/components/bt/host/nimble/nimble/nimble/controller/include \
@ -62,28 +63,31 @@ INC += \
-isystem esp-idf/components/bt/host/nimble/nimble/porting/npl/freertos/include \
-isystem esp-idf/components/bt/host/nimble/port/include \
-isystem esp-idf/components/driver/include \
-isystem esp-idf/components/driver/deprecated \
-isystem esp-idf/components/driver/$(IDF_TARGET)/include \
-isystem esp-idf/components/efuse/include \
-isystem esp-idf/components/efuse/$(IDF_TARGET)/include \
-isystem esp-idf/components/$(IDF_TARGET)/include \
-isystem esp-idf/components/esp_adc_cal/include \
-isystem esp-idf/components/esp_adc/deprecated/include \
-isystem esp-idf/components/esp_app_format/include \
-isystem esp-idf/components/esp_common/include \
-isystem esp-idf/components/esp_event/include \
-isystem esp-idf/components/esp_hw_support/include \
-isystem esp-idf/components/esp_hw_support/include/soc \
-isystem esp-idf/components/esp_ipc/include \
-isystem esp-idf/components/esp_netif/include \
-isystem esp-idf/components/esp_partition/include \
-isystem esp-idf/components/esp_pm/include \
-isystem esp-idf/components/esp_psram/include \
-isystem esp-idf/components/esp_ringbuf/include \
-isystem esp-idf/components/esp_rom/include \
-isystem esp-idf/components/esp_system/include \
-isystem esp-idf/components/esp_timer/include \
-isystem esp-idf/components/esp_wifi/include \
-isystem esp-idf/components/freertos/include \
-isystem esp-idf/components/freertos/include/freertos \
-isystem esp-idf/components/freertos/include/esp_additions \
-isystem esp-idf/components/freertos/include/esp_additions/freertos \
-isystem esp-idf/components/freertos/port/$(IDF_TARGET_ARCH)/include \
-isystem esp-idf/components/freertos/esp_additions/include \
-isystem esp-idf/components/freertos/esp_additions/include/freertos \
-isystem esp-idf/components/freertos/FreeRTOS-Kernel/include \
-isystem esp-idf/components/freertos/FreeRTOS-Kernel/include/freertos \
-isystem esp-idf/components/freertos/FreeRTOS-Kernel/portable/$(IDF_TARGET_ARCH)/include \
-isystem esp-idf/components/hal/include \
-isystem esp-idf/components/hal/$(IDF_TARGET)/include \
-isystem esp-idf/components/hal/platform_port/include \
@ -100,13 +104,13 @@ INC += \
-isystem esp-idf/components/soc/include \
-isystem esp-idf/components/soc/$(IDF_TARGET)/include \
-isystem esp-idf/components/spi_flash/include \
-isystem esp-idf/components/ulp/include \
-isystem esp-idf/components/ulp/ulp_riscv/include \
-isystem esp-idf/components/ulp/ulp_common/include \
-isystem esp-idf/components/ulp/ulp_common/include/$(IDF_TARGET) \
-isystem esp-idf/components/$(IDF_TARGET_ARCH)/include \
-isystem esp-idf/components/$(IDF_TARGET_ARCH)/$(IDF_TARGET)/include
# See https://github.com/espressif/esp-idf/issues/6906
ifeq ($(IDF_TARGET),esp32c3)
CFLAGS += -include "esp32c3_fix.h"
endif
-isystem esp-idf/components/$(IDF_TARGET_ARCH)/$(IDF_TARGET)/include \
-isystem esp-protocols/components/mdns/include
CFLAGS += \
-DHAVE_CONFIG_H \
@ -232,22 +236,15 @@ SRC_C += \
peripherals/timer.c \
peripherals/$(IDF_TARGET)/pins.c
ifneq ($(IDF_TARGET),esp32c3)
SRC_C += $(wildcard common-hal/espidf/*.c)
ifeq ($(IDF_TARGET),esp32c3)
SRC_C += supervisor/usb_serial_jtag.c
else
SRC_C += \
peripherals/pcnt.c \
peripherals/touch.c
ifeq ($(IDF_TARGET),esp32s2)
SRC_C += \
i2s_lcd_esp32s2_driver.c
endif
endif
ifeq ($(IDF_TARGET),esp32c3)
SRC_C += \
supervisor/usb_serial_jtag.c
endif
$(BUILD)/i2s_lcd_esp32s2_driver.o: CFLAGS += -Wno-sign-compare
ifneq ($(CIRCUITPY_USB),0)
SRC_C += lib/tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c
@ -257,6 +254,17 @@ ifneq ($(CIRCUITPY_BLEIO),0)
SRC_C += common-hal/_bleio/ble_events.c
endif
ifneq ($(CIRCUITPY_PARALLELDISPLAY),0)
ifeq ($(IDF_TARGET),esp32s3)
LCD_SRC = 8080_lcd_$(IDF_TARGET)
else
LCD_SRC = i2s_lcd_$(IDF_TARGET)_driver
endif
SRC_C += esp-iot-solution/components/bus/$(LCD_SRC).c
$(BUILD)/esp-iot-solution/components/bus/$(LCD_SRC).o: CFLAGS += -Wno-sign-compare
CFLAGS += -isystem esp-iot-solution/components/bus/include
endif
ifneq ($(CIRCUITPY_DOTCLOCKFRAMEBUFFER),0)
CFLAGS += -isystem esp-idf/components/esp_lcd/include
CFLAGS += -isystem esp-idf/components/esp_lcd/interface
@ -290,8 +298,6 @@ SRC_ULP := \
$(wildcard common-hal/espulp/*.c) \
$(wildcard bindings/espulp/*.c)
SRC_C += $(SRC_ULP)
CFLAGS += -isystem esp-idf/components/ulp/include
CFLAGS += -isystem esp-idf/components/ulp/ulp_riscv/include
endif
SRC_COMMON_HAL_EXPANDED = \
@ -389,7 +395,7 @@ ifeq ($(IDF_TARGET),esp32)
BINARY_BLOBS += esp-idf/components/esp_phy/lib/$(IDF_TARGET)/librtc.a
endif
ESP_IDF_COMPONENTS_LINK = $(IDF_TARGET_ARCH) app_update bootloader_support driver efuse esp_adc_cal esp_common esp_event esp_hw_support esp_ipc esp_netif esp_pm esp_phy esp_ringbuf esp_rom esp_system esp_timer esp-tls esp_wifi freertos hal heap log lwip mbedtls mdns newlib nvs_flash pthread soc spi_flash vfs wpa_supplicant
ESP_IDF_COMPONENTS_LINK = $(IDF_TARGET_ARCH) app_update bootloader_support driver efuse esp_adc esp_app_format esp_common esp_event esp_hw_support esp_netif esp_partition esp_phy esp_pm esp_psram esp_ringbuf esp_rom esp_system esp_timer esp-tls esp_wifi freertos hal heap log lwip mbedtls mdns newlib nvs_flash pthread soc spi_flash vfs wpa_supplicant
ifneq ($(CIRCUITPY_BLEIO),0)
ESP_IDF_COMPONENTS_LINK += bt
BINARY_BLOBS += esp-idf/components/esp_phy/lib/$(IDF_TARGET)/libbtbb.a \
@ -440,8 +446,6 @@ IDF_CMAKE_TARGETS = \
PARTITION_TABLE_OFFSET = 0x8000
FIRMWARE_OFFSET = 0x10000
ESP_AUTOGEN_LD = $(BUILD)/esp-idf/esp-idf/$(IDF_TARGET)/$(IDF_TARGET)_out.ld $(BUILD)/esp-idf/esp-idf/$(IDF_TARGET)/ld/$(IDF_TARGET).project.ld
FLASH_FLAGS = --flash_mode $(CIRCUITPY_ESP_FLASH_MODE) --flash_freq $(CIRCUITPY_ESP_FLASH_FREQ) --flash_size $(CIRCUITPY_ESP_FLASH_SIZE)
ESPTOOL_FLAGS ?= --before=default_reset --after=no_reset --baud 921600
@ -460,7 +464,7 @@ esp-idf-stamp: $(BUILD)/esp-idf/config/sdkconfig.h
$(BUILD)/firmware.elf: $(OBJ) | esp-idf-stamp $(IDF_CMAKE_TARGETS)
$(STEPECHO) "LINK $@"
$(Q)$(CC) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(ESP_IDF_COMPONENTS_EXPANDED) $(BINARY_BLOBS) $(MBEDTLS_COMPONENTS_LINK_EXPANDED) $(BUILD)/esp-idf/esp-idf/newlib/libnewlib.a -Wl,--end-group -u newlib_include_pthread_impl -u ld_include_highint_hdl -Wl,--start-group $(LIBS) -Wl,--end-group $(BUILD)/esp-idf/esp-idf/pthread/libpthread.a -u __cxx_fatal_exception
$(Q)$(CC) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(ESP_IDF_COMPONENTS_EXPANDED) $(BINARY_BLOBS) $(MBEDTLS_COMPONENTS_LINK_EXPANDED) $(LIBS) -Wl,--end-group -u newlib_include_pthread_impl -u ld_include_highint_hdl -u __cxx_fatal_exception
$(BUILD)/circuitpython-firmware.bin: $(BUILD)/firmware.elf | tools/build_memory_info.py
$(STEPECHO) "Create $@"

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@ -9,7 +9,7 @@ Support Status:
.. csv-table::
:header: SoC, Status
ESP, "beta"
ESP32, "beta"
ESP32-C3, "beta"
ESP32-S2, "stable"
ESP32-S3, "beta"

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@ -95,7 +95,6 @@ void common_hal_bleio_adapter_set_enabled(bleio_adapter_obj_t *self, bool enable
}
if (enabled) {
esp_nimble_hci_and_controller_init();
nimble_port_init();
// ble_hs_cfg.reset_cb = blecent_on_reset;
ble_hs_cfg.sync_cb = _on_sync;

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@ -36,8 +36,8 @@
#include "hal/gpio_ll.h"
#include "esp_debug_helpers.h"
#include "components/driver/include/driver/rtc_io.h"
#include "components/freertos/include/freertos/FreeRTOS.h"
#include "driver/rtc_io.h"
#include "freertos/FreeRTOS.h"
void common_hal_alarm_pin_pinalarm_construct(alarm_pin_pinalarm_obj_t *self, const mcu_pin_obj_t *pin, bool value, bool edge, bool pull) {
if (edge) {

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@ -30,8 +30,9 @@
#include "py/runtime.h"
#include "supervisor/shared/translate/translate.h"
#include "components/driver/include/driver/adc_common.h"
#include "components/esp_adc_cal/include/esp_adc_cal.h"
#include "driver/adc.h"
#include "driver/gpio.h"
#include "esp_adc_cal.h"
#include "shared-bindings/microcontroller/Pin.h"
@ -54,7 +55,7 @@
void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self,
const mcu_pin_obj_t *pin) {
if (pin->adc_index == 0 || pin->adc_channel == ADC_CHANNEL_MAX) {
if (pin->adc_index == 0 || pin->adc_channel == NO_ADC_CHANNEL) {
raise_ValueError_invalid_pin();
}
common_hal_mcu_pin_claim(pin);

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@ -37,9 +37,9 @@
#define I2S_QUEUE_SIZE (3)
static i2s_t *i2s_instance[I2S_NUM_MAX];
static QueueHandle_t i2s_queues[I2S_NUM_MAX];
static TaskHandle_t i2s_tasks[I2S_NUM_MAX];
static i2s_t *i2s_instance[I2S_NUM_AUTO];
static QueueHandle_t i2s_queues[I2S_NUM_AUTO];
static TaskHandle_t i2s_tasks[I2S_NUM_AUTO];
void port_i2s_allocate_i2s0(void) {
if (!i2s_instance[0]) {
@ -64,7 +64,7 @@ static int8_t port_i2s_allocate(void) {
}
void port_i2s_reset_instance(int i) {
assert(i >= 0 && i < I2S_NUM_MAX);
assert(i >= 0 && i < I2S_NUM_AUTO);
if (i2s_tasks[i]) {
vTaskDelete(i2s_tasks[i]);
}
@ -75,7 +75,7 @@ void port_i2s_reset_instance(int i) {
}
void i2s_reset(void) {
for (int i = 0; i < I2S_NUM_MAX; i++) {
for (int i = 0; i < I2S_NUM_AUTO; i++) {
port_i2s_reset_instance(i);
}
}
@ -83,7 +83,7 @@ void i2s_reset(void) {
#define I2S_WRITE_DELAY pdMS_TO_TICKS(1)
static void i2s_fill_buffer(i2s_t *self) {
if (self->instance < 0 || self->instance >= I2S_NUM_MAX) {
if (self->instance < 0 || self->instance >= I2S_NUM_AUTO) {
return;
}
#define STACK_BUFFER_SIZE (4096)

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@ -30,7 +30,7 @@
#include "shared-bindings/busio/SPI.h"
#include "shared-bindings/microcontroller/Pin.h"
#include "driver/spi_common_internal.h"
#include "esp_private/spi_common_internal.h"
#define SPI_MAX_DMA_BITS (SPI_MAX_DMA_LEN * 8)
#define MAX_SPI_TRANSACTIONS 10

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@ -31,6 +31,8 @@
#include "py/runtime.h"
#include "supervisor/shared/translate/translate.h"
#include "driver/gpio.h"
void common_hal_countio_counter_construct(countio_counter_obj_t *self,
const mcu_pin_obj_t *pin, countio_edge_t edge, digitalio_pull_t pull) {
claim_pin(pin);

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@ -31,6 +31,7 @@
#include "esp_log.h"
#include "esp_ota_ops.h"
#include "esp_app_format.h"
static const esp_partition_t *update_partition = NULL;
static esp_ota_handle_t update_handle = 0;
@ -59,10 +60,10 @@ void common_hal_dualbank_flash(const void *buf, const size_t len, const size_t o
update_partition = esp_ota_get_next_update_partition(NULL);
assert(update_partition != NULL);
ESP_LOGI(TAG, "Running partition type %d subtype %d (offset 0x%08x)",
ESP_LOGI(TAG, "Running partition type %d subtype %d (offset 0x%08lu)",
running->type, running->subtype, running->address);
ESP_LOGI(TAG, "Writing partition type %d subtype %d (offset 0x%08x)\n",
ESP_LOGI(TAG, "Writing partition type %d subtype %d (offset 0x%08lu)\n",
update_partition->type, update_partition->subtype, update_partition->address);
}

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@ -35,7 +35,7 @@
#define TAG "espidf"
#ifdef CONFIG_SPIRAM
#include "esp32/spiram.h"
#include "esp_psram.h"
#include "esp_heap_caps.h"
#include "esp_heap_caps_init.h"
#include "soc/soc.h"
@ -51,7 +51,7 @@ size_t reserved_psram = DEFAULT_RESERVED_PSRAM;
static size_t psram_size_usable(void) {
#ifdef CONFIG_SPIRAM
/* PSRAM chip may be larger than the size we can map into address space */
size_t s = MIN(esp_spiram_get_size(), SOC_EXTRAM_DATA_SIZE);
size_t s = MIN(esp_psram_get_size(), SOC_EXTRAM_DATA_SIZE);
return s - esp_himem_reserved_area_size();
#else
return 0;
@ -60,7 +60,7 @@ static size_t psram_size_usable(void) {
bool common_hal_espidf_set_reserved_psram(size_t amount) {
#ifdef CONFIG_SPIRAM
if (!esp_spiram_is_initialized()) {
if (!esp_psram_is_initialized()) {
return false;
}
if (!ok_to_reserve_psram) {
@ -112,7 +112,7 @@ size_t common_hal_espidf_get_total_psram(void) {
intptr_t common_hal_espidf_get_psram_start(void) {
#ifdef CONFIG_SPIRAM
if (esp_spiram_is_initialized()) {
if (esp_psram_is_initialized()) {
#ifdef CONFIG_IDF_TARGET_ESP32
return SOC_EXTRAM_DATA_LOW;
#else
@ -125,7 +125,7 @@ intptr_t common_hal_espidf_get_psram_start(void) {
intptr_t common_hal_espidf_get_psram_end(void) {
#ifdef CONFIG_SPIRAM
if (esp_spiram_is_initialized()) {
if (esp_psram_is_initialized()) {
return common_hal_espidf_get_psram_start() + psram_size_usable();
}
#endif

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@ -28,7 +28,6 @@
#include "bindings/espulp/ULP.h"
#include "py/runtime.h"
#include "shared-bindings/microcontroller/Pin.h"
#if defined(CONFIG_IDF_TARGET_ESP32)
@ -56,7 +55,7 @@ void espulp_reset(void) {
}
void common_hal_espulp_ulp_run(espulp_ulp_obj_t *self, uint32_t *program, size_t length, uint32_t pin_mask) {
if (length > ULP_COPROC_RESERVE_MEM) {
if (length > CONFIG_ULP_COPROC_RESERVE_MEM) {
mp_raise_ValueError(translate("Program too long"));
}
@ -111,18 +110,8 @@ void common_hal_espulp_ulp_halt(espulp_ulp_obj_t *self) {
#ifdef CONFIG_IDF_TARGET_ESP32
mp_raise_NotImplementedError(NULL);
#else
// To-do idf v5.0: use following functions
// ulp_riscv_timer_stop();
// ulp_riscv_halt();
// stop the ulp timer so that it doesn't restart the cpu
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
// suspends the ulp operation
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
// resets the processor
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
ulp_riscv_timer_stop();
ulp_riscv_halt();
#endif
// Release pins we were using.

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@ -29,7 +29,7 @@
#include "common-hal/alarm/__init__.h"
#include "supervisor/port.h"
#include "driver/rtc_cntl.h"
#include "esp_private/rtc_ctrl.h"
#include "soc/rtc_cntl_reg.h"
#include "esp_sleep.h"
@ -117,7 +117,9 @@ void espulp_ulpalarm_prepare_for_deep_sleep(void) {
// enable ulp wakeup
esp_sleep_enable_ulp_wakeup();
#if defined(SOC_PM_SUPPORT_RTC_SLOW_MEM_PD) && SOC_PM_SUPPORT_RTC_SLOW_MEM_PD
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_SLOW_MEM, ESP_PD_OPTION_ON);
#endif
}
bool espulp_ulpalarm_woke_this_cycle(void) {

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@ -28,6 +28,10 @@
#include "py/runtime.h"
#include "driver/gpio.h"
#include "driver/timer.h"
#include "soc/timer_group_struct.h"
static void IRAM_ATTR pcnt_overflow_handler(void *self_in) {
frequencyio_frequencyin_obj_t *self = self_in;
// reset counter
@ -56,28 +60,16 @@ static void IRAM_ATTR timer_interrupt_handler(void *self_in) {
// reset interrupt
timg_dev_t *device = self->timer.group ? &(TIMERG1) : &(TIMERG0);
#if defined(CONFIG_IDF_TARGET_ESP32)
if (self->timer.idx) {
device->int_clr_timers.t1 = 1;
} else {
device->int_clr_timers.t0 = 1;
}
#else
if (self->timer.idx) {
device->int_clr_timers.t1_int_clr = 1;
} else {
device->int_clr_timers.t0_int_clr = 1;
}
#endif
#if defined(CONFIG_IDF_TARGET_ESP32)
device->hw_timer[self->timer.idx].config.alarm_en = 1;
#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32C2)
device->hw_timer[self->timer.idx].config.tx_alarm_en = 1;
#elif defined(CONFIG_IDF_TARGET_ESP32S3)
#if defined(CONFIG_IDF_TARGET_ESP32S3)
device->hw_timer[self->timer.idx].config.tn_alarm_en = 1;
#else
#error No known CONFIG_IDF_TARGET_xxx found
device->hw_timer[self->timer.idx].config.tx_alarm_en = 1;
#endif
}

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@ -30,7 +30,7 @@
void common_hal_hashlib_hash_update(hashlib_hash_obj_t *self, const uint8_t *data, size_t datalen) {
if (self->hash_type == MBEDTLS_SSL_HASH_SHA1) {
mbedtls_sha1_update_ret(&self->sha1, data, datalen);
mbedtls_sha1_update(&self->sha1, data, datalen);
return;
}
}
@ -44,7 +44,7 @@ void common_hal_hashlib_hash_digest(hashlib_hash_obj_t *self, uint8_t *data, siz
// the digest a second time.
mbedtls_sha1_context copy;
mbedtls_sha1_clone(&copy, &self->sha1);
mbedtls_sha1_finish_ret(&self->sha1, data);
mbedtls_sha1_finish(&self->sha1, data);
mbedtls_sha1_clone(&self->sha1, &copy);
}
}

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@ -33,7 +33,7 @@ bool common_hal_hashlib_new(hashlib_hash_obj_t *self, const char *algorithm) {
if (strcmp(algorithm, "sha1") == 0) {
self->hash_type = MBEDTLS_SSL_HASH_SHA1;
mbedtls_sha1_init(&self->sha1);
mbedtls_sha1_starts_ret(&self->sha1);
mbedtls_sha1_starts(&self->sha1);
return true;
}
return false;

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@ -26,7 +26,7 @@
#pragma once
#include "components/mdns/include/mdns.h"
#include "mdns.h"
typedef struct {
mp_obj_base_t base;

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@ -31,7 +31,7 @@
#include "shared-bindings/mdns/RemoteService.h"
#include "shared-bindings/wifi/__init__.h"
#include "components/mdns/include/mdns.h"
#include "mdns.h"
// Track whether the underlying IDF mdns has been started so that we only
// create a single inited MDNS object to CircuitPython. (After deinit, another
@ -125,22 +125,13 @@ size_t mdns_server_find(mdns_server_obj_t *self, const char *service_type, const
if (search == NULL) {
return 0;
}
uint8_t num_results;
mdns_result_t *results;
while (!mdns_query_async_get_results(search, 1, &results)) {
while (!mdns_query_async_get_results(search, 1, &results, &num_results)) {
RUN_BACKGROUND_TASKS;
}
mdns_query_async_delete(search);
// Count how many results we got.
// TODO: Remove this loop when moving off 4.4. Newer APIs will give us num_results
// back directly.
mdns_result_t *next = results;
uint8_t num_results = 0;
while (next != NULL) {
num_results++;
next = next->next;
}
next = results;
// Don't error if we're out of memory. Instead, truncate the tuple.
uint8_t added = 0;
while (next != NULL && added < out_len) {
@ -166,27 +157,19 @@ mp_obj_t common_hal_mdns_server_find(mdns_server_obj_t *self, const char *servic
if (search == NULL) {
mp_raise_RuntimeError(translate("Unable to start mDNS query"));
}
uint8_t num_results;
mdns_result_t *results;
while (!mdns_query_async_get_results(search, 1, &results)) {
while (!mdns_query_async_get_results(search, 1, &results, &num_results)) {
RUN_BACKGROUND_TASKS;
}
mdns_query_async_delete(search);
// Count how many results we got.
// TODO: Remove this loop when moving off 4.4. Newer APIs will give us num_results
// back directly.
mdns_result_t *next = results;
uint8_t num_results = 0;
while (next != NULL) {
num_results++;
next = next->next;
}
mp_obj_tuple_t *tuple = MP_OBJ_TO_PTR(mp_obj_new_tuple(num_results, NULL));
// The empty tuple object is shared and stored in flash so return early if
// we got it. Without this we'll crash when trying to set len below.
if (num_results == 0) {
return MP_OBJ_FROM_PTR(tuple);
}
next = results;
mdns_result_t *next = results;
// Don't error if we're out of memory. Instead, truncate the tuple.
uint8_t added = 0;
while (next != NULL) {

View File

@ -29,7 +29,6 @@
#include "shared-bindings/memorymap/AddressRange.h"
#include "py/runtime.h"
#include "soc/soc.h"
size_t allow_ranges[][2] = {
@ -39,7 +38,6 @@ size_t allow_ranges[][2] = {
{SOC_RTC_DRAM_LOW, SOC_RTC_DRAM_HIGH},
// RTC peripheral registers
{0x60008000, 0x60009000}
};
void common_hal_memorymap_addressrange_construct(memorymap_addressrange_obj_t *self, uint8_t *start_address, size_t length) {

View File

@ -38,7 +38,63 @@ STATIC uint64_t _skip_reset_once_pin_mask;
STATIC uint64_t _preserved_pin_mask;
STATIC uint64_t _in_use_pin_mask;
// Bit mask of all pins that should never EVER be reset or used by user code.
#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */
#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */
#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */
#define GPIO_SEL_3 (BIT(3)) /*!< Pin 3 selected */
#define GPIO_SEL_4 (BIT(4)) /*!< Pin 4 selected */
#define GPIO_SEL_5 (BIT(5)) /*!< Pin 5 selected */
#define GPIO_SEL_6 (BIT(6)) /*!< Pin 6 selected */
#define GPIO_SEL_7 (BIT(7)) /*!< Pin 7 selected */
#define GPIO_SEL_8 (BIT(8)) /*!< Pin 8 selected */
#define GPIO_SEL_9 (BIT(9)) /*!< Pin 9 selected */
#define GPIO_SEL_10 (BIT(10)) /*!< Pin 10 selected */
#define GPIO_SEL_11 (BIT(11)) /*!< Pin 11 selected */
#define GPIO_SEL_12 (BIT(12)) /*!< Pin 12 selected */
#define GPIO_SEL_13 (BIT(13)) /*!< Pin 13 selected */
#define GPIO_SEL_14 (BIT(14)) /*!< Pin 14 selected */
#define GPIO_SEL_15 (BIT(15)) /*!< Pin 15 selected */
#define GPIO_SEL_16 (BIT(16)) /*!< Pin 16 selected */
#define GPIO_SEL_17 (BIT(17)) /*!< Pin 17 selected */
#define GPIO_SEL_18 (BIT(18)) /*!< Pin 18 selected */
#define GPIO_SEL_19 (BIT(19)) /*!< Pin 19 selected */
#define GPIO_SEL_20 (BIT(20)) /*!< Pin 20 selected */
#define GPIO_SEL_21 (BIT(21)) /*!< Pin 21 selected */
#if defined(CONFIG_IDF_TARGET_ESP32)
#define GPIO_SEL_22 (BIT(22)) /*!< Pin 22 selected */
#define GPIO_SEL_23 (BIT(23)) /*!< Pin 23 selected */
#define GPIO_SEL_25 (BIT(25)) /*!< Pin 25 selected */
#endif
#define GPIO_SEL_26 (BIT(26)) /*!< Pin 26 selected */
#define GPIO_SEL_27 (BIT(27)) /*!< Pin 27 selected */
#define GPIO_SEL_28 (BIT(28)) /*!< Pin 28 selected */
#define GPIO_SEL_29 (BIT(29)) /*!< Pin 29 selected */
#define GPIO_SEL_30 (BIT(30)) /*!< Pin 30 selected */
#define GPIO_SEL_31 (BIT(31)) /*!< Pin 31 selected */
#define GPIO_SEL_32 ((uint64_t)PIN_BIT(32)) /*!< Pin 32 selected */
#define GPIO_SEL_33 ((uint64_t)PIN_BIT(33)) /*!< Pin 33 selected */
#define GPIO_SEL_34 ((uint64_t)PIN_BIT(34)) /*!< Pin 34 selected */
#define GPIO_SEL_35 ((uint64_t)PIN_BIT(35)) /*!< Pin 35 selected */
#define GPIO_SEL_36 ((uint64_t)PIN_BIT(36)) /*!< Pin 36 selected */
#define GPIO_SEL_37 ((uint64_t)PIN_BIT(37)) /*!< Pin 37 selected */
#define GPIO_SEL_38 ((uint64_t)PIN_BIT(38)) /*!< Pin 38 selected */
#define GPIO_SEL_39 ((uint64_t)PIN_BIT(39)) /*!< Pin 39 selected */
#if SOC_GPIO_PIN_COUNT > 40
#define GPIO_SEL_40 ((uint64_t)PIN_BIT(40)) /*!< Pin 40 selected */
#define GPIO_SEL_41 ((uint64_t)PIN_BIT(41)) /*!< Pin 41 selected */
#define GPIO_SEL_42 ((uint64_t)PIN_BIT(42)) /*!< Pin 42 selected */
#define GPIO_SEL_43 ((uint64_t)PIN_BIT(43)) /*!< Pin 43 selected */
#define GPIO_SEL_44 ((uint64_t)PIN_BIT(44)) /*!< Pin 44 selected */
#define GPIO_SEL_45 ((uint64_t)PIN_BIT(45)) /*!< Pin 45 selected */
#define GPIO_SEL_46 ((uint64_t)PIN_BIT(46)) /*!< Pin 46 selected */
#if defined(CONFIG_IDF_TARGET_ESP32S3)
#define GPIO_SEL_47 ((uint64_t)PIN_BIT(47)) /*!< Pin 47 selected */
#define GPIO_SEL_48 ((uint64_t)PIN_BIT(48)) /*!< Pin 48 selected */
#endif
#endif
// Bit mask of all pins that should never EVER be reset.
// Typically these are SPI flash and PSRAM control pins, and communication pins.
// "Reset forbidden" is stronger than "never reset" below, which may only be temporary.
static const uint64_t pin_mask_reset_forbidden =

View File

@ -41,21 +41,23 @@
#include "soc/efuse_reg.h"
#if !defined(CONFIG_IDF_TARGET_ESP32)
#include "driver/temp_sensor.h"
#include "driver/temperature_sensor.h"
#endif
float common_hal_mcu_processor_get_temperature(void) {
float tsens_out;
float tsens_value;
#if defined(CONFIG_IDF_TARGET_ESP32)
return NAN;
#else
temp_sensor_config_t temp_sensor = TSENS_CONFIG_DEFAULT(); // DEFAULT: range:-10℃ ~ 80℃, error < 1℃.
temp_sensor_set_config(temp_sensor);
temp_sensor_start();
temp_sensor_read_celsius(&tsens_out);
temp_sensor_stop();
temperature_sensor_handle_t temp_sensor = NULL;
temperature_sensor_config_t temp_sensor_config = TEMPERATURE_SENSOR_CONFIG_DEFAULT(-10, 80); // DEFAULT: range:-10℃ ~ 80℃, error < 1℃.
temperature_sensor_install(&temp_sensor_config, &temp_sensor);
temperature_sensor_enable(temp_sensor);
temperature_sensor_get_celsius(temp_sensor, &tsens_value);
temperature_sensor_disable(temp_sensor);
temperature_sensor_uninstall(temp_sensor);
#endif
return tsens_out;
return tsens_value;
}
float common_hal_mcu_processor_get_voltage(void) {

View File

@ -44,7 +44,6 @@
#include "py/runtime.h"
#include "shared-bindings/neopixel_write/__init__.h"
#include "supervisor/port.h"
#include "components/driver/include/driver/rmt.h"
#include "peripherals/rmt.h"
// Use closer to WS2812-style timings instead of WS2812B, to accommodate more varieties.

View File

@ -33,6 +33,7 @@
#include "shared-bindings/os/__init__.h"
#include "esp_system.h"
#include "esp_random.h"
STATIC const qstr os_uname_info_fields[] = {
MP_QSTR_sysname, MP_QSTR_nodename,
@ -60,7 +61,7 @@ mp_obj_t common_hal_os_uname(void) {
return (mp_obj_t)&os_uname_info_obj;
}
bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) {
bool common_hal_os_urandom(uint8_t *buffer, mp_uint_t length) {
uint32_t i = 0;
while (i < length) {
uint32_t new_random = esp_random();

View File

@ -36,8 +36,8 @@
#include "common-hal/microcontroller/Pin.h"
#include "py/runtime.h"
#include "i2s_lcd_driver.h"
#include "driver/gpio.h"
/*
* Current pin limitations for ESP32-S2 ParallelBus:
* - data0 pin must be byte aligned
@ -166,11 +166,12 @@ bool common_hal_paralleldisplay_parallelbus_bus_free(mp_obj_t obj) {
bool common_hal_paralleldisplay_parallelbus_begin_transaction(mp_obj_t obj) {
paralleldisplay_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj);
bool r = i2s_lcd_acquire_nonblocking(self->handle, 1);
if (r) {
bool lock_acquired = false;
i2s_lcd_acquire_nonblocking(self->handle, 1, &lock_acquired);
if (lock_acquired) {
gpio_set_level(self->config.pin_num_cs, false);
}
return r;
return lock_acquired;
}
void common_hal_paralleldisplay_parallelbus_send(mp_obj_t obj, display_byte_type_t byte_type,

View File

@ -30,7 +30,6 @@
#include "common-hal/microcontroller/Pin.h"
#include "py/obj.h"
#include "components/driver/include/driver/rmt.h"
#include "peripherals/rmt.h"
typedef struct {

View File

@ -28,7 +28,6 @@
#define MICROPY_INCLUDED_ESPRESSIF_COMMON_HAL_PULSEIO_PULSEOUT_H
#include "common-hal/microcontroller/Pin.h"
#include "components/driver/include/driver/rmt.h"
#include "peripherals/rmt.h"
#include "py/obj.h"

View File

@ -28,7 +28,8 @@
#include "common-hal/pwmio/PWMOut.h"
#include "shared-bindings/pwmio/PWMOut.h"
#include "py/runtime.h"
#include "components/driver/include/driver/ledc.h"
#include "driver/ledc.h"
#include "soc/soc.h"
#define INDEX_EMPTY 0xFF
@ -40,7 +41,7 @@ STATIC bool never_reset_chan[LEDC_CHANNEL_MAX];
STATIC uint32_t calculate_duty_cycle(uint32_t frequency) {
uint32_t duty_bits = 0;
uint32_t interval = LEDC_APB_CLK_HZ / frequency;
uint32_t interval = APB_CLK_FREQ / frequency;
for (size_t i = 0; i < 32; i++) {
if (!(interval >> i)) {
duty_bits = i - 1;

View File

@ -402,7 +402,7 @@ void common_hal_socketpool_socket_connect(socketpool_socket_obj_t *self,
#pragma GCC diagnostic ignored "-Wcast-align"
dest_addr.sin_addr.s_addr = ((struct sockaddr_in *)result_i->ai_addr)->sin_addr.s_addr;
#pragma GCC diagnostic pop
freeaddrinfo(result_i);
lwip_freeaddrinfo(result_i);
dest_addr.sin_family = AF_INET;
dest_addr.sin_port = htons(port);
@ -582,7 +582,7 @@ mp_uint_t common_hal_socketpool_socket_sendto(socketpool_socket_obj_t *self,
#pragma GCC diagnostic ignored "-Wcast-align"
dest_addr.sin_addr.s_addr = ((struct sockaddr_in *)result_i->ai_addr)->sin_addr.s_addr;
#pragma GCC diagnostic pop
freeaddrinfo(result_i);
lwip_freeaddrinfo(result_i);
dest_addr.sin_family = AF_INET;
dest_addr.sin_port = htons(port);

View File

@ -32,6 +32,7 @@
#include "common-hal/ssl/SSLContext.h"
#include "components/esp-tls/esp_tls.h"
#include "components/lwip/lwip/src/include/lwip/sockets.h"
typedef struct ssl_sslsocket_obj ssl_sslsocket_obj_t;

View File

@ -60,7 +60,7 @@ mp_obj_t common_hal_socketpool_socketpool_gethostbyname(socketpool_socketpool_ob
.ai_socktype = SOCK_STREAM,
};
struct addrinfo *res;
int err = getaddrinfo(host, NULL, &hints, &res);
int err = lwip_getaddrinfo(host, NULL, &hints, &res);
if (err != 0 || res == NULL) {
return mp_const_none;
}
@ -72,7 +72,7 @@ mp_obj_t common_hal_socketpool_socketpool_gethostbyname(socketpool_socketpool_ob
char ip_str[IP4ADDR_STRLEN_MAX];
inet_ntoa_r(*addr, ip_str, IP4ADDR_STRLEN_MAX);
mp_obj_t ip_obj = mp_obj_new_str(ip_str, strlen(ip_str));
freeaddrinfo(res);
lwip_freeaddrinfo(res);
return ip_obj;
}

View File

@ -32,6 +32,7 @@
#include "components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h"
#include "py/runtime.h"
#include "lwip/sockets.h"
void common_hal_ssl_sslcontext_construct(ssl_sslcontext_obj_t *self) {

View File

@ -34,6 +34,7 @@
#include "py/mperrno.h"
#include "py/runtime.h"
#include "supervisor/shared/tick.h"
#include "lwip/sockets.h"
ssl_sslsocket_obj_t *common_hal_ssl_sslsocket_accept(ssl_sslsocket_obj_t *self,
uint8_t *ip, uint32_t *port) {
@ -60,7 +61,7 @@ void common_hal_ssl_sslsocket_connect(ssl_sslsocket_obj_t *self,
if (result < 0) {
int esp_tls_code;
int flags;
esp_err_t err = esp_tls_get_and_clear_last_error(self->tls->error_handle, &esp_tls_code, &flags);
esp_err_t err = esp_tls_get_and_clear_last_error(self->tls_error_handle, &esp_tls_code, &flags);
if (err == ESP_ERR_MBEDTLS_SSL_SETUP_FAILED) {
mp_raise_espidf_MemoryError();
@ -154,7 +155,7 @@ mp_uint_t common_hal_ssl_sslsocket_send(ssl_sslsocket_obj_t *self, const uint8_t
if (sent < 0) {
int esp_tls_code;
int flags;
esp_err_t err = esp_tls_get_and_clear_last_error(self->tls->error_handle, &esp_tls_code, &flags);
esp_err_t err = esp_tls_get_and_clear_last_error(self->tls_error_handle, &esp_tls_code, &flags);
if (err == ESP_ERR_MBEDTLS_SSL_SETUP_FAILED) {
mp_raise_espidf_MemoryError();

View File

@ -38,6 +38,7 @@ typedef struct ssl_sslsocket_obj {
mp_obj_base_t base;
socketpool_socket_obj_t *sock;
esp_tls_t *tls;
esp_tls_error_handle_t tls_error_handle;
ssl_sslcontext_obj_t *ssl_context;
esp_tls_cfg_t ssl_config;
} ssl_sslsocket_obj_t;

View File

@ -62,7 +62,12 @@ void watchdog_reset(void) {
static void wdt_config(watchdog_watchdogtimer_obj_t *self) {
// enable panic hanler in WATCHDOGMODE_RESET mode
// initialize Task Watchdog Timer (TWDT)
if (esp_task_wdt_init((uint32_t)self->timeout, (self->mode == WATCHDOGMODE_RESET)) != ESP_OK) {
esp_task_wdt_config_t twdt_config = {
.timeout_ms = (uint32_t)self->timeout,
.idle_core_mask = (1 << portNUM_PROCESSORS) - 1, // Bitmask of all cores
.trigger_panic = (self->mode == WATCHDOGMODE_RESET),
};
if (esp_task_wdt_init(&twdt_config) != ESP_OK) {
mp_raise_RuntimeError(translate("Initialization failed due to lack of memory"));
}
esp_task_wdt_add(NULL);

View File

@ -44,7 +44,7 @@
#include "components/lwip/include/apps/ping/ping_sock.h"
#if CIRCUITPY_MDNS
#include "components/mdns/include/mdns.h"
#include "mdns.h"
#endif
#define MAC_ADDRESS_LENGTH 6

View File

@ -34,6 +34,8 @@
#include "shared-bindings/wifi/ScannedNetworks.h"
#include "shared-bindings/wifi/Network.h"
#include "esp_netif_types.h"
// Event bits for the Radio event group.
#define WIFI_SCAN_DONE_BIT BIT0
#define WIFI_CONNECTED_BIT BIT1

View File

@ -121,7 +121,7 @@ static void event_handler(void *arg, esp_event_base_t event_base,
// Cases to handle later.
// case WIFI_EVENT_STA_AUTHMODE_CHANGE:
default: {
ESP_LOGW(TAG, "event %d 0x%02x", event_id, event_id);
ESP_LOGW(TAG, "event %ld 0x%02ld", event_id, event_id);
break;
}
}

@ -1 +1 @@
Subproject commit 69f9a4f566d49afe97fd8b47444bd394af005e23
Subproject commit f2ee41e622694ead7caa3dcac0d04c96c5a7b027

View File

@ -1,171 +1,4 @@
CONFIG_IDF_TARGET_ARCH_RISCV=y
CONFIG_IDF_TARGET="esp32c3"
CONFIG_IDF_TARGET_ESP32C3=y
CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
# SDK tool configuration
#
CONFIG_SDK_TOOLPREFIX="riscv32-esp-elf-"
# end of SDK tool configuration
#
# Bootloader config
#
CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0
# end of Bootloader config
#
# Component config
#
#
# Bluetooth
#
CONFIG_BT_SOC_SUPPORT_5_0=y
#
# NimBLE Options
#
CONFIG_BT_NIMBLE_PINNED_TO_CORE=0
# end of NimBLE Options
# end of Bluetooth
#
# ESP32C3-Specific
#
# CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 is not set
CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y
CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32C3_REV_MIN_0 is not set
# CONFIG_ESP32C3_REV_MIN_1 is not set
# CONFIG_ESP32C3_REV_MIN_2 is not set
CONFIG_ESP32C3_REV_MIN_3=y
CONFIG_ESP32C3_REV_MIN=3
CONFIG_ESP32C3_DEBUG_OCDAWARE=y
CONFIG_ESP32C3_BROWNOUT_DET=y
CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set
CONFIG_ESP32C3_BROWNOUT_DET_LVL=7
CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y
# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set
# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set
# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set
CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y
# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set
# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024
# end of ESP32C3-Specific
#
# Hardware Settings
#
#
# MAC Config
#
# CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO is not set
CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR=y
CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES=4
# end of MAC Config
#
# Sleep Config
#
CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y
# end of Sleep Config
# end of Hardware Settings
#
# PHY
#
CONFIG_ESP_PHY_ENABLE_USB=y
# end of PHY
#
# ESP System Settings
#
CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
#
# Memory protection
#
CONFIG_ESP_SYSTEM_MEMPROT_DEPCHECK=y
CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y
CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y
CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE=512
# end of Memory protection
CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y
# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set
CONFIG_ESP_MAIN_TASK_AFFINITY=0x0
CONFIG_ESP_CONSOLE_SECONDARY_NONE=y
# CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG is not set
# end of ESP System Settings
#
# Wi-Fi
#
CONFIG_ESP32_WIFI_ENABLED=y
CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE=y
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=4
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=8
# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=16
# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
CONFIG_ESP32_WIFI_TX_BA_WIN=6
CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
CONFIG_ESP32_WIFI_RX_BA_WIN=6
# CONFIG_ESP32_WIFI_NVS_ENABLED is not set
CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
CONFIG_ESP32_WIFI_IRAM_OPT=y
CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
# CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE is not set
# end of Wi-Fi
#
# FreeRTOS
#
CONFIG_FREERTOS_UNICORE=y
CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
# end of FreeRTOS
# end of Component config
#
# Deprecated options for backward compatibility
#
CONFIG_TOOLPREFIX="riscv32-esp-elf-"
# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
CONFIG_ESP32_APPTRACE_DEST_NONE=y
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
CONFIG_NIMBLE_PINNED_TO_CORE=0
CONFIG_ESP_SYSTEM_PD_FLASH=y
CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
CONFIG_ESP32_PHY_MAX_TX_POWER=20
CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y
CONFIG_ESP32H2_MEMPROT_FEATURE=y
CONFIG_ESP32H2_MEMPROT_FEATURE_LOCK=y
# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
CONFIG_ESP32_PTHREAD_STACK_MIN=768
CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
# end of Deprecated options for backward compatibility

View File

@ -1,167 +1,11 @@
#
# Espressif IoT Development Framework (ESP-IDF) Project Configuration
#
CONFIG_IDF_TARGET_ARCH_XTENSA=y
CONFIG_IDF_TARGET="esp32s2"
CONFIG_IDF_TARGET_ESP32S2=y
CONFIG_IDF_FIRMWARE_CHIP_ID=0x0002
# end of Espressif IoT Development Framework (ESP-IDF) Project Configuration
CONFIG_SDK_TOOLPREFIX="xtensa-esp32s2-elf-"
#
# Bootloader config
#
CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000
# end of Bootloader config
# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_80 is not set
#
# ESP32S2-specific
#
# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160 is not set
CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240=y
CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ=240
# end of ESP32S2-specific
# CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB is not set
#
# Cache config
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_ESP32S2_INSTRUCTION_CACHE_16KB=y
# CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B is not set
CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B=y
# CONFIG_ESP32S2_DATA_CACHE_0KB is not set
# CONFIG_ESP32S2_DATA_CACHE_8KB is not set
CONFIG_ESP32S2_DATA_CACHE_16KB=y
# CONFIG_ESP32S2_DATA_CACHE_LINE_16B is not set
CONFIG_ESP32S2_DATA_CACHE_LINE_32B=y
# CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP is not set
# CONFIG_ESP32S2_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S2_TRAX is not set
CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM=0x0
CONFIG_ESP32S2_ULP_COPROC_ENABLED=y
CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=8176
CONFIG_ESP32S2_ULP_COPROC_RISCV=y
CONFIG_ESP32S2_DEBUG_OCDAWARE=y
# CONFIG_ESP32S2_DEBUG_STUBS_ENABLE is not set
CONFIG_ESP32S2_BROWNOUT_DET=y
CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_2 is not set
# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_1 is not set
CONFIG_ESP32S2_BROWNOUT_DET_LVL=7
CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1=y
# CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC is not set
# CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 is not set
# CONFIG_ESP32S2_TIME_SYSCALL_USE_NONE is not set
CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y
# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS is not set
# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576
# CONFIG_ESP32S2_NO_BLOBS is not set
# CONFIG_ESP32S2_KEEP_USB_ALIVE is not set
CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y
# CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE is not set
#
# MAC Config
#
# CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE is not set
CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO=y
CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES=2
# end of MAC Config
CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
#
# Sleep Config
#
# CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set
# end of Sleep Config
#
# PHY
#
# CONFIG_ESP_PHY_ENABLE_USB is not set
# end of PHY
CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
#
# Memory protection
#
CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y
CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y
CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE=4
# end of Memory protection
CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y
# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set
CONFIG_ESP_MAIN_TASK_AFFINITY=0x0
#
# Wi-Fi
#
CONFIG_ESP32_WIFI_ENABLED=y
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=4
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=8
# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=16
CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=16
# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
CONFIG_ESP32_WIFI_TX_BA_WIN=6
CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
CONFIG_ESP32_WIFI_RX_BA_WIN=6
# CONFIG_ESP32_WIFI_NVS_ENABLED is not set
CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
CONFIG_ESP32_WIFI_IRAM_OPT=y
CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
# CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE is not set
# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
# end of Wi-Fi
CONFIG_FREERTOS_UNICORE=y
#
# FreeRTOS
#
CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
CONFIG_FREERTOS_CORETIMER_0=y
# CONFIG_FREERTOS_CORETIMER_1 is not set
CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
# end of FreeRTOS
CONFIG_MBEDTLS_HARDWARE_GCM=y
#
# Deprecated options for backward compatibility
#
CONFIG_TOOLPREFIX="xtensa-esp32s2-elf-"
# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
CONFIG_ESP32_APPTRACE_DEST_NONE=y
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
CONFIG_ESP_SYSTEM_PD_FLASH=y
# CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND is not set
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
CONFIG_ESP32_PHY_MAX_TX_POWER=20
CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y
CONFIG_ESP32H2_MEMPROT_FEATURE=y
CONFIG_ESP32H2_MEMPROT_FEATURE_LOCK=y
# CONFIG_EXTERNAL_COEX_ENABLE is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
CONFIG_ESP32_PTHREAD_STACK_MIN=768
CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
# end of Deprecated options for backward compatibility
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_TYPE_RISCV=y
CONFIG_ULP_COPROC_RESERVE_MEM=8176

View File

@ -1,221 +1,12 @@
CONFIG_IDF_TARGET_ARCH_XTENSA=y
CONFIG_IDF_TARGET="esp32s3"
CONFIG_IDF_TARGET_ESP32S3=y
CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
# SDK tool configuration
#
CONFIG_SDK_TOOLPREFIX="xtensa-esp32s3-elf-"
# end of SDK tool configuration
#
# Bootloader config
#
CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0
# end of Bootloader config
#
# Component config
#
#
# Bluetooth
#
CONFIG_BT_SOC_SUPPORT_5_0=y
#
# NimBLE Options
#
# CONFIG_BT_NIMBLE_PINNED_TO_CORE_0 is not set
CONFIG_BT_NIMBLE_PINNED_TO_CORE_1=y
CONFIG_BT_NIMBLE_PINNED_TO_CORE=1
# end of NimBLE Options
# end of Bluetooth
#
# ESP32S3-Specific
#
# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set
# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160 is not set
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240=y
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=240
#
# Cache config
#
CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y
# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set
CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000
# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set
CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y
CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8
# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set
CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y
CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP is not set
# CONFIG_ESP32S3_DATA_CACHE_16KB is not set
CONFIG_ESP32S3_DATA_CACHE_32KB=y
# CONFIG_ESP32S3_DATA_CACHE_64KB is not set
CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000
# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set
CONFIG_ESP32S3_DATA_CACHE_8WAYS=y
CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8
# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set
CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y
# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set
CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
CONFIG_ESP32S3_ULP_COPROC_ENABLED=y
CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=8176
CONFIG_ESP32S3_ULP_COPROC_RISCV=y
CONFIG_ESP32S3_BROWNOUT_DET=y
CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set
# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set
CONFIG_ESP32S3_BROWNOUT_DET_LVL=7
CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y
# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set
# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set
# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set
CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y
# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set
# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM=y
# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set
# end of ESP32S3-Specific
#
# Hardware Settings
#
#
# MAC Config
#
# CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set
CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y
CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4
# end of MAC Config
#
# Sleep Config
#
CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y
# end of Sleep Config
# end of Hardware Settings
#
# PHY
#
CONFIG_ESP_PHY_ENABLE_USB=y
# end of PHY
#
# ESP System Settings
#
# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 is not set
CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1=y
# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set
CONFIG_ESP_MAIN_TASK_AFFINITY=0x1
# end of ESP System Settings
#
# Wi-Fi
#
CONFIG_ESP32_WIFI_ENABLED=y
CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE=y
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=4
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=8
# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=16
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=16
# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
CONFIG_ESP32_WIFI_TX_BA_WIN=6
CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
CONFIG_ESP32_WIFI_RX_BA_WIN=6
# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set
# CONFIG_ESP32_WIFI_NVS_ENABLED is not set
CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
CONFIG_ESP32_WIFI_IRAM_OPT=y
CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
# CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE is not set
# end of Wi-Fi
CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM=y
#
# FreeRTOS
#
# CONFIG_FREERTOS_UNICORE is not set
# end of FreeRTOS
# end of Component config
#
# Deprecated options for backward compatibility
#
CONFIG_TOOLPREFIX="xtensa-esp32s3-elf-"
# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
CONFIG_ESP32_APPTRACE_DEST_NONE=y
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
# CONFIG_NIMBLE_PINNED_TO_CORE_0 is not set
CONFIG_NIMBLE_PINNED_TO_CORE_1=y
CONFIG_NIMBLE_PINNED_TO_CORE=1
CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
CONFIG_ESP32_PHY_MAX_TX_POWER=20
CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y
# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
CONFIG_ESP32_PTHREAD_STACK_MIN=768
CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y
# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set
# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set
CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
# end of Deprecated options for backward compatibility
#
# Camera configuration
#
CONFIG_OV7670_SUPPORT=y
# CONFIG_OV7725_SUPPORT is not set
# CONFIG_NT99141_SUPPORT is not set
CONFIG_OV2640_SUPPORT=y
CONFIG_OV3660_SUPPORT=y
CONFIG_OV5640_SUPPORT=y
# CONFIG_GC2145_SUPPORT is not set
# CONFIG_GC032A_SUPPORT is not set
# CONFIG_GC0308_SUPPORT is not set
# CONFIG_BF3005_SUPPORT is not set
# CONFIG_BF20A6_SUPPORT is not set
# CONFIG_SC101IOT_SUPPORT is not set
# CONFIG_SC030IOT_SUPPORT is not set
# CONFIG_SCCB_HARDWARE_I2C_PORT0 is not set
CONFIG_SCCB_HARDWARE_I2C_PORT1=y
CONFIG_SCCB_CLK_FREQ=100000
CONFIG_CAMERA_CORE0=y
# CONFIG_CAMERA_CORE1 is not set
# CONFIG_CAMERA_NO_AFFINITY is not set
CONFIG_CAMERA_DMA_BUFFER_SIZE_MAX=32768
# CONFIG_CAMERA_CONVERTER_ENABLED is not set
# end of Camera configuration
# end of Component config
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_TYPE_RISCV=y
CONFIG_ULP_COPROC_RESERVE_MEM=8176

View File

@ -1,118 +1,15 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
# Bootloader config
#
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set
CONFIG_BOOTLOADER_LOG_LEVEL_NONE=y
# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_INFO is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set
# end of Bootloader config
#
# Compiler options
#
# CONFIG_COMPILER_OPTIMIZATION_DEFAULT is not set
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
# CONFIG_COMPILER_OPTIMIZATION_PERF is not set
# CONFIG_COMPILER_OPTIMIZATION_NONE is not set
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE is not set
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=1
# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
# end of Compiler options
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
#
# Component config
#
#
# ESP32S3-Specific
#
CONFIG_ESP32S3_DEBUG_OCDAWARE=y
# end of ESP32S3-Specific
#
# Common ESP-related
#
# CONFIG_ESP_ERR_TO_NAME_LOOKUP is not set
# end of Common ESP-related
#
# ESP System Settings
#
# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
# CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT is not set
CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT=y
# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
# CONFIG_ESP_CONSOLE_UART_DEFAULT is not set
# CONFIG_ESP_CONSOLE_USB_CDC is not set
# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set
# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set
CONFIG_ESP_CONSOLE_NONE=y
# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set
CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y
CONFIG_ESP_CONSOLE_MULTIPLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=-1
# end of ESP System Settings
#
# FreeRTOS
#
CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
# CONFIG_FREERTOS_ASSERT_DISABLE is not set
CONFIG_FREERTOS_DEBUG_OCDAWARE=y
# end of FreeRTOS
CONFIG_ESP_ERR_TO_NAME_LOOKUP=n
#
# Hardware Abstraction Layer (HAL) and Low Level (LL)
#
CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
# CONFIG_HAL_ASSERTION_DISABLE is not set
# CONFIG_HAL_ASSERTION_SILIENT is not set
CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=1
# end of Hardware Abstraction Layer (HAL) and Low Level (LL)
CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT=y
#
# Log output
#
CONFIG_LOG_DEFAULT_LEVEL_NONE=y
# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set
# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set
# CONFIG_LOG_DEFAULT_LEVEL_INFO is not set
# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set
# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set
# end of Log output
#
# LWIP
#
CONFIG_LWIP_ESP_LWIP_ASSERT=y
# end of LWIP
# end of Component config
#
# Deprecated options for backward compatibility
#
# CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set
CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y
# CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED is not set
CONFIG_OPTIMIZATION_ASSERTIONS_SILENT=y
# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set
CONFIG_OPTIMIZATION_ASSERTION_LEVEL=1
# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
# CONFIG_ESP32S2_PANIC_PRINT_REBOOT is not set
CONFIG_ESP32S2_PANIC_SILENT_REBOOT=y
# CONFIG_ESP32S2_PANIC_GDBSTUB is not set
# CONFIG_CONSOLE_UART_DEFAULT is not set
# CONFIG_CONSOLE_UART_CUSTOM is not set
CONFIG_ESP_CONSOLE_UART_NONE=y
CONFIG_CONSOLE_UART_NUM=-1
# end of Deprecated options for backward compatibility

View File

@ -1,877 +1,56 @@
CONFIG_IDF_CMAKE=y
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
# SDK tool configuration
#
# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
# end of SDK tool configuration
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
#
# Build type
#
CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
CONFIG_APP_BUILD_GENERATE_BINARIES=y
CONFIG_APP_BUILD_BOOTLOADER=y
CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
# end of Build type
#
# Application manager
#
CONFIG_APP_COMPILE_TIME_DATE=y
# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
# end of Application manager
#
# Bootloader config
#
# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set
CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y
# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set
CONFIG_BOOTLOADER_LOG_LEVEL=3
# CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V is not set
CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y
# CONFIG_BOOTLOADER_FACTORY_RESET is not set
# CONFIG_BOOTLOADER_APP_TEST is not set
CONFIG_BOOTLOADER_WDT_ENABLE=y
# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set
CONFIG_BOOTLOADER_WDT_TIME_MS=9000
# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set
CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0
# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set
CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
# end of Bootloader config
#
# Security features
#
CONFIG_SECURE_BOOT_SUPPORTS_RSA=y
CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y
# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
# CONFIG_SECURE_BOOT is not set
# CONFIG_SECURE_FLASH_ENC_ENABLED is not set
# end of Security features
#
# Boot ROM Behavior
#
CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y
# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set
# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set
# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set
# end of Boot ROM Behavior
#
# Serial flasher config
#
CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
# CONFIG_ESPTOOLPY_NO_STUB is not set
# CONFIG_ESPTOOLPY_OCT_FLASH is not set
# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set
CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
CONFIG_ESPTOOLPY_FLASHMODE="dio"
# CONFIG_ESPTOOLPY_FLASHFREQ_120M is not set
# CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set
CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
CONFIG_ESPTOOLPY_FLASHFREQ="40m"
CONFIG_ESPTOOLPY_BEFORE_RESET=y
# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
CONFIG_ESPTOOLPY_BEFORE="default_reset"
CONFIG_ESPTOOLPY_AFTER_RESET=y
# CONFIG_ESPTOOLPY_AFTER_NORESET is not set
CONFIG_ESPTOOLPY_AFTER="hard_reset"
# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
# end of Serial flasher config
#
# Partition Table
#
# CONFIG_PARTITION_TABLE_SINGLE_APP is not set
# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set
# CONFIG_PARTITION_TABLE_TWO_OTA is not set
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_OFFSET=0x8000
CONFIG_PARTITION_TABLE_MD5=y
# end of Partition Table
#
# Compiler options
#
CONFIG_COMPILER_HIDE_PATHS_MACROS=y
# CONFIG_COMPILER_CXX_EXCEPTIONS is not set
# CONFIG_COMPILER_CXX_RTTI is not set
CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set
# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set
# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
# CONFIG_COMPILER_DUMP_RTL_FILES is not set
# end of Compiler options
#
# Component config
#
#
# Application Level Tracing
#
# CONFIG_APPTRACE_DEST_JTAG is not set
CONFIG_APPTRACE_DEST_NONE=y
CONFIG_APPTRACE_LOCK_ENABLE=y
# end of Application Level Tracing
# CONFIG_BLE_MESH is not set
#
# Driver configurations
#
#
# ADC configuration
#
# CONFIG_ADC_FORCE_XPD_FSM is not set
CONFIG_ADC_DISABLE_DAC=y
# end of ADC configuration
#
# MCPWM configuration
#
# CONFIG_MCPWM_ISR_IN_IRAM is not set
# end of MCPWM configuration
#
# SPI configuration
#
# CONFIG_SPI_MASTER_IN_IRAM is not set
CONFIG_SPI_MASTER_ISR_IN_IRAM=y
# CONFIG_SPI_SLAVE_IN_IRAM is not set
CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
# end of SPI configuration
#
# TWAI configuration
#
# CONFIG_TWAI_ISR_IN_IRAM is not set
# end of TWAI configuration
#
# UART configuration
#
# CONFIG_UART_ISR_IN_IRAM is not set
# end of UART configuration
#
# GDMA Configuration
#
# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
# CONFIG_GDMA_ISR_IRAM_SAFE is not set
# end of GDMA Configuration
# end of Driver configurations
#
# eFuse Bit Manager
#
# CONFIG_EFUSE_CUSTOM_TABLE is not set
# CONFIG_EFUSE_VIRTUAL is not set
CONFIG_EFUSE_MAX_BLK_LEN=256
# end of eFuse Bit Manager
#
# ESP-TLS
#
CONFIG_ESP_TLS_USING_MBEDTLS=y
CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
CONFIG_ESP_TLS_SERVER=y
# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
# CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set
# CONFIG_ESP_TLS_PSK_VERIFICATION is not set
# CONFIG_ESP_TLS_INSECURE is not set
# end of ESP-TLS
#
# Ethernet
#
# CONFIG_ETH_USE_SPI_ETHERNET is not set
# CONFIG_ETH_USE_OPENETH is not set
# end of Ethernet
#
# Event Loop Library
#
# CONFIG_ESP_EVENT_LOOP_PROFILING is not set
CONFIG_ESP_EVENT_POST_FROM_ISR=y
CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y
# end of Event Loop Library
#
# Hardware Settings
#
#
# MAC Config
#
CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
# end of MAC Config
#
# Sleep Config
#
CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y
# CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND is not set
# CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND is not set
# end of Sleep Config
#
# RTC Clock Config
#
CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB=y
# end of RTC Clock Config
# end of Hardware Settings
#
# IPC (Inter-Processor Call)
#
CONFIG_ESP_IPC_TASK_STACK_SIZE=1536
CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
CONFIG_ESP_IPC_ISR_ENABLE=y
# end of IPC (Inter-Processor Call)
#
# ESP NETIF Adapter
#
CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
CONFIG_ESP_NETIF_TCPIP_LWIP=y
# CONFIG_ESP_NETIF_LOOPBACK is not set
# CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER is not set
# end of ESP NETIF Adapter
#
# PHY
#
CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
CONFIG_ESP_PHY_MAX_TX_POWER=20
# end of PHY
#
# Power Management
#
# CONFIG_PM_ENABLE is not set
CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y
# end of Power Management
#
# ESP System Settings
#
# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304
CONFIG_ESP_MAIN_TASK_STACK_SIZE=16384
CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048
CONFIG_ESP_INT_WDT=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
CONFIG_ESP_INT_WDT_CHECK_CPU1=y
# CONFIG_ESP_TASK_WDT is not set
# CONFIG_ESP_PANIC_HANDLER_IRAM is not set
# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
# end of ESP System Settings
#
# High resolution timer (esp_timer)
#
# CONFIG_ESP_TIMER_PROFILING is not set
CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584
CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
# end of High resolution timer (esp_timer)
CONFIG_ESP_TASK_WDT=n
#
# Wi-Fi
#
# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
# CONFIG_ESP_WIFI_FTM_ENABLE is not set
# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set
# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
# end of Wi-Fi
CONFIG_ESP_TLS_SERVER=y
#
# Core dump
#
# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set
# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set
CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y
# end of Core dump
#
# FreeRTOS
#
CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
CONFIG_FREERTOS_HZ=100
# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
CONFIG_FREERTOS_ISR_STACKSIZE=1536
# CONFIG_FREERTOS_LEGACY_HOOKS is not set
CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set
# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set
CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
# CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
# end of FreeRTOS
#
# Heap memory debugging
#
CONFIG_HEAP_POISONING_DISABLED=y
# CONFIG_HEAP_POISONING_LIGHT is not set
# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set
CONFIG_HEAP_TRACING_OFF=y
# CONFIG_HEAP_TRACING_STANDALONE is not set
# CONFIG_HEAP_TRACING_TOHOST is not set
# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
# end of Heap memory debugging
#
# Log output
#
# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set
# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set
# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set
CONFIG_LOG_DEFAULT_LEVEL_INFO=y
# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set
# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set
CONFIG_LOG_DEFAULT_LEVEL=3
CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y
# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set
# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set
CONFIG_LOG_MAXIMUM_LEVEL=3
CONFIG_LOG_COLORS=y
CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set
# end of Log output
#
# LWIP
#
# CONFIG_LWIP_NETIF_API is not set
# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set
CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
# CONFIG_LWIP_L2_TO_L3_COPY is not set
# CONFIG_LWIP_IRAM_OPTIMIZATION is not set
CONFIG_LWIP_TIMERS_ONDEMAND=y
CONFIG_LWIP_MAX_SOCKETS=8
# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set
# CONFIG_LWIP_SO_LINGER is not set
CONFIG_LWIP_SO_REUSE=y
CONFIG_LWIP_SO_REUSE_RXTOALL=y
CONFIG_LWIP_SO_RCVBUF=y
# CONFIG_LWIP_NETBUF_RECVINFO is not set
CONFIG_LWIP_IP4_FRAG=y
CONFIG_LWIP_IP6_FRAG=y
# CONFIG_LWIP_IP4_REASSEMBLY is not set
# CONFIG_LWIP_IP6_REASSEMBLY is not set
# CONFIG_LWIP_IP_FORWARD is not set
# CONFIG_LWIP_STATS is not set
# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
CONFIG_LWIP_GARP_TMR_INTERVAL=60
CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
CONFIG_LWIP_DHCP_OPTIONS_LEN=68
#
# DHCP server
#
CONFIG_LWIP_DHCPS=y
CONFIG_LWIP_DHCPS_LEASE_UNIT=60
CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
# end of DHCP server
# CONFIG_LWIP_AUTOIP is not set
CONFIG_LWIP_IPV6=y
# CONFIG_LWIP_IPV6_AUTOCONFIG is not set
CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
# CONFIG_LWIP_IPV6_FORWARD is not set
# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=y
CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8
#
# TCP
#
CONFIG_LWIP_MAX_ACTIVE_TCP=4
CONFIG_LWIP_MAX_LISTENING_TCP=4
CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y
CONFIG_LWIP_TCP_MAXRTX=12
CONFIG_LWIP_TCP_SYNMAXRTX=6
CONFIG_LWIP_TCP_MSS=1440
CONFIG_LWIP_TCP_TMR_INTERVAL=250
CONFIG_LWIP_TCP_MSL=60000
CONFIG_LWIP_TCP_SND_BUF_DEFAULT=2880
CONFIG_LWIP_TCP_WND_DEFAULT=2880
CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
# CONFIG_LWIP_TCP_SACK_OUT is not set
# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
CONFIG_LWIP_TCP_OVERSIZE_MSS=y
# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
CONFIG_LWIP_MAX_SOCKETS=8
CONFIG_LWIP_SO_RCVBUF=y
CONFIG_LWIP_TCP_RTO_TIME=3000
# end of TCP
#
# UDP
#
CONFIG_LWIP_MAX_UDP_PCBS=16
CONFIG_LWIP_UDP_RECVMBOX_SIZE=6
# end of UDP
CONFIG_LWIP_TCP_SND_BUF_DEFAULT=2880
CONFIG_LWIP_TCP_SYNMAXRTX=6
CONFIG_LWIP_TCP_WND_DEFAULT=2880
#
# Checksums
#
# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set
# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set
CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y
# end of Checksums
CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072
CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set
# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set
CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF
# CONFIG_LWIP_PPP_SUPPORT is not set
CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3
CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5
# CONFIG_LWIP_SLIP_SUPPORT is not set
#
# ICMP
#
CONFIG_LWIP_ICMP=y
# CONFIG_LWIP_MULTICAST_PING is not set
# CONFIG_LWIP_BROADCAST_PING is not set
# end of ICMP
#
# LWIP RAW API
#
CONFIG_LWIP_MAX_RAW_PCBS=16
# end of LWIP RAW API
#
# SNTP
#
CONFIG_LWIP_SNTP_MAX_SERVERS=1
# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set
CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
# end of SNTP
#
# Hooks
#
# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set
CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y
# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set
CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y
# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set
# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set
CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set
# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set
CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
# end of Hooks
# CONFIG_LWIP_DEBUG is not set
# end of LWIP
#
# mbedTLS
#
CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set
# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set
CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y
CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384
CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=2048
# CONFIG_MBEDTLS_DEBUG is not set
#
# mbedTLS v2.28.x related
#
# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
CONFIG_MBEDTLS_ECDH_LEGACY_CONTEXT=y
# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
#
# DTLS-based configurations
#
# CONFIG_MBEDTLS_SSL_DTLS_CONNECTION_ID is not set
# CONFIG_MBEDTLS_SSL_DTLS_SRTP is not set
# end of DTLS-based configurations
# end of mbedTLS v2.28.x related
#
# Certificate Bundle
#
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y
# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL is not set
# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE=y
CONFIG_MBEDTLS_CMAC_C=y
CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE=y
CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE_PATH="../../lib/certificates/data/roots.pem"
# end of Certificate Bundle
CONFIG_MBEDTLS_ECP_RESTARTABLE=y
CONFIG_MBEDTLS_CMAC_C=y
CONFIG_MBEDTLS_HARDWARE_AES=y
CONFIG_MBEDTLS_AES_USE_INTERRUPT=y
CONFIG_MBEDTLS_HARDWARE_MPI=y
CONFIG_MBEDTLS_HARDWARE_SHA=y
CONFIG_MBEDTLS_ROM_MD5=y
# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
CONFIG_MBEDTLS_HAVE_TIME=y
# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
CONFIG_MBEDTLS_SHA512_C=y
CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set
# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set
# CONFIG_MBEDTLS_TLS_DISABLED is not set
CONFIG_MBEDTLS_TLS_SERVER=y
CONFIG_MBEDTLS_TLS_CLIENT=y
CONFIG_MBEDTLS_TLS_ENABLED=y
#
# TLS Key Exchange Methods
#
CONFIG_MBEDTLS_PSK_MODES=y
CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y
CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK=y
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK=y
CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y
CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK=y
CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
# end of TLS Key Exchange Methods
CONFIG_MBEDTLS_PSK_MODES=y
CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
# CONFIG_MBEDTLS_SSL_PROTO_TLS1 is not set
# CONFIG_MBEDTLS_SSL_PROTO_TLS1_1 is not set
CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=2048
CONFIG_MBEDTLS_SSL_PROTO_DTLS=y
CONFIG_MBEDTLS_SSL_ALPN=y
CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
#
# Symmetric Ciphers
#
CONFIG_MBEDTLS_AES_C=y
# CONFIG_MBEDTLS_CAMELLIA_C is not set
# CONFIG_MBEDTLS_DES_C is not set
CONFIG_MBEDTLS_RC4_DISABLED=y
# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
# CONFIG_MBEDTLS_RC4_ENABLED is not set
# CONFIG_MBEDTLS_BLOWFISH_C is not set
# CONFIG_MBEDTLS_XTEA_C is not set
CONFIG_MBEDTLS_CCM_C=y
CONFIG_MBEDTLS_GCM_C=y
# CONFIG_MBEDTLS_NIST_KW_C is not set
# end of Symmetric Ciphers
# CONFIG_MBEDTLS_RIPEMD160_C is not set
#
# Certificates
#
CONFIG_MBEDTLS_PEM_PARSE_C=y
CONFIG_MBEDTLS_PEM_WRITE_C=y
CONFIG_MBEDTLS_X509_CRL_PARSE_C=y
CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
# end of Certificates
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_MBEDTLS_ECP_C=y
CONFIG_MBEDTLS_ECDH_C=y
CONFIG_MBEDTLS_ECDSA_C=y
# CONFIG_MBEDTLS_ECJPAKE_C is not set
CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y
CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y
CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
# CONFIG_MBEDTLS_POLY1305_C is not set
# CONFIG_MBEDTLS_CHACHA20_C is not set
# CONFIG_MBEDTLS_HKDF_C is not set
# CONFIG_MBEDTLS_THREADING_C is not set
# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set
# CONFIG_MBEDTLS_SECURITY_RISKS is not set
# end of mbedTLS
#
# mDNS
#
CONFIG_MDNS_MAX_SERVICES=10
CONFIG_MDNS_TASK_PRIORITY=1
CONFIG_MDNS_TASK_STACK_SIZE=4096
# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
CONFIG_MDNS_TASK_AFFINITY_CPU0=y
# CONFIG_MDNS_TASK_AFFINITY_CPU1 is not set
CONFIG_MDNS_TASK_AFFINITY=0x0
CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
# CONFIG_MDNS_STRICT_MODE is not set
CONFIG_MDNS_TIMER_PERIOD_MS=100
# CONFIG_MDNS_NETWORKING_SOCKET is not set
CONFIG_MDNS_MULTIPLE_INSTANCE=y
# end of mDNS
#
# Newlib
#
CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set
# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set
# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set
# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
# CONFIG_NEWLIB_NANO_FORMAT is not set
# end of Newlib
#
# OpenThread
#
# CONFIG_OPENTHREAD_ENABLED is not set
# end of OpenThread
#
# PThreads
#
CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5
CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
CONFIG_PTHREAD_STACK_MIN=768
CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y
# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set
# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set
CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
# end of PThreads
#
# SPI Flash driver
#
# CONFIG_SPI_FLASH_VERIFY_WRITE is not set
# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set
CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
# CONFIG_SPI_FLASH_ROM_IMPL is not set
CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set
# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
# CONFIG_SPI_FLASH_YIELD_DURING_ERASE is not set
CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=4096
# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set
# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
#
# Auto-detect flash chips
#
CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y
CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y
CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y
CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP=y
# end of Auto-detect flash chips
CONFIG_SPI_FLASH_YIELD_DURING_ERASE=n
CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y
# end of SPI Flash driver
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=4
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=8
CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=16
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=16
CONFIG_ESP32_WIFI_NVS_ENABLED=n
#
# Virtual file system
#
CONFIG_VFS_SUPPORT_IO=y
CONFIG_VFS_SUPPORT_DIR=y
CONFIG_VFS_SUPPORT_SELECT=y
CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y
CONFIG_VFS_SUPPORT_TERMIOS=y
#
# Host File System I/O (Semihosting)
#
CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1
CONFIG_VFS_SEMIHOSTFS_HOST_PATH_MAX_LEN=128
# end of Host File System I/O (Semihosting)
# end of Virtual file system
#
# Supplicant
#
CONFIG_WPA_MBEDTLS_CRYPTO=y
# CONFIG_WPA_WAPI_PSK is not set
# CONFIG_WPA_SUITE_B_192 is not set
# CONFIG_WPA_DEBUG_PRINT is not set
# CONFIG_WPA_TESTING_OPTIONS is not set
# CONFIG_WPA_WPS_STRICT is not set
# CONFIG_WPA_11KV_SUPPORT is not set
# end of Supplicant
# end of Component config
#
# Compatibility options
#
# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
# end of Compatibility options
#
# Deprecated options for backward compatibility
#
# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set
CONFIG_LOG_BOOTLOADER_LEVEL=3
# CONFIG_APP_ROLLBACK_ENABLE is not set
# CONFIG_FLASH_ENCRYPTION_ENABLED is not set
CONFIG_FLASHMODE_QIO=y
# CONFIG_FLASHMODE_QOUT is not set
# CONFIG_FLASHMODE_DIO is not set
# CONFIG_FLASHMODE_DOUT is not set
# CONFIG_MONITOR_BAUD_9600B is not set
# CONFIG_MONITOR_BAUD_57600B is not set
CONFIG_MONITOR_BAUD_115200B=y
# CONFIG_MONITOR_BAUD_230400B is not set
# CONFIG_MONITOR_BAUD_921600B is not set
# CONFIG_MONITOR_BAUD_2MB is not set
# CONFIG_MONITOR_BAUD_OTHER is not set
CONFIG_MONITOR_BAUD_OTHER_VAL=115200
CONFIG_MONITOR_BAUD=115200
# CONFIG_CXX_EXCEPTIONS is not set
CONFIG_STACK_CHECK_NONE=y
# CONFIG_STACK_CHECK_NORM is not set
# CONFIG_STACK_CHECK_STRONG is not set
# CONFIG_STACK_CHECK_ALL is not set
# CONFIG_WARN_WRITE_STRINGS is not set
# CONFIG_DISABLE_GCC8_WARNINGS is not set
CONFIG_ADC2_DISABLE_DAC=y
# CONFIG_EVENT_LOOP_PROFILING is not set
CONFIG_POST_EVENTS_FROM_ISR=y
CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
CONFIG_IPC_TASK_STACK_SIZE=1536
CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y
CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
CONFIG_MAIN_TASK_STACK_SIZE=8192
CONFIG_INT_WDT=y
CONFIG_INT_WDT_TIMEOUT_MS=300
CONFIG_INT_WDT_CHECK_CPU1=y
# CONFIG_TASK_WDT is not set
CONFIG_TIMER_TASK_STACK_SIZE=3584
# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
CONFIG_TIMER_TASK_PRIORITY=1
CONFIG_TIMER_TASK_STACK_DEPTH=2048
CONFIG_TIMER_QUEUE_LENGTH=10
# CONFIG_L2_TO_L3_COPY is not set
# CONFIG_USE_ONLY_LWIP_SELECT is not set
CONFIG_ESP_GRATUITOUS_ARP=y
CONFIG_GARP_TMR_INTERVAL=60
CONFIG_TCPIP_RECVMBOX_SIZE=32
CONFIG_TCP_MAXRTX=12
CONFIG_TCP_SYNMAXRTX=6
CONFIG_TCP_MSS=1440
CONFIG_TCP_MSL=60000
CONFIG_TCP_SND_BUF_DEFAULT=2880
CONFIG_TCP_WND_DEFAULT=2880
CONFIG_TCP_RECVMBOX_SIZE=6
CONFIG_TCP_QUEUE_OOSEQ=y
# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
CONFIG_TCP_OVERSIZE_MSS=y
# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
# CONFIG_TCP_OVERSIZE_DISABLE is not set
CONFIG_UDP_RECVMBOX_SIZE=6
CONFIG_TCPIP_TASK_STACK_SIZE=3072
CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set
CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
# CONFIG_PPP_SUPPORT is not set
CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
CONFIG_SUPPORT_TERMIOS=y
CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
CONFIG_SEMIHOSTFS_HOST_PATH_MAX_LEN=128
# end of Deprecated options for backward compatibility
CONFIG_ADC_SUPPRESS_DEPRECATE_WARN=y
CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN=y
CONFIG_RMT_SUPPRESS_DEPRECATE_WARN=y
CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN=y
CONFIG_I2S_SUPPRESS_DEPRECATE_WARN=y

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Subproject commit d07eb2733ca5d3379578f3952de04b4a4d188f36

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Subproject commit 457f8335bb876b8af80a65b096e5381f49f29878

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Subproject commit 2758089a06ccae79d8fcab6c93e2ca3761646f9f
Subproject commit 75035312ed9427557acfee1cd32af2b8e1f13f72

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2021 microDev
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// See https://github.com/espressif/esp-idf/issues/6906
#ifndef MICROPY_INCLUDED_ESPRESSIF_ESP32C3_FIX_H
#define MICROPY_INCLUDED_ESPRESSIF_ESP32C3_FIX_H
#ifdef __riscv
#undef __INT32_TYPE__
#define __INT32_TYPE__ int
#undef __UINT32_TYPE__
#define __UINT32_TYPE__ unsigned int
#endif // __riscv
#endif // MICROPY_INCLUDED_ESPRESSIF_ESP32C3_FIX_H

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/* *INDENT-OFF* */
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __I2S_LCD_DRIVER_H__
#define __I2S_LCD_DRIVER_H__
#include "driver/i2s.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define LCD_CMD_LEV (0)
#define LCD_DATA_LEV (1)
typedef void *i2s_lcd_handle_t; /** Handle of i2s lcd driver */
/**
* @brief Configuration of i2s lcd mode
*
*/
typedef struct {
int8_t data_width; /*!< Parallel data width, 16bit or 8bit available */
int8_t pin_data_num[16]; /*!< Parallel data output IO*/
int8_t pin_num_cs; /*!< CS io num */
int8_t pin_num_wr; /*!< Write clk io*/
int8_t pin_num_rs; /*!< RS io num */
int clk_freq; /*!< I2s clock frequency */
i2s_port_t i2s_port; /*!< I2S port number */
bool swap_data; /*!< Swap the 2 bytes of RGB565 color */
uint32_t buffer_size; /*!< DMA buffer size */
} i2s_lcd_config_t;
/**
* @brief Initialize i2s lcd driver.
*
* @param config configuration of i2s
*
* @return A handle to the created i2s lcd driver, or NULL in case of error.
*/
i2s_lcd_handle_t i2s_lcd_driver_init(const i2s_lcd_config_t *config);
/**
* @brief Deinit i2s lcd driver.
*
* @param handle i2s lcd driver handle to deinitilize
*
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG handle is invalid
*/
esp_err_t i2s_lcd_driver_deinit(i2s_lcd_handle_t handle);
/**
* @brief Write a data to LCD
*
* @param handle i2s lcd driver handle
* @param data Data to write
*
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG handle is invalid
*/
esp_err_t i2s_lcd_write_data(i2s_lcd_handle_t handle, uint16_t data);
/**
* @brief Write a command to LCD
*
* @param handle Handle of i2s lcd driver
* @param cmd command to write
*
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG handle is invalid
*/
esp_err_t i2s_lcd_write_cmd(i2s_lcd_handle_t handle, uint16_t cmd);
/**
* @brief Write block data to LCD
*
* @param handle Handle of i2s lcd driver
* @param data Pointer of data
* @param length length of data
*
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG handle is invalid
*/
esp_err_t i2s_lcd_write(i2s_lcd_handle_t handle, const uint8_t *data, uint32_t length);
/**
* @brief acquire a lock
*
* @param handle Handle of i2s lcd driver
*
* @return Always return ESP_OK
*/
esp_err_t i2s_lcd_acquire(i2s_lcd_handle_t handle);
/**
* @brief acquire a lock, but only wait a certain period of time
*
* @param handle Handle of i2s lcd driver
*
* @return true if the lock was acquired, false otherwise
*/
bool i2s_lcd_acquire_nonblocking(i2s_lcd_handle_t handle, TickType_t ticks_to_wait);
/**
* @brief release a lock
*
* @param handle Handle of i2s lcd driver
*
* @return Always return ESP_OK
*/
esp_err_t i2s_lcd_release(i2s_lcd_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif

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/* *INDENT-OFF* */
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include <stdio.h>
#include <string.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "esp_log.h"
#include "driver/gpio.h"
#include "driver/i2s.h"
#include "esp_heap_caps.h"
#include "esp32s2/rom/lldesc.h"
#include "soc/system_reg.h"
#include "i2s_lcd_driver.h"
static const char *TAG = "ESP32S2_I2S_LCD";
#define I2S_CHECK(a, str, ret) if (!(a)) { \
ESP_LOGE(TAG, "%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str); \
return ret; \
}
#define LCD_CAM_DMA_NODE_BUFFER_MAX_SIZE (4000) // 4-byte aligned
#define LCD_DATA_MAX_WIDTH (24) /*!< Maximum width of LCD data bus */
typedef struct {
uint32_t dma_buffer_size;
uint32_t dma_half_buffer_size;
uint32_t dma_node_buffer_size;
uint32_t dma_node_cnt;
uint32_t dma_half_node_cnt;
lldesc_t *dma;
uint8_t *dma_buffer;
QueueHandle_t event_queue;
uint8_t width;
bool swap_data;
} lcd_obj_t;
typedef struct {
lcd_obj_t lcd;
intr_handle_t lcd_cam_intr_handle;
i2s_dev_t *i2s_dev;
} lcd_cam_obj_t;
typedef struct {
int rs_io_num;
lcd_cam_obj_t *lcd_cam_obj;
SemaphoreHandle_t mutex;
} i2s_lcd_driver_t;
static void IRAM_ATTR i2s_isr(void *arg) {
BaseType_t HPTaskAwoken = pdFALSE;
lcd_cam_obj_t *lcd_cam_obj = (lcd_cam_obj_t *)arg;
i2s_dev_t *i2s_dev = lcd_cam_obj->i2s_dev;
typeof(i2s_dev->int_st) status = i2s_dev->int_st;
i2s_dev->int_clr.val = status.val;
if (status.val == 0) {
return;
}
if (status.out_eof) {
xQueueSendFromISR(lcd_cam_obj->lcd.event_queue, (void *)&status.val, &HPTaskAwoken);
}
if (HPTaskAwoken == pdTRUE) {
portYIELD_FROM_ISR();
}
}
static void lcd_dma_set_int(lcd_cam_obj_t *lcd_cam_obj) {
// Generate a data DMA linked list
for (int x = 0; x < lcd_cam_obj->lcd.dma_node_cnt; x++) {
lcd_cam_obj->lcd.dma[x].size = lcd_cam_obj->lcd.dma_node_buffer_size;
lcd_cam_obj->lcd.dma[x].length = lcd_cam_obj->lcd.dma_node_buffer_size;
lcd_cam_obj->lcd.dma[x].buf = (lcd_cam_obj->lcd.dma_buffer + lcd_cam_obj->lcd.dma_node_buffer_size * x);
lcd_cam_obj->lcd.dma[x].eof = !((x + 1) % lcd_cam_obj->lcd.dma_half_node_cnt);
lcd_cam_obj->lcd.dma[x].empty = (uint32_t)&lcd_cam_obj->lcd.dma[(x + 1) % lcd_cam_obj->lcd.dma_node_cnt];
}
lcd_cam_obj->lcd.dma[lcd_cam_obj->lcd.dma_half_node_cnt - 1].empty = (uint32_t)NULL;
lcd_cam_obj->lcd.dma[lcd_cam_obj->lcd.dma_node_cnt - 1].empty = (uint32_t)NULL;
}
static void lcd_dma_set_left(lcd_cam_obj_t *lcd_cam_obj, int pos, size_t len) {
int end_pos = 0, size = 0;
// Processing data length is an integer multiple of lcd_cam_obj->lcd.dma_node_buffer_size
if (len % lcd_cam_obj->lcd.dma_node_buffer_size) {
end_pos = (pos % 2) * lcd_cam_obj->lcd.dma_half_node_cnt + len / lcd_cam_obj->lcd.dma_node_buffer_size;
size = len % lcd_cam_obj->lcd.dma_node_buffer_size;
} else {
end_pos = (pos % 2) * lcd_cam_obj->lcd.dma_half_node_cnt + len / lcd_cam_obj->lcd.dma_node_buffer_size - 1;
size = lcd_cam_obj->lcd.dma_node_buffer_size;
}
// Process the tail node to make it a DMA tail
lcd_cam_obj->lcd.dma[end_pos].size = size;
lcd_cam_obj->lcd.dma[end_pos].length = size;
lcd_cam_obj->lcd.dma[end_pos].eof = 1;
lcd_cam_obj->lcd.dma[end_pos].empty = (uint32_t)NULL;
}
static void lcd_i2s_start(i2s_dev_t *i2s_dev, uint32_t addr, size_t len) {
while (!i2s_dev->state.tx_idle) {
;
}
i2s_dev->conf.tx_reset = 1;
i2s_dev->conf.tx_reset = 0;
i2s_dev->conf.tx_fifo_reset = 1;
i2s_dev->conf.tx_fifo_reset = 0;
i2s_dev->out_link.addr = addr;
i2s_dev->out_link.start = 1;
ets_delay_us(1);
i2s_dev->conf.tx_start = 1;
}
static void i2s_write_data(lcd_cam_obj_t *lcd_cam_obj, uint8_t *data, size_t len) {
int event = 0;
int x = 0, y = 0, left = 0, cnt = 0;
if (len <= 0) {
ESP_LOGE(TAG, "wrong len!");
return;
}
lcd_dma_set_int(lcd_cam_obj);
cnt = len / lcd_cam_obj->lcd.dma_half_buffer_size;
// Start signal
xQueueSend(lcd_cam_obj->lcd.event_queue, &event, 0);
// Process a complete piece of data, ping-pong operation
for (x = 0; x < cnt; x++) {
uint8_t *out = (uint8_t *)lcd_cam_obj->lcd.dma[(x % 2) * lcd_cam_obj->lcd.dma_half_node_cnt].buf;
uint8_t *in = data;
if (lcd_cam_obj->lcd.swap_data) {
for (y = 0; y < lcd_cam_obj->lcd.dma_half_buffer_size; y += 2) {
out[y + 1] = in[y + 0];
out[y + 0] = in[y + 1];
}
} else {
memcpy(out, in, lcd_cam_obj->lcd.dma_half_buffer_size);
}
data += lcd_cam_obj->lcd.dma_half_buffer_size;
xQueueReceive(lcd_cam_obj->lcd.event_queue, (void *)&event, portMAX_DELAY);
lcd_i2s_start(lcd_cam_obj->i2s_dev, ((uint32_t)&lcd_cam_obj->lcd.dma[(x % 2) * lcd_cam_obj->lcd.dma_half_node_cnt]) & 0xfffff, lcd_cam_obj->lcd.dma_half_buffer_size);
}
left = len % lcd_cam_obj->lcd.dma_half_buffer_size;
// Process remaining incomplete segment data
if (left) {
uint8_t *out = (uint8_t *)lcd_cam_obj->lcd.dma[(x % 2) * lcd_cam_obj->lcd.dma_half_node_cnt].buf;
uint8_t *in = data;
cnt = left - left % 2;
if (cnt) {
if (lcd_cam_obj->lcd.swap_data) {
for (y = 0; y < cnt; y += 2) {
out[y + 1] = in[y + 0];
out[y + 0] = in[y + 1];
}
} else {
memcpy(out, in, cnt);
}
}
if (left % 2) {
out[cnt] = in[cnt];
}
lcd_dma_set_left(lcd_cam_obj, x, left);
xQueueReceive(lcd_cam_obj->lcd.event_queue, (void *)&event, portMAX_DELAY);
lcd_i2s_start(lcd_cam_obj->i2s_dev, ((uint32_t)&lcd_cam_obj->lcd.dma[(x % 2) * lcd_cam_obj->lcd.dma_half_node_cnt]) & 0xfffff, left);
}
xQueueReceive(lcd_cam_obj->lcd.event_queue, (void *)&event, portMAX_DELAY);
}
static esp_err_t i2s_lcd_reg_config(i2s_dev_t *i2s_dev, uint16_t data_width, uint32_t clk_freq) {
// Configure the clock
i2s_dev->clkm_conf.clkm_div_num = 2; // 160MHz / 2 = 80MHz
i2s_dev->clkm_conf.clkm_div_b = 0;
i2s_dev->clkm_conf.clkm_div_a = 0;
i2s_dev->clkm_conf.clk_sel = 2; // PLL_160M_CLK
i2s_dev->clkm_conf.clk_en = 1;
i2s_dev->conf.val = 0;
i2s_dev->fifo_conf.val = 0;
i2s_dev->fifo_conf.dscr_en = 1;
i2s_dev->lc_conf.ahbm_fifo_rst = 1;
i2s_dev->lc_conf.ahbm_fifo_rst = 0;
i2s_dev->lc_conf.ahbm_rst = 1;
i2s_dev->lc_conf.ahbm_rst = 0;
i2s_dev->lc_conf.check_owner = 0;
i2s_dev->timing.val = 0;
i2s_dev->int_ena.val = 0;
i2s_dev->int_clr.val = ~0;
i2s_dev->conf2.lcd_en = 1;
// Configure sampling rate
// The datasheet states that Fws = Fbck / (W*2), but empirically storing
// 1 in the register gives the highest value of 20MHz, storing 2 gives
// 10MHz, (and storing 0 causes a freeze instead of acting as though 64 was
// specified).
int div_num = (20000000 + clk_freq - 1) / clk_freq;
if (div_num == 0) {
div_num = 1;
}
if (div_num > 63) {
div_num = 63;
}
i2s_dev->sample_rate_conf.tx_bck_div_num = div_num;
i2s_dev->sample_rate_conf.tx_bits_mod = data_width;
// Configuration data format
i2s_dev->conf.tx_right_first = 1;
i2s_dev->conf.tx_msb_right = 1;
i2s_dev->conf.tx_dma_equal = 1;
i2s_dev->conf1.tx_pcm_bypass = 1;
i2s_dev->conf1.tx_stop_en = 1;
i2s_dev->conf2.lcd_en = 1;
i2s_dev->conf_chan.tx_chan_mod = 1;
i2s_dev->fifo_conf.tx_fifo_mod_force_en = 1;
i2s_dev->fifo_conf.tx_data_num = 32;
i2s_dev->fifo_conf.tx_fifo_mod = 2;
i2s_dev->fifo_conf.tx_24msb_en = 0;
i2s_dev->lc_conf.out_rst = 1;
i2s_dev->lc_conf.out_rst = 0;
i2s_dev->int_ena.out_eof = 1;
return ESP_OK;
}
static esp_err_t lcd_set_pin(const i2s_lcd_config_t *config) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[config->pin_num_wr], PIN_FUNC_GPIO);
gpio_set_direction(config->pin_num_wr, GPIO_MODE_OUTPUT);
gpio_set_pull_mode(config->pin_num_wr, GPIO_FLOATING);
gpio_matrix_out(config->pin_num_wr, I2S0O_WS_OUT_IDX, true, false);
for (int i = 0; i < config->data_width; i++) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[config->pin_data_num[i]], PIN_FUNC_GPIO);
gpio_set_direction(config->pin_data_num[i], GPIO_MODE_OUTPUT);
gpio_set_pull_mode(config->pin_data_num[i], GPIO_FLOATING);
// High bit aligned, OUT23 is always the highest bit
gpio_matrix_out(config->pin_data_num[i], I2S0O_DATA_OUT0_IDX + (LCD_DATA_MAX_WIDTH - config->data_width) + i, false, false);
}
return ESP_OK;
}
static esp_err_t lcd_dma_config(lcd_cam_obj_t *lcd_cam_obj, uint32_t max_dma_buffer_size) {
int cnt = 0;
if (LCD_CAM_DMA_NODE_BUFFER_MAX_SIZE % 2 != 0) {
ESP_LOGE(TAG, "ESP32 only supports 2-byte aligned data length");
return ESP_FAIL;
}
if (max_dma_buffer_size >= LCD_CAM_DMA_NODE_BUFFER_MAX_SIZE * 2) {
lcd_cam_obj->lcd.dma_node_buffer_size = LCD_CAM_DMA_NODE_BUFFER_MAX_SIZE;
for (cnt = 0; cnt < max_dma_buffer_size - 8; cnt++) { // Find a buffer size that can divide dma_size
if ((max_dma_buffer_size - cnt) % (lcd_cam_obj->lcd.dma_node_buffer_size * 2) == 0) {
break;
}
}
lcd_cam_obj->lcd.dma_buffer_size = max_dma_buffer_size - cnt;
} else {
lcd_cam_obj->lcd.dma_node_buffer_size = max_dma_buffer_size / 2;
lcd_cam_obj->lcd.dma_buffer_size = lcd_cam_obj->lcd.dma_node_buffer_size * 2;
}
lcd_cam_obj->lcd.dma_half_buffer_size = lcd_cam_obj->lcd.dma_buffer_size / 2;
lcd_cam_obj->lcd.dma_node_cnt = (lcd_cam_obj->lcd.dma_buffer_size) / lcd_cam_obj->lcd.dma_node_buffer_size; // Number of DMA nodes
lcd_cam_obj->lcd.dma_half_node_cnt = lcd_cam_obj->lcd.dma_node_cnt / 2;
ESP_LOGI(TAG, "lcd_buffer_size: %d, lcd_dma_size: %d, lcd_dma_node_cnt: %d", lcd_cam_obj->lcd.dma_buffer_size, lcd_cam_obj->lcd.dma_node_buffer_size, lcd_cam_obj->lcd.dma_node_cnt);
lcd_cam_obj->lcd.dma = (lldesc_t *)heap_caps_malloc(lcd_cam_obj->lcd.dma_node_cnt * sizeof(lldesc_t), MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
lcd_cam_obj->lcd.dma_buffer = (uint8_t *)heap_caps_malloc(lcd_cam_obj->lcd.dma_buffer_size * sizeof(uint8_t), MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
return ESP_OK;
}
static esp_err_t lcd_cam_deinit(i2s_lcd_driver_t *drv) {
if (!drv->lcd_cam_obj) {
return ESP_FAIL;
}
if (drv->lcd_cam_obj->lcd.event_queue) {
vQueueDelete(drv->lcd_cam_obj->lcd.event_queue);
}
if (drv->lcd_cam_obj->lcd.dma) {
heap_caps_free(drv->lcd_cam_obj->lcd.dma);
}
if (drv->lcd_cam_obj->lcd.dma_buffer) {
heap_caps_free(drv->lcd_cam_obj->lcd.dma_buffer);
}
if (drv->lcd_cam_obj->lcd_cam_intr_handle) {
esp_intr_free(drv->lcd_cam_obj->lcd_cam_intr_handle);
}
heap_caps_free(drv->lcd_cam_obj);
drv->lcd_cam_obj = NULL;
return ESP_OK;
}
static esp_err_t lcd_cam_init(i2s_lcd_driver_t *drv, const i2s_lcd_config_t *config) {
esp_err_t ret = ESP_OK;
lcd_cam_obj_t *lcd_cam_obj = (lcd_cam_obj_t *)heap_caps_calloc(1, sizeof(lcd_cam_obj_t), MALLOC_CAP_DMA);
if (lcd_cam_obj == NULL) {
ESP_LOGE(TAG, "lcd_cam object malloc error");
return ESP_ERR_NO_MEM;
}
drv->lcd_cam_obj = lcd_cam_obj;
if (I2S_NUM_0 == config->i2s_port) {
lcd_cam_obj->i2s_dev = &I2S0;
periph_module_enable(PERIPH_I2S0_MODULE);
} else {
ESP_LOGE(TAG, "Designated I2S peripheral not found");
}
ret |= i2s_lcd_reg_config(lcd_cam_obj->i2s_dev, config->data_width, config->clk_freq);
if (ret != ESP_OK) {
ESP_LOGE(TAG, "lcd_cam config fail!");
lcd_cam_deinit(drv);
return ESP_FAIL;
}
ret |= lcd_set_pin(config);
ret |= lcd_dma_config(lcd_cam_obj, config->buffer_size);
if (ret != ESP_OK) {
ESP_LOGE(TAG, "lcd config fail!");
lcd_cam_deinit(drv);
return ESP_FAIL;
}
lcd_cam_obj->lcd.event_queue = xQueueCreate(1, sizeof(int));
lcd_cam_obj->lcd.width = config->data_width;
lcd_cam_obj->lcd.swap_data = config->swap_data;
if (lcd_cam_obj->lcd.event_queue == NULL) {
ESP_LOGE(TAG, "lcd config fail!");
lcd_cam_deinit(drv);
return ESP_FAIL;
}
ret |= esp_intr_alloc(ETS_I2S0_INTR_SOURCE, ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_IRAM, i2s_isr, lcd_cam_obj, &lcd_cam_obj->lcd_cam_intr_handle);
if (ret != ESP_OK) {
ESP_LOGE(TAG, "lcd_cam intr alloc fail!");
lcd_cam_deinit(drv);
return ESP_FAIL;
}
ESP_LOGI(TAG, "lcd init ok");
return ESP_OK;
}
/**< Public functions */
i2s_lcd_handle_t i2s_lcd_driver_init(const i2s_lcd_config_t *config) {
I2S_CHECK(NULL != config, "config pointer invalid", NULL);
I2S_CHECK(GPIO_IS_VALID_GPIO(config->pin_num_wr), "GPIO WR invalid", NULL);
I2S_CHECK(GPIO_IS_VALID_GPIO(config->pin_num_rs), "GPIO RS invalid", NULL);
I2S_CHECK(config->data_width > 0 && config->data_width <= 16, "Bit width out of range", NULL);
I2S_CHECK(0 == (config->data_width % 8), "Bit width must be a multiple of 8", NULL);
uint64_t pin_mask = 0;
for (size_t i = 0; i < config->data_width; i++) {
uint64_t mask = 1ULL << config->pin_data_num[i];
I2S_CHECK(!(pin_mask & mask), "Data bus GPIO has a duplicate", NULL);
I2S_CHECK(GPIO_IS_VALID_GPIO(config->pin_data_num[i]), "Data bus gpio invalid", NULL);
pin_mask |= mask;
}
i2s_lcd_driver_t *i2s_lcd_drv = (i2s_lcd_driver_t *)heap_caps_malloc(sizeof(i2s_lcd_driver_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
I2S_CHECK(NULL != i2s_lcd_drv, "Error malloc handle of i2s lcd driver", NULL);
esp_err_t ret = lcd_cam_init(i2s_lcd_drv, config);
if (ESP_OK != ret) {
ESP_LOGE(TAG, "%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, "i2s lcd driver initialize failed");
heap_caps_free(i2s_lcd_drv);
return NULL;
}
i2s_lcd_drv->mutex = xSemaphoreCreateMutex();
if (i2s_lcd_drv->mutex == NULL) {
ESP_LOGE(TAG, "%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, "lcd create mutex failed");
lcd_cam_deinit(i2s_lcd_drv);
heap_caps_free(i2s_lcd_drv);
return NULL;
}
if (config->pin_num_cs >= 0) {
gpio_pad_select_gpio(config->pin_num_cs);
gpio_set_direction(config->pin_num_cs, GPIO_MODE_OUTPUT);
gpio_set_level(config->pin_num_cs, 0);
}
gpio_pad_select_gpio(config->pin_num_rs);
gpio_set_direction(config->pin_num_rs, GPIO_MODE_OUTPUT);
i2s_lcd_drv->rs_io_num = config->pin_num_rs;
return (i2s_lcd_handle_t)i2s_lcd_drv;
}
esp_err_t i2s_lcd_driver_deinit(i2s_lcd_handle_t handle) {
i2s_lcd_driver_t *i2s_lcd_drv = (i2s_lcd_driver_t *)handle;
I2S_CHECK(NULL != i2s_lcd_drv, "handle pointer invalid", ESP_ERR_INVALID_ARG);
lcd_cam_deinit(i2s_lcd_drv);
vSemaphoreDelete(i2s_lcd_drv->mutex);
heap_caps_free(handle);
return ESP_OK;
}
esp_err_t i2s_lcd_write_data(i2s_lcd_handle_t handle, uint16_t data) {
i2s_lcd_driver_t *i2s_lcd_drv = (i2s_lcd_driver_t *)handle;
I2S_CHECK(NULL != i2s_lcd_drv, "handle pointer invalid", ESP_ERR_INVALID_ARG);
i2s_write_data(i2s_lcd_drv->lcd_cam_obj, (uint8_t *)&data, 2);
return ESP_OK;
}
esp_err_t i2s_lcd_write_cmd(i2s_lcd_handle_t handle, uint16_t cmd) {
i2s_lcd_driver_t *i2s_lcd_drv = (i2s_lcd_driver_t *)handle;
I2S_CHECK(NULL != i2s_lcd_drv, "handle pointer invalid", ESP_ERR_INVALID_ARG);
gpio_set_level(i2s_lcd_drv->rs_io_num, LCD_CMD_LEV);
i2s_write_data(i2s_lcd_drv->lcd_cam_obj, (uint8_t *)&cmd, 2);
gpio_set_level(i2s_lcd_drv->rs_io_num, LCD_DATA_LEV);
return ESP_OK;
}
esp_err_t i2s_lcd_write(i2s_lcd_handle_t handle, const uint8_t *data, uint32_t length) {
i2s_lcd_driver_t *i2s_lcd_drv = (i2s_lcd_driver_t *)handle;
I2S_CHECK(NULL != i2s_lcd_drv, "handle pointer invalid", ESP_ERR_INVALID_ARG);
i2s_write_data(i2s_lcd_drv->lcd_cam_obj, (uint8_t *)data, length);
return ESP_OK;
}
esp_err_t i2s_lcd_acquire(i2s_lcd_handle_t handle) {
i2s_lcd_driver_t *i2s_lcd_drv = (i2s_lcd_driver_t *)handle;
I2S_CHECK(NULL != i2s_lcd_drv, "handle pointer invalid", ESP_ERR_INVALID_ARG);
BaseType_t ret = xSemaphoreTake(i2s_lcd_drv->mutex, portMAX_DELAY);
I2S_CHECK(pdTRUE == ret, "Take semaphore failed", ESP_FAIL);
return ESP_OK;
}
bool i2s_lcd_acquire_nonblocking(i2s_lcd_handle_t handle, TickType_t ticks_to_wait) {
i2s_lcd_driver_t *i2s_lcd_drv = (i2s_lcd_driver_t *)handle;
return xSemaphoreTake(i2s_lcd_drv->mutex, ticks_to_wait);
}
esp_err_t i2s_lcd_release(i2s_lcd_handle_t handle) {
i2s_lcd_driver_t *i2s_lcd_drv = (i2s_lcd_driver_t *)handle;
I2S_CHECK(NULL != i2s_lcd_drv, "handle pointer invalid", ESP_ERR_INVALID_ARG);
i2s_dev_t *i2s_dev = &I2S0;
// at this point, the DMA is done but there could still be data in the FIFO. so we need
// to wait for I2S_TX_IDLE so that it's safe e.g., for calling code to deassert CS
while (!i2s_dev->state.tx_idle) {
;
}
BaseType_t ret = xSemaphoreGive(i2s_lcd_drv->mutex);
I2S_CHECK(pdTRUE == ret, "Give semaphore failed", ESP_FAIL);
return ESP_OK;
}
#endif // CONFIG_IDF_TARGET_ESP32S2

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@ -45,6 +45,8 @@ CIRCUITPY_WIFI ?= 1
ifeq ($(IDF_TARGET),esp32)
# Modules
CIRCUITPY_BLEIO = 0
CIRCUITPY_ESPULP = 0
CIRCUITPY_MEMORYMAP = 0
CIRCUITPY_PARALLELDISPLAY = 0
CIRCUITPY_RGBMATRIX = 0
# Features

View File

@ -35,7 +35,7 @@ typedef enum {
static i2c_status_t i2c_status[I2C_NUM_MAX];
void i2c_reset(void) {
for (i2c_port_t num = 0; num < I2C_NUM_MAX; num++) {
for (i2c_port_t num = 0; num < (int)I2C_NUM_MAX; num++) {
if (i2c_status[num] == STATUS_IN_USE) {
i2c_driver_delete(num);
i2c_status[num] = STATUS_FREE;
@ -70,7 +70,7 @@ void peripherals_i2c_deinit(i2c_port_t num) {
i2c_port_t peripherals_i2c_get_free_num(void) {
i2c_port_t i2c_num = I2C_NUM_MAX;
for (i2c_port_t num = 0; num < I2C_NUM_MAX; num++) {
for (i2c_port_t num = 0; num < (int)I2C_NUM_MAX; num++) {
if (i2c_status[num] == STATUS_FREE) {
i2c_num = num;
break;

View File

@ -50,7 +50,7 @@ extern const mp_obj_type_t mcu_pin_type;
#define NO_PIN (GPIO_NUM_NC)
#define NO_ADC 0
#define NO_ADC_CHANNEL ADC_CHANNEL_MAX
#define NO_ADC_CHANNEL SOC_ADC_MAX_CHANNEL_NUM
#define NO_TOUCH_CHANNEL TOUCH_PAD_MAX

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@ -27,9 +27,11 @@
#ifndef MICROPY_INCLUDED_ESPRESSIF_PERIPHERALS_RMT_H
#define MICROPY_INCLUDED_ESPRESSIF_PERIPHERALS_RMT_H
#include "py/mphal.h"
#include "components/driver/include/driver/rmt.h"
#include <stdint.h>
#include "py/mphal.h"
#include "driver/rmt.h"
#define TRANSMIT_MODE true
#define RECEIVE_MODE false

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@ -28,6 +28,7 @@
#define MICROPY_INCLUDED_ESPRESSIF_PERIPHERALS_TIMER_HANDLER_H
#include "driver/timer.h"
#include "soc/timer_group_struct.h"
typedef struct {
timg_dev_t *hw;

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@ -86,21 +86,20 @@
#include "esp_camera.h"
#endif
#ifndef CONFIG_IDF_TARGET_ESP32
#include "soc/cache_memory.h"
#endif
#include "soc/efuse_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "esp_debug_helpers.h"
#include "soc/spi_pins.h"
#include "bootloader_flash_config.h"
#include "esp_debug_helpers.h"
#include "esp_efuse.h"
#include "esp_ipc.h"
#include "esp_rom_efuse.h"
#include "esp_timer.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "hal/efuse_hal.h"
#include "esp32/rom/efuse.h"
#endif
@ -187,7 +186,7 @@ static void _never_reset_spi_ram_flash(void) {
if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
never_reset_pin_number(D2WD_PSRAM_CLK_IO);
never_reset_pin_number(D2WD_PSRAM_CS_IO);
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && esp_efuse_get_chip_ver() >= 3) {
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && efuse_hal_get_major_chip_version() >= 3) {
// This chip is ESP32-PICO-V3 and doesn't have PSRAM.
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
never_reset_pin_number(PICO_PSRAM_CLK_IO);

View File

@ -35,8 +35,8 @@
#include "hal/usb_hal.h"
#include "soc/usb_periph.h"
#include "components/driver/include/driver/gpio.h"
#include "components/driver/include/driver/periph_ctrl.h"
#include "driver/gpio.h"
#include "esp_private/periph_ctrl.h"
#ifdef CONFIG_IDF_TARGET_ESP32C3
#include "components/esp_rom/include/esp32c3/rom/gpio.h"