stm32/sdio: Allow configuring the SDMMC periph used for SDIO.
This can now be selected by setting MICROPY_HW_SDIO_SDMMC, which defaults to 1, ie SDMMC1. The pins can also be selected and default to the standard C8/C9/C10/C11/C12/D2.
This commit is contained in:
iabdalkader
Damien George
parent
0d4eb15392
commit
a1111b83ed
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@ -122,6 +122,11 @@
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#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT (MICROPY_HW_ENABLE_SDCARD)
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#endif
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// Which SDMMC peripheral to use for the SDIO driver (1 or 2)
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#ifndef MICROPY_HW_SDIO_SDMMC
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#define MICROPY_HW_SDIO_SDMMC (1)
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#endif
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// Whether to enable the MMA7660 driver, exposed as pyb.Accel
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#ifndef MICROPY_HW_HAS_MMA7660
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#define MICROPY_HW_HAS_MMA7660 (0)
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@ -390,10 +395,10 @@
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// Define MICROPY_HW_SDMMCx_CK values if that peripheral is used, so that make-pins.py
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// generates the relevant AF constants.
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#if MICROPY_HW_SDCARD_SDMMC == 1
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#if MICROPY_HW_SDCARD_SDMMC == 1 || MICROPY_HW_SDIO_SDMMC == 1
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#define MICROPY_HW_SDMMC1_CK (1)
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#endif
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#if MICROPY_HW_SDCARD_SDMMC == 2
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#if MICROPY_HW_SDCARD_SDMMC == 2 || MICROPY_HW_SDIO_SDMMC == 2
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#define MICROPY_HW_SDMMC2_CK (1)
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#endif
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@ -28,7 +28,8 @@
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "genhdr/pins.h"
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#include "pin.h"
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#include "pin_static_af.h"
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#include "pendsv.h"
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#include "sdio.h"
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@ -50,18 +51,62 @@ static volatile uint32_t sdmmc_error;
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static volatile uint8_t *sdmmc_buf_cur;
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static volatile uint8_t *sdmmc_buf_top;
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// The H7/F7/L4 have 2 SDMMC peripherals, but at the moment this driver only supports
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// using one of them in a given build, selected by MICROPY_HW_SDIO_SDMMC.
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#if MICROPY_HW_SDIO_SDMMC == 1
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#define SDMMC SDMMC1
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#define SDMMC_IRQn SDMMC1_IRQn
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#define SDMMC_IRQHandler SDMMC1_IRQHandler
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#define SDMMC_CLK_ENABLE() __HAL_RCC_SDMMC1_CLK_ENABLE()
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#define SDMMC_CLK_DISABLE() __HAL_RCC_SDMMC1_CLK_DISABLE()
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#define SDMMC_IS_CLK_DISABLED() __HAL_RCC_SDMMC1_IS_CLK_DISABLED()
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#define STATIC_AF_SDMMC_CK STATIC_AF_SDMMC1_CK
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#define STATIC_AF_SDMMC_CMD STATIC_AF_SDMMC1_CMD
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#define STATIC_AF_SDMMC_D0 STATIC_AF_SDMMC1_D0
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#define STATIC_AF_SDMMC_D1 STATIC_AF_SDMMC1_D1
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#define STATIC_AF_SDMMC_D2 STATIC_AF_SDMMC1_D2
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#define STATIC_AF_SDMMC_D3 STATIC_AF_SDMMC1_D3
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#else
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#if defined(STM32F7)
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#error Due to DMA configuration, only SDMMC1 is currently supported on F7
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#endif
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#define SDMMC SDMMC2
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#define SDMMC_IRQn SDMMC2_IRQn
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#define SDMMC_IRQHandler SDMMC2_IRQHandler
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#define SDMMC_CLK_ENABLE() __HAL_RCC_SDMMC2_CLK_ENABLE()
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#define SDMMC_CLK_DISABLE() __HAL_RCC_SDMMC2_CLK_DISABLE()
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#define SDMMC_IS_CLK_DISABLED() __HAL_RCC_SDMMC2_IS_CLK_DISABLED()
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#define STATIC_AF_SDMMC_CK STATIC_AF_SDMMC2_CK
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#define STATIC_AF_SDMMC_CMD STATIC_AF_SDMMC2_CMD
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#define STATIC_AF_SDMMC_D0 STATIC_AF_SDMMC2_D0
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#define STATIC_AF_SDMMC_D1 STATIC_AF_SDMMC2_D1
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#define STATIC_AF_SDMMC_D2 STATIC_AF_SDMMC2_D2
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#define STATIC_AF_SDMMC_D3 STATIC_AF_SDMMC2_D3
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#endif
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// If no custom SDIO pins defined, use the default ones
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#ifndef MICROPY_HW_SDIO_CK
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#define MICROPY_HW_SDIO_D0 (pin_C8)
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#define MICROPY_HW_SDIO_D1 (pin_C9)
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#define MICROPY_HW_SDIO_D2 (pin_C10)
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#define MICROPY_HW_SDIO_D3 (pin_C11)
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#define MICROPY_HW_SDIO_CK (pin_C12)
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#define MICROPY_HW_SDIO_CMD (pin_D2)
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#endif
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void sdio_init(uint32_t irq_pri) {
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// configure IO pins
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mp_hal_pin_config(pin_C8, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config(pin_C9, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config(pin_C10, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config(pin_C11, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config(pin_C12, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, 12); // CLK doesn't need pull-up
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mp_hal_pin_config(pin_D2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config_alt_static(MICROPY_HW_SDIO_D0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, STATIC_AF_SDMMC_D0);
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mp_hal_pin_config_alt_static(MICROPY_HW_SDIO_D1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, STATIC_AF_SDMMC_D1);
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mp_hal_pin_config_alt_static(MICROPY_HW_SDIO_D2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, STATIC_AF_SDMMC_D2);
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mp_hal_pin_config_alt_static(MICROPY_HW_SDIO_D3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, STATIC_AF_SDMMC_D3);
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mp_hal_pin_config_alt_static(MICROPY_HW_SDIO_CK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_SDMMC_CK);
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mp_hal_pin_config_alt_static(MICROPY_HW_SDIO_CMD, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, STATIC_AF_SDMMC_CMD);
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__HAL_RCC_SDMMC1_CLK_ENABLE(); // enable SDIO peripheral
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SDMMC_CLK_ENABLE(); // enable SDIO peripheral
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SDMMC_TypeDef *SDIO = SDMMC1;
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SDMMC_TypeDef *SDIO = SDMMC;
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#if defined(STM32F7)
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SDIO->CLKCR = SDMMC_CLKCR_HWFC_EN | SDMMC_CLKCR_PWRSAV | (120 - 2); // 1-bit, 400kHz
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#else
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@ -80,36 +125,36 @@ void sdio_init(uint32_t irq_pri) {
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__HAL_RCC_DMA2_CLK_ENABLE(); // enable DMA2 peripheral
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#endif
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NVIC_SetPriority(SDMMC1_IRQn, irq_pri);
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NVIC_SetPriority(SDMMC_IRQn, irq_pri);
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SDIO->MASK = 0;
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HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
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HAL_NVIC_EnableIRQ(SDMMC_IRQn);
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}
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void sdio_deinit(void) {
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__HAL_RCC_SDMMC1_CLK_DISABLE();
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SDMMC_CLK_DISABLE();
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#if defined(STM32F7)
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__HAL_RCC_DMA2_CLK_DISABLE();
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#endif
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}
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void sdio_reenable(void) {
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if (__HAL_RCC_SDMMC1_IS_CLK_DISABLED()) {
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__HAL_RCC_SDMMC1_CLK_ENABLE(); // enable SDIO peripheral
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if (SDMMC_IS_CLK_DISABLED()) {
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SDMMC_CLK_ENABLE(); // enable SDIO peripheral
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sdio_enable_high_speed_4bit();
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}
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}
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void sdio_enable_irq(bool enable) {
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if (enable) {
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SDMMC1->MASK |= SDMMC_MASK_SDIOITIE;
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SDMMC->MASK |= SDMMC_MASK_SDIOITIE;
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} else {
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SDMMC1->MASK &= ~SDMMC_MASK_SDIOITIE;
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SDMMC->MASK &= ~SDMMC_MASK_SDIOITIE;
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}
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}
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void sdio_enable_high_speed_4bit(void) {
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SDMMC_TypeDef *SDIO = SDMMC1;
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SDMMC_TypeDef *SDIO = SDMMC;
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SDIO->POWER = 0; // power off
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mp_hal_delay_us(10);
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#if defined(STM32F7)
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@ -128,33 +173,33 @@ void sdio_enable_high_speed_4bit(void) {
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mp_hal_delay_us(10);
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}
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void SDMMC1_IRQHandler(void) {
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if (SDMMC1->STA & SDMMC_STA_CMDREND) {
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SDMMC1->ICR = SDMMC_ICR_CMDRENDC;
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uint32_t r1 = SDMMC1->RESP1;
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if (SDMMC1->RESPCMD == 53 && r1 & 0x800) {
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printf("bad RESP1: %lu %lx\n", SDMMC1->RESPCMD, r1);
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void SDMMC_IRQHandler(void) {
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if (SDMMC->STA & SDMMC_STA_CMDREND) {
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SDMMC->ICR = SDMMC_ICR_CMDRENDC;
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uint32_t r1 = SDMMC->RESP1;
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if (SDMMC->RESPCMD == 53 && r1 & 0x800) {
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printf("bad RESP1: %lu %lx\n", SDMMC->RESPCMD, r1);
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sdmmc_error = 0xffffffff;
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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SDMMC->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_irq_state = SDMMC_IRQ_STATE_DONE;
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return;
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}
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#if defined(STM32H7)
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if (!sdmmc_dma) {
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while (sdmmc_buf_cur < sdmmc_buf_top && (SDMMC1->STA & SDMMC_STA_DPSMACT) && !(SDMMC1->STA & SDMMC_STA_RXFIFOE)) {
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*(uint32_t *)sdmmc_buf_cur = SDMMC1->FIFO;
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while (sdmmc_buf_cur < sdmmc_buf_top && (SDMMC->STA & SDMMC_STA_DPSMACT) && !(SDMMC->STA & SDMMC_STA_RXFIFOE)) {
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*(uint32_t *)sdmmc_buf_cur = SDMMC->FIFO;
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sdmmc_buf_cur += 4;
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}
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}
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#endif
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if (sdmmc_buf_cur >= sdmmc_buf_top) {
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// data transfer finished, so we are done
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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SDMMC->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_irq_state = SDMMC_IRQ_STATE_DONE;
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return;
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}
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if (sdmmc_write) {
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SDMMC1->DCTRL =
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SDMMC->DCTRL =
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SDMMC_DCTRL_SDIOEN
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| SDMMC_DCTRL_RWMOD
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| sdmmc_block_size_log2 << SDMMC_DCTRL_DBLOCKSIZE_Pos
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@ -165,51 +210,51 @@ void SDMMC1_IRQHandler(void) {
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| SDMMC_DCTRL_DTEN
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;
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if (!sdmmc_dma) {
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SDMMC1->MASK |= SDMMC_MASK_TXFIFOHEIE;
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SDMMC->MASK |= SDMMC_MASK_TXFIFOHEIE;
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}
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}
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sdmmc_irq_state = SDMMC_IRQ_STATE_CMD_DONE;
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} else if (SDMMC1->STA & SDMMC_STA_DATAEND) {
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} else if (SDMMC->STA & SDMMC_STA_DATAEND) {
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// data transfer complete
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// note: it's possible to get DATAEND before CMDREND
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SDMMC1->ICR = SDMMC_ICR_DATAENDC;
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SDMMC->ICR = SDMMC_ICR_DATAENDC;
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#if defined(STM32F7)
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// check if there is some remaining data in RXFIFO
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if (!sdmmc_dma) {
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while (SDMMC1->STA & SDMMC_STA_RXDAVL) {
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*(uint32_t *)sdmmc_buf_cur = SDMMC1->FIFO;
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while (SDMMC->STA & SDMMC_STA_RXDAVL) {
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*(uint32_t *)sdmmc_buf_cur = SDMMC->FIFO;
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sdmmc_buf_cur += 4;
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}
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}
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#endif
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if (sdmmc_irq_state == SDMMC_IRQ_STATE_CMD_DONE) {
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// command and data finished, so we are done
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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SDMMC->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_irq_state = SDMMC_IRQ_STATE_DONE;
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}
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} else if (SDMMC1->STA & SDMMC_STA_TXFIFOHE) {
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} else if (SDMMC->STA & SDMMC_STA_TXFIFOHE) {
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if (!sdmmc_dma && sdmmc_write) {
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// write up to 8 words to fifo
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for (size_t i = 8; i && sdmmc_buf_cur < sdmmc_buf_top; --i) {
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SDMMC1->FIFO = *(uint32_t *)sdmmc_buf_cur;
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SDMMC->FIFO = *(uint32_t *)sdmmc_buf_cur;
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sdmmc_buf_cur += 4;
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}
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if (sdmmc_buf_cur >= sdmmc_buf_top) {
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// finished, disable IRQ
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SDMMC1->MASK &= ~SDMMC_MASK_TXFIFOHEIE;
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SDMMC->MASK &= ~SDMMC_MASK_TXFIFOHEIE;
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}
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}
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} else if (SDMMC1->STA & SDMMC_STA_RXFIFOHF) {
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} else if (SDMMC->STA & SDMMC_STA_RXFIFOHF) {
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if (!sdmmc_dma && !sdmmc_write) {
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// read up to 8 words from fifo
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for (size_t i = 8; i && sdmmc_buf_cur < sdmmc_buf_top; --i) {
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*(uint32_t *)sdmmc_buf_cur = SDMMC1->FIFO;
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*(uint32_t *)sdmmc_buf_cur = SDMMC->FIFO;
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sdmmc_buf_cur += 4;
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}
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}
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} else if (SDMMC1->STA & SDMMC_STA_SDIOIT) {
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SDMMC1->MASK &= ~SDMMC_MASK_SDIOITIE;
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SDMMC1->ICR = SDMMC_ICR_SDIOITC;
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} else if (SDMMC->STA & SDMMC_STA_SDIOIT) {
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SDMMC->MASK &= ~SDMMC_MASK_SDIOITIE;
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SDMMC->ICR = SDMMC_ICR_SDIOITC;
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#if MICROPY_PY_NETWORK_CYW43
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extern void (*cyw43_poll)(void);
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@ -217,11 +262,11 @@ void SDMMC1_IRQHandler(void) {
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pendsv_schedule_dispatch(PENDSV_DISPATCH_CYW43, cyw43_poll);
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}
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#endif
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} else if (SDMMC1->STA & 0x3f) {
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} else if (SDMMC->STA & 0x3f) {
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// an error
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sdmmc_error = SDMMC1->STA;
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SDMMC1->ICR = SDMMC_STATIC_FLAGS;
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_error = SDMMC->STA;
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SDMMC->ICR = SDMMC_STATIC_FLAGS;
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SDMMC->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_irq_state = SDMMC_IRQ_STATE_DONE;
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}
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}
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@ -229,22 +274,22 @@ void SDMMC1_IRQHandler(void) {
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int sdio_transfer(uint32_t cmd, uint32_t arg, uint32_t *resp) {
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#if defined(STM32F7)
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// Wait for any outstanding TX to complete
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while (SDMMC1->STA & SDMMC_STA_TXACT) {
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while (SDMMC->STA & SDMMC_STA_TXACT) {
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}
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#endif
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#if defined(STM32F7)
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DMA2_Stream3->CR = 0; // ensure DMA is reset
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#endif
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SDMMC1->ICR = SDMMC_STATIC_FLAGS; // clear interrupts
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SDMMC1->ARG = arg;
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SDMMC1->CMD = cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN;
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SDMMC->ICR = SDMMC_STATIC_FLAGS; // clear interrupts
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SDMMC->ARG = arg;
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SDMMC->CMD = cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN;
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sdmmc_irq_state = SDMMC_IRQ_STATE_CMD_DATA_PENDING;
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sdmmc_error = 0;
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sdmmc_buf_cur = NULL;
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sdmmc_buf_top = NULL;
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SDMMC1->MASK = (SDMMC1->MASK & SDMMC_MASK_SDIOITIE) | SDMMC_MASK_CMDRENDIE | 0x3f;
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SDMMC->MASK = (SDMMC->MASK & SDMMC_MASK_SDIOITIE) | SDMMC_MASK_CMDRENDIE | 0x3f;
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uint32_t start = mp_hal_ticks_ms();
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for (;;) {
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@ -253,13 +298,13 @@ int sdio_transfer(uint32_t cmd, uint32_t arg, uint32_t *resp) {
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break;
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}
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if (mp_hal_ticks_ms() - start > 1000) {
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SDMMC1->MASK = DEFAULT_MASK;
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printf("sdio_transfer timeout STA=0x%08x\n", (uint)SDMMC1->STA);
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SDMMC->MASK = DEFAULT_MASK;
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printf("sdio_transfer timeout STA=0x%08x\n", (uint)SDMMC->STA);
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return -MP_ETIMEDOUT;
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}
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}
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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SDMMC->MASK &= SDMMC_MASK_SDIOITIE;
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if (sdmmc_error == SDMMC_STA_CCRCFAIL && cmd == 5) {
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// Errata: CMD CRC error is incorrectly generated for CMD 5
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@ -268,13 +313,13 @@ int sdio_transfer(uint32_t cmd, uint32_t arg, uint32_t *resp) {
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return -(0x1000000 | sdmmc_error);
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}
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uint32_t rcmd = SDMMC1->RESPCMD;
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uint32_t rcmd = SDMMC->RESPCMD;
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if (rcmd != cmd) {
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printf("sdio_transfer: cmd=%lu rcmd=%lu\n", cmd, rcmd);
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return -MP_EIO;
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}
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if (resp != NULL) {
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*resp = SDMMC1->RESP1;
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*resp = SDMMC->RESP1;
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}
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return 0;
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}
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@ -282,7 +327,7 @@ int sdio_transfer(uint32_t cmd, uint32_t arg, uint32_t *resp) {
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int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t len, uint8_t *buf) {
|
||||
#if defined(STM32F7)
|
||||
// Wait for any outstanding TX to complete
|
||||
while (SDMMC1->STA & SDMMC_STA_TXACT) {
|
||||
while (SDMMC->STA & SDMMC_STA_TXACT) {
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -309,11 +354,11 @@ int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t le
|
|||
|
||||
bool dma = (len > 16);
|
||||
|
||||
SDMMC1->ICR = SDMMC_STATIC_FLAGS; // clear interrupts
|
||||
SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
|
||||
SDMMC->ICR = SDMMC_STATIC_FLAGS; // clear interrupts
|
||||
SDMMC->MASK &= SDMMC_MASK_SDIOITIE;
|
||||
|
||||
SDMMC1->DTIMER = 0x2000000; // about 700ms running at 48MHz
|
||||
SDMMC1->DLEN = (len + block_size - 1) & ~(block_size - 1);
|
||||
SDMMC->DTIMER = 0x2000000; // about 700ms running at 48MHz
|
||||
SDMMC->DLEN = (len + block_size - 1) & ~(block_size - 1);
|
||||
|
||||
#if defined(STM32F7)
|
||||
DMA2_Stream3->CR = 0;
|
||||
|
|
@ -339,7 +384,7 @@ int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t le
|
|||
#if defined(STM32F7)
|
||||
DMA2->LIFCR = 0x3f << 22;
|
||||
DMA2_Stream3->FCR = 0x07; // ?
|
||||
DMA2_Stream3->PAR = (uint32_t)&SDMMC1->FIFO;
|
||||
DMA2_Stream3->PAR = (uint32_t)&SDMMC->FIFO;
|
||||
if ((uint32_t)buf & 3) {
|
||||
printf("sdio_transfer_cmd53: buf=%p is not aligned for DMA\n", buf);
|
||||
return -MP_EINVAL;
|
||||
|
|
@ -359,12 +404,12 @@ int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t le
|
|||
| 1 << 0 // EN
|
||||
;
|
||||
#else
|
||||
SDMMC1->IDMABASE0 = (uint32_t)buf;
|
||||
SDMMC1->IDMACTRL = SDMMC_IDMA_IDMAEN;
|
||||
SDMMC->IDMABASE0 = (uint32_t)buf;
|
||||
SDMMC->IDMACTRL = SDMMC_IDMA_IDMAEN;
|
||||
#endif
|
||||
} else {
|
||||
#if defined(STM32H7)
|
||||
SDMMC1->IDMACTRL = 0;
|
||||
SDMMC->IDMACTRL = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -373,7 +418,7 @@ int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t le
|
|||
// (and in case we get a long-running unrelated IRQ here on the host just
|
||||
// after writing to CMD to initiate the command)
|
||||
if (!write) {
|
||||
SDMMC1->DCTRL =
|
||||
SDMMC->DCTRL =
|
||||
SDMMC_DCTRL_SDIOEN
|
||||
| SDMMC_DCTRL_RWMOD
|
||||
| block_size_log2 << SDMMC_DCTRL_DBLOCKSIZE_Pos
|
||||
|
|
@ -385,8 +430,8 @@ int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t le
|
|||
;
|
||||
}
|
||||
|
||||
SDMMC1->ARG = arg;
|
||||
SDMMC1->CMD = 53 | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN;
|
||||
SDMMC->ARG = arg;
|
||||
SDMMC->CMD = 53 | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN;
|
||||
|
||||
sdmmc_irq_state = SDMMC_IRQ_STATE_CMD_DATA_PENDING;
|
||||
sdmmc_block_size_log2 = block_size_log2;
|
||||
|
|
@ -395,7 +440,7 @@ int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t le
|
|||
sdmmc_error = 0;
|
||||
sdmmc_buf_cur = (uint8_t *)buf;
|
||||
sdmmc_buf_top = (uint8_t *)buf + len;
|
||||
SDMMC1->MASK = (SDMMC1->MASK & SDMMC_MASK_SDIOITIE) | SDMMC_MASK_CMDRENDIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_RXFIFOHFIE | 0x3f;
|
||||
SDMMC->MASK = (SDMMC->MASK & SDMMC_MASK_SDIOITIE) | SDMMC_MASK_CMDRENDIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_RXFIFOHFIE | 0x3f;
|
||||
|
||||
// wait to complete transfer
|
||||
uint32_t start = mp_hal_ticks_ms();
|
||||
|
|
@ -405,23 +450,23 @@ int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t le
|
|||
break;
|
||||
}
|
||||
if (mp_hal_ticks_ms() - start > 200) {
|
||||
SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
|
||||
SDMMC->MASK &= SDMMC_MASK_SDIOITIE;
|
||||
#if defined(STM32F7)
|
||||
printf("sdio_transfer_cmd53: timeout wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x DMA=%08x:%08x:%08x RCC=%08x\n", write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC1->STA, (uint)SDMMC1->DCOUNT, (uint)SDMMC1->FIFOCNT, (uint)DMA2->LISR, (uint)DMA2->HISR, (uint)DMA2_Stream3->NDTR, (uint)RCC->AHB1ENR);
|
||||
printf("sdio_transfer_cmd53: timeout wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x DMA=%08x:%08x:%08x RCC=%08x\n", write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC->STA, (uint)SDMMC->DCOUNT, (uint)SDMMC->FIFOCNT, (uint)DMA2->LISR, (uint)DMA2->HISR, (uint)DMA2_Stream3->NDTR, (uint)RCC->AHB1ENR);
|
||||
#else
|
||||
printf("sdio_transfer_cmd53: timeout wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x IDMA=%08x\n", write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC1->STA, (uint)SDMMC1->DCOUNT, (uint)SDMMC1->DCTRL, (uint)SDMMC1->IDMACTRL);
|
||||
printf("sdio_transfer_cmd53: timeout wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x IDMA=%08x\n", write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC->STA, (uint)SDMMC->DCOUNT, (uint)SDMMC->DCTRL, (uint)SDMMC->IDMACTRL);
|
||||
#endif
|
||||
return -MP_ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
|
||||
SDMMC->MASK &= SDMMC_MASK_SDIOITIE;
|
||||
|
||||
if (sdmmc_error) {
|
||||
#if defined(STM32F7)
|
||||
printf("sdio_transfer_cmd53: error=%08lx wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x DMA=%08x:%08x:%08x RCC=%08x\n", sdmmc_error, write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC1->STA, (uint)SDMMC1->DCOUNT, (uint)SDMMC1->FIFOCNT, (uint)DMA2->LISR, (uint)DMA2->HISR, (uint)DMA2_Stream3->NDTR, (uint)RCC->AHB1ENR);
|
||||
printf("sdio_transfer_cmd53: error=%08lx wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x DMA=%08x:%08x:%08x RCC=%08x\n", sdmmc_error, write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC->STA, (uint)SDMMC->DCOUNT, (uint)SDMMC->FIFOCNT, (uint)DMA2->LISR, (uint)DMA2->HISR, (uint)DMA2_Stream3->NDTR, (uint)RCC->AHB1ENR);
|
||||
#else
|
||||
printf("sdio_transfer_cmd53: error=%08lx wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x IDMA=%08x\n", sdmmc_error, write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC1->STA, (uint)SDMMC1->DCOUNT, (uint)SDMMC1->DCTRL, (uint)SDMMC1->IDMACTRL);
|
||||
printf("sdio_transfer_cmd53: error=%08lx wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x IDMA=%08x\n", sdmmc_error, write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC->STA, (uint)SDMMC->DCOUNT, (uint)SDMMC->DCTRL, (uint)SDMMC->IDMACTRL);
|
||||
#endif
|
||||
return -(0x1000000 | sdmmc_error);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue