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stm32/irq: Define IRQ priorities directly as encoded hardware values.

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For a given IRQn (eg UART) there's no need to carry around both a PRI and
SUBPRI value (eg IRQ_PRI_UART, IRQ_SUBPRI_UART).  Instead, the IRQ_PRI_UART
value has been changed in this patch to be the encoded hardware value,
using NVIC_EncodePriority.  This way the NVIC_SetPriority function can be
used directly, instead of going through HAL_NVIC_SetPriority which must do
extra processing to encode the PRI+SUBPRI.

For a priority grouping of 4 (4 bits for preempt priority, 0 bits for the
sub-priority), which is used in the stm32 port, the IRQ_PRI_xxx constants
remain unchanged in their value.

This patch also "fixes" the use of raise_irq_pri() which should be passed
the encoded value (but as mentioned above the unencoded value is the same
as the encoded value for priority grouping 4, so there was no bug from this
error).
This commit is contained in:
Damien George 2018-05-02 14:41:02 +10:00
parent 266446624f
commit a03e6c1e05
12 changed files with 35 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
ports/stm32/can.c
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@ -153,7 +153,7 @@ STATIC bool can_init(pyb_can_obj_t *can_obj) {
__HAL_CAN_ENABLE_IT(&can_obj->can, CAN_IT_ERR | CAN_IT_BOF | CAN_IT_EPV | CAN_IT_EWG); __HAL_CAN_ENABLE_IT(&can_obj->can, CAN_IT_ERR | CAN_IT_BOF | CAN_IT_EPV | CAN_IT_EWG);
HAL_NVIC_SetPriority(sce_irq, IRQ_PRI_CAN, IRQ_SUBPRI_CAN); NVIC_SetPriority(sce_irq, IRQ_PRI_CAN);
HAL_NVIC_EnableIRQ(sce_irq); HAL_NVIC_EnableIRQ(sce_irq);
return true; return true;
@ -934,7 +934,7 @@ STATIC mp_obj_t pyb_can_rxcallback(mp_obj_t self_in, mp_obj_t fifo_in, mp_obj_t
irq = (fifo == 0) ? CAN2_RX0_IRQn : CAN2_RX1_IRQn; irq = (fifo == 0) ? CAN2_RX0_IRQn : CAN2_RX1_IRQn;
#endif #endif
} }
HAL_NVIC_SetPriority(irq, IRQ_PRI_CAN, IRQ_SUBPRI_CAN); NVIC_SetPriority(irq, IRQ_PRI_CAN);
HAL_NVIC_EnableIRQ(irq); HAL_NVIC_EnableIRQ(irq);
__HAL_CAN_ENABLE_IT(&self->can, (fifo == 0) ? CAN_IT_FMP0 : CAN_IT_FMP1); __HAL_CAN_ENABLE_IT(&self->can, (fifo == 0) ? CAN_IT_FMP0 : CAN_IT_FMP1);
__HAL_CAN_ENABLE_IT(&self->can, (fifo == 0) ? CAN_IT_FF0 : CAN_IT_FF1); __HAL_CAN_ENABLE_IT(&self->can, (fifo == 0) ? CAN_IT_FF0 : CAN_IT_FF1);

4
ports/stm32/dma.c
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@ -504,7 +504,7 @@ void dma_init(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, void *data){
// TODO: understand how L4 DMA works so this is not needed // TODO: understand how L4 DMA works so this is not needed
HAL_DMA_DeInit(dma); HAL_DMA_DeInit(dma);
HAL_DMA_Init(dma); HAL_DMA_Init(dma);
HAL_NVIC_SetPriority(dma_irqn[dma_id], IRQ_PRI_DMA, IRQ_SUBPRI_DMA); NVIC_SetPriority(IRQn_NONNEG(dma_irqn[dma_id]), IRQ_PRI_DMA);
#else #else
// if this stream was previously configured for this channel/request then we // if this stream was previously configured for this channel/request then we
// can skip most of the initialisation // can skip most of the initialisation
@ -516,7 +516,7 @@ void dma_init(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, void *data){
// (dma->State is set to HAL_DMA_STATE_RESET by memset above) // (dma->State is set to HAL_DMA_STATE_RESET by memset above)
HAL_DMA_DeInit(dma); HAL_DMA_DeInit(dma);
HAL_DMA_Init(dma); HAL_DMA_Init(dma);
HAL_NVIC_SetPriority(dma_irqn[dma_id], IRQ_PRI_DMA, IRQ_SUBPRI_DMA); NVIC_SetPriority(IRQn_NONNEG(dma_irqn[dma_id]), IRQ_PRI_DMA);
} else { } else {
// only necessary initialization // only necessary initialization
dma->State = HAL_DMA_STATE_READY; dma->State = HAL_DMA_STATE_READY;

4
ports/stm32/extint.c
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@ -214,7 +214,7 @@ uint extint_register(mp_obj_t pin_obj, uint32_t mode, uint32_t pull, mp_obj_t ca
// Calling HAL_GPIO_Init does an implicit extint_enable // Calling HAL_GPIO_Init does an implicit extint_enable
/* Enable and set NVIC Interrupt to the lowest priority */ /* Enable and set NVIC Interrupt to the lowest priority */
HAL_NVIC_SetPriority(nvic_irq_channel[v_line], IRQ_PRI_EXTINT, IRQ_SUBPRI_EXTINT); NVIC_SetPriority(IRQn_NONNEG(nvic_irq_channel[v_line]), IRQ_PRI_EXTINT);
HAL_NVIC_EnableIRQ(nvic_irq_channel[v_line]); HAL_NVIC_EnableIRQ(nvic_irq_channel[v_line]);
} }
return v_line; return v_line;
@ -270,7 +270,7 @@ void extint_register_pin(const pin_obj_t *pin, uint32_t mode, bool hard_irq, mp_
} }
// Configure the NVIC // Configure the NVIC
HAL_NVIC_SetPriority(nvic_irq_channel[line], IRQ_PRI_EXTINT, IRQ_SUBPRI_EXTINT); NVIC_SetPriority(IRQn_NONNEG(nvic_irq_channel[line]), IRQ_PRI_EXTINT);
HAL_NVIC_EnableIRQ(nvic_irq_channel[line]); HAL_NVIC_EnableIRQ(nvic_irq_channel[line]);
// Enable the interrupt // Enable the interrupt

48
ports/stm32/irq.h
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@ -26,6 +26,10 @@
#ifndef MICROPY_INCLUDED_STM32_IRQ_H #ifndef MICROPY_INCLUDED_STM32_IRQ_H
#define MICROPY_INCLUDED_STM32_IRQ_H #define MICROPY_INCLUDED_STM32_IRQ_H
// Use this macro together with NVIC_SetPriority to indicate that an IRQn is non-negative,
// which helps the compiler optimise the resulting inline function.
#define IRQn_NONNEG(pri) ((pri) & 0x7f)
// these states correspond to values from query_irq, enable_irq and disable_irq // these states correspond to values from query_irq, enable_irq and disable_irq
#define IRQ_STATE_DISABLED (0x00000001) #define IRQ_STATE_DISABLED (0x00000001)
#define IRQ_STATE_ENABLED (0x00000000) #define IRQ_STATE_ENABLED (0x00000000)
@ -98,55 +102,37 @@ MP_DECLARE_CONST_FUN_OBJ_0(pyb_irq_stats_obj);
// The following interrupts are arranged from highest priority to lowest // The following interrupts are arranged from highest priority to lowest
// priority to make it a bit easier to figure out. // priority to make it a bit easier to figure out.
// Priority Sub-Priority //#def IRQ_PRI_SYSTICK NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 0, 0)
// -------- ------------
//#def IRQ_PRI_SYSTICK 0
//#def IRQ_SUBPRI_SYSTICK 0
// The UARTs have no FIFOs, so if they don't get serviced quickly then characters // The UARTs have no FIFOs, so if they don't get serviced quickly then characters
// get dropped. The handling for each character only consumes about 0.5 usec // get dropped. The handling for each character only consumes about 0.5 usec
#define IRQ_PRI_UART 1 #define IRQ_PRI_UART NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 1, 0)
#define IRQ_SUBPRI_UART 0
// Flash IRQ must be higher priority than interrupts of all those components // Flash IRQ must be higher priority than interrupts of all those components
// that rely on the flash storage. // that rely on the flash storage.
#define IRQ_PRI_FLASH 2 #define IRQ_PRI_FLASH NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 2, 0)
#define IRQ_SUBPRI_FLASH 0
// SDIO must be higher priority than DMA for SDIO DMA transfers to work. // SDIO must be higher priority than DMA for SDIO DMA transfers to work.
#define IRQ_PRI_SDIO 4 #define IRQ_PRI_SDIO NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 4, 0)
#define IRQ_SUBPRI_SDIO 0
// DMA should be higher priority than USB, since USB Mass Storage calls // DMA should be higher priority than USB, since USB Mass Storage calls
// into the sdcard driver which waits for the DMA to complete. // into the sdcard driver which waits for the DMA to complete.
#define IRQ_PRI_DMA 5 #define IRQ_PRI_DMA NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 5, 0)
#define IRQ_SUBPRI_DMA 0
#define IRQ_PRI_OTG_FS 6 #define IRQ_PRI_OTG_FS NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0)
#define IRQ_SUBPRI_OTG_FS 0 #define IRQ_PRI_OTG_HS NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0)
#define IRQ_PRI_TIM5 NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0)
#define IRQ_PRI_OTG_HS 6 #define IRQ_PRI_CAN NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 7, 0)
#define IRQ_SUBPRI_OTG_HS 0
#define IRQ_PRI_TIM5 6
#define IRQ_SUBPRI_TIM5 0
#define IRQ_PRI_CAN 7
#define IRQ_SUBPRI_CAN 0
// Interrupt priority for non-special timers. // Interrupt priority for non-special timers.
#define IRQ_PRI_TIMX 13 #define IRQ_PRI_TIMX NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 13, 0)
#define IRQ_SUBPRI_TIMX 0
#define IRQ_PRI_EXTINT 14 #define IRQ_PRI_EXTINT NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 14, 0)
#define IRQ_SUBPRI_EXTINT 0
// PENDSV should be at the lowst priority so that other interrupts complete // PENDSV should be at the lowst priority so that other interrupts complete
// before exception is raised. // before exception is raised.
#define IRQ_PRI_PENDSV 15 #define IRQ_PRI_PENDSV NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0)
#define IRQ_SUBPRI_PENDSV 0 #define IRQ_PRI_RTC_WKUP NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0)
#define IRQ_PRI_RTC_WKUP 15
#define IRQ_SUBPRI_RTC_WKUP 0
#endif // MICROPY_INCLUDED_STM32_IRQ_H #endif // MICROPY_INCLUDED_STM32_IRQ_H

2
ports/stm32/pendsv.c
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@ -40,7 +40,7 @@ void *pendsv_object;
void pendsv_init(void) { void pendsv_init(void) {
// set PendSV interrupt at lowest priority // set PendSV interrupt at lowest priority
HAL_NVIC_SetPriority(PendSV_IRQn, IRQ_PRI_PENDSV, IRQ_SUBPRI_PENDSV); NVIC_SetPriority(PendSV_IRQn, IRQ_PRI_PENDSV);
} }
// Call this function to raise a pending exception during an interrupt. // Call this function to raise a pending exception during an interrupt.

2
ports/stm32/rtc.c
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@ -656,7 +656,7 @@ mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) {
EXTI->PR = 1 << 22; EXTI->PR = 1 << 22;
#endif #endif
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, IRQ_PRI_RTC_WKUP, IRQ_SUBPRI_RTC_WKUP); NVIC_SetPriority(RTC_WKUP_IRQn, IRQ_PRI_RTC_WKUP);
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
//printf("wut=%d wucksel=%d\n", wut, wucksel); //printf("wut=%d wucksel=%d\n", wut, wucksel);

2
ports/stm32/sdcard.c
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@ -173,7 +173,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef *hsd) {
#endif #endif
// NVIC configuration for SDIO interrupts // NVIC configuration for SDIO interrupts
HAL_NVIC_SetPriority(SDMMC_IRQn, IRQ_PRI_SDIO, IRQ_SUBPRI_SDIO); NVIC_SetPriority(SDMMC_IRQn, IRQ_PRI_SDIO);
HAL_NVIC_EnableIRQ(SDMMC_IRQn); HAL_NVIC_EnableIRQ(SDMMC_IRQn);
// GPIO have already been initialised by sdcard_init // GPIO have already been initialised by sdcard_init

2
ports/stm32/storage.c
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@ -55,7 +55,7 @@ void storage_init(void) {
// Enable the flash IRQ, which is used to also call our storage IRQ handler // Enable the flash IRQ, which is used to also call our storage IRQ handler
// It needs to go at a higher priority than all those components that rely on // It needs to go at a higher priority than all those components that rely on
// the flash storage (eg higher than USB MSC). // the flash storage (eg higher than USB MSC).
HAL_NVIC_SetPriority(FLASH_IRQn, IRQ_PRI_FLASH, IRQ_SUBPRI_FLASH); NVIC_SetPriority(FLASH_IRQn, IRQ_PRI_FLASH);
HAL_NVIC_EnableIRQ(FLASH_IRQn); HAL_NVIC_EnableIRQ(FLASH_IRQn);
} }
} }

2
ports/stm32/system_stm32.c
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@ -599,7 +599,7 @@ void SystemClock_Config(void)
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
HAL_NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY, 0); NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, TICK_INT_PRIORITY, 0));
#endif #endif
} }

8
ports/stm32/timer.c
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@ -170,7 +170,7 @@ void timer_tim5_init(void) {
__HAL_RCC_TIM5_CLK_ENABLE(); __HAL_RCC_TIM5_CLK_ENABLE();
// set up and enable interrupt // set up and enable interrupt
HAL_NVIC_SetPriority(TIM5_IRQn, IRQ_PRI_TIM5, IRQ_SUBPRI_TIM5); NVIC_SetPriority(TIM5_IRQn, IRQ_PRI_TIM5);
HAL_NVIC_EnableIRQ(TIM5_IRQn); HAL_NVIC_EnableIRQ(TIM5_IRQn);
// PWM clock configuration // PWM clock configuration
@ -611,12 +611,12 @@ STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *self, size_t n_args, cons
// set IRQ priority (if not a special timer) // set IRQ priority (if not a special timer)
if (self->tim_id != 5) { if (self->tim_id != 5) {
HAL_NVIC_SetPriority(self->irqn, IRQ_PRI_TIMX, IRQ_SUBPRI_TIMX); NVIC_SetPriority(IRQn_NONNEG(self->irqn), IRQ_PRI_TIMX);
if (self->tim_id == 1) { if (self->tim_id == 1) {
HAL_NVIC_SetPriority(TIM1_CC_IRQn, IRQ_PRI_TIMX, IRQ_SUBPRI_TIMX); NVIC_SetPriority(TIM1_CC_IRQn, IRQ_PRI_TIMX);
#if defined(TIM8) #if defined(TIM8)
} else if (self->tim_id == 8) { } else if (self->tim_id == 8) {
HAL_NVIC_SetPriority(TIM8_CC_IRQn, IRQ_PRI_TIMX, IRQ_SUBPRI_TIMX); NVIC_SetPriority(TIM8_CC_IRQn, IRQ_PRI_TIMX);
#endif #endif
} }
} }

2
ports/stm32/uart.c
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@ -691,7 +691,7 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, size_t n_args, const
self->read_buf_len = args.read_buf_len.u_int + 1; // +1 to adjust for usable length of buffer self->read_buf_len = args.read_buf_len.u_int + 1; // +1 to adjust for usable length of buffer
self->read_buf = m_new(byte, self->read_buf_len << self->char_width); self->read_buf = m_new(byte, self->read_buf_len << self->char_width);
__HAL_UART_ENABLE_IT(&self->uart, UART_IT_RXNE); __HAL_UART_ENABLE_IT(&self->uart, UART_IT_RXNE);
HAL_NVIC_SetPriority(self->irqn, IRQ_PRI_UART, IRQ_SUBPRI_UART); NVIC_SetPriority(IRQn_NONNEG(self->irqn), IRQ_PRI_UART);
HAL_NVIC_EnableIRQ(self->irqn); HAL_NVIC_EnableIRQ(self->irqn);
} }

4
ports/stm32/usbd_conf.c
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@ -107,7 +107,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
#endif #endif
/* Set USBFS Interrupt priority */ /* Set USBFS Interrupt priority */
HAL_NVIC_SetPriority(OTG_FS_IRQn, IRQ_PRI_OTG_FS, IRQ_SUBPRI_OTG_FS); NVIC_SetPriority(OTG_FS_IRQn, IRQ_PRI_OTG_FS);
/* Enable USBFS Interrupt */ /* Enable USBFS Interrupt */
HAL_NVIC_EnableIRQ(OTG_FS_IRQn); HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
@ -211,7 +211,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
#endif // !MICROPY_HW_USB_HS_IN_FS #endif // !MICROPY_HW_USB_HS_IN_FS
/* Set USBHS Interrupt to the lowest priority */ /* Set USBHS Interrupt to the lowest priority */
HAL_NVIC_SetPriority(OTG_HS_IRQn, IRQ_PRI_OTG_HS, IRQ_SUBPRI_OTG_HS); NVIC_SetPriority(OTG_HS_IRQn, IRQ_PRI_OTG_HS);
/* Enable USBHS Interrupt */ /* Enable USBHS Interrupt */
HAL_NVIC_EnableIRQ(OTG_HS_IRQn); HAL_NVIC_EnableIRQ(OTG_HS_IRQn);