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stm32: Add peripheral support for STM32L432.

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The L432 does not have: GPIOD, TIM3, SPI2, ADC dual mode operation, 2-banks
flash.
This commit is contained in:
boochow 2018-12-01 10:38:29 +09:00 committed by Damien George
parent 1a8baad7ca
commit 9d3372bded
6 changed files with 37 additions and 10 deletions
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6
ports/stm32/adc.c
View File

@ -134,8 +134,8 @@
#define VBAT_DIV (4) #define VBAT_DIV (4)
#elif defined(STM32H743xx) #elif defined(STM32H743xx)
#define VBAT_DIV (4) #define VBAT_DIV (4)
#elif defined(STM32L475xx) || defined(STM32L476xx) || \ #elif defined(STM32L432xx) || defined(STM32L475xx) || \
defined(STM32L496xx) defined(STM32L476xx) || defined(STM32L496xx)
#define VBAT_DIV (3) #define VBAT_DIV (3)
#else #else
#error Unsupported processor #error Unsupported processor
@ -281,7 +281,7 @@ STATIC void adc_init_single(pyb_obj_adc_t *adc_obj) {
adcx_init_periph(&adc_obj->handle, ADC_RESOLUTION_12B); adcx_init_periph(&adc_obj->handle, ADC_RESOLUTION_12B);
#if defined(STM32L4) #if defined(STM32L4) && defined(ADC_DUALMODE_REGSIMULT_INJECSIMULT)
ADC_MultiModeTypeDef multimode; ADC_MultiModeTypeDef multimode;
multimode.Mode = ADC_MODE_INDEPENDENT; multimode.Mode = ADC_MODE_INDEPENDENT;
if (HAL_ADCEx_MultiModeConfigChannel(&adc_obj->handle, &multimode) != HAL_OK) if (HAL_ADCEx_MultiModeConfigChannel(&adc_obj->handle, &multimode) != HAL_OK)

9
ports/stm32/flash.c
View File

@ -84,7 +84,7 @@ static const flash_layout_t flash_layout[] = {
#error Unsupported processor #error Unsupported processor
#endif #endif
#if defined(STM32L4) || defined(STM32H7) #if (defined(STM32L4) && defined(SYSCFG_MEMRMP_FB_MODE)) || defined(STM32H7)
// get the bank of a given flash address // get the bank of a given flash address
static uint32_t get_bank(uint32_t addr) { static uint32_t get_bank(uint32_t addr) {
@ -109,7 +109,7 @@ static uint32_t get_bank(uint32_t addr) {
} }
} }
#if defined(STM32L4) #if (defined(STM32L4) && defined(SYSCFG_MEMRMP_FB_MODE))
// get the page of a given flash address // get the page of a given flash address
static uint32_t get_page(uint32_t addr) { static uint32_t get_page(uint32_t addr) {
if (addr < (FLASH_BASE + FLASH_BANK_SIZE)) { if (addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
@ -164,6 +164,11 @@ void flash_erase(uint32_t flash_dest, uint32_t num_word32) {
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
EraseInitStruct.PageAddress = flash_dest; EraseInitStruct.PageAddress = flash_dest;
EraseInitStruct.NbPages = (4 * num_word32 + FLASH_PAGE_SIZE - 4) / FLASH_PAGE_SIZE; EraseInitStruct.NbPages = (4 * num_word32 + FLASH_PAGE_SIZE - 4) / FLASH_PAGE_SIZE;
#elif (defined(STM32L4) && !defined(SYSCFG_MEMRMP_FB_MODE))
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
EraseInitStruct.Page = flash_dest;
EraseInitStruct.NbPages = (4 * num_word32 + FLASH_PAGE_SIZE - 4) / FLASH_PAGE_SIZE;
#elif defined(STM32L4) #elif defined(STM32L4)
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);

2
ports/stm32/flashbdev.c
View File

@ -94,7 +94,7 @@ STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k
#define FLASH_MEM_SEG1_START_ADDR (0x08020000) // sector 1 #define FLASH_MEM_SEG1_START_ADDR (0x08020000) // sector 1
#define FLASH_MEM_SEG1_NUM_BLOCKS (256) // Sector 1: 128k / 512b = 256 blocks #define FLASH_MEM_SEG1_NUM_BLOCKS (256) // Sector 1: 128k / 512b = 256 blocks
#elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L496xx) #elif defined(STM32L432xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L496xx)
// The STM32L475/6 doesn't have CCRAM, so we use the 32K SRAM2 for this, although // The STM32L475/6 doesn't have CCRAM, so we use the 32K SRAM2 for this, although
// actual location and size is defined by the linker script. // actual location and size is defined by the linker script.

2
ports/stm32/main.c
View File

@ -474,7 +474,9 @@ void stm32_main(uint32_t reset_mode) {
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE();
#if defined(GPIOD)
__HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE();
#endif
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F4) || defined(STM32F7)
#if defined(__HAL_RCC_DTCMRAMEN_CLK_ENABLE) #if defined(__HAL_RCC_DTCMRAMEN_CLK_ENABLE)

22
ports/stm32/spi.c
View File

@ -186,9 +186,14 @@ void spi_set_params(const spi_t *spi_obj, uint32_t prescale, int32_t baudrate,
spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6); spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
} }
#else #else
if (spi->Instance == SPI2 || spi->Instance == SPI3) { if (spi->Instance == SPI3) {
// SPI2 and SPI3 are on APB1 // SPI3 is on APB1
spi_clock = HAL_RCC_GetPCLK1Freq(); spi_clock = HAL_RCC_GetPCLK1Freq();
#if defined(SPI2)
} else if (spi->Instance == SPI2) {
// SPI2 is on APB1
spi_clock = HAL_RCC_GetPCLK1Freq();
#endif
} else { } else {
// SPI1, SPI4, SPI5 and SPI6 are on APB2 // SPI1, SPI4, SPI5 and SPI6 are on APB2
spi_clock = HAL_RCC_GetPCLK2Freq(); spi_clock = HAL_RCC_GetPCLK2Freq();
@ -510,7 +515,10 @@ void spi_print(const mp_print_t *print, const spi_t *spi_obj, bool legacy) {
SPI_HandleTypeDef *spi = spi_obj->spi; SPI_HandleTypeDef *spi = spi_obj->spi;
uint spi_num = 1; // default to SPI1 uint spi_num = 1; // default to SPI1
if (spi->Instance == SPI2) { spi_num = 2; } if (0) { }
#if defined(SPI2)
else if (spi->Instance == SPI2) { spi_num = 2; }
#endif
#if defined(SPI3) #if defined(SPI3)
else if (spi->Instance == SPI3) { spi_num = 3; } else if (spi->Instance == SPI3) { spi_num = 3; }
#endif #endif
@ -540,7 +548,13 @@ void spi_print(const mp_print_t *print, const spi_t *spi_obj, bool legacy) {
spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6); spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
} }
#else #else
if (spi->Instance == SPI2 || spi->Instance == SPI3) { #if defined(SPI2)
if (spi->Instance == SPI2) {
// SPI2 is on APB1
spi_clock = HAL_RCC_GetPCLK1Freq();
} else
#endif
if (spi->Instance == SPI3) {
// SPI2 and SPI3 are on APB1 // SPI2 and SPI3 are on APB1
spi_clock = HAL_RCC_GetPCLK1Freq(); spi_clock = HAL_RCC_GetPCLK1Freq();
} else { } else {

6
ports/stm32/timer.c
View File

@ -611,7 +611,9 @@ STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *self, size_t n_args, cons
switch (self->tim_id) { switch (self->tim_id) {
case 1: __HAL_RCC_TIM1_CLK_ENABLE(); break; case 1: __HAL_RCC_TIM1_CLK_ENABLE(); break;
case 2: __HAL_RCC_TIM2_CLK_ENABLE(); break; case 2: __HAL_RCC_TIM2_CLK_ENABLE(); break;
#if defined(TIM3)
case 3: __HAL_RCC_TIM3_CLK_ENABLE(); break; case 3: __HAL_RCC_TIM3_CLK_ENABLE(); break;
#endif
#if defined(TIM4) #if defined(TIM4)
case 4: __HAL_RCC_TIM4_CLK_ENABLE(); break; case 4: __HAL_RCC_TIM4_CLK_ENABLE(); break;
#endif #endif
@ -706,7 +708,9 @@ STATIC const uint32_t tim_instance_table[MICROPY_HW_MAX_TIMER] = {
TIM_ENTRY(1, TIM1_UP_TIM16_IRQn), TIM_ENTRY(1, TIM1_UP_TIM16_IRQn),
#endif #endif
TIM_ENTRY(2, TIM2_IRQn), TIM_ENTRY(2, TIM2_IRQn),
#if defined(TIM3)
TIM_ENTRY(3, TIM3_IRQn), TIM_ENTRY(3, TIM3_IRQn),
#endif
#if defined(TIM4) #if defined(TIM4)
TIM_ENTRY(4, TIM4_IRQn), TIM_ENTRY(4, TIM4_IRQn),
#endif #endif
@ -1127,7 +1131,9 @@ STATIC mp_obj_t pyb_timer_channel(size_t n_args, const mp_obj_t *pos_args, mp_ma
// Only Timers 1, 2, 3, 4, 5, and 8 support encoder mode // Only Timers 1, 2, 3, 4, 5, and 8 support encoder mode
if (self->tim.Instance != TIM1 if (self->tim.Instance != TIM1
&& self->tim.Instance != TIM2 && self->tim.Instance != TIM2
#if defined(TIM3)
&& self->tim.Instance != TIM3 && self->tim.Instance != TIM3
#endif
#if defined(TIM4) #if defined(TIM4)
&& self->tim.Instance != TIM4 && self->tim.Instance != TIM4
#endif #endif