stm32/boards/NUCLEO_G0B1RE: Add NUCLEO_G0B1RE board definition.

This commit adds a board definition for NUCLEO_G0B1RE. This board has the
REPL on UART2 which is connected to the on-board ST-link USB-UART.

Signed-off-by: Asensio Lorenzo Sempere <asensio.aerospace@gmail.com>

ports/stm32/boards/NUCLEO_G0B1RE/board.json

@@ -0,0 +1,15 @@
+{
+    "deploy": [
+        "../deploy.md"
+    ],
+    "docs": "",
+    "features": [],
+    "images": [
+        "nucleo_g0b1re.jpg"
+    ],
+    "mcu": "stm32g0",
+    "product": "Nucleo G0B1RE",
+    "thumbnail": "",
+    "url": "",
+    "vendor": "ST Microelectronics"
+}

ports/stm32/boards/NUCLEO_G0B1RE/mpconfigboard.h

@@ -0,0 +1,89 @@
+#define MICROPY_HW_BOARD_NAME       "NUCLEO-G0B1RE"
+#define MICROPY_HW_MCU_NAME         "STM32G0B1xE"
+
+#define MICROPY_HW_HAS_SWITCH       (1)
+#define MICROPY_HW_HAS_FLASH        (1)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (1)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_PY_PYB_LEGACY       (0)
+
+#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1)
+
+// HSE is 8MHz, HSI is 16MHz CPU freq set to 64MHz
+// Default source for the clock is HSI.
+#define MICROPY_HW_CLK_USE_HSI (1)
+
+#define MICROPY_HW_FLASH_LATENCY    FLASH_LATENCY_2
+
+#if MICROPY_HW_CLK_USE_HSI
+#define MICROPY_HW_CLK_PLLM (16)
+#else
+#define MICROPY_HW_CLK_PLLM (8)
+#endif
+#define MICROPY_HW_CLK_PLLN (336)
+#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV4)
+#define MICROPY_HW_CLK_PLLQ (7)
+
+// USART1 config
+#define MICROPY_HW_UART1_TX         (pin_A9)
+#define MICROPY_HW_UART1_RX         (pin_A10)
+// UART2 config
+#define MICROPY_HW_UART2_TX         (pin_A2)
+#define MICROPY_HW_UART2_RX         (pin_A3)
+// USART3 config
+#define MICROPY_HW_UART3_TX         (pin_C4)
+#define MICROPY_HW_UART3_RX         (pin_C5)
+#define MICROPY_HW_UART3_RTS        (pin_B14)
+#define MICROPY_HW_UART3_CTS        (pin_B13)
+// USART4 config
+#define MICROPY_HW_UART4_TX         (pin_A0)
+#define MICROPY_HW_UART4_RX         (pin_A1)
+// USART5 config
+#define MICROPY_HW_UART5_TX         (pin_B0)
+#define MICROPY_HW_UART5_RX         (pin_B1)
+// USART6 config
+#define MICROPY_HW_UART6_TX         (pin_C0)
+#define MICROPY_HW_UART6_RX         (pin_C1)
+// LPUART1 config
+#define MICROPY_HW_LPUART1_TX       (pin_C1)
+#define MICROPY_HW_LPUART1_RX       (pin_C0)
+// LPUART2 config
+#define MICROPY_HW_LPUART2_TX       (pin_C6)
+#define MICROPY_HW_LPUART2_RX       (pin_C7)
+// USART2 is connected to the virtual com port on the ST-Link
+#define MICROPY_HW_UART_REPL        PYB_UART_2
+#define MICROPY_HW_UART_REPL_BAUD   115200
+
+// I2C buses
+#define MICROPY_HW_I2C1_SCL         (pin_B8)
+#define MICROPY_HW_I2C1_SDA         (pin_B9)
+#define MICROPY_HW_I2C2_SCL         (pin_B10)
+#define MICROPY_HW_I2C2_SDA         (pin_B11)
+
+// SPI buses
+#define MICROPY_HW_SPI1_NSS         (pin_A4)
+#define MICROPY_HW_SPI1_SCK         (pin_B3)
+#define MICROPY_HW_SPI1_MISO        (pin_B4)
+#define MICROPY_HW_SPI1_MOSI        (pin_B5)
+#define MICROPY_HW_SPI2_NSS         (pin_B12)
+#define MICROPY_HW_SPI2_SCK         (pin_B13)
+#define MICROPY_HW_SPI2_MISO        (pin_B14)
+#define MICROPY_HW_SPI2_MOSI        (pin_B15)
+
+// CAN buses
+// #define MICROPY_HW_CAN1_TX          (pin_A12)
+// #define MICROPY_HW_CAN1_RX          (pin_A11)
+// #define MICROPY_HW_CAN2_TX          (pin_C2)
+// #define MICROPY_HW_CAN2_RX          (pin_C3)
+
+// USRSW is pulled low. Pressing the button makes the input go high.
+#define MICROPY_HW_USRSW_PIN        (pin_C13)
+#define MICROPY_HW_USRSW_PULL       (GPIO_NOPULL)
+#define MICROPY_HW_USRSW_EXTI_MODE  (GPIO_MODE_IT_FALLING)
+#define MICROPY_HW_USRSW_PRESSED    (0)
+
+// LEDs
+#define MICROPY_HW_LED1             (pin_A5) // Green LD2 LED on Nucleo
+#define MICROPY_HW_LED_ON(pin)      (mp_hal_pin_high(pin))
+#define MICROPY_HW_LED_OFF(pin)     (mp_hal_pin_low(pin))

ports/stm32/boards/NUCLEO_G0B1RE/mpconfigboard.mk

@@ -0,0 +1,4 @@
+MCU_SERIES = g0
+CMSIS_MCU = STM32G0B1xx
+AF_FILE = boards/stm32g0b1_af.csv
+LD_FILES = boards/stm32g0b1xe.ld boards/common_basic.ld

ports/stm32/boards/NUCLEO_G0B1RE/pins.csv

@@ -0,0 +1,79 @@
+A0,PA0
+A1,PA1
+A2,PA4
+A3,PB1
+A4,PB11
+A5,PB12
+D0,PC5
+D1,PC4
+D10,PB0
+D11,PA7
+D12,PA6
+D13,PA5
+D14,PB9
+D15,PB8
+D2,PA10
+D3,PB3
+D4,PB5
+D5,PB4
+D6,PB14
+D7,PA8
+D8,PA9
+D9,PC7
+PA0,PA0
+PA1,PA1
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,TMS
+PA15,PA15
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA5,PA5
+PA6,PA6
+PA7,PA7
+PA8,PA8
+PA9,PA9
+PB0,PB0
+PB1,PB1
+PB10,PB10
+PB11,PB11
+PB12,PB12
+PB13,PB13
+PB14,PB14
+PB15,PB15
+PB2,PB2
+PB3,PB3
+PB4,PB4
+PB5,PB5
+PB6,PB6
+PB7,PB7
+PB8,PB8
+PB9,PB9
+PC0,PC0
+PC1,PC1
+PC10,PC10
+PC11,PC11
+PC12,PC12
+PC13,PC13
+PC2,PC2
+PC3,PC3
+PC4,PC4
+PC5,PC5
+PC6,PC6
+PC7,PC7
+PC8,PC8
+PC9,PC9
+PD0,PD0
+PD1,PD1
+PD2,PD2
+PD3,PD3
+PD4,PD4
+PD5,PD5
+PD6,PD6
+PD8,PD8
+PD9,PD9
+PD13,PD13
+LED_GREEN,PD13
+SW,PC13

ports/stm32/boards/NUCLEO_G0B1RE/stm32g0xx_hal_conf.h

@@ -0,0 +1,22 @@
+/* This file is part of the MicroPython project, http://micropython.org/
+ * The MIT License (MIT)
+ * Copyright (c) 2019 Damien P. George
+ */
+#ifndef MICROPY_INCLUDED_STM32G0XX_HAL_CONF_H
+#define MICROPY_INCLUDED_STM32G0XX_HAL_CONF_H
+
+// Oscillator values in Hz
+#define HSE_VALUE (8000000)
+#define LSE_VALUE (32768)
+#define EXTERNAL_I2S1_CLOCK_VALUE (48000)
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+#define EXTERNAL_I2S2_CLOCK_VALUE (48000)
+#endif
+
+// Oscillator timeouts in ms
+#define HSE_STARTUP_TIMEOUT (100)
+#define LSE_STARTUP_TIMEOUT (5000)
+
+#include "boards/stm32g0xx_hal_conf_base.h"
+
+#endif // MICROPY_INCLUDED_STM32G0XX_HAL_CONF_H

ports/stm32/boards/stm32g0b1_af.csv

@@ -0,0 +1,96 @@
+Port,Pin,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
+,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,ADC
+PortA,PA0,SPI2_SCK/I2S2_CK,USART2_CTS,TIM2_CH1/TIM2_ETR,,USART4_TX,LPTIM1_OUT,UCPD2_FRSTX,COMP1_OUT,,,,,,,,,ADC1_IN0
+PortA,PA1,SPI1_SCK/I2S1_CK,USART2_RTS/USART2_DE/USART2_CK,TIM2_CH2,,USART4_RX,TIM15_CH1N,I2C1_SMBA,EVENTOUT,,,,,,,,,ADC1_IN1
+PortA,PA2,SPI1_MOSI/I2S1_SD,USART2_TX,TIM2_CH3,,UCPD1_FRSTX,TIM15_CH1,LPUART1_TX,COMP2_OUT,,,,,,,,,ADC1_IN2
+PortA,PA3,SPI2_MISO/I2S2_MCK,USART2_RX,TIM2_CH4,,UCPD2_FRSTX,TIM15_CH2,LPUART1_RX,EVENTOUT,,,,,,,,,ADC1_IN3
+PortA,PA4,SPI1_NSS/I2S1_WS,SPI2_MOSI/I2S2_SD,USB_NOE,USART6_TX,TIM14_CH1,LPTIM2_OUT,UCPD2_FRSTX,EVENTOUT,,SPI3_NSS,,,,,,,ADC1_IN4
+PortA,PA5,SPI1_SCK/I2S1_CK,CEC,TIM2_CH1/TIM2_ETR,USART6_RX,USART3_TX,LPTIM2_ETR,UCPD1_FRSTX,EVENTOUT,,,,,,,,,ADC1_IN5
+PortA,PA6,SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,USART6_CTS,USART3_CTS,TIM16_CH1,LPUART1_CTS,COMP1_OUT,I2C2_SDA,I2C3_SDA,,,,,,,ADC1_IN6
+PortA,PA7,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,USART6_RTS/USART6_DE/USART6_CK,TIM14_CH1,TIM17_CH1,UCPD1_FRSTX,COMP2_OUT,I2C2_SCL,I2C3_SCL,,,,,,,ADC1_IN7
+PortA,PA8,MCO,SPI2_NSS/I2S2_WS,TIM1_CH1,,CRS1_SYNC,LPTIM2_OUT,,EVENTOUT,I2C2_SMBA,,,,,,,,
+PortA,PA9,MCO,USART1_TX,TIM1_CH2,,SPI2_MISO/I2S2_MCK,TIM15_BKIN,I2C1_SCL,EVENTOUT,I2C2_SCL,,,,,,,,
+PortA,PA10,SPI2_MOSI/I2S2_SD,USART1_RX,TIM1_CH3,MCO2,,TIM17_BKIN,I2C1_SDA,EVENTOUT,I2C2_SDA,,,,,,,,
+PortA,PA11,SPI1_MISO/I2S1_MCK,USART1_CTS,TIM1_CH4,FDCAN1_RX,,TIM1_BKIN2,I2C2_SCL,COMP1_OUT,,,,,,,,,
+PortA,PA12,SPI1_MOSI/I2S1_SD,USART1_RTS/USART1_DE/USART1_CK,TIM1_ETR,FDCAN1_TX,,I2S_CKIN,I2C2_SDA,COMP2_OUT,,,,,,,,,
+PortA,PA13,SWDIO,IR_OUT,USB_NOE,,,,,EVENTOUT,,,LPUART2_RX,,,,,,
+PortA,PA14,SWCLK,USART2_TX,,,,,,EVENTOUT,,,LPUART2_TX,,,,,,
+PortA,PA15,SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1/TIM2_ETR,MCO2,USART4_RTS/USART4_DE/USART4_CK,USART3_RTS/USART3_DE/USART3_CK,USB_NOE,EVENTOUT,I2C2_SMBA,SPI3_NSS,,,,,,,
+PortB,PB0,SPI1_NSS/I2S1_WS,TIM3_CH3,TIM1_CH2N,FDCAN2_RX,USART3_RX,LPTIM1_OUT,UCPD1_FRSTX,COMP1_OUT,USART5_TX,,LPUART2_CTS,,,,,,ADC1_IN8
+PortB,PB1,TIM14_CH1,TIM3_CH4,TIM1_CH3N,FDCAN2_TX,USART3_RTS/USART3_DE/USART3_CK,LPTIM2_IN1,LPUART1_RTS/LPUART1_DE,COMP3_OUT,USART5_RX,,LPUART2_RTS/LPUART2_DE,,,,,,ADC1_IN9
+PortB,PB2,,SPI2_MISO/I2S2_MCK,,MCO2,USART3_TX,LPTIM1_OUT,,EVENTOUT,,,,,,,,,ADC1_IN10
+PortB,PB3,SPI1_SCK/I2S1_CK,TIM1_CH2,TIM2_CH2,USART5_TX,USART1_RTS/USART1_DE/USART1_CK,,I2C3_SCL,EVENTOUT,I2C2_SCL,SPI3_SCK,,,,,,,
+PortB,PB4,SPI1_MISO/I2S1_MCK,TIM3_CH1,,USART5_RX,USART1_CTS,TIM17_BKIN,I2C3_SDA,EVENTOUT,I2C2_SDA,SPI3_MISO,,,,,,,
+PortB,PB5,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,FDCAN2_RX,,LPTIM1_IN1,I2C1_SMBA,COMP2_OUT,USART5_RTS/USART5_DE/USART5_CK,SPI3_MOSI,,,,,,,
+PortB,PB6,USART1_TX,TIM1_CH3,TIM16_CH1N,FDCAN2_TX,SPI2_MISO/I2S2_MCK,LPTIM1_ETR,I2C1_SCL,EVENTOUT,USART5_CTS,TIM4_CH1,LPUART2_TX,,,,,,
+PortB,PB7,USART1_RX,SPI2_MOSI/I2S2_SD,TIM17_CH1N,,USART4_CTS,LPTIM1_IN2,I2C1_SDA,EVENTOUT,,TIM4_CH2,LPUART2_RX,,,,,,
+PortB,PB8,CEC,SPI2_SCK/I2S2_CK,TIM16_CH1,FDCAN1_RX,USART3_TX,TIM15_BKIN,I2C1_SCL,EVENTOUT,USART6_TX,TIM4_CH3,,,,,,,
+PortB,PB9,IR_OUT,UCPD2_FRSTX,TIM17_CH1,FDCAN1_TX,USART3_RX,SPI2_NSS/I2S2_WS,I2C1_SDA,EVENTOUT,USART6_RX,TIM4_CH4,,,,,,,
+PortB,PB10,CEC,LPUART1_RX,TIM2_CH3,,USART3_TX,SPI2_SCK/I2S2_CK,I2C2_SCL,COMP1_OUT,,,,,,,,,ADC1_IN11
+PortB,PB11,SPI2_MOSI/I2S2_SD,LPUART1_TX,TIM2_CH4,,USART3_RX,,I2C2_SDA,COMP2_OUT,,,,,,,,,
+PortB,PB12,SPI2_NSS/I2S2_WS,LPUART1_RTS/LPUART1_DE,TIM1_BKIN,FDCAN2_RX,,TIM15_BKIN,UCPD2_FRSTX,EVENTOUT,I2C2_SMBA,,,,,,,,
+PortB,PB13,SPI2_SCK/I2S2_CK,LPUART1_CTS,TIM1_CH1N,FDCAN2_TX,USART3_CTS,TIM15_CH1N,I2C2_SCL,EVENTOUT,,,,,,,,,
+PortB,PB14,SPI2_MISO/I2S2_MCK,UCPD1_FRSTX,TIM1_CH2N,,USART3_RTS/USART3_DE/USART3_CK,TIM15_CH1,I2C2_SDA,EVENTOUT,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,
+PortB,PB15,SPI2_MOSI/I2S2_SD,,TIM1_CH3N,,TIM15_CH1N,TIM15_CH2,,EVENTOUT,USART6_CTS,,,,,,,,
+PortC,PC0,LPTIM1_IN1,LPUART1_RX,LPTIM2_IN1,LPUART2_TX,USART6_TX,,I2C3_SCL,COMP3_OUT,,,,,,,,,
+PortC,PC1,LPTIM1_OUT,LPUART1_TX,TIM15_CH1,LPUART2_RX,USART6_RX,,I2C3_SDA,,,,,,,,,,
+PortC,PC2,LPTIM1_IN2,SPI2_MISO/I2S2_MCK,TIM15_CH2,FDCAN2_RX,,,,COMP3_OUT,,,,,,,,,
+PortC,PC3,LPTIM1_ETR,SPI2_MOSI/I2S2_SD,LPTIM2_ETR,FDCAN2_TX,,,,,,,,,,,,,
+PortC,PC4,USART3_TX,USART1_TX,TIM2_CH1/TIM2_ETR,FDCAN1_RX,,,,,,,,,,,,,
+PortC,PC5,USART3_RX,USART1_RX,TIM2_CH2,FDCAN1_TX,,,,,,,,,,,,,ADC1_IN18
+PortC,PC6,UCPD1_FRSTX,TIM3_CH1,TIM2_CH3,LPUART2_TX,,,,,,,,,,,,,
+PortC,PC7,UCPD2_FRSTX,TIM3_CH2,TIM2_CH4,LPUART2_RX,,,,,,,,,,,,,
+PortC,PC8,UCPD2_FRSTX,TIM3_CH3,TIM1_CH1,LPUART2_CTS,,,,,,,,,,,,,
+PortC,PC9,I2S_CKIN,TIM3_CH4,TIM1_CH2,LPUART2_RTS/LPUART2_DE,,,USB_NOE,,,,,,,,,,
+PortC,PC10,USART3_TX,USART4_TX,TIM1_CH3,,SPI3_SCK,,,,,,,,,,,,
+PortC,PC11,USART3_RX,USART4_RX,TIM1_CH4,,SPI3_MISO,,,,,,,,,,,,
+PortC,PC12,LPTIM1_IN1,UCPD1_FRSTX,TIM14_CH1,USART5_TX,SPI3_MOSI,,,,,,,,,,,,
+PortC,PC13,,,TIM1_BKIN,,,,,,,,,,,,,,
+PortC,PC14,,,TIM1_BKIN2,,,,,,,,,,,,,,
+PortC,PC15,OSC32_EN,OSC_EN,TIM15_BKIN,,,,,,,,,,,,,,
+PortD,PD0,EVENTOUT,SPI2_NSS/I2S2_WS,TIM16_CH1,FDCAN1_RX,,,,,,,,,,,,,
+PortD,PD1,EVENTOUT,SPI2_SCK/I2S2_CK,TIM17_CH1,FDCAN1_TX,,,,,,,,,,,,,
+PortD,PD2,USART3_RTS/USART3_DE/USART3_CK,TIM3_ETR,TIM1_CH1N,USART5_RX,,,,,,,,,,,,,
+PortD,PD3,USART2_CTS,SPI2_MISO/I2S2_MCK,TIM1_CH2N,USART5_TX,,,,,,,,,,,,,
+PortD,PD4,USART2_RTS/USART2_DE/USART2_CK,SPI2_MOSI/I2S2_SD,TIM1_CH3N,USART5_RTS/USART5_DE/USART5_CK,,,,,,,,,,,,,
+PortD,PD5,USART2_TX,SPI1_MISO/I2S1_MCK,TIM1_BKIN,USART5_CTS,,,,,,,,,,,,,
+PortD,PD6,USART2_RX,SPI1_MOSI/I2S1_SD,LPTIM2_OUT,,,,,,,,,,,,,,
+PortD,PD7,,,,MCO2,,,,,,,,,,,,,
+PortD,PD8,USART3_TX,SPI1_SCK/I2S1_CK,LPTIM1_OUT,,,,,,,,,,,,,,
+PortD,PD9,USART3_RX,SPI1_NSS/I2S1_WS,TIM1_BKIN2,,,,,,,,,,,,,,
+PortD,PD10,MCO,,,,,,,,,,,,,,,,
+PortD,PD11,USART3_CTS,LPTIM2_ETR,,,,,,,,,,,,,,,
+PortD,PD12,USART3_RTS/USART3_DE/USART3_CK,LPTIM2_IN1,TIM4_CH1,FDCAN1_RX,,,,,,,,,,,,,
+PortD,PD13,,LPTIM2_OUT,TIM4_CH2,FDCAN1_TX,,,,,,,,,,,,,
+PortD,PD14,,LPUART2_CTS,TIM4_CH3,FDCAN2_RX,,,,,,,,,,,,,
+PortD,PD15,CRS1_SYNC,LPUART2_RTS/LPUART2_DE,TIM4_CH4,FDCAN2_TX,,,,,,,,,,,,,
+PortE,PE0,TIM16_CH1,EVENTOUT,TIM4_ETR,,,,,,,,,,,,,,
+PortE,PE1,TIM17_CH1,EVENTOUT,,,,,,,,,,,,,,,
+PortE,PE2,,TIM3_ETR,,,,,,,,,,,,,,,
+PortE,PE3,,TIM3_CH1,,,,,,,,,,,,,,,
+PortE,PE4,,TIM3_CH2,,,,,,,,,,,,,,,
+PortE,PE5,,TIM3_CH3,,,,,,,,,,,,,,,
+PortE,PE6,,TIM3_CH4,,,,,,,,,,,,,,,
+PortE,PE7,,TIM1_ETR,,USART5_RTS/USART5_DE/USART5_CK,,,,,,,,,,,,,
+PortE,PE8,USART4_TX,TIM1_CH1N,,,,,,,,,,,,,,,
+PortE,PE9,USART4_RX,TIM1_CH1,,,,,,,,,,,,,,,
+PortE,PE10,,TIM1_CH2N,,USART5_TX,,,,,,,,,,,,,
+PortE,PE11,,TIM1_CH2,,USART5_RX,,,,,,,,,,,,,
+PortE,PE12,SPI1_NSS/I2S1_WS,TIM1_CH3N,,,,,,,,,,,,,,,
+PortE,PE13,SPI1_SCK/I2S1_CK,TIM1_CH3,,,,,,,,,,,,,,,
+PortE,PE14,SPI1_MISO/I2S1_MCK,TIM1_CH4,TIM1_BK2,,,,,,,,,,,,,,
+PortE,PE15,SPI1_MOSI/I2S1_SD,TIM1_BK,,,,,,,,,,,,,,,
+PortF,PF0,CRS1_SYNC,EVENTOUT,TIM14_CH1,,,,,,,,,,,,,,
+PortF,PF1,OSC_EN,EVENTOUT,TIM15_CH1N,,,,,,,,,,,,,,
+PortF,PF2,MCO,LPUART2_TX,,LPUART2_RTS/LPUART2_DE,,,,,,,,,,,,,
+PortF,PF3,,LPUART2_RX,,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,,,,,,
+PortF,PF4,,LPUART1_TX,,,,,,,,,,,,,,,
+PortF,PF5,,LPUART1_RX,,,,,,,,,,,,,,,
+PortF,PF6,,LPUART1_RTS/LPUART1_DE,,,,,,,,,,,,,,,
+PortF,PF7,,LPUART1_CTS,,USART5_CTS,,,,,,,,,,,,,
+PortF,PF8,,,,,,,,,,,,,,,,,
+PortF,PF9,,,,USART6_TX,,,,,,,,,,,,,
+PortF,PF10,,,,USART6_RX,,,,,,,,,,,,,
+PortF,PF11,,,,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,,,,,,
+PortF,PF12,TIM15_CH1,,,USART6_CTS,,,,,,,,,,,,,
+PortF,PF13,TIM15_CH2,,,,,,,,,,,,,,,,

ports/stm32/boards/stm32g0b1xe.ld

@@ -0,0 +1,28 @@
+/* Specify the memory areas */
+MEMORY
+{
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 352K
+    FLASH_FS (rx)   : ORIGIN = 0x08058000, LENGTH = 160K  /* starting @ 352K */
+}
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_minimum_heap_size = 0x200; /* required amount of heap  */
+_minimum_stack_size = 0x400; /* required amount of stack */
+
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+
+_micropy_hw_internal_flash_storage_ram_cache_end = ORIGIN(RAM) + LENGTH(RAM);
+_micropy_hw_internal_flash_storage_ram_cache_start = _micropy_hw_internal_flash_storage_ram_cache_end - 2K; /* fs cache = 2K RAM */
+
+/* Define the stack.  The stack is full descending so begins just above last byte
+   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. */
+_estack = _micropy_hw_internal_flash_storage_ram_cache_start - _estack_reserve;
+_sstack = _estack - 8K; /* tunable */
+
+_heap_start = _ebss; /* heap starts just after statically allocated memory */
+_heap_end = _sstack;
+
+_micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS);
+_micropy_hw_internal_flash_storage_end   = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);