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Python doc generator fixes

This commit is contained in:
Hierophect 2019-07-23 13:48:59 -04:00
parent 10aac2be05
commit 9c1487cff6
9 changed files with 18 additions and 12 deletions
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4
conf.py
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@ -121,6 +121,10 @@ exclude_patterns = ["**/build*",
"ports/nrf/nrfx", "ports/nrf/nrfx",
"ports/nrf/peripherals", "ports/nrf/peripherals",
"ports/nrf/usb", "ports/nrf/usb",
"ports/stm32f4/stm32cube",
"ports/stm32f4/peripherals",
"ports/stm32f4/ref",
"ports/stm32f4/README.md",
"ports/pic16bit", "ports/pic16bit",
"ports/qemu-arm", "ports/qemu-arm",
"ports/stm32", "ports/stm32",

4
ports/stm32f4/README.md
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@ -1 +1,3 @@
##Not Done # CircuitPython Port To The ST Microelectronics STM32F4 Series
This is a port of CircuitPython to the STM32F4 series of chips.

4
ports/stm32f4/stm32cube/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
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@ -8,8 +8,8 @@
* is using in the C source code, usually in main.c. This file contains: * is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select: * - Configuration section that allows to select:
* - The STM32F4xx device used in the target application * - The STM32F4xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e. * - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by * rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER" * "#define USE_HAL_DRIVER"
* *

4
ports/stm32f4/stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c
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@ -463,7 +463,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
} }
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
/* Set the key size(This bit field is don’t care in the DES or TDES modes) data type and Algorithm */ /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */
#if defined (CRYP) #if defined (CRYP)
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
hcryp->Init.B0 = pConf->B0; hcryp->Init.B0 = pConf->B0;
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
/* Set the key size(This bit field is don’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/ /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/
#if defined (CRYP) #if defined (CRYP)
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);

4
ports/stm32f4/stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c
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@ -170,7 +170,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Select final phase */ /* Select final phase */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
/*ALGODIR bit must be set to ‘0’.*/ /*ALGODIR bit must be set to '0'.*/
hcryp->Instance->CR &= ~CRYP_CR_ALGODIR; hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
/* Enable the CRYP peripheral */ /* Enable the CRYP peripheral */
@ -388,7 +388,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Disable CRYP to start the final phase */ /* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp); __HAL_CRYP_DISABLE(hcryp);
/* Select final phase & ALGODIR bit must be set to ‘0’. */ /* Select final phase & ALGODIR bit must be set to '0'. */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT); MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */ /* Enable the CRYP peripheral */

4
ports/stm32f4/stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c
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@ -214,7 +214,7 @@
* @{ * @{
*/ */
#define SPI_DEFAULT_TIMEOUT 100U #define SPI_DEFAULT_TIMEOUT 100U
#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */ #define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 us */
/** /**
* @} * @}
*/ */
@ -3488,7 +3488,7 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t
*/ */
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{ {
/* Timeout in µs */ /* Timeout in us */
__IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
/* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
if (hspi->Init.Mode == SPI_MODE_MASTER) if (hspi->Init.Mode == SPI_MODE_MASTER)

2
ports/stm32f4/stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c
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@ -21,7 +21,7 @@
HAL_RTC_MODULE_ENABLED define in stm32f4xx_hal_conf.h HAL_RTC_MODULE_ENABLED define in stm32f4xx_hal_conf.h
[..] [..]
(@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes: (@) HAL RTC alarm and HAL RTC wakeup drivers can't be used with low power modes:
The wake up capability of the RTC may be intrusive in case of prior low power mode The wake up capability of the RTC may be intrusive in case of prior low power mode
configuration requiring different wake up sources. configuration requiring different wake up sources.
Application/Example behavior is no more guaranteed Application/Example behavior is no more guaranteed

2
ports/stm32f4/stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c
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@ -22,7 +22,7 @@
HAL_RTC_MODULE_ENABLED define in stm32f4xx_hal_conf.h HAL_RTC_MODULE_ENABLED define in stm32f4xx_hal_conf.h
[..] [..]
(@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes: (@) HAL RTC alarm and HAL RTC wakeup drivers can't be used with low power modes:
The wake up capability of the RTC may be intrusive in case of prior low power mode The wake up capability of the RTC may be intrusive in case of prior low power mode
configuration requiring different wake up sources. configuration requiring different wake up sources.
Application/Example behavior is no more guaranteed Application/Example behavior is no more guaranteed

2
ports/stm32f4/stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c
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@ -33,7 +33,7 @@
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values: (+) Typical values:
(++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler: (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
max timeout before reset: ~73.14µs max timeout before reset: ~73.14us
(++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128: (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: ~599.18ms max timeout before reset: ~599.18ms