stm32/boards: Add MCU support files for STM32L072.
This commit is contained in:
Damien George
parent
23d9c6a0fd
commit
9c096c190c
84
ports/stm32/boards/stm32l072_af.csv
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84
ports/stm32/boards/stm32l072_af.csv
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Port,Pin,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,,
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,,SPI1/SPI2/I2S2/USART1/2/LPUART1/USB/LPTIM1/TSC/TIM2/21/22/EVENTOUT/SYS_AF,SPI1/SPI2/I2S2/I2C1/TIM2/21,SPI1/SPI2/I2S2/LPUART1/USART5/USB/LPTIM1/TIM2/3/EVENTOUT/SYS_AF,I2C1/TSC/EVENTOUT,I2C1/USART1/2/LPUART1/TIM3/22/EVENTOUT,SPI2/I2S2/I2C2/USART1/TIM2/21/22,I2C1/2/LPUART1/USART4/UASRT5/TIM21/EVENTOUT,I2C3/LPUART1/COMP1/2/TIM3,,ADC
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PortA,PA0,,,TIM2_CH1,TSC_G1_IO1,USART2_CTS,TIM2_ETR,USART4_TX,COMP1_OUT,,ADC_IN0
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PortA,PA1,EVENTOUT,,TIM2_CH2,TSC_G1_IO2,USART2_RTS_DE,TIM21_ETR,USART4_RX,,,ADC_IN1
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PortA,PA2,TIM21_CH1,,TIM2_CH3,TSC_G1_IO3,USART2_TX,,LPUART1_TX,COMP2_OUT,,ADC_IN2
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PortA,PA3,TIM21_CH2,,TIM2_CH4,TSC_G1_IO4,USART2_RX,,LPUART1_RX,,,ADC_IN3
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PortA,PA4,SPI1_NSS,,,TSC_G2_IO1,USART2_CK,TIM22_ETR,,,,ADC_IN4
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PortA,PA5,SPI1_SCK,,TIM2_ETR,TSC_G2_IO2,,TIM2_CH1,,,,ADC_IN5
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PortA,PA6,SPI1_MISO,,TIM3_CH1,TSC_G2_IO3,LPUART1_CTS,TIM22_CH1,EVENTOUT,COMP1_OUT,,ADC_IN6
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PortA,PA7,SPI1_MOSI,,TIM3_CH2,TSC_G2_IO4,,TIM22_CH2,EVENTOUT,COMP2_OUT,,ADC_IN7
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PortA,PA8,MCO,,USB_CRS_SYNC,EVENTOUT,USART1_CK,,,I2C3_SCL,,
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PortA,PA9,MCO,,,TSC_G4_IO1,USART1_TX,,I2C1_SCL,I2C3_SMBA,,
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PortA,PA10,,,,TSC_G4_IO2,USART1_RX,,I2C1_SDA,,,
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PortA,PA11,SPI1_MISO,,EVENTOUT,TSC_G4_IO3,USART1_CTS,,,COMP1_OUT,,
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PortA,PA12,SPI1_MOSI,,EVENTOUT,TSC_G4_IO4,USART1_RTS_DE,,,COMP2_OUT,,
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PortA,PA13,SWDIO,,USB_NOE,,,,LPUART1_RX,,,
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PortA,PA14,SWCLK,,,,USART2_TX,,LPUART1_TX,,,
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PortA,PA15,SPI1_NSS,,TIM2_ETR,EVENTOUT,USART2_RX,TIM2_CH1,USART4_RTS_DE,,,
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PortB,PB0,EVENTOUT,,TIM3_CH3,TSC_G3_IO2,,,,,,ADC_IN8
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PortB,PB1,,,TIM3_CH4,TSC_G3_IO3,LPUART1_RTS_DE,,,,,ADC_IN9
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PortB,PB2,,,LPTIM1_OUT,TSC_G3_IO4,,,,I2C3_SMBA,,
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PortB,PB3,SPI1_SCK,,TIM2_CH2,TSC_G5_IO1,EVENTOUT,USART1_RTS_DE,USART5_TX,,,
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PortB,PB4,SPI1_MISO,,TIM3_CH1,TSC_G5_IO2,TIM22_CH1,USART1_CTS,USART5_RX,I2C3_SDA,,
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PortB,PB5,SPI1_MOSI,,LPTIM1_IN1,I2C1_SMBA,TIM3_CH2/TIM22_CH2,USART1_CK,USART5_CK/USART5_RTS_DE,,,
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PortB,PB6,USART1_TX,I2C1_SCL,LPTIM1_ETR,TSC_G5_IO3,,,,,,
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PortB,PB7,USART1_RX,I2C1_SDA,LPTIM1_IN2,TSC_G5_IO4,,,USART4_CTS,,,
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PortB,PB8,,,,TSC_SYNC,I2C1_SCL,,,,,
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PortB,PB9,,,EVENTOUT,,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,
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PortB,PB10,,,TIM2_CH3,TSC_SYNC,LPUART1_TX,SPI2_SCK,I2C2_SCL,LPUART1_RX,,
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PortB,PB11,EVENTOUT,,TIM2_CH4,TSC_G6_IO1,LPUART1_RX,,I2C2_SDA,LPUART1_TX,,
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PortB,PB12,SPI2_NSS/I2S2_WS,,LPUART1_RTS_DE,TSC_G6_IO2,I2C2_SMBA,,EVENTOUT,,,
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PortB,PB13,SPI2_SCK/I2S2_CK,,MCO,TSC_G6_IO3,LPUART1_CTS,I2C2_SCL,TIM21_CH1,,,
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PortB,PB14,SPI2_MISO/I2S2_MCK,,RTC_OUT,TSC_G6_IO4,LPUART1_RTS_DE,I2C2_SDA,TIM21_CH2,,,
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PortB,PB15,SPI2_MOSI/I2S2_SD,,RTC_REFIN,,,,,,,
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PortC,PC0,LPTIM1_IN1,,EVENTOUT,TSC_G7_IO1,,,LPUART1_RX,I2C3_SCL,,ADC_IN10
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PortC,PC1,LPTIM1_OUT,,EVENTOUT,TSC_G7_IO2,,,LPUART1_TX,I2C3_SDA,,ADC_IN11
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PortC,PC2,LPTIM1_IN2,,SPI2_MISO/I2S2_MCK,TSC_G7_IO3,,,,,,ADC_IN12
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PortC,PC3,LPTIM1_ETR,,SPI2_MOSI/I2S2_SD,TSC_G7_IO4,,,,,,ADC_IN13
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PortC,PC4,EVENTOUT,,LPUART1_TX,,,,,,,ADC_IN14
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PortC,PC5,LPUART1_RX,,TSC_G3_IO1,,,,,,,ADC_IN15
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PortC,PC6,TIM22_CH1,,TIM3_CH1,TSC_G8_IO1,,,,,,
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PortC,PC7,TIM22_CH2,,TIM3_CH2,TSC_G8_IO2,,,,,,
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PortC,PC8,TIM22_ETR,,TIM3_CH3,TSC_G8_IO3,,,,,,
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PortC,PC9,TIM21_ETR,,USB_NOE/TIM3_CH4,TSC_G8_IO4,,,,I2C3_SDA,,
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PortC,PC10,LPUART1_TX,,,,,,USART4_TX,,,
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PortC,PC11,LPUART1_RX,,,,,,USART4_RX,,,
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PortC,PC12,,,USART5_TX,,,,USART4_CK,,,
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PortC,PC13,,,,,,,,,,
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PortC,PC14,,,,,,,,,,
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PortC,PC15,,,,,,,,,,
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PortD,PD0,TIM21_CH1,SPI2_NSS/I2S2_WS,,,,,,,,
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PortD,PD1,,SPI2_SCK/I2S2_CK,,,,,,,,
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PortD,PD2,LPUART1_RTS_DE,,TIM3_ETR,,,,USART5_RX,,,
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PortD,PD3,USART2_CTS,,SPI2_MISO/I2S2_MCK,,,,,,,
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PortD,PD4,USART2_RTS_DE,SPI2_MOSI/I2S2_SD,,,,,,,,
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PortD,PD5,USART2_TX,,,,,,,,,
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PortD,PD6,USART2_RX,,,,,,,,,
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PortD,PD7,USART2_CK,TIM21_CH2,,,,,,,,
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PortD,PD8,LPUART1_TX,,,,,,,,,
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PortD,PD9,LPUART1_RX,,,,,,,,,
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PortD,PD10,,,,,,,,,,
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PortD,PD11,LPUART1_CTS,,,,,,,,,
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PortD,PD12,LPUART1_RTS_DE,,,,,,,,,
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PortD,PD13,,,,,,,,,,
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PortD,PD14,,,,,,,,,,
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PortD,PD15,USB_CRS_SYNC,,,,,,,,,
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PortE,PE0,,,EVENTOUT,,,,,,,
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PortE,PE1,,,EVENTOUT,,,,,,,
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PortE,PE2,,,TIM3_ETR,,,,,,,
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PortE,PE3,TIM22_CH1,,TIM3_CH1,,,,,,,
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PortE,PE4,TIM22_CH2,,TIM3_CH2,,,,,,,
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PortE,PE5,TIM21_CH1,,TIM3_CH3,,,,,,,
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PortE,PE6,TIM21_CH2,,TIM3_CH4,,,,,,,
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PortE,PE7,,,,,,,USART5_CK/USART5_RTS_DE,,,
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PortE,PE8,,,,,,,USART4_TX,,,
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PortE,PE9,TIM2_CH1,,TIM2_ETR,,,,USART4_RX,,,
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PortE,PE10,TIM2_CH2,,,,,,USART5_TX,,,
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PortE,PE11,TIM2_CH3,,,,,,USART5_RX,,,
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PortE,PE12,TIM2_CH4,,SPI1_NSS,,,,,,,
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PortE,PE13,,,SPI1_SCK,,,,,,,
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PortE,PE14,,,SPI1_MISO,,,,,,,
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PortE,PE15,,,SPI1_MOSI,,,,,,,
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PortH,PH0,USB_CRS_SYNC,,,,,,,,,
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PortH,PH1,,,,,,,,,,
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27
ports/stm32/boards/stm32l072xz.ld
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27
ports/stm32/boards/stm32l072xz.ld
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/*
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GNU linker script for STM32F072xZ
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*/
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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 192K
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
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}
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/* produce a link error if there is not this amount of RAM for these sections */
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_minimum_stack_size = 2K;
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_minimum_heap_size = 8K;
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_ram_start = ORIGIN(RAM);
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);
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/* Define the top end of the stack. The stack is full descending so begins just
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above last byte of RAM. Note that EABI requires the stack to be 8-byte
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aligned for a call. */
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_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
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_sstack = _estack - 4K;
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/* RAM extents for the main heap */
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_heap_start = _ebss;
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_heap_end = _sstack;
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91
ports/stm32/boards/stm32l0xx_hal_conf_base.h
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91
ports/stm32/boards/stm32l0xx_hal_conf_base.h
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MICROPY_INCLUDED_STM32L0XX_HAL_CONF_BASE_H
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#define MICROPY_INCLUDED_STM32L0XX_HAL_CONF_BASE_H
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// Include various HAL modules for convenience
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#include "stm32l0xx_hal_dma.h"
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#include "stm32l0xx_hal_adc.h"
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#include "stm32l0xx_hal_cortex.h"
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#include "stm32l0xx_hal_crc.h"
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#include "stm32l0xx_hal_dac.h"
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#include "stm32l0xx_hal_flash.h"
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#include "stm32l0xx_hal_gpio.h"
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#include "stm32l0xx_hal_i2c.h"
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#include "stm32l0xx_hal_i2s.h"
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#include "stm32l0xx_hal_iwdg.h"
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#include "stm32l0xx_hal_pcd.h"
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#include "stm32l0xx_hal_pwr.h"
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#include "stm32l0xx_hal_rcc.h"
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#include "stm32l0xx_hal_rtc.h"
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#include "stm32l0xx_hal_spi.h"
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#include "stm32l0xx_hal_tim.h"
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#include "stm32l0xx_hal_uart.h"
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#include "stm32l0xx_hal_usart.h"
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#include "stm32l0xx_hal_wwdg.h"
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// Enable various HAL modules
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#define HAL_MODULE_ENABLED
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#define HAL_ADC_MODULE_ENABLED
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#define HAL_CORTEX_MODULE_ENABLED
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#define HAL_CRC_MODULE_ENABLED
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#define HAL_DAC_MODULE_ENABLED
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#define HAL_DMA_MODULE_ENABLED
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#define HAL_FLASH_MODULE_ENABLED
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#define HAL_GPIO_MODULE_ENABLED
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#define HAL_I2C_MODULE_ENABLED
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#define HAL_I2S_MODULE_ENABLED
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#define HAL_IWDG_MODULE_ENABLED
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#define HAL_PCD_MODULE_ENABLED
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#define HAL_PWR_MODULE_ENABLED
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#define HAL_RCC_MODULE_ENABLED
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#define HAL_RTC_MODULE_ENABLED
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#define HAL_SPI_MODULE_ENABLED
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#define HAL_TIM_MODULE_ENABLED
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#define HAL_UART_MODULE_ENABLED
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#define HAL_USART_MODULE_ENABLED
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#define HAL_WWDG_MODULE_ENABLED
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// Oscillator values in Hz
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#define HSI_VALUE (16000000)
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#define HSI48_VALUE (48000000)
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#define LSI_VALUE (37000)
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#define MSI_VALUE (2097152)
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// SysTick has the highest priority
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#define TICK_INT_PRIORITY (0x00)
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// Miscellaneous HAL settings
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#define PREFETCH_ENABLE 1
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#define PREREAD_ENABLE 0
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#define BUFFER_CACHE_DISABLE 0
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#define USE_RTOS 0
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#define USE_SPI_CRC 0
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// HAL parameter assertions are disabled
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#define assert_param(expr) ((void)0)
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#endif // MICROPY_INCLUDED_STM32L0XX_HAL_CONF_BASE_H
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