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stmhal: Add pyb.stop() and pyb.standby() functions.

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This commit is contained in:
Damien George 2014-10-06 21:20:12 +01:00
parent cc5b4a2653
commit 9b6617ea8b
2 changed files with 20 additions and 41 deletions
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1
stmhal/Makefile
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@ -143,6 +143,7 @@ SRC_HAL = $(addprefix $(HAL_DIR)/src/,\
stm32f4xx_hal_i2c.c \ stm32f4xx_hal_i2c.c \
stm32f4xx_hal_pcd.c \ stm32f4xx_hal_pcd.c \
stm32f4xx_hal_pcd_ex.c \ stm32f4xx_hal_pcd_ex.c \
stm32f4xx_hal_pwr.c \
stm32f4xx_hal_rcc.c \ stm32f4xx_hal_rcc.c \
stm32f4xx_hal_rcc_ex.c \ stm32f4xx_hal_rcc_ex.c \
stm32f4xx_hal_rng.c \ stm32f4xx_hal_rng.c \

60
stmhal/modpyb.c
View File

@ -359,58 +359,36 @@ STATIC mp_obj_t pyb_udelay(mp_obj_t usec_in) {
} }
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_udelay_obj, pyb_udelay); STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_udelay_obj, pyb_udelay);
#if 0 /// \function stop()
STATIC void SYSCLKConfig_STOP(void) {
/* After wake-up from STOP reconfigure the system clock */
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET) {
}
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) {
}
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while (RCC_GetSYSCLKSource() != 0x08) {
}
}
#endif
STATIC mp_obj_t pyb_stop(void) { STATIC mp_obj_t pyb_stop(void) {
#if 0 HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
PWR_EnterSTANDBYMode();
//PWR_FlashPowerDownCmd(ENABLE); don't know what the logic is with this
/* Enter Stop Mode */ // reconfigure the system clock after waking up
PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
/* Configures system clock after wake-up from STOP: enable HSE, PLL and select // enable HSE
* PLL as system clock source (HSE and PLL are disabled in STOP mode) */ __HAL_RCC_HSE_CONFIG(RCC_HSE_ON);
SYSCLKConfig_STOP(); while (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY)) {
}
// enable PLL
__HAL_RCC_PLL_ENABLE();
while (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)) {
}
// select PLL as system clock source
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
}
//PWR_FlashPowerDownCmd(DISABLE);
#endif
return mp_const_none; return mp_const_none;
} }
MP_DEFINE_CONST_FUN_OBJ_0(pyb_stop_obj, pyb_stop); MP_DEFINE_CONST_FUN_OBJ_0(pyb_stop_obj, pyb_stop);
/// \function standby()
STATIC mp_obj_t pyb_standby(void) { STATIC mp_obj_t pyb_standby(void) {
#if 0 HAL_PWR_EnterSTANDBYMode();
PWR_EnterSTANDBYMode();
#endif
return mp_const_none; return mp_const_none;
} }
MP_DEFINE_CONST_FUN_OBJ_0(pyb_standby_obj, pyb_standby); MP_DEFINE_CONST_FUN_OBJ_0(pyb_standby_obj, pyb_standby);
/// \function have_cdc() /// \function have_cdc()