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Merge pull request #7663 from blues/fix-swan_r5_LSE_drive_level 

fix: Increases drive strength of the 32kHz external crystal
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Dan Halbert 2023-03-01 15:39:08 -05:00 committed by GitHub
parent 8e87b92deb e2c6cf5929
commit 965caa0302
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 6 additions and 1 deletions
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3
ports/stm/boards/swan_r5/mpconfigboard.h
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@ -45,6 +45,9 @@
#define BOARD_HAS_LOW_SPEED_CRYSTAL (1)
#define BOARD_HAS_HIGH_SPEED_CRYSTAL (0)
// Increase drive strength of 32kHz external crystal, in line with calculations specified in ST AN2867 sections 3.3, 3.4, and STM32L4 datasheet DS12023 Table 58. LSE oscillator characteristics.
// The drive strength RCC_LSEDRIVE_LOW is marginal for the 32kHz crystal oscillator stability, and RCC_LSEDRIVE_MEDIUMLOW meets the calculated drive strength with a small margin for parasitic capacitance.
#define BOARD_LSE_DRIVE_LEVEL RCC_LSEDRIVE_MEDIUMLOW
// Bootloader only
#ifdef UF2_BOOTLOADER_ENABLED

4
ports/stm/peripherals/stm32l4/clocks.c
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@ -39,6 +39,8 @@
#error HSE support needs to be added for the L4 family.
#elif !BOARD_HAS_LOW_SPEED_CRYSTAL
#error LSE clock source required
#elif !defined(BOARD_LSE_DRIVE_LEVEL)
#error BOARD_LSE_DRIVE_LEVEL is not defined for this board. The board should define the drive strength of 32kHz external crystal in line with calculations specified in ST AN2867 sections 3.3, 3.4, and STM32L4 datasheet DS12023 Table 58, LSE oscillator characteristics.
#endif
void Error_Handler(void) {
@ -57,7 +59,7 @@ void stm32_peripherals_clocks_init(void) {
// Configure LSE Drive
HAL_PWR_EnableBkUpAccess();
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
__HAL_RCC_LSEDRIVE_CONFIG(BOARD_LSE_DRIVE_LEVEL);
__HAL_RCC_PWR_CLK_ENABLE();
/** Configure the main internal regulator output voltage