djsundog
/
circuitpython
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Cosmetic fixes

This commit is contained in:
Hierophect 2019-08-18 19:08:27 -04:00
parent 7dbf1a8caa
commit 95411a62b3
6 changed files with 73 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ports/stm32f4/boards/stm32f411ve_discovery/mpconfigboard.h
View File

@ -39,4 +39,4 @@
#define BOARD_FLASH_SIZE (FLASH_SIZE - 0x2000 - 0xC000 - CIRCUITPY_INTERNAL_NVM_SIZE)
#define AUTORESET_DELAY_MS 500
#define AUTORESET_DELAY_MS 500

2
ports/stm32f4/mpconfigport.mk
View File

@ -21,4 +21,4 @@ CIRCUITPY_MINIMAL_BUILD = 1
CIRCUITPY_MICROCONTROLLER = 1
CIRCUITPY_BUSIO = 1
CIRCUITPY_TIME = 1
#endif
#endif

52
ports/stm32f4/peripherals/stm32f4/stm32f411xe/clocks.c
View File

@ -28,34 +28,34 @@
void stm32f4_peripherals_clocks_init(void) {
//System clock init
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
/* Enable Power Control clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable Power Control clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
}

68
ports/stm32f4/peripherals/stm32f4/stm32f411xe/gpio.c
View File

@ -108,47 +108,47 @@
#include "stm32f4/gpio.h"
void stm32f4_peripherals_gpio_init(void) {
//Enable all GPIO for now
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
//Enable all GPIO for now
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, LD4_Pin|LD3_Pin|LD5_Pin|LD6_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, LD4_Pin|LD3_Pin|LD5_Pin|LD6_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : LD4_Pin LD3_Pin LD5_Pin LD6_Pin */
GPIO_InitStruct.Pin = LD4_Pin|LD3_Pin|LD5_Pin|LD6_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pins : LD4_Pin LD3_Pin LD5_Pin LD6_Pin */
GPIO_InitStruct.Pin = LD4_Pin|LD3_Pin|LD5_Pin|LD6_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
//Status LED chain
stm32f4_peripherals_status_led(0,1);
stm32f4_peripherals_status_led(1,0);
stm32f4_peripherals_status_led(2,0);
stm32f4_peripherals_status_led(3,0);
//Status LED chain
stm32f4_peripherals_status_led(0,1);
stm32f4_peripherals_status_led(1,0);
stm32f4_peripherals_status_led(2,0);
stm32f4_peripherals_status_led(3,0);
}
//LEDs are inverted on F411 DISCO
void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
switch(led)
{
case 0: HAL_GPIO_WritePin(GPIOD, LD4_Pin, (state ^ 1));
break;
case 1: HAL_GPIO_WritePin(GPIOD, LD3_Pin, (state ^ 1));
break;
case 2: HAL_GPIO_WritePin(GPIOD, LD5_Pin, (state ^ 1));
break;
case 3: HAL_GPIO_WritePin(GPIOD, LD6_Pin, (state ^ 1));
break;
default: break;
}
switch(led)
{
case 0: HAL_GPIO_WritePin(GPIOD, LD4_Pin, (state ^ 1));
break;
case 1: HAL_GPIO_WritePin(GPIOD, LD3_Pin, (state ^ 1));
break;
case 2: HAL_GPIO_WritePin(GPIOD, LD5_Pin, (state ^ 1));
break;
case 3: HAL_GPIO_WritePin(GPIOD, LD6_Pin, (state ^ 1));
break;
default: break;
}
}

20
ports/stm32f4/supervisor/internal_flash.c
View File

@ -113,8 +113,8 @@ static int32_t convert_block_to_flash_addr(uint32_t block) {
}
mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) {
int32_t src = convert_block_to_flash_addr(block);
if (src == -1) {
int32_t src = convert_block_to_flash_addr(block);
if (src == -1) {
// bad block number
return false;
}
@ -163,14 +163,14 @@ bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) {
return false;
}
__HAL_FLASH_DATA_CACHE_DISABLE();
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
__HAL_FLASH_DATA_CACHE_DISABLE();
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
__HAL_FLASH_DATA_CACHE_RESET();
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
__HAL_FLASH_DATA_CACHE_RESET();
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
__HAL_FLASH_DATA_CACHE_ENABLE();
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
__HAL_FLASH_DATA_CACHE_ENABLE();
// reprogram the sector
for (uint32_t i = 0; i < sector_size; i++) {
@ -183,7 +183,7 @@ bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) {
sector_start_addr += 1;
}
// lock the flash
// lock the flash
HAL_FLASH_Lock();
return true;
@ -191,7 +191,7 @@ bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) {
mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) {
for (size_t i = 0; i < num_blocks; i++) {
for (size_t i = 0; i < num_blocks; i++) {
if (!supervisor_flash_write_block(src + i * FILESYSTEM_BLOCK_SIZE, block_num + i)) {
return 1; // error
}

2
ports/stm32f4/supervisor/port.c
View File

@ -70,5 +70,5 @@ uint32_t port_get_saved_word(void) {
}
void HardFault_Handler(void) {
while(1) {}
}