Merge pull request #3281 from dhalbert/fix-spim3-buffer-location
SPIM3 buffer must be in first 64kB of RAM
This commit is contained in:
commit
94ecf33a5c
@ -6,10 +6,3 @@ USB_MANUFACTURER = "Arduino"
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MCU_CHIP = nrf52840
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INTERNAL_FLASH_FILESYSTEM = 1
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# Allocate two, not just one I2C peripheral, so that we have both
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# on-board and off-board I2C available.
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# When SPIM3 becomes available we'll be able to have two I2C and two SPI peripherals.
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# We use a CFLAGS define here because there are include order issues
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# if we try to include "mpconfigport.h" into nrfx_config.h .
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CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2
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@ -8,9 +8,3 @@ MCU_CHIP = nrf52840
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QSPI_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICE_COUNT = 1
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EXTERNAL_FLASH_DEVICES = "GD25Q16C"
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# Allocate two, not just one I2C peripheral for CPB, so that we have both
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# on-board and off-board I2C available.
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# We use a CFLAGS define here because there are include order issues
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# if we try to include "mpconfigport.h" into nrfx_config.h .
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CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2
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@ -18,13 +18,16 @@ MEMORY
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FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}
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/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice */
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/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.
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/* To measure the minimum required amount of memory for given configuration, set this number
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high enough to work and then check the mutation of the value done by sd_ble_enable. */
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SPIM3_RAM (rw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}
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RAM (xrw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}
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/* SoftDevice RAM must start at the beginning of RAM: 0x2000000 (RAM_START_ADDR).
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On nRF52840, the first 64kB of RAM is composed of 8 8kB RAM blocks. Above those is
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RAM block 8, which is 192kB.
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If SPIM3_BUFFER_RAM_SIZE is 8kB, as opposed to zero, it must be in the first 64kB of RAM.
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So the amount of RAM reserved for the SoftDevice must be no more than 56kB.
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*/
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RAM (xrw) : ORIGIN = ${RAM_START_ADDR}, LENGTH = ${RAM_SIZE}
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SD_RAM (rw) : ORIGIN = ${SOFTDEVICE_RAM_START_ADDR}, LENGTH = ${SOFTDEVICE_RAM_SIZE}
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SPIM3_RAM (rw) : ORIGIN = ${SPIM3_BUFFER_RAM_START_ADDR}, LENGTH = ${SPIM3_BUFFER_RAM_SIZE}
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APP_RAM (xrw) : ORIGIN = ${APP_RAM_START_ADDR}, LENGTH = ${APP_RAM_SIZE}
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}
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/* produce a link error if there is not this amount of RAM available */
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@ -32,16 +35,16 @@ _minimum_heap_size = 0;
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/* top end of the stack */
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/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
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_estack = ORIGIN(RAM) + LENGTH(RAM);
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/*_stack_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);*/
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_estack = ORIGIN(APP_RAM) + LENGTH(APP_RAM);
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/* RAM extents for the garbage collector */
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);
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_ram_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);
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_heap_end = 0x20020000; /* tunable */
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/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. */
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_spim3_ram = ORIGIN(SPIM3_RAM);
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_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);
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_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(SPIM3_RAM);
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/* define output sections */
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SECTIONS
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@ -87,7 +90,7 @@ SECTIONS
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
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} >RAM
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} >APP_RAM
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/* Zero-initialized data section */
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.bss :
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@ -100,7 +103,7 @@ SECTIONS
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
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} >RAM
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} >APP_RAM
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/* Uninitialized data section
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Data placed into this section will remain unchanged across reboots. */
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@ -113,7 +116,7 @@ SECTIONS
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. = ALIGN(4);
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_euninitialized = .; /* define a global symbol at uninitialized end; currently unused */
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} >RAM
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} >APP_RAM
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/* this is to define the start of the heap, and make sure we have a minimum size */
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.heap :
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@ -123,7 +126,7 @@ SECTIONS
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PROVIDE ( _end = . );
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_heap_start = .; /* define a global symbol at heap start */
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. = . + _minimum_heap_size;
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} >RAM
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} >APP_RAM
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/* this just checks there is enough RAM for the stack */
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.stack :
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@ -131,7 +134,7 @@ SECTIONS
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. = ALIGN(4);
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. = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};
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. = ALIGN(4);
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} >RAM
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} >APP_RAM
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/* Remove exception unwinding information, since Circuit Python
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does not support this GCC feature. */
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@ -8,10 +8,3 @@ MCU_CHIP = nrf52840
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QSPI_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICE_COUNT = 1
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EXTERNAL_FLASH_DEVICES = "W25Q16JV_IQ"
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# Allocate two, not just one I2C peripheral for Bluefi, so that we have both
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# on-board and off-board I2C available.
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# When SPIM3 becomes available we'll be able to have two I2C and two SPI peripherals.
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# We use a CFLAGS define here because there are include order issues
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# if we try to include "mpconfigport.h" into nrfx_config.h .
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CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2
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@ -46,3 +46,5 @@
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#define BLEIO_PERIPH_ROLE_COUNT 2
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#define BLEIO_TOTAL_CONNECTION_COUNT 2
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#define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 2)
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#define SOFTDEVICE_RAM_SIZE (32*1024)
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@ -27,9 +27,5 @@ CIRCUITPY_ULAB = 0
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SUPEROPT_GC = 0
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# These defines must be overridden before mpconfigboard.h is included, which is
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# why they are passed on the command line.
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CFLAGS += -DSPIM3_BUFFER_SIZE=0 -DSOFTDEVICE_RAM_SIZE='(32*1024)'
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# Override optimization to keep binary small
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OPTIMIZATION_FLAGS = -Os
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@ -52,3 +52,5 @@
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#define BLEIO_PERIPH_ROLE_COUNT 2
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#define BLEIO_TOTAL_CONNECTION_COUNT 2
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#define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 2)
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#define SOFTDEVICE_RAM_SIZE (32*1024)
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@ -29,9 +29,5 @@ CIRCUITPY_WATCHDOG = 1
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# Enable micropython.native
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#CIRCUITPY_ENABLE_MPY_NATIVE = 1
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# These defines must be overridden before mpconfigboard.h is included, which is
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# why they are passed on the command line.
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CFLAGS += -DSPIM3_BUFFER_SIZE=0 -DSOFTDEVICE_RAM_SIZE='(32*1024)' -DNRFX_SPIM3_ENABLED=0
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# Override optimization to keep binary small
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OPTIMIZATION_FLAGS = -Os
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@ -61,7 +61,7 @@
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#endif
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#ifndef BLEIO_HVN_TX_QUEUE_SIZE
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#define BLEIO_HVN_TX_QUEUE_SIZE 9
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#define BLEIO_HVN_TX_QUEUE_SIZE 5
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#endif
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#ifndef BLEIO_CENTRAL_ROLE_COUNT
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@ -120,11 +120,11 @@ STATIC uint32_t ble_stack_enable(void) {
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// Start with no event handlers, etc.
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ble_drv_reset();
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// Set everything up to have one persistent code editing connection and one user managed
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// connection. In the future we could move .data and .bss to the other side of the stack and
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// In the future we might move .data and .bss to the other side of the stack and
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// dynamically adjust for different memory requirements of the SD based on boot.py
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// configuration.
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uint32_t app_ram_start = (uint32_t) &_ram_start;
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// configuration. But we still need to keep the SPIM3 buffer (if needed) in the first 64kB of RAM.
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uint32_t sd_ram_end = SOFTDEVICE_RAM_START_ADDR + SOFTDEVICE_RAM_SIZE;
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ble_cfg_t ble_conf;
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ble_conf.conn_cfg.conn_cfg_tag = BLE_CONN_CFG_TAG_CUSTOM;
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@ -135,7 +135,7 @@ STATIC uint32_t ble_stack_enable(void) {
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// Event length here can influence throughput so perhaps make multiple connection profiles
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// available.
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ble_conf.conn_cfg.params.gap_conn_cfg.event_length = BLE_GAP_EVENT_LENGTH_DEFAULT;
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err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &ble_conf, app_ram_start);
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err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &ble_conf, sd_ram_end);
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if (err_code != NRF_SUCCESS) {
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return err_code;
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}
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@ -147,7 +147,7 @@ STATIC uint32_t ble_stack_enable(void) {
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ble_conf.gap_cfg.role_count_cfg.periph_role_count = BLEIO_PERIPH_ROLE_COUNT;
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// central_role_count costs 648 bytes for 1 to 2, then ~1250 for each further increment.
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ble_conf.gap_cfg.role_count_cfg.central_role_count = BLEIO_CENTRAL_ROLE_COUNT;
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err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_conf, app_ram_start);
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err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_conf, sd_ram_end);
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if (err_code != NRF_SUCCESS) {
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return err_code;
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}
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@ -158,7 +158,7 @@ STATIC uint32_t ble_stack_enable(void) {
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// DevZone recommends not setting this directly, but instead changing gap_conn_cfg.event_length.
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// However, we are setting connection extension, so this seems to make sense.
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ble_conf.conn_cfg.params.gatts_conn_cfg.hvn_tx_queue_size = BLEIO_HVN_TX_QUEUE_SIZE;
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err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATTS, &ble_conf, app_ram_start);
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err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATTS, &ble_conf, sd_ram_end);
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if (err_code != NRF_SUCCESS) {
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return err_code;
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}
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@ -167,7 +167,7 @@ STATIC uint32_t ble_stack_enable(void) {
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memset(&ble_conf, 0, sizeof(ble_conf));
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ble_conf.conn_cfg.conn_cfg_tag = BLE_CONN_CFG_TAG_CUSTOM;
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ble_conf.conn_cfg.params.gatt_conn_cfg.att_mtu = BLE_GATTS_VAR_ATTR_LEN_MAX;
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err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &ble_conf, app_ram_start);
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err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &ble_conf, sd_ram_end);
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if (err_code != NRF_SUCCESS) {
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return err_code;
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}
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@ -177,7 +177,7 @@ STATIC uint32_t ble_stack_enable(void) {
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memset(&ble_conf, 0, sizeof(ble_conf));
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// Each increment to the BLE_GATTS_ATTR_TAB_SIZE_DEFAULT multiplier costs 1408 bytes.
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ble_conf.gatts_cfg.attr_tab_size.attr_tab_size = BLEIO_ATTR_TAB_SIZE;
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err_code = sd_ble_cfg_set(BLE_GATTS_CFG_ATTR_TAB_SIZE, &ble_conf, app_ram_start);
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err_code = sd_ble_cfg_set(BLE_GATTS_CFG_ATTR_TAB_SIZE, &ble_conf, sd_ram_end);
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if (err_code != NRF_SUCCESS) {
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return err_code;
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}
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@ -187,13 +187,15 @@ STATIC uint32_t ble_stack_enable(void) {
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memset(&ble_conf, 0, sizeof(ble_conf));
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// Each additional vs_uuid_count costs 16 bytes.
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ble_conf.common_cfg.vs_uuid_cfg.vs_uuid_count = BLEIO_VS_UUID_COUNT; // Defaults to 10.
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err_code = sd_ble_cfg_set(BLE_COMMON_CFG_VS_UUID, &ble_conf, app_ram_start);
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err_code = sd_ble_cfg_set(BLE_COMMON_CFG_VS_UUID, &ble_conf, sd_ram_end);
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if (err_code != NRF_SUCCESS) {
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return err_code;
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}
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// This sets app_ram_start to the minimum value needed for the settings set above.
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err_code = sd_ble_enable(&app_ram_start);
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// This sets sd_ram_end to the minimum value needed for the settings set above.
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// You can set a breakpoint just after this call and examine sd_ram_end to see
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// how much RAM the SD needs with the configuration above.
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err_code = sd_ble_enable(&sd_ram_end);
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if (err_code != NRF_SUCCESS) {
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return err_code;
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}
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@ -57,7 +57,7 @@ STATIC spim_peripheral_t spim_peripherals[] = {
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// Allocate SPIM3 first.
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{ .spim = NRFX_SPIM_INSTANCE(3),
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.max_frequency = 32000000,
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.max_xfer_size = MIN(SPIM3_BUFFER_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1)
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.max_xfer_size = MIN(SPIM3_BUFFER_RAM_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1)
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},
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#endif
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#if NRFX_CHECK(NRFX_SPIM2_ENABLED)
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@ -87,8 +87,7 @@ STATIC bool never_reset[MP_ARRAY_SIZE(spim_peripherals)];
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// Separate RAM area for SPIM3 transmit buffer to avoid SPIM3 hardware errata.
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// https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF52840_Rev2%2FERR%2FnRF52840%2FRev2%2Flatest%2Fanomaly_840_198.html
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extern uint32_t _spim3_ram;
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STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) &_spim3_ram;
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STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) SPIM3_BUFFER_RAM_START_ADDR;
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void spi_reset(void) {
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for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) {
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@ -10,6 +10,7 @@
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// START_LD_DEFINES
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/*FLASH_SIZE=*/ FLASH_SIZE;
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/*RAM_START_ADDR=*/ RAM_START_ADDR;
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/*RAM_SIZE=*/ RAM_SIZE;
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/*MBR_START_ADDR=*/ MBR_START_ADDR;
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@ -41,5 +42,11 @@
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/*BOOTLOADER_SETTINGS_START_ADDR=*/ BOOTLOADER_SETTINGS_START_ADDR;
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/*BOOTLOADER_SETTINGS_SIZE=*/ BOOTLOADER_SETTINGS_SIZE;
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/*SOFTDEVICE_RAM_START_ADDR=*/ SOFTDEVICE_RAM_START_ADDR;
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/*SOFTDEVICE_RAM_SIZE=*/ SOFTDEVICE_RAM_SIZE;
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/*SPIM3_BUFFER_SIZE=*/ SPIM3_BUFFER_SIZE;
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/*SPIM3_BUFFER_RAM_START_ADDR=*/ SPIM3_BUFFER_RAM_START_ADDR;
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/*SPIM3_BUFFER_RAM_SIZE=*/ SPIM3_BUFFER_RAM_SIZE;
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/*APP_RAM_START_ADDR=*/ APP_RAM_START_ADDR;
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/*APP_RAM_SIZE=*/ APP_RAM_SIZE;
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@ -34,32 +34,6 @@
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#include "nrf_sdm.h" // for SD_FLASH_SIZE
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#include "peripherals/nrf/nvm.h" // for FLASH_PAGE_SIZE
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// Max RAM used by SoftDevice. Can be changed when SoftDevice parameters are changed.
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// See common.template.ld.
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#ifndef SOFTDEVICE_RAM_SIZE
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#define SOFTDEVICE_RAM_SIZE (64*1024)
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#endif
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#ifdef NRF52840
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#define MICROPY_PY_SYS_PLATFORM "nRF52840"
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#define FLASH_SIZE (0x100000) // 1MiB
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#define RAM_SIZE (0x40000) // 256 KiB
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// Special RAM area for SPIM3 transmit buffer, to work around hardware bug.
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// See common.template.ld.
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#define SPIM3_BUFFER_SIZE (8192)
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#endif
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#ifdef NRF52833
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#define MICROPY_PY_SYS_PLATFORM "nRF52833"
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#define FLASH_SIZE (0x80000) // 512 KiB
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#define RAM_SIZE (0x20000) // 128 KiB
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// Special RAM area for SPIM3 transmit buffer, to work around hardware bug.
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// See common.template.ld.
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#ifndef SPIM3_BUFFER_SIZE
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#define SPIM3_BUFFER_SIZE (8192)
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#endif
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#endif
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#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1)
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#define MICROPY_PY_FUNCTION_ATTRS (1)
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#define MICROPY_PY_IO (1)
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@ -69,7 +43,26 @@
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#define MICROPY_PY_UJSON (1)
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// 24kiB stack
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#define CIRCUITPY_DEFAULT_STACK_SIZE 0x6000
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#define CIRCUITPY_DEFAULT_STACK_SIZE (24*1024)
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#ifdef NRF52840
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#define MICROPY_PY_SYS_PLATFORM "nRF52840"
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#define FLASH_SIZE (1024*1024) // 1MiB
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#define RAM_SIZE (256*1024) // 256 KiB
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// Special RAM area for SPIM3 transmit buffer, to work around hardware bug.
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// See common.template.ld.
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#define SPIM3_BUFFER_RAM_SIZE (8*1024) // 8 KiB
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#endif
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#ifdef NRF52833
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#define MICROPY_PY_SYS_PLATFORM "nRF52833"
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#define FLASH_SIZE (512*1024) // 512 KiB
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#define RAM_SIZE (128*1024) // 128 KiB
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// SPIM3 buffer is not needed on nRF52833: the SPIM3 hw bug is not present.
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#ifndef SPIM3_BUFFER_RAM_SIZE
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#define SPIM3_BUFFER_RAM_SIZE (0)
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#endif
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#endif
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@ -79,7 +72,7 @@
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// Definitions that might be overriden by mpconfigboard.h
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#ifndef CIRCUITPY_INTERNAL_NVM_SIZE
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#define CIRCUITPY_INTERNAL_NVM_SIZE (8192)
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#define CIRCUITPY_INTERNAL_NVM_SIZE (8*1024)
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#endif
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#ifndef BOARD_HAS_32KHZ_XTAL
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@ -88,11 +81,11 @@
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#endif
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#if INTERNAL_FLASH_FILESYSTEM
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#ifndef CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE
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#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (256*1024)
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#endif
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#ifndef CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE
|
||||
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (256*1024)
|
||||
#endif
|
||||
#else
|
||||
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0)
|
||||
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0)
|
||||
#endif
|
||||
|
||||
// Flash layout, starting at 0x00000000
|
||||
@ -116,7 +109,7 @@
|
||||
|
||||
// SD_FLASH_SIZE is from nrf_sdm.h
|
||||
#define ISR_START_ADDR (SD_FLASH_START_ADDR + SD_FLASH_SIZE)
|
||||
#define ISR_SIZE (0x1000) // 4kiB
|
||||
#define ISR_SIZE (4*1024) // 4kiB
|
||||
|
||||
// Smallest unit of flash that can be erased.
|
||||
#define FLASH_ERASE_SIZE FLASH_PAGE_SIZE
|
||||
@ -127,12 +120,12 @@
|
||||
|
||||
// Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld
|
||||
#define BOOTLOADER_START_ADDR (FLASH_SIZE - BOOTLOADER_SIZE - BOOTLOADER_SETTINGS_SIZE - BOOTLOADER_MBR_SIZE)
|
||||
#define BOOTLOADER_MBR_SIZE (0x1000) // 4kib
|
||||
#define BOOTLOADER_MBR_SIZE (4*1024) // 4kib
|
||||
#ifndef BOOTLOADER_SIZE
|
||||
#define BOOTLOADER_SIZE (0xA000) // 40kiB
|
||||
#define BOOTLOADER_SIZE (40*1024) // 40kiB
|
||||
#endif
|
||||
#define BOOTLOADER_SETTINGS_START_ADDR (FLASH_SIZE - BOOTLOADER_SETTINGS_SIZE)
|
||||
#define BOOTLOADER_SETTINGS_SIZE (0x1000) // 4kiB
|
||||
#define BOOTLOADER_SETTINGS_SIZE (4*1024) // 4kiB
|
||||
|
||||
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR (BOOTLOADER_START_ADDR - CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE)
|
||||
|
||||
@ -180,11 +173,46 @@
|
||||
#error No space left in flash for firmware after specifying other regions!
|
||||
#endif
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// RAM space definitions
|
||||
|
||||
#define MICROPY_PORT_ROOT_POINTERS \
|
||||
CIRCUITPY_COMMON_ROOT_POINTERS \
|
||||
uint16_t* pixels_pattern_heap; \
|
||||
ble_drv_evt_handler_entry_t* ble_drv_evt_handler_entries; \
|
||||
// Max RAM used by SoftDevice. Can be changed when SoftDevice parameters are changed.
|
||||
// On nRF52840, the first 64kB of RAM is composed of 8 8kB RAM blocks. Above those is
|
||||
// RAM block 8, which is 192kB.
|
||||
// If SPIM3_BUFFER_RAM_SIZE is 8kB, as opposed to zero, it must be in the first 64kB of RAM.
|
||||
// So the amount of RAM reserved for the SoftDevice must be no more than 56kB.
|
||||
// SoftDevice 6.1.0 with 5 connections and various increases can be made to use < 56kB.
|
||||
// To measure the minimum required amount of memory for given configuration, set this number
|
||||
// high enough to work and then check the mutation of the value done by sd_ble_enable().
|
||||
// See common.template.ld.
|
||||
#ifndef SOFTDEVICE_RAM_SIZE
|
||||
#define SOFTDEVICE_RAM_SIZE (56*1024)
|
||||
#endif
|
||||
|
||||
|
||||
#define RAM_START_ADDR (0x20000000)
|
||||
#define SOFTDEVICE_RAM_START_ADDR (RAM_START_ADDR)
|
||||
#define SPIM3_BUFFER_RAM_START_ADDR (SOFTDEVICE_RAM_START_ADDR + SOFTDEVICE_RAM_SIZE)
|
||||
#define APP_RAM_START_ADDR (SPIM3_BUFFER_RAM_START_ADDR + SPIM3_BUFFER_RAM_SIZE)
|
||||
#define APP_RAM_SIZE (RAM_START_ADDR + RAM_SIZE - APP_RAM_START_ADDR)
|
||||
|
||||
#if SPIM3_BUFFER_RAM_SIZE > 0 && SOFTDEVICE_RAM_SIZE + SPIM3_BUFFER_RAM_SIZE > (64*1024)
|
||||
#error SPIM3 buffer must be in the first 64kB of RAM.
|
||||
#endif
|
||||
|
||||
#if SOFTDEVICE_RAM_SIZE + SPIM3_BUFFER_RAM_SIZE + APP_RAM_SIZE > RAM_SIZE
|
||||
#error RAM size regions overflow RAM
|
||||
#endif
|
||||
|
||||
#if SOFTDEVICE_RAM_SIZE + SPIM3_BUFFER_RAM_SIZE + APP_RAM_SIZE < RAM_SIZE
|
||||
#error RAM size regions do not use all of RAM
|
||||
#endif
|
||||
|
||||
|
||||
#define MICROPY_PORT_ROOT_POINTERS \
|
||||
CIRCUITPY_COMMON_ROOT_POINTERS \
|
||||
uint16_t* pixels_pattern_heap; \
|
||||
ble_drv_evt_handler_entry_t* ble_drv_evt_handler_entries; \
|
||||
|
||||
|
||||
#endif // NRF5_MPCONFIGPORT_H__
|
||||
|
@ -5,7 +5,7 @@
|
||||
#define NRFX_POWER_ENABLED 1
|
||||
#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
|
||||
|
||||
// NOTE: THIS WORKAROUND CAUSES BLE CODE TO CRASH.
|
||||
// NOTE: THIS WORKAROUND CAUSES BLE CODE TO CRASH. DO NOT USE.
|
||||
// It doesn't work with the SoftDevice.
|
||||
// See https://devzone.nordicsemi.com/f/nordic-q-a/33982/sdk-15-software-crash-during-spi-session
|
||||
// Turn on nrfx supported workarounds for errata in Rev1 of nRF52840
|
||||
|
Loading…
Reference in New Issue
Block a user