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Merge pull request #3281 from dhalbert/fix-spim3-buffer-location 

SPIM3 buffer must be in first 64kB of RAM
This commit is contained in:
Dan Halbert 2020-08-17 19:28:03 -04:00 committed by GitHub
parent abfe718f46 cf0f3d70b5
commit 94ecf33a5c
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GPG Key ID: 4AEE18F83AFDEB23
13 changed files with 117 additions and 102 deletions
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7
ports/nrf/boards/arduino_nano_33_ble/mpconfigboard.mk
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@ -6,10 +6,3 @@ USB_MANUFACTURER = "Arduino"
MCU_CHIP = nrf52840
INTERNAL_FLASH_FILESYSTEM = 1
# Allocate two, not just one I2C peripheral, so that we have both
# on-board and off-board I2C available.
# When SPIM3 becomes available we'll be able to have two I2C and two SPI peripherals.
# We use a CFLAGS define here because there are include order issues
# if we try to include "mpconfigport.h" into nrfx_config.h .
CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2

6
ports/nrf/boards/circuitplayground_bluefruit/mpconfigboard.mk
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@ -8,9 +8,3 @@ MCU_CHIP = nrf52840
QSPI_FLASH_FILESYSTEM = 1
EXTERNAL_FLASH_DEVICE_COUNT = 1
EXTERNAL_FLASH_DEVICES = "GD25Q16C"
# Allocate two, not just one I2C peripheral for CPB, so that we have both
# on-board and off-board I2C available.
# We use a CFLAGS define here because there are include order issues
# if we try to include "mpconfigport.h" into nrfx_config.h .
CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2

35
ports/nrf/boards/common.template.ld
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@ -18,13 +18,16 @@ MEMORY
FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}
/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice */
/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.
/* To measure the minimum required amount of memory for given configuration, set this number
high enough to work and then check the mutation of the value done by sd_ble_enable. */
SPIM3_RAM (rw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}
RAM (xrw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}
/* SoftDevice RAM must start at the beginning of RAM: 0x2000000 (RAM_START_ADDR).
On nRF52840, the first 64kB of RAM is composed of 8 8kB RAM blocks. Above those is
RAM block 8, which is 192kB.
If SPIM3_BUFFER_RAM_SIZE is 8kB, as opposed to zero, it must be in the first 64kB of RAM.
So the amount of RAM reserved for the SoftDevice must be no more than 56kB.
*/
RAM (xrw) : ORIGIN = ${RAM_START_ADDR}, LENGTH = ${RAM_SIZE}
SD_RAM (rw) : ORIGIN = ${SOFTDEVICE_RAM_START_ADDR}, LENGTH = ${SOFTDEVICE_RAM_SIZE}
SPIM3_RAM (rw) : ORIGIN = ${SPIM3_BUFFER_RAM_START_ADDR}, LENGTH = ${SPIM3_BUFFER_RAM_SIZE}
APP_RAM (xrw) : ORIGIN = ${APP_RAM_START_ADDR}, LENGTH = ${APP_RAM_SIZE}
}
/* produce a link error if there is not this amount of RAM available */
@ -32,16 +35,16 @@ _minimum_heap_size = 0;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/*_stack_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);*/
_estack = ORIGIN(APP_RAM) + LENGTH(APP_RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_ram_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);
_heap_end = 0x20020000; /* tunable */
/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. */
_spim3_ram = ORIGIN(SPIM3_RAM);
_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);
_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(SPIM3_RAM);
/* define output sections */
SECTIONS
@ -87,7 +90,7 @@ SECTIONS
. = ALIGN(4);
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
} >RAM
} >APP_RAM
/* Zero-initialized data section */
.bss :
@ -100,7 +103,7 @@ SECTIONS
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
} >RAM
} >APP_RAM
/* Uninitialized data section
Data placed into this section will remain unchanged across reboots. */
@ -113,7 +116,7 @@ SECTIONS
. = ALIGN(4);
_euninitialized = .; /* define a global symbol at uninitialized end; currently unused */
} >RAM
} >APP_RAM
/* this is to define the start of the heap, and make sure we have a minimum size */
.heap :
@ -123,7 +126,7 @@ SECTIONS
PROVIDE ( _end = . );
_heap_start = .; /* define a global symbol at heap start */
. = . + _minimum_heap_size;
} >RAM
} >APP_RAM
/* this just checks there is enough RAM for the stack */
.stack :
@ -131,7 +134,7 @@ SECTIONS
. = ALIGN(4);
. = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};
. = ALIGN(4);
} >RAM
} >APP_RAM
/* Remove exception unwinding information, since Circuit Python
does not support this GCC feature. */

7
ports/nrf/boards/hiibot_bluefi/mpconfigboard.mk
View File

@ -8,10 +8,3 @@ MCU_CHIP = nrf52840
QSPI_FLASH_FILESYSTEM = 1
EXTERNAL_FLASH_DEVICE_COUNT = 1
EXTERNAL_FLASH_DEVICES = "W25Q16JV_IQ"
# Allocate two, not just one I2C peripheral for Bluefi, so that we have both
# on-board and off-board I2C available.
# When SPIM3 becomes available we'll be able to have two I2C and two SPI peripherals.
# We use a CFLAGS define here because there are include order issues
# if we try to include "mpconfigport.h" into nrfx_config.h .
CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2

2
ports/nrf/boards/pca10100/mpconfigboard.h
View File

@ -46,3 +46,5 @@
#define BLEIO_PERIPH_ROLE_COUNT 2
#define BLEIO_TOTAL_CONNECTION_COUNT 2
#define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 2)
#define SOFTDEVICE_RAM_SIZE (32*1024)

4
ports/nrf/boards/pca10100/mpconfigboard.mk
View File

@ -27,9 +27,5 @@ CIRCUITPY_ULAB = 0
SUPEROPT_GC = 0
# These defines must be overridden before mpconfigboard.h is included, which is
# why they are passed on the command line.
CFLAGS += -DSPIM3_BUFFER_SIZE=0 -DSOFTDEVICE_RAM_SIZE='(32*1024)'
# Override optimization to keep binary small
OPTIMIZATION_FLAGS = -Os

2
ports/nrf/boards/simmel/mpconfigboard.h
View File

@ -52,3 +52,5 @@
#define BLEIO_PERIPH_ROLE_COUNT 2
#define BLEIO_TOTAL_CONNECTION_COUNT 2
#define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 2)
#define SOFTDEVICE_RAM_SIZE (32*1024)

4
ports/nrf/boards/simmel/mpconfigboard.mk
View File

@ -29,9 +29,5 @@ CIRCUITPY_WATCHDOG = 1
# Enable micropython.native
#CIRCUITPY_ENABLE_MPY_NATIVE = 1
# These defines must be overridden before mpconfigboard.h is included, which is
# why they are passed on the command line.
CFLAGS += -DSPIM3_BUFFER_SIZE=0 -DSOFTDEVICE_RAM_SIZE='(32*1024)' -DNRFX_SPIM3_ENABLED=0
# Override optimization to keep binary small
OPTIMIZATION_FLAGS = -Os

28
ports/nrf/common-hal/_bleio/Adapter.c
View File

@ -61,7 +61,7 @@
#endif
#ifndef BLEIO_HVN_TX_QUEUE_SIZE
#define BLEIO_HVN_TX_QUEUE_SIZE 9
#define BLEIO_HVN_TX_QUEUE_SIZE 5
#endif
#ifndef BLEIO_CENTRAL_ROLE_COUNT
@ -120,11 +120,11 @@ STATIC uint32_t ble_stack_enable(void) {
// Start with no event handlers, etc.
ble_drv_reset();
// Set everything up to have one persistent code editing connection and one user managed
// connection. In the future we could move .data and .bss to the other side of the stack and
// In the future we might move .data and .bss to the other side of the stack and
// dynamically adjust for different memory requirements of the SD based on boot.py
// configuration.
uint32_t app_ram_start = (uint32_t) &_ram_start;
// configuration. But we still need to keep the SPIM3 buffer (if needed) in the first 64kB of RAM.
uint32_t sd_ram_end = SOFTDEVICE_RAM_START_ADDR + SOFTDEVICE_RAM_SIZE;
ble_cfg_t ble_conf;
ble_conf.conn_cfg.conn_cfg_tag = BLE_CONN_CFG_TAG_CUSTOM;
@ -135,7 +135,7 @@ STATIC uint32_t ble_stack_enable(void) {
// Event length here can influence throughput so perhaps make multiple connection profiles
// available.
ble_conf.conn_cfg.params.gap_conn_cfg.event_length = BLE_GAP_EVENT_LENGTH_DEFAULT;
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &ble_conf, app_ram_start);
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &ble_conf, sd_ram_end);
if (err_code != NRF_SUCCESS) {
return err_code;
}
@ -147,7 +147,7 @@ STATIC uint32_t ble_stack_enable(void) {
ble_conf.gap_cfg.role_count_cfg.periph_role_count = BLEIO_PERIPH_ROLE_COUNT;
// central_role_count costs 648 bytes for 1 to 2, then ~1250 for each further increment.
ble_conf.gap_cfg.role_count_cfg.central_role_count = BLEIO_CENTRAL_ROLE_COUNT;
err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_conf, app_ram_start);
err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_conf, sd_ram_end);
if (err_code != NRF_SUCCESS) {
return err_code;
}
@ -158,7 +158,7 @@ STATIC uint32_t ble_stack_enable(void) {
// DevZone recommends not setting this directly, but instead changing gap_conn_cfg.event_length.
// However, we are setting connection extension, so this seems to make sense.
ble_conf.conn_cfg.params.gatts_conn_cfg.hvn_tx_queue_size = BLEIO_HVN_TX_QUEUE_SIZE;
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATTS, &ble_conf, app_ram_start);
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATTS, &ble_conf, sd_ram_end);
if (err_code != NRF_SUCCESS) {
return err_code;
}
@ -167,7 +167,7 @@ STATIC uint32_t ble_stack_enable(void) {
memset(&ble_conf, 0, sizeof(ble_conf));
ble_conf.conn_cfg.conn_cfg_tag = BLE_CONN_CFG_TAG_CUSTOM;
ble_conf.conn_cfg.params.gatt_conn_cfg.att_mtu = BLE_GATTS_VAR_ATTR_LEN_MAX;
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &ble_conf, app_ram_start);
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &ble_conf, sd_ram_end);
if (err_code != NRF_SUCCESS) {
return err_code;
}
@ -177,7 +177,7 @@ STATIC uint32_t ble_stack_enable(void) {
memset(&ble_conf, 0, sizeof(ble_conf));
// Each increment to the BLE_GATTS_ATTR_TAB_SIZE_DEFAULT multiplier costs 1408 bytes.
ble_conf.gatts_cfg.attr_tab_size.attr_tab_size = BLEIO_ATTR_TAB_SIZE;
err_code = sd_ble_cfg_set(BLE_GATTS_CFG_ATTR_TAB_SIZE, &ble_conf, app_ram_start);
err_code = sd_ble_cfg_set(BLE_GATTS_CFG_ATTR_TAB_SIZE, &ble_conf, sd_ram_end);
if (err_code != NRF_SUCCESS) {
return err_code;
}
@ -187,13 +187,15 @@ STATIC uint32_t ble_stack_enable(void) {
memset(&ble_conf, 0, sizeof(ble_conf));
// Each additional vs_uuid_count costs 16 bytes.
ble_conf.common_cfg.vs_uuid_cfg.vs_uuid_count = BLEIO_VS_UUID_COUNT; // Defaults to 10.
err_code = sd_ble_cfg_set(BLE_COMMON_CFG_VS_UUID, &ble_conf, app_ram_start);
err_code = sd_ble_cfg_set(BLE_COMMON_CFG_VS_UUID, &ble_conf, sd_ram_end);
if (err_code != NRF_SUCCESS) {
return err_code;
}
// This sets app_ram_start to the minimum value needed for the settings set above.
err_code = sd_ble_enable(&app_ram_start);
// This sets sd_ram_end to the minimum value needed for the settings set above.
// You can set a breakpoint just after this call and examine sd_ram_end to see
// how much RAM the SD needs with the configuration above.
err_code = sd_ble_enable(&sd_ram_end);
if (err_code != NRF_SUCCESS) {
return err_code;
}

5
ports/nrf/common-hal/busio/SPI.c
View File

@ -57,7 +57,7 @@ STATIC spim_peripheral_t spim_peripherals[] = {
// Allocate SPIM3 first.
{ .spim = NRFX_SPIM_INSTANCE(3),
.max_frequency = 32000000,
.max_xfer_size = MIN(SPIM3_BUFFER_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1)
.max_xfer_size = MIN(SPIM3_BUFFER_RAM_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1)
},
#endif
#if NRFX_CHECK(NRFX_SPIM2_ENABLED)
@ -87,8 +87,7 @@ STATIC bool never_reset[MP_ARRAY_SIZE(spim_peripherals)];
// Separate RAM area for SPIM3 transmit buffer to avoid SPIM3 hardware errata.
// https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF52840_Rev2%2FERR%2FnRF52840%2FRev2%2Flatest%2Fanomaly_840_198.html
extern uint32_t _spim3_ram;
STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) &_spim3_ram;
STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) SPIM3_BUFFER_RAM_START_ADDR;
void spi_reset(void) {
for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) {

9
ports/nrf/ld_defines.c
View File

@ -10,6 +10,7 @@
// START_LD_DEFINES
/*FLASH_SIZE=*/ FLASH_SIZE;
/*RAM_START_ADDR=*/ RAM_START_ADDR;
/*RAM_SIZE=*/ RAM_SIZE;
/*MBR_START_ADDR=*/ MBR_START_ADDR;
@ -41,5 +42,11 @@
/*BOOTLOADER_SETTINGS_START_ADDR=*/ BOOTLOADER_SETTINGS_START_ADDR;
/*BOOTLOADER_SETTINGS_SIZE=*/ BOOTLOADER_SETTINGS_SIZE;
/*SOFTDEVICE_RAM_START_ADDR=*/ SOFTDEVICE_RAM_START_ADDR;
/*SOFTDEVICE_RAM_SIZE=*/ SOFTDEVICE_RAM_SIZE;
/*SPIM3_BUFFER_SIZE=*/ SPIM3_BUFFER_SIZE;
/*SPIM3_BUFFER_RAM_START_ADDR=*/ SPIM3_BUFFER_RAM_START_ADDR;
/*SPIM3_BUFFER_RAM_SIZE=*/ SPIM3_BUFFER_RAM_SIZE;
/*APP_RAM_START_ADDR=*/ APP_RAM_START_ADDR;
/*APP_RAM_SIZE=*/ APP_RAM_SIZE;

108
ports/nrf/mpconfigport.h
View File

@ -34,32 +34,6 @@
#include "nrf_sdm.h" // for SD_FLASH_SIZE
#include "peripherals/nrf/nvm.h" // for FLASH_PAGE_SIZE
// Max RAM used by SoftDevice. Can be changed when SoftDevice parameters are changed.
// See common.template.ld.
#ifndef SOFTDEVICE_RAM_SIZE
#define SOFTDEVICE_RAM_SIZE (64*1024)
#endif
#ifdef NRF52840
#define MICROPY_PY_SYS_PLATFORM "nRF52840"
#define FLASH_SIZE (0x100000) // 1MiB
#define RAM_SIZE (0x40000) // 256 KiB
// Special RAM area for SPIM3 transmit buffer, to work around hardware bug.
// See common.template.ld.
#define SPIM3_BUFFER_SIZE (8192)
#endif
#ifdef NRF52833
#define MICROPY_PY_SYS_PLATFORM "nRF52833"
#define FLASH_SIZE (0x80000) // 512 KiB
#define RAM_SIZE (0x20000) // 128 KiB
// Special RAM area for SPIM3 transmit buffer, to work around hardware bug.
// See common.template.ld.
#ifndef SPIM3_BUFFER_SIZE
#define SPIM3_BUFFER_SIZE (8192)
#endif
#endif
#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1)
#define MICROPY_PY_FUNCTION_ATTRS (1)
#define MICROPY_PY_IO (1)
@ -69,7 +43,26 @@
#define MICROPY_PY_UJSON (1)
// 24kiB stack
#define CIRCUITPY_DEFAULT_STACK_SIZE 0x6000
#define CIRCUITPY_DEFAULT_STACK_SIZE (24*1024)
#ifdef NRF52840
#define MICROPY_PY_SYS_PLATFORM "nRF52840"
#define FLASH_SIZE (1024*1024) // 1MiB
#define RAM_SIZE (256*1024) // 256 KiB
// Special RAM area for SPIM3 transmit buffer, to work around hardware bug.
// See common.template.ld.
#define SPIM3_BUFFER_RAM_SIZE (8*1024) // 8 KiB
#endif
#ifdef NRF52833
#define MICROPY_PY_SYS_PLATFORM "nRF52833"
#define FLASH_SIZE (512*1024) // 512 KiB
#define RAM_SIZE (128*1024) // 128 KiB
// SPIM3 buffer is not needed on nRF52833: the SPIM3 hw bug is not present.
#ifndef SPIM3_BUFFER_RAM_SIZE
#define SPIM3_BUFFER_RAM_SIZE (0)
#endif
#endif
////////////////////////////////////////////////////////////////////////////////////////////////////
@ -79,7 +72,7 @@
// Definitions that might be overriden by mpconfigboard.h
#ifndef CIRCUITPY_INTERNAL_NVM_SIZE
#define CIRCUITPY_INTERNAL_NVM_SIZE (8192)
#define CIRCUITPY_INTERNAL_NVM_SIZE (8*1024)
#endif
#ifndef BOARD_HAS_32KHZ_XTAL
@ -88,11 +81,11 @@
#endif
#if INTERNAL_FLASH_FILESYSTEM
#ifndef CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (256*1024)
#endif
#ifndef CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (256*1024)
#endif
#else
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0)
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0)
#endif
// Flash layout, starting at 0x00000000
@ -116,7 +109,7 @@
// SD_FLASH_SIZE is from nrf_sdm.h
#define ISR_START_ADDR (SD_FLASH_START_ADDR + SD_FLASH_SIZE)
#define ISR_SIZE (0x1000) // 4kiB
#define ISR_SIZE (4*1024) // 4kiB
// Smallest unit of flash that can be erased.
#define FLASH_ERASE_SIZE FLASH_PAGE_SIZE
@ -127,12 +120,12 @@
// Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld
#define BOOTLOADER_START_ADDR (FLASH_SIZE - BOOTLOADER_SIZE - BOOTLOADER_SETTINGS_SIZE - BOOTLOADER_MBR_SIZE)
#define BOOTLOADER_MBR_SIZE (0x1000) // 4kib
#define BOOTLOADER_MBR_SIZE (4*1024) // 4kib
#ifndef BOOTLOADER_SIZE
#define BOOTLOADER_SIZE (0xA000) // 40kiB
#define BOOTLOADER_SIZE (40*1024) // 40kiB
#endif
#define BOOTLOADER_SETTINGS_START_ADDR (FLASH_SIZE - BOOTLOADER_SETTINGS_SIZE)
#define BOOTLOADER_SETTINGS_SIZE (0x1000) // 4kiB
#define BOOTLOADER_SETTINGS_SIZE (4*1024) // 4kiB
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR (BOOTLOADER_START_ADDR - CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE)
@ -180,11 +173,46 @@
#error No space left in flash for firmware after specifying other regions!
#endif
////////////////////////////////////////////////////////////////////////////////////////////////////
// RAM space definitions
#define MICROPY_PORT_ROOT_POINTERS \
CIRCUITPY_COMMON_ROOT_POINTERS \
uint16_t* pixels_pattern_heap; \
ble_drv_evt_handler_entry_t* ble_drv_evt_handler_entries; \
// Max RAM used by SoftDevice. Can be changed when SoftDevice parameters are changed.
// On nRF52840, the first 64kB of RAM is composed of 8 8kB RAM blocks. Above those is
// RAM block 8, which is 192kB.
// If SPIM3_BUFFER_RAM_SIZE is 8kB, as opposed to zero, it must be in the first 64kB of RAM.
// So the amount of RAM reserved for the SoftDevice must be no more than 56kB.
// SoftDevice 6.1.0 with 5 connections and various increases can be made to use < 56kB.
// To measure the minimum required amount of memory for given configuration, set this number
// high enough to work and then check the mutation of the value done by sd_ble_enable().
// See common.template.ld.
#ifndef SOFTDEVICE_RAM_SIZE
#define SOFTDEVICE_RAM_SIZE (56*1024)
#endif
#define RAM_START_ADDR (0x20000000)
#define SOFTDEVICE_RAM_START_ADDR (RAM_START_ADDR)
#define SPIM3_BUFFER_RAM_START_ADDR (SOFTDEVICE_RAM_START_ADDR + SOFTDEVICE_RAM_SIZE)
#define APP_RAM_START_ADDR (SPIM3_BUFFER_RAM_START_ADDR + SPIM3_BUFFER_RAM_SIZE)
#define APP_RAM_SIZE (RAM_START_ADDR + RAM_SIZE - APP_RAM_START_ADDR)
#if SPIM3_BUFFER_RAM_SIZE > 0 && SOFTDEVICE_RAM_SIZE + SPIM3_BUFFER_RAM_SIZE > (64*1024)
#error SPIM3 buffer must be in the first 64kB of RAM.
#endif
#if SOFTDEVICE_RAM_SIZE + SPIM3_BUFFER_RAM_SIZE + APP_RAM_SIZE > RAM_SIZE
#error RAM size regions overflow RAM
#endif
#if SOFTDEVICE_RAM_SIZE + SPIM3_BUFFER_RAM_SIZE + APP_RAM_SIZE < RAM_SIZE
#error RAM size regions do not use all of RAM
#endif
#define MICROPY_PORT_ROOT_POINTERS \
CIRCUITPY_COMMON_ROOT_POINTERS \
uint16_t* pixels_pattern_heap; \
ble_drv_evt_handler_entry_t* ble_drv_evt_handler_entries; \
#endif // NRF5_MPCONFIGPORT_H__

2
ports/nrf/nrfx_config.h
View File

@ -5,7 +5,7 @@
#define NRFX_POWER_ENABLED 1
#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
// NOTE: THIS WORKAROUND CAUSES BLE CODE TO CRASH.
// NOTE: THIS WORKAROUND CAUSES BLE CODE TO CRASH. DO NOT USE.
// It doesn't work with the SoftDevice.
// See https://devzone.nordicsemi.com/f/nordic-q-a/33982/sdk-15-software-crash-during-spi-session
// Turn on nrfx supported workarounds for errata in Rev1 of nRF52840