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stm32/boards/NUCLEO_F767ZI: Enable lwIP and Ethernet peripheral.

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This commit is contained in:
Damien George 2019-02-22 22:26:54 +11:00
parent ac3e2f380d
commit 8daec24168
2 changed files with 22 additions and 0 deletions
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13
ports/stm32/boards/NUCLEO_F767ZI/mpconfigboard.h
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@ -6,6 +6,8 @@
#define MICROPY_HW_BOARD_NAME "NUCLEO-F767ZI" #define MICROPY_HW_BOARD_NAME "NUCLEO-F767ZI"
#define MICROPY_HW_MCU_NAME "STM32F767" #define MICROPY_HW_MCU_NAME "STM32F767"
#define MICROPY_PY_LWIP (1)
#define MICROPY_HW_HAS_SWITCH (1) #define MICROPY_HW_HAS_SWITCH (1)
#define MICROPY_HW_HAS_FLASH (1) #define MICROPY_HW_HAS_FLASH (1)
#define MICROPY_HW_ENABLE_RNG (1) #define MICROPY_HW_ENABLE_RNG (1)
@ -70,3 +72,14 @@ void NUCLEO_F767ZI_board_early_init(void);
#define MICROPY_HW_USB_FS (1) #define MICROPY_HW_USB_FS (1)
#define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9) #define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9)
#define MICROPY_HW_USB_OTG_ID_PIN (pin_A10) #define MICROPY_HW_USB_OTG_ID_PIN (pin_A10)
// Ethernet via RMII
#define MICROPY_HW_ETH_MDC (pin_C1)
#define MICROPY_HW_ETH_MDIO (pin_A2)
#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1)
#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7)
#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4)
#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5)
#define MICROPY_HW_ETH_RMII_TX_EN (pin_G11)
#define MICROPY_HW_ETH_RMII_TXD0 (pin_G13)
#define MICROPY_HW_ETH_RMII_TXD1 (pin_B13)

9
ports/stm32/boards/NUCLEO_F767ZI/pins.csv
View File

@ -70,3 +70,12 @@ UART6_RX,PG9
SPI_B_NSS,PA4 SPI_B_NSS,PA4
SPI_B_SCK,PB3 SPI_B_SCK,PB3
SPI_B_MOSI,PB5 SPI_B_MOSI,PB5
ETH_MDC,PC1
ETH_MDIO,PA2
ETH_RMII_REF_CLK,PA1
ETH_RMII_CRS_DV,PA7
ETH_RMII_RXD0,PC4
ETH_RMII_RXD1,PC5
ETH_RMII_TX_EN,PG11
ETH_RMII_TXD0,PG13
ETH_RMII_TXD1,PB13

1 A0 PA3
70 SPI_B_NSS PA4
71 SPI_B_SCK PB3
72 SPI_B_MOSI PB5
73 ETH_MDC PC1
74 ETH_MDIO PA2
75 ETH_RMII_REF_CLK PA1
76 ETH_RMII_CRS_DV PA7
77 ETH_RMII_RXD0 PC4
78 ETH_RMII_RXD1 PC5
79 ETH_RMII_TX_EN PG11
80 ETH_RMII_TXD0 PG13
81 ETH_RMII_TXD1 PB13