From a74ec22aa4b6c723c14bd7d523f4b81fea5fda66 Mon Sep 17 00:00:00 2001 From: KurtE Date: Wed, 6 Apr 2022 14:19:38 -0700 Subject: [PATCH 1/2] Start setting up a Teensy MicroMod port I have done a first pass through the files this also includes a new VID/PID from sparkfun --- ports/mimxrt10xx/boards/teensyMM/board.c | 64 ++++++ ports/mimxrt10xx/boards/teensyMM/board.ld | 1 + .../mimxrt10xx/boards/teensyMM/flash_config.c | 170 +++++++++++++++ .../boards/teensyMM/mpconfigboard.h | 21 ++ .../boards/teensyMM/mpconfigboard.mk | 10 + ports/mimxrt10xx/boards/teensyMM/pins.c | 204 ++++++++++++++++++ 6 files changed, 470 insertions(+) create mode 100644 ports/mimxrt10xx/boards/teensyMM/board.c create mode 100644 ports/mimxrt10xx/boards/teensyMM/board.ld create mode 100644 ports/mimxrt10xx/boards/teensyMM/flash_config.c create mode 100644 ports/mimxrt10xx/boards/teensyMM/mpconfigboard.h create mode 100644 ports/mimxrt10xx/boards/teensyMM/mpconfigboard.mk create mode 100644 ports/mimxrt10xx/boards/teensyMM/pins.c diff --git a/ports/mimxrt10xx/boards/teensyMM/board.c b/ports/mimxrt10xx/boards/teensyMM/board.c new file mode 100644 index 0000000000..1a1dc7e5ec --- /dev/null +++ b/ports/mimxrt10xx/boards/teensyMM/board.c @@ -0,0 +1,64 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2019 Artur Pacholec + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "supervisor/board.h" +#include "boards/flash_config.h" +#include "mpconfigboard.h" +#include "shared-bindings/microcontroller/Pin.h" + +void board_init(void) { + // FLEX flash + common_hal_never_reset_pin(&pin_GPIO_SD_B1_06); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_07); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_08); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_09); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_10); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_11); + + // FLEX flash 2 + common_hal_never_reset_pin(&pin_GPIO_AD_B0_04); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_06); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_07); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_08); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_09); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_10); + common_hal_never_reset_pin(&pin_GPIO_EMC_01); + common_hal_never_reset_pin(&pin_GPIO_B0_13); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_11); + // Data strobe needs protection despite being grounded + common_hal_never_reset_pin(&pin_GPIO_SD_B1_05); +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} + +void board_deinit(void) { +} diff --git a/ports/mimxrt10xx/boards/teensyMM/board.ld b/ports/mimxrt10xx/boards/teensyMM/board.ld new file mode 100644 index 0000000000..8f19810a35 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensyMM/board.ld @@ -0,0 +1 @@ +_ld_reserved_flash_size = 4K; diff --git a/ports/mimxrt10xx/boards/teensyMM/flash_config.c b/ports/mimxrt10xx/boards/teensyMM/flash_config.c new file mode 100644 index 0000000000..09886dece6 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensyMM/flash_config.c @@ -0,0 +1,170 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "boards/flash_config.h" + +#include "fsl_flexspi_nor_boot.h" + + +__attribute__((section(".boot_hdr.ivt"))) +/************************************* + * IVT Data + *************************************/ +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +__attribute__((section(".boot_hdr.boot_data"))) +/************************************* + * Boot Data + *************************************/ +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +// Config for W25Q64JV with QSPI routed. +__attribute__((section(".boot_hdr.conf"))) +const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + { + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE + }, + }, +}; diff --git a/ports/mimxrt10xx/boards/teensyMM/mpconfigboard.h b/ports/mimxrt10xx/boards/teensyMM/mpconfigboard.h new file mode 100644 index 0000000000..ac9fa5ae14 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensyMM/mpconfigboard.h @@ -0,0 +1,21 @@ +#define MICROPY_HW_BOARD_NAME "Teensy MM" +#define MICROPY_HW_MCU_NAME "IMXRT1062DVL6A" + +// If you change this, then make sure to update the linker scripts as well to +// make sure you don't overwrite code +#define CIRCUITPY_INTERNAL_NVM_SIZE 0 + +#define BOARD_FLASH_SIZE (16 * 1024 * 1024) + +#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_00) +#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_01) + +#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_B0_03) +#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_B0_02) +#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_B0_01) + +#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B0_03) +#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B0_02) + +#define CIRCUITPY_USB_DEVICE_INSTANCE 0 +#define CIRCUITPY_USB_HOST_INSTANCE 1 diff --git a/ports/mimxrt10xx/boards/teensyMM/mpconfigboard.mk b/ports/mimxrt10xx/boards/teensyMM/mpconfigboard.mk new file mode 100644 index 0000000000..1aa9220e00 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensyMM/mpconfigboard.mk @@ -0,0 +1,10 @@ +USB_VID = 0x1B4F +USB_PID = 0x002E +USB_PRODUCT = "Teensy MicroMod" +USB_MANUFACTURER = "PJRC" + +CHIP_VARIANT = MIMXRT1062DVJ6A +CHIP_FAMILY = MIMXRT1062 +FLASH = W25Q128JV +CIRCUITPY__EVE = 1 +CIRCUITPY_USB_HOST = 1 diff --git a/ports/mimxrt10xx/boards/teensyMM/pins.c b/ports/mimxrt10xx/boards/teensyMM/pins.c new file mode 100644 index 0000000000..1b48485087 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensyMM/pins.c @@ -0,0 +1,204 @@ +#include "shared-bindings/board/__init__.h" + +#include "supervisor/board.h" + +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { + CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS + + // Micromod pins mapped to logical Teensy pins + {MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B0_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_RX1), MP_ROM_PTR(&pin_GPIO_AD_B0_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_UART_RX1), MP_ROM_PTR(&pin_GPIO_AD_B0_03)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B0_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_TX1), MP_ROM_PTR(&pin_GPIO_AD_B0_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_UART_TX1), MP_ROM_PTR(&pin_GPIO_AD_B0_02)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_EMC_04)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_PWM1), MP_ROM_PTR(&pin_GPIO_EMC_04)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_EMC_05)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_PWM0), MP_ROM_PTR(&pin_GPIO_EMC_05)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_EMC_06)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_MM_D0), MP_ROM_PTR(&pin_GPIO_EMC_06)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_EMC_08)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_MM_D1), MP_ROM_PTR(&pin_GPIO_EMC_08)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_B0_10)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G6), MP_ROM_PTR(&pin_GPIO_B0_10)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_B1_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_RX4), MP_ROM_PTR(&pin_GPIO_B1_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_AUD_OUT), MP_ROM_PTR(&pin_GPIO_B1_01)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_B1_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_TX4), MP_ROM_PTR(&pin_GPIO_B1_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_AUD_IN), MP_ROM_PTR(&pin_GPIO_B1_00)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_B0_11)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G7), MP_ROM_PTR(&pin_GPIO_B0_11)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_B0_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_CS), MP_ROM_PTR(&pin_GPIO_B0_00)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_B0_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO_B0_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SPI_COPI), MP_ROM_PTR(&pin_GPIO_B0_02)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_B0_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO_B0_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SPI_CIPO), MP_ROM_PTR(&pin_GPIO_B0_01)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_B0_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO_B0_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO_B0_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SPI_SCK), MP_ROM_PTR(&pin_GPIO_B0_03)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_TX3), MP_ROM_PTR(&pin_GPIO_AD_B1_02)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_RX3), MP_ROM_PTR(&pin_GPIO_AD_B1_03)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_GPIO_AD_B1_07)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_07)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_RX2), MP_ROM_PTR(&pin_GPIO_AD_B1_07)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_GPIO_AD_B1_06)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_06)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_TX2), MP_ROM_PTR(&pin_GPIO_AD_B1_06)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_GPIO_AD_B1_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SDA0), MP_ROM_PTR(&pin_GPIO_AD_B1_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_GPIO_AD_B1_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SCL0), MP_ROM_PTR(&pin_GPIO_AD_B1_00)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_GPIO_AD_B1_10)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_GPIO_AD_B1_10)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_TX5), MP_ROM_PTR(&pin_GPIO_AD_B1_10)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_AUD_LRCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_10)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_GPIO_AD_B1_11)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_GPIO_AD_B1_11)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_RX5), MP_ROM_PTR(&pin_GPIO_AD_B1_11)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_AUD_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_11)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_GPIO_AD_B1_08)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_GPIO_AD_B1_08)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_BATT_VIN3), MP_ROM_PTR(&pin_GPIO_AD_B1_08)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_GPIO_AD_B1_09)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_GPIO_AD_B1_09)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_AUD_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_09)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_GPIO_AD_B0_12)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_GPIO_AD_B0_12)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_TX6), MP_ROM_PTR(&pin_GPIO_AD_B0_12)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_I2C_SCL1), MP_ROM_PTR(&pin_GPIO_AD_B0_12)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_GPIO_AD_B0_13)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_GPIO_AD_B0_13)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_RX6), MP_ROM_PTR(&pin_GPIO_AD_B0_13)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_I2C_SDA1), MP_ROM_PTR(&pin_GPIO_AD_B0_13)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_GPIO_AD_B1_14)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_GPIO_AD_B1_14)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G8), MP_ROM_PTR(&pin_GPIO_AD_B1_14)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_GPIO_AD_B1_15)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_GPIO_AD_B1_15)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G11), MP_ROM_PTR(&pin_GPIO_AD_B1_15)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_GPIO_EMC_32)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_RX7), MP_ROM_PTR(&pin_GPIO_EMC_32)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_GPIO_EMC_31)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_TX7), MP_ROM_PTR(&pin_GPIO_EMC_32)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_I2C_INT), MP_ROM_PTR(&pin_GPIO_EMC_32)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_GPIO_EMC_37)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_GPIO_EMC_37)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_GPIO_EMC_36)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_GPIO_EMC_36)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_GPIO_B0_12)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G9), MP_ROM_PTR(&pin_GPIO_B0_12)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_GPIO_EMC_07)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G10), MP_ROM_PTR(&pin_GPIO_EMC_07)}, + + // SD Card slot + {MP_OBJ_NEW_QSTR(MP_QSTR_DAT1), MP_ROM_PTR(&pin_GPIO_SD_B0_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_DAT1), MP_ROM_PTR(&pin_GPIO_SD_B0_03)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_GPIO_SD_B0_03)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_DAT0), MP_ROM_PTR(&pin_GPIO_SD_B0_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_DAT0), MP_ROM_PTR(&pin_GPIO_SD_B0_02)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_GPIO_SD_B0_02)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_GPIO_SD_B0_01)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_GPIO_SD_B0_00)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_DAT3), MP_ROM_PTR(&pin_GPIO_SD_B0_05)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_DAT3), MP_ROM_PTR(&pin_GPIO_SD_B0_05)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_GPIO_SD_B0_05)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_DAT2), MP_ROM_PTR(&pin_GPIO_SD_B0_04)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_SDIO_DAT2), MP_ROM_PTR(&pin_GPIO_SD_B0_04)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_GPIO_SD_B0_04)}, + + // new + + {MP_OBJ_NEW_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_GPIO_B0_04)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G0), MP_ROM_PTR(&pin_GPIO_B0_04)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_BUS0), MP_ROM_PTR(&pin_GPIO_B0_04)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_GPIO_B0_05)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G1), MP_ROM_PTR(&pin_GPIO_B0_05)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_BUS1), MP_ROM_PTR(&pin_GPIO_B0_05)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_GPIO_B0_06)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G2), MP_ROM_PTR(&pin_GPIO_B0_06)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_BUS2), MP_ROM_PTR(&pin_GPIO_B0_06)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_GPIO_B0_07)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G3), MP_ROM_PTR(&pin_GPIO_B0_07)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_BUS3), MP_ROM_PTR(&pin_GPIO_B0_07)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_GPIO_B0_08)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G4), MP_ROM_PTR(&pin_GPIO_B0_08)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_BUS4), MP_ROM_PTR(&pin_GPIO_B0_08)}, + + {MP_OBJ_NEW_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_GPIO_B0_09)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_G5), MP_ROM_PTR(&pin_GPIO_B0_09)}, + {MP_OBJ_NEW_QSTR(MP_QSTR_BUS5), MP_ROM_PTR(&pin_GPIO_B0_09)}, + + // USB Host + {MP_ROM_QSTR(MP_QSTR_USB_HOST_POWER), MP_ROM_PTR(&pin_GPIO_EMC_40)}, + {MP_ROM_QSTR(MP_QSTR_USB_HOST_DP), MP_ROM_PTR(&pin_USB_OTG2_DP)}, + {MP_ROM_QSTR(MP_QSTR_USB_HOST_DM), MP_ROM_PTR(&pin_USB_OTG2_DN)}, + + {MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj)}, + {MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj)}, + {MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj)}, + +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); From 2cb422fb192384dfe3df82e778fd2d58eed98139 Mon Sep 17 00:00:00 2001 From: KurtE Date: Thu, 7 Apr 2022 12:09:56 -0700 Subject: [PATCH 2/2] Create W25Q128JV.ld Add flash file needed for Teensy MicroMod, --- ports/mimxrt10xx/linking/flash/W25Q128JV.ld | 1 + 1 file changed, 1 insertion(+) create mode 100644 ports/mimxrt10xx/linking/flash/W25Q128JV.ld diff --git a/ports/mimxrt10xx/linking/flash/W25Q128JV.ld b/ports/mimxrt10xx/linking/flash/W25Q128JV.ld new file mode 100644 index 0000000000..4c055f4ba4 --- /dev/null +++ b/ports/mimxrt10xx/linking/flash/W25Q128JV.ld @@ -0,0 +1 @@ +_ld_flash_size = 16M; \ No newline at end of file