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adds standard (non-queued) SPI support to QSPI for external flash

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This commit is contained in:
Max Holliday 2020-04-07 18:17:25 -07:00
parent 78c1448764
commit 826837186c
10 changed files with 272 additions and 46 deletions
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1
.github/workflows/build.yml vendored
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@ -204,6 +204,7 @@ jobs:
- "pybadge_airlift"
- "pyboard_v11"
- "pycubed"
- "pycubed_mram"
- "pygamer"
- "pygamer_advance"
- "pyportal"

2
ports/atmel-samd/boards/pycubed/mpconfigboard.h
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@ -3,6 +3,7 @@
#define MICROPY_HW_MCU_NAME "samd51j19"
#define CIRCUITPY_MCU_FAMILY samd51
#define MICROPY_HW_LED_STATUS (&pin_PA16)
#define MICROPY_HW_NEOPIXEL (&pin_PA21)
#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11)
@ -16,6 +17,7 @@
#define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000 - CIRCUITPY_INTERNAL_NVM_SIZE)
// External flash W25Q80DV
#define EXTERNAL_FLASH_QSPI_DUAL
#define BOARD_HAS_CRYSTAL 1

61
ports/atmel-samd/boards/pycubed_mram/board.c Normal file
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@ -0,0 +1,61 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <string.h>
#include "boards/board.h"
#include "py/mpconfig.h"
#include "shared-bindings/nvm/ByteArray.h"
#include "common-hal/microcontroller/Pin.h"
#include "hal/include/hal_gpio.h"
#include "shared-bindings/pulseio/PWMOut.h"
nvm_bytearray_obj_t bootcnt = {
.base = {
.type = &nvm_bytearray_type
},
.len = ( uint32_t) 8192,
.start_address = (uint8_t*) (0x00080000 - 8192)
};
void board_init(void) {
pulseio_pwmout_obj_t pwm;
common_hal_pulseio_pwmout_construct(&pwm, &pin_PA23, 4096, 2, false);
common_hal_pulseio_pwmout_never_reset(&pwm);
}
bool board_requests_safe_mode(void) {
return false;
}
void reset_board(void) {
uint8_t value_out = 0;
common_hal_nvm_bytearray_get_bytes(&bootcnt,0,1,&value_out);
++value_out;
common_hal_nvm_bytearray_set_bytes(&bootcnt,0,&value_out,1);
}

37
ports/atmel-samd/boards/pycubed_mram/mpconfigboard.h Normal file
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@ -0,0 +1,37 @@
#define MICROPY_HW_BOARD_NAME "PyCubedv04-MRAM"
#define MICROPY_HW_MCU_NAME "samd51j19"
#define CIRCUITPY_MCU_FAMILY samd51
#define MICROPY_HW_LED_STATUS (&pin_PA16)
#define MICROPY_HW_NEOPIXEL (&pin_PA21)
#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11)
#define MICROPY_PORT_B (PORT_PA21 | PORT_PB10 | PORT_PB11)
#define MICROPY_PORT_C (0)
#define MICROPY_PORT_D (0)
// External flash MR2xH40 MRAM
#define EXTERNAL_FLASH_QSPI_SINGLE
#define AUTORESET_DELAY_MS 500
#define CIRCUITPY_INTERNAL_NVM_SIZE 8192
#define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000 - CIRCUITPY_INTERNAL_NVM_SIZE)
#define BOARD_HAS_CRYSTAL 1
#define DEFAULT_I2C_BUS_SCL (&pin_PB13)
#define DEFAULT_I2C_BUS_SDA (&pin_PB12)
#define DEFAULT_SPI_BUS_SCK (&pin_PA13)
#define DEFAULT_SPI_BUS_MOSI (&pin_PA12)
#define DEFAULT_SPI_BUS_MISO (&pin_PA14)
#define DEFAULT_UART_BUS_TX (&pin_PB02)
#define DEFAULT_UART_BUS_RX (&pin_PB03)
#define IGNORE_PIN_PA24 1
#define IGNORE_PIN_PA25 1

24
ports/atmel-samd/boards/pycubed_mram/mpconfigboard.mk Normal file
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@ -0,0 +1,24 @@
LD_FILE = boards/samd51x19-bootloader-external-flash.ld
USB_VID = 0x04D8
USB_PID = 0xEC44
USB_PRODUCT = "PyCubed"
USB_MANUFACTURER = "maholli"
CHIP_VARIANT = SAMD51J19A
CHIP_FAMILY = samd51
QSPI_FLASH_FILESYSTEM = 1
EXTERNAL_FLASH_DEVICE_COUNT = 1
EXTERNAL_FLASH_DEVICES = MR2xH40
LONGINT_IMPL = MPZ
# Not needed.
CIRCUITPY_AUDIOBUSIO = 0
CIRCUITPY_DISPLAYIO = 0
CIRCUITPY_GAMEPAD = 0
CIRCUITPY_PS2IO = 0
FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_BusDevice
FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel
FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Register
FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_SD

55
ports/atmel-samd/boards/pycubed_mram/pins.c Normal file
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@ -0,0 +1,55 @@
#include "shared-bindings/board/__init__.h"
#include "boards/board.h"
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA13) },
{ MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA12) },
{ MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA14) },
{ MP_ROM_QSTR(MP_QSTR_xSDCS), MP_ROM_PTR(&pin_PA27) },
{ MP_ROM_QSTR(MP_QSTR_RELAY_A), MP_ROM_PTR(&pin_PB15) },
{ MP_ROM_QSTR(MP_QSTR_BURN1), MP_ROM_PTR(&pin_PB31) },
{ MP_ROM_QSTR(MP_QSTR_BURN2), MP_ROM_PTR(&pin_PA15) },
{ MP_ROM_QSTR(MP_QSTR_BATTERY), MP_ROM_PTR(&pin_PA06) },
{ MP_ROM_QSTR(MP_QSTR_L1PROG), MP_ROM_PTR(&pin_PA07) },
{ MP_ROM_QSTR(MP_QSTR_AIN4), MP_ROM_PTR(&pin_PA04) },
{ MP_ROM_QSTR(MP_QSTR_AIN5), MP_ROM_PTR(&pin_PA05) },
{ MP_ROM_QSTR(MP_QSTR_CHRG), MP_ROM_PTR(&pin_PB08) },
{ MP_ROM_QSTR(MP_QSTR_DAC0), MP_ROM_PTR(&pin_PA02) },
{ MP_ROM_QSTR(MP_QSTR_PA17), MP_ROM_PTR(&pin_PA17) },
{ MP_ROM_QSTR(MP_QSTR_PA18), MP_ROM_PTR(&pin_PA18) },
{ MP_ROM_QSTR(MP_QSTR_PA19), MP_ROM_PTR(&pin_PA19) },
{ MP_ROM_QSTR(MP_QSTR_PA20), MP_ROM_PTR(&pin_PA20) },
{ MP_ROM_QSTR(MP_QSTR_PA22), MP_ROM_PTR(&pin_PA22) },
{ MP_ROM_QSTR(MP_QSTR_PB16), MP_ROM_PTR(&pin_PB16) },
{ MP_ROM_QSTR(MP_QSTR_PB17), MP_ROM_PTR(&pin_PB17) },
{ MP_ROM_QSTR(MP_QSTR_PB22), MP_ROM_PTR(&pin_PB22) },
{ MP_ROM_QSTR(MP_QSTR_PB23), MP_ROM_PTR(&pin_PB23) },
{ MP_ROM_QSTR(MP_QSTR_RF1_RST), MP_ROM_PTR(&pin_PB00) },
{ MP_ROM_QSTR(MP_QSTR_RF1_CS), MP_ROM_PTR(&pin_PB30) },
{ MP_ROM_QSTR(MP_QSTR_RF1_IO0), MP_ROM_PTR(&pin_PB05) },
{ MP_ROM_QSTR(MP_QSTR_RF1_IO4), MP_ROM_PTR(&pin_PB04) },
{ MP_ROM_QSTR(MP_QSTR_RF2_RST), MP_ROM_PTR(&pin_PB14) },
{ MP_ROM_QSTR(MP_QSTR_RF2_CS), MP_ROM_PTR(&pin_PB09) },
{ MP_ROM_QSTR(MP_QSTR_RF2_IO1), MP_ROM_PTR(&pin_PB06) },
{ MP_ROM_QSTR(MP_QSTR_RF2_BSY), MP_ROM_PTR(&pin_PB07) },
{ MP_ROM_QSTR(MP_QSTR_EN_GPS), MP_ROM_PTR(&pin_PB01) },
{ MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB02) },
{ MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB03) },
{ MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB12) },
{ MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB13) },
{ MP_ROM_QSTR(MP_QSTR_WDT_WDI), MP_ROM_PTR(&pin_PA23) },
{ MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA21) },
{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
{ MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
};
MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);

15
ports/atmel-samd/supervisor/qspi_flash.c
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@ -166,7 +166,10 @@ bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) {
bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
samd_peripherals_disable_and_clear_cache();
#ifdef EXTERNAL_FLASH_QSPI_DUAL
#ifdef EXTERNAL_FLASH_QSPI_SINGLE
QSPI->INSTRCTRL.bit.INSTR = CMD_READ_DATA;
uint32_t mode = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI;
#elif defined EXTERNAL_FLASH_QSPI_DUAL
QSPI->INSTRCTRL.bit.INSTR = CMD_DUAL_READ;
uint32_t mode = QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT;
#else
@ -174,6 +177,15 @@ bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
uint32_t mode = QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT;
#endif
#ifdef IS_MRAM
QSPI->INSTRFRAME.reg = mode |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN |
QSPI_INSTRFRAME_DATAEN |
QSPI_INSTRFRAME_DUMMYLEN(0);
#else
QSPI->INSTRFRAME.reg = mode |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
@ -181,6 +193,7 @@ bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
QSPI_INSTRFRAME_ADDREN |
QSPI_INSTRFRAME_DATAEN |
QSPI_INSTRFRAME_DUMMYLEN(8);
#endif
memcpy(data, ((uint8_t *) QSPI_AHB) + address, length);
// TODO(tannewt): Fix DMA and enable it.

1
supervisor/shared/external_flash/common_commands.h
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@ -43,5 +43,6 @@
#define CMD_QUAD_READ 0x6b
#define CMD_ENABLE_RESET 0x66
#define CMD_RESET 0x99
#define CMD_WAKE 0xab
#endif // MICROPY_INCLUDED_ATMEL_SAMD_EXTERNAL_FLASH_COMMON_COMMANDS_H

17
supervisor/shared/external_flash/devices.h
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@ -426,6 +426,23 @@ typedef struct {
.single_status_byte = false, \
}
// Everspin MRAM
#define MR2xH40 {\
.total_size = (1 << 22), /* 4 MiB */ \
.start_up_time_us = 10000, \
.manufacturer_id = 0xef, /*no JDEC*/ \
.memory_type = 0x40, /*no JDEC*/ \
.capacity = 0x14, /*no JDEC*/ \
.max_clock_speed_mhz = 40, \
.quad_enable_bit_mask = 0x00, \
.has_sector_protection = false, \
.supports_fast_read = false, \
.supports_qspi = false, \
.supports_qspi_writes = false, \
.write_status_register_split = false, \
.single_status_byte = true, \
}
// Settings for the Macronix MX25L1606 2MiB SPI flash.
// Datasheet:
#define MX25L1606 {\

105
supervisor/shared/external_flash/external_flash.c
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@ -27,7 +27,7 @@
#include <stdint.h>
#include <string.h>
#include "mpconfigboard.h"
#include "supervisor/spi_flash_api.h"
#include "supervisor/shared/external_flash/common_commands.h"
#include "extmod/vfs.h"
@ -57,13 +57,18 @@ static supervisor_allocation* supervisor_cache = NULL;
// Wait until both the write enable and write in progress bits have cleared.
static bool wait_for_flash_ready(void) {
uint8_t read_status_response[1] = {0x00};
bool ok = true;
// Both the write enable and write in progress bits should be low.
do {
ok = spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1);
} while (ok && (read_status_response[0] & 0x3) != 0);
return ok;
#ifdef EXTERNAL_FLASH_QSPI_SINGLE
// For NVM without a ready bit in status register
return ok;
#else
uint8_t read_status_response[1] = {0x00};
do {
ok = spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1);
} while (ok && (read_status_response[0] & 0x3) != 0);
return ok;
#endif
}
// Turn on the write enable bit so we can program and erase the flash.
@ -91,16 +96,18 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len
}
// Don't bother writing if the data is all 1s. Thats equivalent to the flash
// state after an erase.
bool all_ones = true;
for (uint16_t i = 0; i < data_length; i++) {
if (data[i] != 0xff) {
all_ones = false;
break;
#ifndef EXTERNAL_FLASH_QSPI_SINGLE
bool all_ones = true;
for (uint16_t i = 0; i < data_length; i++) {
if (data[i] != 0xff) {
all_ones = false;
break;
}
}
}
if (all_ones) {
return true;
}
if (all_ones) {
return true;
}
#endif
for (uint32_t bytes_written = 0;
bytes_written < data_length;
@ -191,41 +198,49 @@ void supervisor_flash_init(void) {
spi_flash_init();
// The response will be 0xff if the flash needs more time to start up.
uint8_t jedec_id_response[3] = {0xff, 0xff, 0xff};
while (jedec_id_response[0] == 0xff) {
spi_flash_read_command(CMD_READ_JEDEC_ID, jedec_id_response, 3);
}
for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
const external_flash_device* possible_device = &possible_devices[i];
if (jedec_id_response[0] == possible_device->manufacturer_id &&
jedec_id_response[1] == possible_device->memory_type &&
jedec_id_response[2] == possible_device->capacity) {
#ifdef EXTERNAL_FLASH_QSPI_SINGLE
// For NVM that don't have JEDEC response
spi_flash_command(CMD_WAKE);
for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
const external_flash_device* possible_device = &possible_devices[i];
flash_device = possible_device;
break;
}
}
#else
// The response will be 0xff if the flash needs more time to start up.
uint8_t jedec_id_response[3] = {0xff, 0xff, 0xff};
while (jedec_id_response[0] == 0xff) {
spi_flash_read_command(CMD_READ_JEDEC_ID, jedec_id_response, 3);
}
if (flash_device == NULL) {
return;
}
// We don't know what state the flash is in so wait for any remaining writes and then reset.
uint8_t read_status_response[1] = {0x00};
// The write in progress bit should be low.
do {
spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1);
} while ((read_status_response[0] & 0x1) != 0);
// The suspended write/erase bit should be low.
do {
spi_flash_read_command(CMD_READ_STATUS2, read_status_response, 1);
} while ((read_status_response[0] & 0x80) != 0);
spi_flash_command(CMD_ENABLE_RESET);
spi_flash_command(CMD_RESET);
for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
const external_flash_device* possible_device = &possible_devices[i];
if (jedec_id_response[0] == possible_device->manufacturer_id &&
jedec_id_response[1] == possible_device->memory_type &&
jedec_id_response[2] == possible_device->capacity) {
flash_device = possible_device;
break;
}
}
#endif
if (flash_device == NULL) {
return;
}
// We don't know what state the flash is in so wait for any remaining writes and then reset.
uint8_t read_status_response[1] = {0x00};
// The write in progress bit should be low.
do {
spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1);
} while ((read_status_response[0] & 0x1) != 0);
#ifndef EXTERNAL_FLASH_QSPI_SINGLE
// The suspended write/erase bit should be low.
do {
spi_flash_read_command(CMD_READ_STATUS2, read_status_response, 1);
} while ((read_status_response[0] & 0x80) != 0);
spi_flash_command(CMD_ENABLE_RESET);
spi_flash_command(CMD_RESET);
#endif
// Wait 30us for the reset
common_hal_mcu_delay_us(30);