tools/mpy-tool.py: Support qstr linking when freezing Xtensa native mpy.
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@ -428,9 +428,11 @@ class RawCodeNative(RawCode):
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else:
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self.fun_data_attributes = '__attribute__((section(".text,\\"ax\\",%progbits @ ")))'
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# Allow single-byte alignment by default for x86/x64/xtensa, but on ARM we need halfword- or word- alignment.
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if config.native_arch == MP_NATIVE_ARCH_ARMV6:
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# ARMV6 -- four byte align.
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# Allow single-byte alignment by default for x86/x64.
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# ARM needs word alignment, ARM Thumb needs halfword, due to instruction size.
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# Xtensa needs word alignment due to the 32-bit constant table embedded in the code.
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if config.native_arch in (MP_NATIVE_ARCH_ARMV6, MP_NATIVE_ARCH_XTENSA, MP_NATIVE_ARCH_XTENSAWIN):
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# ARMV6 or Xtensa -- four byte align.
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self.fun_data_attributes += ' __attribute__ ((aligned (4)))'
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elif MP_NATIVE_ARCH_ARMV6M <= config.native_arch <= MP_NATIVE_ARCH_ARMV7EMDP:
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# ARMVxxM -- two byte align.
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@ -452,8 +454,11 @@ class RawCodeNative(RawCode):
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is_obj = kind == 2
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if is_obj:
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qst = '((uintptr_t)MP_OBJ_NEW_QSTR(%s))' % qst
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if config.native_arch in (MP_NATIVE_ARCH_X86, MP_NATIVE_ARCH_X64):
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print(' %s & 0xff, %s >> 8, 0, 0,' % (qst, qst))
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if config.native_arch in (
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MP_NATIVE_ARCH_X86, MP_NATIVE_ARCH_X64,
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MP_NATIVE_ARCH_XTENSA, MP_NATIVE_ARCH_XTENSAWIN
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):
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print(' %s & 0xff, (%s >> 8) & 0xff, (%s >> 16) & 0xff, %s >> 24,' % (qst, qst, qst, qst))
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return 4
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elif MP_NATIVE_ARCH_ARMV6M <= config.native_arch <= MP_NATIVE_ARCH_ARMV7EMDP:
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if is_obj:
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