fix FrequencyIn for crystalless boards and simplify clock logic
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92bb909bf0
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7e21344cf0
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@ -57,6 +57,11 @@ static frequencyio_frequencyin_obj_t *active_frequencyins[TC_INST_NUM];
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volatile uint8_t reference_tc;
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#ifdef SAM_D5X_E5X
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static uint8_t dpll_gclk;
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#if !BOARD_HAS_CRYSTAL
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static uint8_t osculp32k_gclk;
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#endif
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#endif
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void frequencyin_reset(void) {
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@ -67,6 +72,11 @@ void frequencyin_reset(void) {
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reference_tc = 0xff;
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#ifdef SAM_D5X_E5X
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dpll_gclk = 0xff;
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#if !BOARD_HAS_CRYSTAL
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osculp32k_gclk = 0xff;
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#endif
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#endif
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}
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@ -208,34 +218,38 @@ static bool frequencyin_samd51_start_dpll(void) {
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return true;
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}
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uint8_t free_gclk = find_free_gclk(1);
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if (free_gclk == 0xff) {
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dpll_gclk = 0xff;
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dpll_gclk = find_free_gclk(1);
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if (dpll_gclk == 0xff) {
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return false;
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}
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(free_gclk);
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// TC4-7 can only have a max of 100MHz source
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// DPLL1 frequency equation with [X]OSC32K as source: 98.304MHz = 32768(2999 + 1 + 0/32)
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// Will also enable the Lock Bypass due to low-frequency sources causing DPLL unlocks
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// as outlined in the Errata (1.12.1)
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OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(2999);
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#if BOARD_HAS_CRYSTAL
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// we can use XOSC32K directly as the source
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OSC32KCTRL->XOSC32K.bit.EN32K = 1;
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OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(1) | OSCCTRL_DPLLCTRLB_LBYPASS;
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#else
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// can't use OSCULP32K directly; need to setup a GCLK as a reference,
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// which must be done in samd/clocks.c to avoid waiting for sync
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return;
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//OSC32KCTRL->OSCULP32K.bit.EN32K = 1;
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//OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(0);
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#endif
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OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
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#if BOARD_HAS_CRYSTAL
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// we can use XOSC32K directly as the source. It has already been initialized in clocks.c
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OSCCTRL->Dpll[1].DPLLCTRLB.reg =
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OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val) | OSCCTRL_DPLLCTRLB_LBYPASS;
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#else
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// We can't use OSCULP32K directly. Set up a GCLK controlled by it
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// Then use that GCLK as the reference oscillator for the DPLL.
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osculp32k_gclk = find_free_gclk(1);
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if (osculp32k_gclk == 0xff) {
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return false;
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}
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enable_clock_generator(osculp32k_gclk, GCLK_GENCTRL_SRC_OSCULP32K_Val, 1);
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(OSCCTRL_GCLK_ID_FDPLL1);
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OSCCTRL->Dpll[1].DPLLCTRLB.reg =
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OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val) | OSCCTRL_DPLLCTRLB_LBYPASS;
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#endif
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OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
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while (!(OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY)) {}
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enable_clock_generator(free_gclk, GCLK_GENCTRL_SRC_DPLL1_Val, 1);
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dpll_gclk = free_gclk;
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enable_clock_generator(dpll_gclk, GCLK_GENCTRL_SRC_DPLL1_Val, 1);
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return true;
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}
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@ -249,6 +263,11 @@ static void frequencyin_samd51_stop_dpll(void) {
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dpll_gclk = 0xff;
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}
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if (osculp32k_gclk != 0xff) {
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disable_clock_generator(osculp32k_gclk);
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osculp32k_gclk = 0xff;
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}
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = 0;
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OSCCTRL->Dpll[1].DPLLCTRLA.reg = 0;
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OSCCTRL->Dpll[1].DPLLRATIO.reg = 0;
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