stm32/rfcore: Add Python API for basic rfcore operations.
The new functions provide FUS/WS status, version and SYS HCI commands: - stm.rfcore_status() - stm.rfcore_fw_version(fw_id) - stm.rfcore_sys_hci(ogf, ocf, cmd)
This commit is contained in:
Jim Mussared
Damien George
parent
9855b9cd82
commit
7c76a2dfcf
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@ -30,6 +30,7 @@
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#include "py/obj.h"
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#include "py/objint.h"
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#include "extmod/machine_mem.h"
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#include "rfcore.h"
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#include "portmodules.h"
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#if MICROPY_PY_STM
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@ -44,6 +45,12 @@ STATIC const mp_rom_map_elem_t stm_module_globals_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_mem32), MP_ROM_PTR(&machine_mem32_obj) },
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#include "genhdr/modstm_const.h"
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#if defined(STM32WB)
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{ MP_ROM_QSTR(MP_QSTR_rfcore_status), MP_ROM_PTR(&rfcore_status_obj) },
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{ MP_ROM_QSTR(MP_QSTR_rfcore_fw_version), MP_ROM_PTR(&rfcore_fw_version_obj) },
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{ MP_ROM_QSTR(MP_QSTR_rfcore_sys_hci), MP_ROM_PTR(&rfcore_sys_hci_obj) },
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#endif
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};
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STATIC MP_DEFINE_CONST_DICT(stm_module_globals, stm_module_globals_table);
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@ -30,6 +30,7 @@
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "py/runtime.h"
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#include "rtc.h"
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#include "rfcore.h"
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@ -66,9 +67,16 @@
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#define HCI_EVENT_COMMAND_COMPLETE (0x0E) // <num packets><opcode 16><status><data...>
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#define SYS_ACK_TIMEOUT_MS (250)
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// There can be quite long delays during firmware update.
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#define SYS_ACK_TIMEOUT_MS (1000)
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#define BLE_ACK_TIMEOUT_MS (250)
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// AN5185
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#define MAGIC_FUS_ACTIVE 0xA94656B9
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// AN5289
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#define MAGIC_IPCC_MEM_INCORRECT 0x3DE96F61
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typedef struct _tl_list_node_t {
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volatile struct _tl_list_node_t *next;
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volatile struct _tl_list_node_t *prev;
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@ -267,10 +275,10 @@ void ipcc_init(uint32_t irq_pri) {
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/******************************************************************************/
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// Transport layer HCI interface
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STATIC void tl_parse_hci_msg(const uint8_t *buf, parse_hci_info_t *parse) {
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STATIC size_t tl_parse_hci_msg(const uint8_t *buf, parse_hci_info_t *parse) {
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const char *info;
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size_t len = 0;
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bool applied_set_event_event_mask2_fix = false;
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size_t len;
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switch (buf[0]) {
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case HCI_KIND_BT_ACL: {
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info = "HCI_ACL";
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@ -334,6 +342,7 @@ STATIC void tl_parse_hci_msg(const uint8_t *buf, parse_hci_info_t *parse) {
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}
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default:
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info = "HCI_UNKNOWN";
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len = 0;
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break;
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}
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@ -354,6 +363,8 @@ STATIC void tl_parse_hci_msg(const uint8_t *buf, parse_hci_info_t *parse) {
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#else
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(void)info;
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#endif
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return len;
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}
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STATIC void tl_process_msg(volatile tl_list_node_t *head, unsigned int ch, parse_hci_info_t *parse) {
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@ -397,7 +408,7 @@ STATIC void tl_check_msg_ble(volatile tl_list_node_t *head, parse_hci_info_t *pa
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}
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}
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STATIC void tl_hci_cmd(uint8_t *cmd, unsigned int ch, uint8_t hdr, uint16_t opcode, size_t len, const uint8_t *buf) {
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STATIC void tl_hci_cmd(uint8_t *cmd, unsigned int ch, uint8_t hdr, uint16_t opcode, const uint8_t *buf, size_t len) {
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tl_list_node_t *n = (tl_list_node_t *)cmd;
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n->next = n;
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n->prev = n;
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@ -407,11 +418,19 @@ STATIC void tl_hci_cmd(uint8_t *cmd, unsigned int ch, uint8_t hdr, uint16_t opco
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cmd[11] = len;
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memcpy(&cmd[12], buf, len);
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#if HCI_TRACE
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printf("[% 8d] >HCI(", mp_hal_ticks_ms());
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for (int i = 0; i < len + 4; ++i) {
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printf(":%02x", cmd[i + 8]);
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}
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printf(")\n");
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#endif
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// Indicate that this channel is ready.
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LL_C1_IPCC_SetFlag_CHx(IPCC, ch);
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}
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STATIC int tl_sys_wait_ack(const uint8_t *buf) {
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STATIC ssize_t tl_sys_wait_ack(const uint8_t *buf) {
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uint32_t t0 = mp_hal_ticks_ms();
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// C2 will clear this bit to acknowledge the request.
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@ -422,14 +441,14 @@ STATIC int tl_sys_wait_ack(const uint8_t *buf) {
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}
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}
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// C1-to-C2 bit cleared, so process (but ignore) the response.
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tl_parse_hci_msg(buf, NULL);
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return 0;
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// C1-to-C2 bit cleared, so process the response (just get the length, do
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// not parse any further).
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return (ssize_t)tl_parse_hci_msg(buf, NULL);
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}
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STATIC void tl_sys_hci_cmd_resp(uint16_t opcode, size_t len, const uint8_t *buf) {
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tl_hci_cmd(ipcc_membuf_sys_cmd_buf, IPCC_CH_SYS, 0x10, opcode, len, buf);
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tl_sys_wait_ack(ipcc_membuf_sys_cmd_buf);
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STATIC ssize_t tl_sys_hci_cmd_resp(uint16_t opcode, const uint8_t *buf, size_t len) {
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tl_hci_cmd(ipcc_membuf_sys_cmd_buf, IPCC_CH_SYS, 0x10, opcode, buf, len);
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return tl_sys_wait_ack(ipcc_membuf_sys_cmd_buf);
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}
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STATIC int tl_ble_wait_resp(void) {
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@ -447,10 +466,9 @@ STATIC int tl_ble_wait_resp(void) {
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}
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// Synchronously send a BLE command.
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STATIC void tl_ble_hci_cmd_resp(uint16_t opcode, size_t len, const uint8_t *buf) {
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tl_hci_cmd(ipcc_membuf_ble_cmd_buf, IPCC_CH_BLE, HCI_KIND_BT_CMD, opcode, len, buf);
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STATIC void tl_ble_hci_cmd_resp(uint16_t opcode, const uint8_t *buf, size_t len) {
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tl_hci_cmd(ipcc_membuf_ble_cmd_buf, IPCC_CH_BLE, HCI_KIND_BT_CMD, opcode, buf, len);
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tl_ble_wait_resp();
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}
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/******************************************************************************/
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@ -522,8 +540,8 @@ void rfcore_ble_init(void) {
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tl_check_msg_ble(&ipcc_mem_ble_evt_queue, NULL);
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// Configure and reset the BLE controller
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tl_sys_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_BLE_INIT), sizeof(ble_init_params), (const uint8_t *)&ble_init_params);
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tl_ble_hci_cmd_resp(HCI_OPCODE(0x03, 0x0003), 0, NULL);
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tl_sys_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_BLE_INIT), (const uint8_t *)&ble_init_params, sizeof(ble_init_params));
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tl_ble_hci_cmd_resp(HCI_OPCODE(0x03, 0x0003), NULL, 0);
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}
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void rfcore_ble_hci_cmd(size_t len, const uint8_t *src) {
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@ -573,14 +591,14 @@ void rfcore_ble_check_msg(int (*cb)(void *, const uint8_t *, size_t), void *env)
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SWAP_UINT8(buf[2], buf[7]);
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SWAP_UINT8(buf[3], buf[6]);
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SWAP_UINT8(buf[4], buf[5]);
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tl_ble_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_WRITE_CONFIG), 8, buf); // set BDADDR
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tl_ble_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_WRITE_CONFIG), buf, 8); // set BDADDR
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}
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}
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// "level" is 0x00-0x1f, ranging from -40 dBm to +6 dBm (not linear).
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void rfcore_ble_set_txpower(uint8_t level) {
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uint8_t buf[2] = { 0x00, level };
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tl_ble_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_SET_TX_POWER), 2, buf);
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tl_ble_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_SET_TX_POWER), buf, 2);
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}
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// IPCC IRQ Handlers
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@ -605,4 +623,53 @@ void IPCC_C1_RX_IRQHandler(void) {
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IRQ_EXIT(IPCC_C1_RX_IRQn);
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}
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/******************************************************************************/
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// MicroPython bindings
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STATIC mp_obj_t rfcore_status(void) {
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return mp_obj_new_int_from_uint(ipcc_mem_dev_info_tab.fus.table_state);
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}
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MP_DEFINE_CONST_FUN_OBJ_0(rfcore_status_obj, rfcore_status);
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STATIC mp_obj_t get_version_tuple(uint32_t data) {
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mp_obj_t items[] = {
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MP_OBJ_NEW_SMALL_INT(data >> 24), MP_OBJ_NEW_SMALL_INT(data >> 16 & 0xFF), MP_OBJ_NEW_SMALL_INT(data >> 8 & 0xFF), MP_OBJ_NEW_SMALL_INT(data >> 4 & 0xF), MP_OBJ_NEW_SMALL_INT(data & 0xF)
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};
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return mp_obj_new_tuple(5, items);
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}
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STATIC mp_obj_t rfcore_fw_version(mp_obj_t fw_id_in) {
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if (ipcc_mem_dev_info_tab.fus.table_state == MAGIC_IPCC_MEM_INCORRECT) {
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mp_raise_OSError(MP_EINVAL);
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}
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mp_int_t fw_id = mp_obj_get_int(fw_id_in);
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bool fus_active = ipcc_mem_dev_info_tab.fus.table_state == MAGIC_FUS_ACTIVE;
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uint32_t v;
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if (fw_id == 0) {
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// FUS
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v = fus_active ? ipcc_mem_dev_info_tab.fus.fus_version : ipcc_mem_dev_info_tab.ws.fus_version;
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} else {
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// WS
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v = fus_active ? ipcc_mem_dev_info_tab.fus.ws_version : ipcc_mem_dev_info_tab.ws.fw_version;
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}
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return get_version_tuple(v);
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}
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MP_DEFINE_CONST_FUN_OBJ_1(rfcore_fw_version_obj, rfcore_fw_version);
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STATIC mp_obj_t rfcore_sys_hci(mp_obj_t ogf_in, mp_obj_t ocf_in, mp_obj_t cmd_in) {
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if (ipcc_mem_dev_info_tab.fus.table_state == MAGIC_IPCC_MEM_INCORRECT) {
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mp_raise_OSError(MP_EINVAL);
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}
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mp_int_t ogf = mp_obj_get_int(ogf_in);
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mp_int_t ocf = mp_obj_get_int(ocf_in);
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mp_buffer_info_t bufinfo = {0};
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mp_get_buffer_raise(cmd_in, &bufinfo, MP_BUFFER_READ);
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ssize_t len = tl_sys_hci_cmd_resp(HCI_OPCODE(ogf, ocf), bufinfo.buf, bufinfo.len);
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if (len < 0) {
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mp_raise_OSError(-len);
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}
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return mp_obj_new_bytes(ipcc_membuf_sys_cmd_buf, len);
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}
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MP_DEFINE_CONST_FUN_OBJ_3(rfcore_sys_hci_obj, rfcore_sys_hci);
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#endif // defined(STM32WB)
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@ -35,4 +35,8 @@ void rfcore_ble_hci_cmd(size_t len, const uint8_t *src);
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void rfcore_ble_check_msg(int (*cb)(void *, const uint8_t *, size_t), void *env);
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void rfcore_ble_set_txpower(uint8_t level);
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MP_DECLARE_CONST_FUN_OBJ_0(rfcore_status_obj);
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MP_DECLARE_CONST_FUN_OBJ_1(rfcore_fw_version_obj);
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MP_DECLARE_CONST_FUN_OBJ_3(rfcore_sys_hci_obj);
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#endif // MICROPY_INCLUDED_STM32_RFCORE_H
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