From de0afcdf2dbdf1c22cb1f9fb5d4c5c3f8781ca45 Mon Sep 17 00:00:00 2001 From: sommersoft Date: Wed, 27 May 2020 16:51:57 -0500 Subject: [PATCH 01/91] add ci_check_duplicate_usb_vid_pid.py; checks that a new board doesn't use duplicate USB VID/PID values unless explicitly whitelisted to do so --- tools/ci_check_duplicate_usb_vid_pid.py | 136 ++++++++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 tools/ci_check_duplicate_usb_vid_pid.py diff --git a/tools/ci_check_duplicate_usb_vid_pid.py b/tools/ci_check_duplicate_usb_vid_pid.py new file mode 100644 index 0000000000..2890070db1 --- /dev/null +++ b/tools/ci_check_duplicate_usb_vid_pid.py @@ -0,0 +1,136 @@ +#!/usr/bin/env python3 +# +# This file is part of the MicroPython project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2020 Michael Schroeder +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +import argparse +import pathlib +import re +import sys + +DEFAULT_WHITELIST = [ + "circuitplayground_express", + "circuitplayground_express_crickit", + "circuitplayground_express_displayio", + "pycubed", + "pycubed_mram", + "pygamer", + "pygamer_advance", + "trinket_m0", + "trinket_m0_haxpress" +] + +cli_parser = argparse.ArgumentParser(description="USB VID/PID Duplicate Checker") +cli_parser.add_argument( + "--whitelist", + dest="whitelist", + nargs="?", + action="store", + default=DEFAULT_WHITELIST, + help=( + "Board names to ignore duplicate VID/PID combinations. Pass an empty " + "string to disable all duplicate ignoring. Defaults are: " + f"{', '.join(DEFAULT_WHITELIST)}" + ) +) + +def configboard_files(): + """ A pathlib glob search for all ports/*/boards/*/mpconfigboard.mk file + paths. + + :returns: A ``pathlib.Path.glob()`` genarator object + """ + working_dir = pathlib.Path().resolve() + if not working_dir.name.startswith("circuitpython"): + raise RuntimeError( + "Please run USB VID/PID duplicate verification at the " + "top-level directory." + ) + return working_dir.glob("ports/**/boards/**/mpconfigboard.mk") + +def check_vid_pid(files, whitelist): + """ Compiles a list of USB VID & PID values for all boards, and checks + for duplicates. Raises a `RuntimeError` if duplicates are found, and + lists the duplicates. + """ + + duplicates_found = False + + usb_ids = {} + + vid_pattern = re.compile(r"^USB_VID\s*\=\s*(.*)", flags=re.M) + pid_pattern = re.compile(r"^USB_PID\s*\=\s*(.*)", flags=re.M) + + for board_config in files: + src_text = board_config.read_text() + + usb_vid = vid_pattern.search(src_text) + usb_pid = pid_pattern.search(src_text) + + board_name = board_config.parts[-2] + + board_whitelisted = False + if board_name in whitelist: + board_whitelisted = True + board_name += " (whitelisted)" + + if usb_vid and usb_pid: + id_group = f"{usb_vid.group(1)}:{usb_pid.group(1)}" + if id_group not in usb_ids: + usb_ids[id_group] = { + "boards": [board_name], + "duplicate": False + } + else: + usb_ids[id_group]['boards'].append(board_name) + if not board_whitelisted: + usb_ids[id_group]['duplicate'] = True + duplicates_found = True + + if duplicates_found: + duplicates = "" + for key, value in usb_ids.items(): + if value["duplicate"]: + duplicates += ( + f"- VID/PID: {key}\n" + f" Boards: {', '.join(value['boards'])}\n" + ) + + duplicate_message = ( + f"Duplicate VID/PID usage found!\n{duplicates}" + ) + sys.exit(duplicate_message) + + +if __name__ == "__main__": + arguments = cli_parser.parse_args() + + print("Running USB VID/PID Duplicate Checker...") + print( + f"Ignoring the following boards: {', '.join(arguments.whitelist)}", + end="\n\n" + ) + + board_files = configboard_files() + check_vid_pid(board_files, arguments.whitelist) From 8e64b1240857340cd86d49a716ae5f542ab35e04 Mon Sep 17 00:00:00 2001 From: sommersoft Date: Wed, 27 May 2020 16:54:52 -0500 Subject: [PATCH 02/91] build.yml: add step to run tools/ci_check_duplicate_usb_vid_pid.py --- .github/workflows/build.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 0719b40e94..dead151423 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -73,6 +73,8 @@ jobs: - name: New boards check run: python3 -u ci_new_boards_check.py working-directory: tools + - name: Duplicate USB VID/PID Check + run: python3 -u -m tools.ci_check_duplicate_usb_vid_pid - name: Build mpy-cross.static-raspbian run: make -C mpy-cross -j2 -f Makefile.static-raspbian - uses: actions/upload-artifact@v1.0.0 From c7b6d35fd43ca192c3e7e95bf0a0f2ea0b0fc4a5 Mon Sep 17 00:00:00 2001 From: sommersoft Date: Wed, 27 May 2020 19:08:56 -0500 Subject: [PATCH 03/91] ci_check_duplicate_usb_vid_pid.py: update docstring; moved to sys.exit from raising RuntimeError --- tools/ci_check_duplicate_usb_vid_pid.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/ci_check_duplicate_usb_vid_pid.py b/tools/ci_check_duplicate_usb_vid_pid.py index 2890070db1..505704f122 100644 --- a/tools/ci_check_duplicate_usb_vid_pid.py +++ b/tools/ci_check_duplicate_usb_vid_pid.py @@ -71,8 +71,8 @@ def configboard_files(): def check_vid_pid(files, whitelist): """ Compiles a list of USB VID & PID values for all boards, and checks - for duplicates. Raises a `RuntimeError` if duplicates are found, and - lists the duplicates. + for duplicates. Exits with ``sys.exit()`` (non-zero exit code) + if duplicates are found, and lists the duplicates. """ duplicates_found = False From 5d158d884d2be6d9f69a8ff747cd87b7917e2963 Mon Sep 17 00:00:00 2001 From: sommersoft Date: Sat, 20 Jun 2020 08:44:24 -0500 Subject: [PATCH 04/91] ci_check_duplicate_usb_vid_pid.py: change 'whitelist' terminology to 'ignorelist' --- tools/ci_check_duplicate_usb_vid_pid.py | 26 ++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tools/ci_check_duplicate_usb_vid_pid.py b/tools/ci_check_duplicate_usb_vid_pid.py index 505704f122..b05d56012f 100644 --- a/tools/ci_check_duplicate_usb_vid_pid.py +++ b/tools/ci_check_duplicate_usb_vid_pid.py @@ -29,7 +29,7 @@ import pathlib import re import sys -DEFAULT_WHITELIST = [ +DEFAULT_IGNORELIST = [ "circuitplayground_express", "circuitplayground_express_crickit", "circuitplayground_express_displayio", @@ -43,15 +43,15 @@ DEFAULT_WHITELIST = [ cli_parser = argparse.ArgumentParser(description="USB VID/PID Duplicate Checker") cli_parser.add_argument( - "--whitelist", - dest="whitelist", + "--ignorelist", + dest="ignorelist", nargs="?", action="store", - default=DEFAULT_WHITELIST, + default=DEFAULT_IGNORELIST, help=( "Board names to ignore duplicate VID/PID combinations. Pass an empty " "string to disable all duplicate ignoring. Defaults are: " - f"{', '.join(DEFAULT_WHITELIST)}" + f"{', '.join(DEFAULT_IGNORELIST)}" ) ) @@ -69,7 +69,7 @@ def configboard_files(): ) return working_dir.glob("ports/**/boards/**/mpconfigboard.mk") -def check_vid_pid(files, whitelist): +def check_vid_pid(files, ignorelist): """ Compiles a list of USB VID & PID values for all boards, and checks for duplicates. Exits with ``sys.exit()`` (non-zero exit code) if duplicates are found, and lists the duplicates. @@ -90,10 +90,10 @@ def check_vid_pid(files, whitelist): board_name = board_config.parts[-2] - board_whitelisted = False - if board_name in whitelist: - board_whitelisted = True - board_name += " (whitelisted)" + board_ignorelisted = False + if board_name in ignorelist: + board_ignorelisted = True + board_name += " (ignorelisted)" if usb_vid and usb_pid: id_group = f"{usb_vid.group(1)}:{usb_pid.group(1)}" @@ -104,7 +104,7 @@ def check_vid_pid(files, whitelist): } else: usb_ids[id_group]['boards'].append(board_name) - if not board_whitelisted: + if not board_ignorelisted: usb_ids[id_group]['duplicate'] = True duplicates_found = True @@ -128,9 +128,9 @@ if __name__ == "__main__": print("Running USB VID/PID Duplicate Checker...") print( - f"Ignoring the following boards: {', '.join(arguments.whitelist)}", + f"Ignoring the following boards: {', '.join(arguments.ignorelist)}", end="\n\n" ) board_files = configboard_files() - check_vid_pid(board_files, arguments.whitelist) + check_vid_pid(board_files, arguments.ignorelist) From 12b81618a3a4d914114aae4ebc647a4f8bd9dc3f Mon Sep 17 00:00:00 2001 From: root Date: Sat, 1 Aug 2020 13:27:02 -0500 Subject: [PATCH 05/91] Changes for getting supervisor ticks --- lib/protomatter | 2 +- locale/circuitpython.pot | 2 +- ports/atmel-samd/common-hal/pulseio/PulseIn.c | 9 ++------- supervisor/background_callback.h | 4 ++++ supervisor/port.h | 3 +++ supervisor/shared/background_callback.c | 7 +++++++ supervisor/shared/tick.c | 6 +----- 7 files changed, 19 insertions(+), 14 deletions(-) diff --git a/lib/protomatter b/lib/protomatter index 761d6437e8..00e00ee8ac 160000 --- a/lib/protomatter +++ b/lib/protomatter @@ -1 +1 @@ -Subproject commit 761d6437e8cd6a131d51de96974337121a9c7164 +Subproject commit 00e00ee8acb043b976302051291bc236ae2676cb diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 5ed32d6382..6176a18dac 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-07-30 07:23-0500\n" +"POT-Creation-Date: 2020-08-01 12:58-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c index ae58b089de..5bd3cc7de1 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c @@ -88,9 +88,8 @@ void pulsein_interrupt_handler(uint8_t channel) { uint32_t current_count = tc->COUNT16.COUNT.reg; pulseio_pulsein_obj_t* self = get_eic_channel_data(channel); - if (!supervisor_background_tasks_ok() || self->errored_too_fast) { - self->errored_too_fast = true; - common_hal_pulseio_pulsein_pause(self); + if (!supervisor_background_tasks_ok() ) { + mp_raise_RuntimeError(translate("Input taking too long")); return; } if (self->first_edge) { @@ -154,7 +153,6 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, self->start = 0; self->len = 0; self->first_edge = true; - self->errored_too_fast = false; if (refcount == 0) { // Find a spare timer. @@ -264,9 +262,6 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, // Make sure we're paused. common_hal_pulseio_pulsein_pause(self); - // Reset erroring - self->errored_too_fast = false; - // Send the trigger pulse. if (trigger_duration > 0) { gpio_set_pin_pull_mode(self->pin, GPIO_PULL_OFF); diff --git a/supervisor/background_callback.h b/supervisor/background_callback.h index 535dd656be..e943830fd0 100644 --- a/supervisor/background_callback.h +++ b/supervisor/background_callback.h @@ -27,6 +27,8 @@ #ifndef CIRCUITPY_INCLUDED_SUPERVISOR_BACKGROUND_CALLBACK_H #define CIRCUITPY_INCLUDED_SUPERVISOR_BACKGROUND_CALLBACK_H +#include "supervisor/port.h" + /** Background callbacks are a linked list of tasks to call in the background. * * Include a member of type `background_callback_t` inside an object @@ -84,4 +86,6 @@ void background_callback_end_critical_section(void); */ void background_callback_gc_collect(void); +uint64_t background_get_ticks(void); + #endif diff --git a/supervisor/port.h b/supervisor/port.h index ad5b3cf32a..c95e43fd2e 100644 --- a/supervisor/port.h +++ b/supervisor/port.h @@ -73,6 +73,9 @@ uint32_t *port_heap_get_top(void); void port_set_saved_word(uint32_t); uint32_t port_get_saved_word(void); +// Used to keep track of last time background was run +uint64_t get_background_ticks(void); + // Get the raw tick count since start up. A tick is 1/1024 of a second, a common low frequency // clock rate. If subticks is not NULL then the port will fill in the number of subticks where each // tick is 32 subticks (for a resolution of 1/32768 or 30.5ish microseconds.) diff --git a/supervisor/shared/background_callback.c b/supervisor/shared/background_callback.c index 8e12dd3625..4502424acc 100644 --- a/supervisor/shared/background_callback.c +++ b/supervisor/shared/background_callback.c @@ -37,6 +37,12 @@ STATIC volatile background_callback_t *callback_head, *callback_tail; #define CALLBACK_CRITICAL_BEGIN (common_hal_mcu_disable_interrupts()) #define CALLBACK_CRITICAL_END (common_hal_mcu_enable_interrupts()) +volatile uint64_t last_background_tick = 0; + +uint64_t get_background_ticks(void) { + return last_background_tick; +} + void background_callback_add_core(background_callback_t *cb) { CALLBACK_CRITICAL_BEGIN; if (cb->prev || callback_head == cb) { @@ -64,6 +70,7 @@ void background_callback_add(background_callback_t *cb, background_callback_fun static bool in_background_callback; void background_callback_run_all() { + last_background_tick = port_get_raw_ticks(NULL); if (!callback_head) { return; } diff --git a/supervisor/shared/tick.c b/supervisor/shared/tick.c index 4af59f78e3..eac5104a5c 100644 --- a/supervisor/shared/tick.c +++ b/supervisor/shared/tick.c @@ -68,8 +68,6 @@ static volatile uint64_t PLACE_IN_DTCM_BSS(background_ticks); static background_callback_t tick_callback; -volatile uint64_t last_finished_tick = 0; - void supervisor_background_tasks(void *unused) { port_start_background_task(); @@ -93,13 +91,11 @@ void supervisor_background_tasks(void *unused) { assert_heap_ok(); - last_finished_tick = port_get_raw_ticks(NULL); - port_finish_background_task(); } bool supervisor_background_tasks_ok(void) { - return port_get_raw_ticks(NULL) - last_finished_tick < 1024; + return port_get_raw_ticks(NULL) - get_background_ticks() < 1024; } void supervisor_tick(void) { From a3d8567d2c3c83f247a2018804a81ee646724e1d Mon Sep 17 00:00:00 2001 From: root Date: Sat, 1 Aug 2020 13:45:31 -0500 Subject: [PATCH 06/91] Adding error message for PulseIn --- locale/circuitpython.pot | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 6176a18dac..8c88ca5be2 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-08-01 12:58-0500\n" +"POT-Creation-Date: 2020-08-01 13:45-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -880,6 +880,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "" From 0ef68d6aea57d87e253df69ad6d4566585fcd858 Mon Sep 17 00:00:00 2001 From: root Date: Sat, 1 Aug 2020 16:35:42 -0500 Subject: [PATCH 07/91] Improved performance for background task tick counter. --- supervisor/shared/background_callback.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/supervisor/shared/background_callback.c b/supervisor/shared/background_callback.c index 4502424acc..ddf723697b 100644 --- a/supervisor/shared/background_callback.c +++ b/supervisor/shared/background_callback.c @@ -70,10 +70,10 @@ void background_callback_add(background_callback_t *cb, background_callback_fun static bool in_background_callback; void background_callback_run_all() { - last_background_tick = port_get_raw_ticks(NULL); if (!callback_head) { return; } + last_background_tick = port_get_raw_ticks(NULL); CALLBACK_CRITICAL_BEGIN; if (in_background_callback) { CALLBACK_CRITICAL_END; From 32bcf88e1847ba9c5460cad4a8244c8d5419384b Mon Sep 17 00:00:00 2001 From: root Date: Sat, 1 Aug 2020 17:08:48 -0500 Subject: [PATCH 08/91] Fixinf up submodules --- extmod/ulab | 2 +- frozen/Adafruit_CircuitPython_BLE | 2 +- frozen/Adafruit_CircuitPython_BLE_Apple_Notification_Center | 2 +- frozen/Adafruit_CircuitPython_BusDevice | 2 +- lib/protomatter | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/extmod/ulab b/extmod/ulab index 11a7ecff6d..4a771347bb 160000 --- a/extmod/ulab +++ b/extmod/ulab @@ -1 +1 @@ -Subproject commit 11a7ecff6d76a02644ff23a734b792afaa615e44 +Subproject commit 4a771347bb49ec0335feb567465a690ef1ba8e5a diff --git a/frozen/Adafruit_CircuitPython_BLE b/frozen/Adafruit_CircuitPython_BLE index 5d584576ef..41f7a3530d 160000 --- a/frozen/Adafruit_CircuitPython_BLE +++ b/frozen/Adafruit_CircuitPython_BLE @@ -1 +1 @@ -Subproject commit 5d584576ef79ca36506e6c7470e7ac5204cf0a8d +Subproject commit 41f7a3530d4cacdbf668399d3a015ea29c7e169b diff --git a/frozen/Adafruit_CircuitPython_BLE_Apple_Notification_Center b/frozen/Adafruit_CircuitPython_BLE_Apple_Notification_Center index 3ffb3f02d2..6a034887e3 160000 --- a/frozen/Adafruit_CircuitPython_BLE_Apple_Notification_Center +++ b/frozen/Adafruit_CircuitPython_BLE_Apple_Notification_Center @@ -1 +1 @@ -Subproject commit 3ffb3f02d2046910e09d1f5a74721bd1a4cdf8cf +Subproject commit 6a034887e370caa61fee5f51db8dd393d3e72542 diff --git a/frozen/Adafruit_CircuitPython_BusDevice b/frozen/Adafruit_CircuitPython_BusDevice index e9411c4244..eb4b21e216 160000 --- a/frozen/Adafruit_CircuitPython_BusDevice +++ b/frozen/Adafruit_CircuitPython_BusDevice @@ -1 +1 @@ -Subproject commit e9411c4244984b69ec6928370ede40cec014c10b +Subproject commit eb4b21e216efd8ec0c4862a938e81b56be961724 diff --git a/lib/protomatter b/lib/protomatter index 00e00ee8ac..2408e9c033 160000 --- a/lib/protomatter +++ b/lib/protomatter @@ -1 +1 @@ -Subproject commit 00e00ee8acb043b976302051291bc236ae2676cb +Subproject commit 2408e9c033f5ec050967b1592b29a950a831d6c2 From 64df244cf5562b66211369c2869ea79b1bde423f Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Sat, 1 Aug 2020 17:10:05 -0500 Subject: [PATCH 09/91] restore protomatter submodule ref --- lib/protomatter | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/protomatter b/lib/protomatter index 00e00ee8ac..761d6437e8 160000 --- a/lib/protomatter +++ b/lib/protomatter @@ -1 +1 @@ -Subproject commit 00e00ee8acb043b976302051291bc236ae2676cb +Subproject commit 761d6437e8cd6a131d51de96974337121a9c7164 From 9203a778042c584138f2852c108b58e900047ac4 Mon Sep 17 00:00:00 2001 From: root Date: Mon, 3 Aug 2020 11:31:12 -0500 Subject: [PATCH 10/91] Turn off interrupts while in handler --- ports/atmel-samd/common-hal/pulseio/PulseIn.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c index 5bd3cc7de1..a47135d566 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c @@ -77,6 +77,8 @@ static void pulsein_set_config(pulseio_pulsein_obj_t* self, bool first_edge) { } void pulsein_interrupt_handler(uint8_t channel) { + // turn off interrupts while in the handler + common_hal_mcu_disable_interrupts(); // Grab the current time first. uint32_t current_overflow = overflow_count; Tc* tc = tc_insts[pulsein_tc_index]; @@ -89,6 +91,7 @@ void pulsein_interrupt_handler(uint8_t channel) { pulseio_pulsein_obj_t* self = get_eic_channel_data(channel); if (!supervisor_background_tasks_ok() ) { + common_hal_mcu_enable_interrupts(); mp_raise_RuntimeError(translate("Input taking too long")); return; } @@ -122,6 +125,7 @@ void pulsein_interrupt_handler(uint8_t channel) { } self->last_overflow = current_overflow; self->last_count = current_count; + common_hal_mcu_enable_interrupts(); } void pulsein_reset() { From c7b6e66426dbff05b10e1f5aa64320f2071e8878 Mon Sep 17 00:00:00 2001 From: root Date: Wed, 5 Aug 2020 10:03:20 -0500 Subject: [PATCH 11/91] Fixes for pulsein tick handling --- ports/atmel-samd/common-hal/pulseio/PulseIn.c | 15 +++++++++------ ports/atmel-samd/common-hal/pulseio/PulseIn.h | 1 + supervisor/shared/background_callback.c | 6 +++++- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c index a47135d566..79f66ceaee 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c @@ -44,6 +44,7 @@ #include "shared-bindings/pulseio/PulseIn.h" #include "supervisor/shared/tick.h" #include "supervisor/shared/translate.h" +#include "supervisor/port.h" // This timer is shared amongst all PulseIn objects as a higher resolution clock. static uint8_t refcount = 0; @@ -77,7 +78,7 @@ static void pulsein_set_config(pulseio_pulsein_obj_t* self, bool first_edge) { } void pulsein_interrupt_handler(uint8_t channel) { - // turn off interrupts while in the handler + // Turn off interrupts while in handler common_hal_mcu_disable_interrupts(); // Grab the current time first. uint32_t current_overflow = overflow_count; @@ -90,10 +91,8 @@ void pulsein_interrupt_handler(uint8_t channel) { uint32_t current_count = tc->COUNT16.COUNT.reg; pulseio_pulsein_obj_t* self = get_eic_channel_data(channel); - if (!supervisor_background_tasks_ok() ) { - common_hal_mcu_enable_interrupts(); - mp_raise_RuntimeError(translate("Input taking too long")); - return; + if (self->len == 0) { + update_background_ticks(); } if (self->first_edge) { self->first_edge = false; @@ -123,6 +122,11 @@ void pulsein_interrupt_handler(uint8_t channel) { self->start++; } } + if (!supervisor_background_tasks_ok() ) { + common_hal_mcu_enable_interrupts(); + mp_raise_RuntimeError(translate("Input taking too long")); + return; + } self->last_overflow = current_overflow; self->last_count = current_count; common_hal_mcu_enable_interrupts(); @@ -304,7 +308,6 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { self->start = (self->start + 1) % self->maxlen; self->len--; common_hal_mcu_enable_interrupts(); - return value; } diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.h b/ports/atmel-samd/common-hal/pulseio/PulseIn.h index 99358178f2..a0f838b373 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.h +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.h @@ -50,6 +50,7 @@ void pulsein_reset(void); void pulsein_interrupt_handler(uint8_t channel); void pulsein_timer_interrupt_handler(uint8_t index); +void update_background_ticks(void); #ifdef SAMD21 void rtc_set_continuous(void); void rtc_start_pulsein(void); diff --git a/supervisor/shared/background_callback.c b/supervisor/shared/background_callback.c index ddf723697b..af64f99aa6 100644 --- a/supervisor/shared/background_callback.c +++ b/supervisor/shared/background_callback.c @@ -37,12 +37,16 @@ STATIC volatile background_callback_t *callback_head, *callback_tail; #define CALLBACK_CRITICAL_BEGIN (common_hal_mcu_disable_interrupts()) #define CALLBACK_CRITICAL_END (common_hal_mcu_enable_interrupts()) -volatile uint64_t last_background_tick = 0; +uint64_t last_background_tick = 0; uint64_t get_background_ticks(void) { return last_background_tick; } +void update_background_ticks(void) { + last_background_tick = port_get_raw_ticks(NULL); +} + void background_callback_add_core(background_callback_t *cb) { CALLBACK_CRITICAL_BEGIN; if (cb->prev || callback_head == cb) { From a778163d0f7888570c3799d4905cf981cba8619d Mon Sep 17 00:00:00 2001 From: root Date: Wed, 5 Aug 2020 10:23:31 -0500 Subject: [PATCH 12/91] Trying to get protomnatter submodule in sync --- lib/protomatter | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/protomatter b/lib/protomatter index 2408e9c033..761d6437e8 160000 --- a/lib/protomatter +++ b/lib/protomatter @@ -1 +1 @@ -Subproject commit 2408e9c033f5ec050967b1592b29a950a831d6c2 +Subproject commit 761d6437e8cd6a131d51de96974337121a9c7164 From 333a10deda918129138144390646952a15aa053d Mon Sep 17 00:00:00 2001 From: root Date: Wed, 5 Aug 2020 10:59:33 -0500 Subject: [PATCH 13/91] getting ulab in sync --- extmod/ulab | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/extmod/ulab b/extmod/ulab index 4a771347bb..11a7ecff6d 160000 --- a/extmod/ulab +++ b/extmod/ulab @@ -1 +1 @@ -Subproject commit 4a771347bb49ec0335feb567465a690ef1ba8e5a +Subproject commit 11a7ecff6d76a02644ff23a734b792afaa615e44 From 6eae7ce78f8dd2c1968e54e98cfe1189c4d35062 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 20 Aug 2020 16:57:00 -0500 Subject: [PATCH 14/91] Requested changes to pulsein --- ports/atmel-samd/common-hal/pulseio/PulseIn.c | 21 +++++++++---------- supervisor/shared/background_callback.c | 2 +- 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c index 79f66ceaee..772948828a 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c @@ -91,9 +91,6 @@ void pulsein_interrupt_handler(uint8_t channel) { uint32_t current_count = tc->COUNT16.COUNT.reg; pulseio_pulsein_obj_t* self = get_eic_channel_data(channel); - if (self->len == 0) { - update_background_ticks(); - } if (self->first_edge) { self->first_edge = false; pulsein_set_config(self, false); @@ -115,17 +112,14 @@ void pulsein_interrupt_handler(uint8_t channel) { } uint16_t i = (self->start + self->len) % self->maxlen; - self->buffer[i] = duration; - if (self->len < self->maxlen) { + if (self->len <= self->maxlen) { self->len++; } else { - self->start++; + self->errored_too_fast = true; + common_hal_mcu_enable_interrupts(); + return; } - } - if (!supervisor_background_tasks_ok() ) { - common_hal_mcu_enable_interrupts(); - mp_raise_RuntimeError(translate("Input taking too long")); - return; + self->buffer[i] = duration; } self->last_overflow = current_overflow; self->last_count = current_count; @@ -161,6 +155,7 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, self->start = 0; self->len = 0; self->first_edge = true; + self->errored_too_fast = false; if (refcount == 0) { // Find a spare timer. @@ -303,6 +298,10 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { if (self->len == 0) { mp_raise_IndexError(translate("pop from an empty PulseIn")); } + if (self->errored_too_fast) { + self->errored_too_fast = false; + mp_raise_RuntimeError(translate("Input taking too long")); + } common_hal_mcu_disable_interrupts(); uint16_t value = self->buffer[self->start]; self->start = (self->start + 1) % self->maxlen; diff --git a/supervisor/shared/background_callback.c b/supervisor/shared/background_callback.c index af64f99aa6..fb46343ab1 100644 --- a/supervisor/shared/background_callback.c +++ b/supervisor/shared/background_callback.c @@ -48,6 +48,7 @@ void update_background_ticks(void) { } void background_callback_add_core(background_callback_t *cb) { + last_background_tick = port_get_raw_ticks(NULL); CALLBACK_CRITICAL_BEGIN; if (cb->prev || callback_head == cb) { CALLBACK_CRITICAL_END; @@ -77,7 +78,6 @@ void background_callback_run_all() { if (!callback_head) { return; } - last_background_tick = port_get_raw_ticks(NULL); CALLBACK_CRITICAL_BEGIN; if (in_background_callback) { CALLBACK_CRITICAL_END; From 7e7f3b41b5acfe856af45c94ee01183dd453c3c7 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 20 Aug 2020 17:13:04 -0500 Subject: [PATCH 15/91] Updated locale/circuitpython.pot --- locale/circuitpython.pot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 8c88ca5be2..99b39e7281 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-08-01 13:45-0500\n" +"POT-Creation-Date: 2020-08-20 17:12-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" From 5b228a77e6a35a6ec08596d3bac1935cc7fb97ce Mon Sep 17 00:00:00 2001 From: root Date: Thu, 20 Aug 2020 17:19:25 -0500 Subject: [PATCH 16/91] Fixing date in locale/circuitpython.pot to avoid merge conflict --- locale/circuitpython.pot | 252 +++++++++++++++++---------------------- 1 file changed, 107 insertions(+), 145 deletions(-) diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 99b39e7281..0bf0cff1cf 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-08-20 17:12-0500\n" +"POT-Creation-Date: 2020-08-18 11:19-0400\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -66,12 +66,16 @@ msgstr "" msgid "%q in use" msgstr "" -#: py/obj.c +#: extmod/moductypes.c ports/atmel-samd/common-hal/pulseio/PulseIn.c +#: ports/cxd56/common-hal/pulseio/PulseIn.c +#: ports/nrf/common-hal/pulseio/PulseIn.c +#: ports/stm/common-hal/pulseio/PulseIn.c py/obj.c py/objstr.c +#: py/objstrunicode.c msgid "%q index out of range" msgstr "" #: py/obj.c -msgid "%q indices must be integers, not %s" +msgid "%q indices must be integers, not %q" msgstr "" #: shared-bindings/vectorio/Polygon.c @@ -110,6 +114,42 @@ msgstr "" msgid "'%q' argument required" msgstr "" +#: py/runtime.c +msgid "'%q' object cannot assign attribute '%q'" +msgstr "" + +#: py/proto.c +msgid "'%q' object does not support '%q'" +msgstr "" + +#: py/obj.c +msgid "'%q' object does not support item assignment" +msgstr "" + +#: py/obj.c +msgid "'%q' object does not support item deletion" +msgstr "" + +#: py/runtime.c +msgid "'%q' object has no attribute '%q'" +msgstr "" + +#: py/runtime.c +msgid "'%q' object is not an iterator" +msgstr "" + +#: py/objtype.c py/runtime.c +msgid "'%q' object is not callable" +msgstr "" + +#: py/runtime.c +msgid "'%q' object is not iterable" +msgstr "" + +#: py/obj.c +msgid "'%q' object is not subscriptable" +msgstr "" + #: py/emitinlinethumb.c py/emitinlinextensa.c #, c-format msgid "'%s' expects a label" @@ -160,48 +200,6 @@ msgstr "" msgid "'%s' integer 0x%x does not fit in mask 0x%x" msgstr "" -#: py/runtime.c -msgid "'%s' object cannot assign attribute '%q'" -msgstr "" - -#: py/proto.c -msgid "'%s' object does not support '%q'" -msgstr "" - -#: py/obj.c -#, c-format -msgid "'%s' object does not support item assignment" -msgstr "" - -#: py/obj.c -#, c-format -msgid "'%s' object does not support item deletion" -msgstr "" - -#: py/runtime.c -msgid "'%s' object has no attribute '%q'" -msgstr "" - -#: py/runtime.c -#, c-format -msgid "'%s' object is not an iterator" -msgstr "" - -#: py/objtype.c py/runtime.c -#, c-format -msgid "'%s' object is not callable" -msgstr "" - -#: py/runtime.c -#, c-format -msgid "'%s' object is not iterable" -msgstr "" - -#: py/obj.c -#, c-format -msgid "'%s' object is not subscriptable" -msgstr "" - #: py/objstr.c msgid "'=' alignment not allowed in string format specifier" msgstr "" @@ -449,6 +447,10 @@ msgstr "" msgid "Buffer length must be a multiple of 512" msgstr "" +#: ports/stm/common-hal/sdioio/SDCard.c +msgid "Buffer must be a multiple of 512 bytes" +msgstr "" + #: shared-bindings/bitbangio/I2C.c shared-bindings/busio/I2C.c msgid "Buffer must be at least length 1" msgstr "" @@ -639,6 +641,10 @@ msgstr "" msgid "Could not restart PWM" msgstr "" +#: shared-bindings/_bleio/Adapter.c +msgid "Could not set address" +msgstr "" + #: ports/stm/common-hal/pulseio/PWMOut.c msgid "Could not start PWM" msgstr "" @@ -738,7 +744,7 @@ msgstr "" #: shared-bindings/aesio/aes.c shared-bindings/busio/SPI.c #: shared-bindings/microcontroller/Pin.c -#: shared-bindings/neopixel_write/__init__.c shared-bindings/pulseio/PulseOut.c +#: shared-bindings/neopixel_write/__init__.c #: shared-bindings/terminalio/Terminal.c msgid "Expected a %q" msgstr "" @@ -821,6 +827,11 @@ msgstr "" msgid "File exists" msgstr "" +#: shared-module/framebufferio/FramebufferDisplay.c +#, c-format +msgid "Framebuffer requires %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c msgid "Frequency captured is above capability. Capture Paused." msgstr "" @@ -845,7 +856,7 @@ msgid "Group full" msgstr "" #: ports/mimxrt10xx/common-hal/busio/SPI.c ports/stm/common-hal/busio/I2C.c -#: ports/stm/common-hal/busio/SPI.c +#: ports/stm/common-hal/busio/SPI.c ports/stm/common-hal/sdioio/SDCard.c msgid "Hardware busy, try alternative pins" msgstr "" @@ -914,6 +925,11 @@ msgstr "" msgid "Invalid %q pin" msgstr "" +#: ports/stm/common-hal/busio/I2C.c ports/stm/common-hal/busio/SPI.c +#: ports/stm/common-hal/busio/UART.c ports/stm/common-hal/sdioio/SDCard.c +msgid "Invalid %q pin selection" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogIn.c msgid "Invalid ADC Unit value" msgstr "" @@ -926,24 +942,12 @@ msgstr "" msgid "Invalid DAC pin supplied" msgstr "" -#: ports/stm/common-hal/busio/I2C.c -msgid "Invalid I2C pin selection" -msgstr "" - #: ports/atmel-samd/common-hal/pulseio/PWMOut.c #: ports/cxd56/common-hal/pulseio/PWMOut.c #: ports/nrf/common-hal/pulseio/PWMOut.c shared-bindings/pulseio/PWMOut.c msgid "Invalid PWM frequency" msgstr "" -#: ports/stm/common-hal/busio/SPI.c -msgid "Invalid SPI pin selection" -msgstr "" - -#: ports/stm/common-hal/busio/UART.c -msgid "Invalid UART pin selection" -msgstr "" - #: py/moduerrno.c shared-module/rgbmatrix/RGBMatrix.c msgid "Invalid argument" msgstr "" @@ -1239,6 +1243,10 @@ msgstr "" msgid "Not playing" msgstr "" +#: main.c +msgid "Not running saved code.\n" +msgstr "" + #: shared-bindings/util.c msgid "" "Object has been deinitialized and can no longer be used. Create a new object." @@ -1324,8 +1332,13 @@ msgstr "" msgid "Polygon needs at least 3 points" msgstr "" -#: shared-bindings/ps2io/Ps2.c -msgid "Pop from an empty Ps2 buffer" +#: ports/atmel-samd/common-hal/pulseio/PulseOut.c +#: ports/cxd56/common-hal/pulseio/PulseOut.c +#: ports/nrf/common-hal/pulseio/PulseOut.c +#: ports/stm/common-hal/pulseio/PulseOut.c +msgid "" +"Port does not accept pins or frequency. " +"Construct and pass a PWMOut Carrier instead" msgstr "" #: shared-bindings/_bleio/Adapter.c @@ -1340,6 +1353,10 @@ msgstr "" msgid "Pull not used when direction is output." msgstr "" +#: ports/stm/ref/pulseout-pre-timeralloc.c +msgid "PulseOut not supported on this chip" +msgstr "" + #: ports/stm/common-hal/os/__init__.c msgid "RNG DeInit Error" msgstr "" @@ -1400,11 +1417,7 @@ msgid "Row entry must be digitalio.DigitalInOut" msgstr "" #: main.c -msgid "Running in safe mode! Auto-reload is off.\n" -msgstr "" - -#: main.c -msgid "Running in safe mode! Not running saved code.\n" +msgid "Running in safe mode! " msgstr "" #: shared-module/sdcardio/SDCard.c @@ -1416,6 +1429,16 @@ msgstr "" msgid "SDA or SCL needs a pull up" msgstr "" +#: ports/stm/common-hal/sdioio/SDCard.c +#, c-format +msgid "SDIO GetCardInfo Error %d" +msgstr "" + +#: ports/stm/common-hal/sdioio/SDCard.c +#, c-format +msgid "SDIO Init Error %d" +msgstr "" + #: ports/stm/common-hal/busio/SPI.c msgid "SPI Init Error" msgstr "" @@ -1765,8 +1788,7 @@ msgid "__init__() should return None" msgstr "" #: py/objtype.c -#, c-format -msgid "__init__() should return None, not '%s'" +msgid "__init__() should return None, not '%q'" msgstr "" #: py/objobject.c @@ -1920,7 +1942,7 @@ msgstr "" msgid "bytes value out of range" msgstr "" -#: ports/atmel-samd/bindings/samd/Clock.c +#: ports/atmel-samd/bindings/samd/Clock.c ports/atmel-samd/common-hal/rtc/RTC.c msgid "calibration is out of range" msgstr "" @@ -1952,47 +1974,17 @@ msgstr "" msgid "can't assign to expression" msgstr "" -#: py/obj.c -#, c-format -msgid "can't convert %s to complex" -msgstr "" - -#: py/obj.c -#, c-format -msgid "can't convert %s to float" -msgstr "" - -#: py/obj.c -#, c-format -msgid "can't convert %s to int" +#: py/obj.c py/objint.c shared-bindings/i2cperipheral/I2CPeripheral.c +#: shared-module/_pixelbuf/PixelBuf.c +msgid "can't convert %q to %q" msgstr "" #: py/objstr.c msgid "can't convert '%q' object to %q implicitly" msgstr "" -#: py/objint.c -msgid "can't convert NaN to int" -msgstr "" - -#: shared-bindings/i2cperipheral/I2CPeripheral.c -msgid "can't convert address to int" -msgstr "" - -#: py/objint.c -msgid "can't convert inf to int" -msgstr "" - #: py/obj.c -msgid "can't convert to complex" -msgstr "" - -#: py/obj.c -msgid "can't convert to float" -msgstr "" - -#: py/obj.c -msgid "can't convert to int" +msgid "can't convert to %q" msgstr "" #: py/objstr.c @@ -2400,7 +2392,7 @@ msgstr "" msgid "function missing required positional argument #%d" msgstr "" -#: py/argcheck.c py/bc.c py/objnamedtuple.c +#: py/argcheck.c py/bc.c py/objnamedtuple.c shared-bindings/time/__init__.c #, c-format msgid "function takes %d positional arguments but %d were given" msgstr "" @@ -2449,10 +2441,7 @@ msgstr "" msgid "index is out of bounds" msgstr "" -#: ports/atmel-samd/common-hal/pulseio/PulseIn.c -#: ports/cxd56/common-hal/pulseio/PulseIn.c -#: ports/nrf/common-hal/pulseio/PulseIn.c -#: ports/stm/common-hal/pulseio/PulseIn.c py/obj.c +#: py/obj.c msgid "index out of range" msgstr "" @@ -2808,8 +2797,7 @@ msgid "number of points must be at least 2" msgstr "" #: py/obj.c -#, c-format -msgid "object '%s' is not a tuple or list" +msgid "object '%q' is not a tuple or list" msgstr "" #: py/obj.c @@ -2845,8 +2833,7 @@ msgid "object not iterable" msgstr "" #: py/obj.c -#, c-format -msgid "object of type '%s' has no len()" +msgid "object of type '%q' has no len()" msgstr "" #: py/obj.c @@ -2939,20 +2926,9 @@ msgstr "" #: ports/atmel-samd/common-hal/pulseio/PulseIn.c #: ports/cxd56/common-hal/pulseio/PulseIn.c #: ports/nrf/common-hal/pulseio/PulseIn.c -#: ports/stm/common-hal/pulseio/PulseIn.c -msgid "pop from an empty PulseIn" -msgstr "" - -#: py/objset.c -msgid "pop from an empty set" -msgstr "" - -#: py/objlist.c -msgid "pop from empty list" -msgstr "" - -#: py/objdict.c -msgid "popitem(): dictionary is empty" +#: ports/stm/common-hal/pulseio/PulseIn.c py/objdict.c py/objlist.c py/objset.c +#: shared-bindings/ps2io/Ps2.c +msgid "pop from empty %q" msgstr "" #: py/objint_mpz.c @@ -3109,12 +3085,7 @@ msgid "stream operation not supported" msgstr "" #: py/objstrunicode.c -msgid "string index out of range" -msgstr "" - -#: py/objstrunicode.c -#, c-format -msgid "string indices must be integers, not %s" +msgid "string indices must be integers, not %q" msgstr "" #: py/stream.c @@ -3125,10 +3096,6 @@ msgstr "" msgid "struct: cannot index" msgstr "" -#: extmod/moductypes.c -msgid "struct: index out of range" -msgstr "" - #: extmod/moductypes.c msgid "struct: no fields" msgstr "" @@ -3198,7 +3165,7 @@ msgstr "" msgid "trapz is defined for 1D arrays of equal length" msgstr "" -#: extmod/ulab/code/linalg/linalg.c py/objstr.c +#: extmod/ulab/code/linalg/linalg.c msgid "tuple index out of range" msgstr "" @@ -3206,10 +3173,6 @@ msgstr "" msgid "tuple/list has wrong length" msgstr "" -#: shared-bindings/_pixelbuf/PixelBuf.c -msgid "tuple/list required on RHS" -msgstr "" - #: ports/atmel-samd/common-hal/busio/UART.c ports/nrf/common-hal/busio/UART.c #: shared-bindings/busio/UART.c msgid "tx and rx cannot both be None" @@ -3265,8 +3228,7 @@ msgid "unknown conversion specifier %c" msgstr "" #: py/objstr.c -#, c-format -msgid "unknown format code '%c' for object of type '%s'" +msgid "unknown format code '%c' for object of type '%q'" msgstr "" #: py/compile.c @@ -3306,7 +3268,7 @@ msgid "unsupported format character '%c' (0x%x) at index %d" msgstr "" #: py/runtime.c -msgid "unsupported type for %q: '%s'" +msgid "unsupported type for %q: '%q'" msgstr "" #: py/runtime.c @@ -3314,7 +3276,7 @@ msgid "unsupported type for operator" msgstr "" #: py/runtime.c -msgid "unsupported types for %q: '%s', '%s'" +msgid "unsupported types for %q: '%q', '%q'" msgstr "" #: py/objint.c From fe0f79adce95dbe88c4826b26f163c573aa8f9c2 Mon Sep 17 00:00:00 2001 From: root Date: Fri, 21 Aug 2020 20:38:19 -0500 Subject: [PATCH 17/91] Making requested modifications --- ports/atmel-samd/common-hal/pulseio/PulseIn.c | 4 ++-- ports/atmel-samd/common-hal/pulseio/PulseIn.h | 1 - supervisor/shared/background_callback.c | 4 ---- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c index 772948828a..27bf842d56 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c @@ -112,7 +112,7 @@ void pulsein_interrupt_handler(uint8_t channel) { } uint16_t i = (self->start + self->len) % self->maxlen; - if (self->len <= self->maxlen) { + if (self->len < self->maxlen) { self->len++; } else { self->errored_too_fast = true; @@ -278,6 +278,7 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, self->first_edge = true; self->last_overflow = 0; self->last_count = 0; + self->errored_too_fast = false; gpio_set_pin_function(self->pin, GPIO_PIN_FUNCTION_A); uint32_t mask = 1 << self->channel; // Clear previous interrupt state and re-enable it. @@ -299,7 +300,6 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { mp_raise_IndexError(translate("pop from an empty PulseIn")); } if (self->errored_too_fast) { - self->errored_too_fast = false; mp_raise_RuntimeError(translate("Input taking too long")); } common_hal_mcu_disable_interrupts(); diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.h b/ports/atmel-samd/common-hal/pulseio/PulseIn.h index a0f838b373..99358178f2 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.h +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.h @@ -50,7 +50,6 @@ void pulsein_reset(void); void pulsein_interrupt_handler(uint8_t channel); void pulsein_timer_interrupt_handler(uint8_t index); -void update_background_ticks(void); #ifdef SAMD21 void rtc_set_continuous(void); void rtc_start_pulsein(void); diff --git a/supervisor/shared/background_callback.c b/supervisor/shared/background_callback.c index fb46343ab1..154618297e 100644 --- a/supervisor/shared/background_callback.c +++ b/supervisor/shared/background_callback.c @@ -43,10 +43,6 @@ uint64_t get_background_ticks(void) { return last_background_tick; } -void update_background_ticks(void) { - last_background_tick = port_get_raw_ticks(NULL); -} - void background_callback_add_core(background_callback_t *cb) { last_background_tick = port_get_raw_ticks(NULL); CALLBACK_CRITICAL_BEGIN; From 4733a672265f97a83353d005160f8e24ed8755b8 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 2 Sep 2020 11:27:42 -0400 Subject: [PATCH 18/91] Add GDB debugging capability --- ports/esp32s2/Makefile | 2 +- ports/esp32s2/boards/esp32s2-saola-1.cfg | 41 ++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 ports/esp32s2/boards/esp32s2-saola-1.cfg diff --git a/ports/esp32s2/Makefile b/ports/esp32s2/Makefile index 19b89a13a1..db05349b6c 100644 --- a/ports/esp32s2/Makefile +++ b/ports/esp32s2/Makefile @@ -116,7 +116,7 @@ CFLAGS += $(OPTIMIZATION_FLAGS) CFLAGS += $(INC) -Werror -Wall -mlongcalls -std=gnu11 -Wl,--gc-sections $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) -LDFLAGS = $(CFLAGS) -Wl,-nostdlib -Wl,-Map=$@.map -Wl,-cref +LDFLAGS = $(CFLAGS) -Wl,-nostdlib -Wl,-Map=$@.map -Wl,-cref -Wl,--undefined=uxTopUsedPriority LDFLAGS += -L$(BUILD)/esp-idf/esp-idf/esp32s2 \ -Tesp32s2_out.ld \ -L$(BUILD)/esp-idf/esp-idf/esp32s2/ld \ diff --git a/ports/esp32s2/boards/esp32s2-saola-1.cfg b/ports/esp32s2/boards/esp32s2-saola-1.cfg new file mode 100644 index 0000000000..6772907570 --- /dev/null +++ b/ports/esp32s2/boards/esp32s2-saola-1.cfg @@ -0,0 +1,41 @@ +# The ESP32-S2 only supports JTAG. +transport select jtag +adapter_khz 1000 + +# Source the ESP common configuration file +source [find target/esp_common.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME esp32s2 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x120034e5 +} + +set _TARGETNAME $_CHIPNAME +set _CPUNAME cpu +set _TAPNAME $_CHIPNAME.$_CPUNAME + +jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID + +if { $_RTOS == "none" } { + target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME +} else { + target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME -rtos $_RTOS +} + +configure_esp_workarea $_TARGETNAME 0x40030000 0x3400 0x3FFE0000 0x6000 +configure_esp_flash_bank $_TARGETNAME $_TARGETNAME $_FLASH_SIZE + +xtensa maskisr on +if { $_SEMIHOST_BASEDIR != "" } { + esp semihost_basedir $_SEMIHOST_BASEDIR +} +if { $_FLASH_SIZE == 0 } { + gdb_breakpoint_override hard +} From e066448e369d33f655b4454562a9711e1cbdb2ff Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Tue, 8 Sep 2020 10:43:24 -0500 Subject: [PATCH 19/91] atmel-samd: add same51, feather_m4_can This is compile-tested, and requires updates in the related submodules: https://github.com/adafruit/samd-peripherals/pull/35 https://github.com/adafruit/asf4/pull/37 This should not be merged until those can also be merged. --- ports/atmel-samd/Makefile | 30 +- ports/atmel-samd/asf4 | 2 +- .../asf4_conf/same51/hpl_adc_config.h | 303 + .../asf4_conf/same51/hpl_dac_config.h | 169 + .../asf4_conf/same51/hpl_dmac_config.h | 7277 +++++++++++++++++ .../asf4_conf/same51/hpl_gclk_config.h | 924 +++ .../asf4_conf/same51/hpl_mclk_config.h | 104 + .../asf4_conf/same51/hpl_nvmctrl_config.h | 36 + .../asf4_conf/same51/hpl_osc32kctrl_config.h | 163 + .../asf4_conf/same51/hpl_oscctrl_config.h | 634 ++ .../asf4_conf/same51/hpl_rtc_config.h | 145 + .../asf4_conf/same51/hpl_sdhc_config.h | 24 + .../asf4_conf/same51/hpl_sercom_config.h | 751 ++ .../asf4_conf/same51/hpl_systick_config.h | 18 + .../asf4_conf/same51/hpl_tc_config.h | 209 + .../asf4_conf/same51/hpl_trng_config.h | 27 + .../asf4_conf/same51/hpl_usb_config.h | 413 + .../asf4_conf/same51/peripheral_clk_config.h | 1170 +++ .../atmel-samd/asf4_conf/same51/usbd_config.h | 850 ++ .../atmel-samd/boards/feather_m4_can/board.c | 38 + .../boards/feather_m4_can/mpconfigboard.h | 35 + .../boards/feather_m4_can/mpconfigboard.mk | 14 + ports/atmel-samd/boards/feather_m4_can/pins.c | 61 + .../common-hal/neopixel_write/__init__.c | 3 + ports/atmel-samd/peripherals | 2 +- ports/atmel-samd/supervisor/internal_flash.c | 3 + ports/atmel-samd/supervisor/port.c | 3 + ports/atmel-samd/supervisor/same51_cpu.s | 27 + 28 files changed, 13432 insertions(+), 3 deletions(-) create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_adc_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_dac_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_dmac_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_mclk_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_nvmctrl_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_osc32kctrl_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_rtc_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_sdhc_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_systick_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_trng_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/hpl_usb_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h create mode 100644 ports/atmel-samd/asf4_conf/same51/usbd_config.h create mode 100644 ports/atmel-samd/boards/feather_m4_can/board.c create mode 100644 ports/atmel-samd/boards/feather_m4_can/mpconfigboard.h create mode 100644 ports/atmel-samd/boards/feather_m4_can/mpconfigboard.mk create mode 100644 ports/atmel-samd/boards/feather_m4_can/pins.c create mode 100755 ports/atmel-samd/supervisor/same51_cpu.s diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile index 489f3a7afb..79573b62ef 100644 --- a/ports/atmel-samd/Makefile +++ b/ports/atmel-samd/Makefile @@ -99,6 +99,13 @@ OPTIMIZATION_FLAGS ?= -O2 CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD51 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024 endif +ifeq ($(CHIP_FAMILY), same51) +PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x +OPTIMIZATION_FLAGS ?= -O2 +# TinyUSB defines +CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAME5X -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024 +endif + ifeq ($(CHIP_FAMILY), same54) PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x OPTIMIZATION_FLAGS ?= -O2 @@ -177,6 +184,15 @@ CFLAGS += \ -mfpu=fpv4-sp-d16 \ -DSAM_D5X_E5X -DSAME54 endif +ifeq ($(CHIP_FAMILY), same51) +CFLAGS += \ + -mthumb \ + -mabi=aapcs-linux \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -DSAM_D5X_E5X -DSAME51 +endif @@ -197,6 +213,9 @@ BOOTLOADER_SIZE := 0x4000 else ifeq ($(CHIP_FAMILY), same54) LDFLAGS += -mthumb -mcpu=cortex-m4 BOOTLOADER_SIZE := 0x4000 +else ifeq ($(CHIP_FAMILY), same51) +LDFLAGS += -mthumb -mcpu=cortex-m4 +BOOTLOADER_SIZE := 0x4000 endif SRC_ASF := \ @@ -241,7 +260,16 @@ SRC_ASF += \ else ifeq ($(CHIP_FAMILY), same54) SRC_ASF += \ - hal/src/hal_rand_sync.c \ + hal/src/hal_rand_sync.c \ + hpl/core/hpl_core_m4.c \ + hpl/mclk/hpl_mclk.c \ + hpl/osc32kctrl/hpl_osc32kctrl.c \ + hpl/oscctrl/hpl_oscctrl.c \ + hpl/trng/hpl_trng.c \ + +else ifeq ($(CHIP_FAMILY), same51) +SRC_ASF += \ + hal/src/hal_rand_sync.c \ hpl/core/hpl_core_m4.c \ hpl/mclk/hpl_mclk.c \ hpl/osc32kctrl/hpl_osc32kctrl.c \ diff --git a/ports/atmel-samd/asf4 b/ports/atmel-samd/asf4 index 35a1525796..f99e36fb00 160000 --- a/ports/atmel-samd/asf4 +++ b/ports/atmel-samd/asf4 @@ -1 +1 @@ -Subproject commit 35a1525796c7ef8a3893d90befdad2f267fca20e +Subproject commit f99e36fb008588bd9ff005099b3b89b7952fcfba diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_adc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_adc_config.h new file mode 100644 index 0000000000..13d8151028 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_adc_config.h @@ -0,0 +1,303 @@ +/* Auto-generated config file hpl_adc_config.h */ +#ifndef HPL_ADC_CONFIG_H +#define HPL_ADC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_ADC_0_ENABLE +#define CONF_ADC_0_ENABLE 1 +#endif + +// Basic Configuration + +// Conversion Result Resolution +// <0x0=>12-bit +// <0x1=>16-bit (averaging must be enabled) +// <0x2=>10-bit +// <0x3=>8-bit +// Defines the bit resolution for the ADC sample values (RESSEL) +// adc_resolution +#ifndef CONF_ADC_0_RESSEL +#define CONF_ADC_0_RESSEL 0x0 +#endif + +// Reference Selection +// <0x0=>Internal bandgap reference +// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V) +// <0x3=>VDDANA +// <0x4=>External reference A +// <0x5=>External reference B +// <0x6=>External reference C +// Select the reference for the ADC (REFSEL) +// adc_reference +#ifndef CONF_ADC_0_REFSEL +#define CONF_ADC_0_REFSEL 0x0 +#endif + +// Prescaler configuration +// <0x0=>Peripheral clock divided by 2 +// <0x1=>Peripheral clock divided by 4 +// <0x2=>Peripheral clock divided by 8 +// <0x3=>Peripheral clock divided by 16 +// <0x4=>Peripheral clock divided by 32 +// <0x5=>Peripheral clock divided by 64 +// <0x6=>Peripheral clock divided by 128 +// <0x7=>Peripheral clock divided by 256 +// These bits define the ADC clock relative to the peripheral clock (PRESCALER) +// adc_prescaler +#ifndef CONF_ADC_0_PRESCALER +#define CONF_ADC_0_PRESCALER 0x3 +#endif + +// Free Running Mode +// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN) +// adc_freerunning_mode +#ifndef CONF_ADC_0_FREERUN +#define CONF_ADC_0_FREERUN 0 +#endif + +// Differential Mode +// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE) +// adc_differential_mode +#ifndef CONF_ADC_0_DIFFMODE +#define CONF_ADC_0_DIFFMODE 0 +#endif + +// Positive Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x08=>ADC AIN8 pin +// <0x09=>ADC AIN9 pin +// <0x0A=>ADC AIN10 pin +// <0x0B=>ADC AIN11 pin +// <0x0C=>ADC AIN12 pin +// <0x0D=>ADC AIN13 pin +// <0x0E=>ADC AIN14 pin +// <0x0F=>ADC AIN15 pin +// <0x18=>1/4 scaled core supply +// <0x19=>1/4 Scaled VBAT Supply +// <0x1A=>1/4 scaled I/O supply +// <0x1B=>Bandgap voltage +// <0x1C=>Temperature reference (PTAT) +// <0x1D=>Temperature reference (CTAT) +// <0x1E=>DAC Output +// These bits define the Mux selection for the positive ADC input. (MUXPOS) +// adc_pinmux_positive +#ifndef CONF_ADC_0_MUXPOS +#define CONF_ADC_0_MUXPOS 0x0 +#endif + +// Negative Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x18=>Internal ground +// <0x19=>I/O ground +// These bits define the Mux selection for the negative ADC input. (MUXNEG) +// adc_pinmux_negative +#ifndef CONF_ADC_0_MUXNEG +#define CONF_ADC_0_MUXNEG 0x0 +#endif + +// + +// Advanced Configuration +// adc_advanced_settings +#ifndef CONF_ADC_0_ADVANCED +#define CONF_ADC_0_ADVANCED 0 +#endif + +// Run in standby +// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY) +// adc_arch_runstdby +#ifndef CONF_ADC_0_RUNSTDBY +#define CONF_ADC_0_RUNSTDBY 0 +#endif + +// Debug Run +// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN) +// adc_arch_dbgrun +#ifndef CONF_ADC_0_DBGRUN +#define CONF_ADC_0_DBGRUN 0 +#endif + +// On Demand Control +// Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND) +// adc_arch_ondemand +#ifndef CONF_ADC_0_ONDEMAND +#define CONF_ADC_0_ONDEMAND 0 +#endif + +// Left-Adjusted Result +// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ) +// adc_arch_leftadj +#ifndef CONF_ADC_0_LEFTADJ +#define CONF_ADC_0_LEFTADJ 0 +#endif + +// Reference Buffer Offset Compensation Enable +// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP) +// adc_arch_refcomp +#ifndef CONF_ADC_0_REFCOMP +#define CONF_ADC_0_REFCOMP 0 +#endif + +// Comparator Offset Compensation Enable +// This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP) +// adc_arch_offcomp +#ifndef CONF_ADC_0_OFFCOMP +#define CONF_ADC_0_OFFCOMP 0 +#endif + +// Digital Correction Logic Enabled +// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN) +// adc_arch_corren +#ifndef CONF_ADC_0_CORREN +#define CONF_ADC_0_CORREN 0 +#endif + +// Offset Correction Value <0-4095> +// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR) +// adc_arch_offsetcorr +#ifndef CONF_ADC_0_OFFSETCORR +#define CONF_ADC_0_OFFSETCORR 0 +#endif + +// Gain Correction Value <0-4095> +// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR) +// adc_arch_gaincorr +#ifndef CONF_ADC_0_GAINCORR +#define CONF_ADC_0_GAINCORR 0 +#endif + +// Adjusting Result / Division Coefficient <0-7> +// These bits define the division coefficient in 2n steps. (ADJRES) +// adc_arch_adjres +#ifndef CONF_ADC_0_ADJRES +#define CONF_ADC_0_ADJRES 0x0 +#endif + +// Number of Samples to be Collected +// <0x0=>1 sample +// <0x1=>2 samples +// <0x2=>4 samples +// <0x3=>8 samples +// <0x4=>16 samples +// <0x5=>32 samples +// <0x6=>64 samples +// <0x7=>128 samples +// <0x8=>256 samples +// <0x9=>512 samples +// <0xA=>1024 samples +// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM) +// adc_arch_samplenum +#ifndef CONF_ADC_0_SAMPLENUM +#define CONF_ADC_0_SAMPLENUM 0x0 +#endif + +// Sampling Time Length <0-63> +// These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) +// adc_arch_samplen +#ifndef CONF_ADC_0_SAMPLEN +#define CONF_ADC_0_SAMPLEN 0 +#endif + +// Window Monitor Mode +// <0x0=>No window mode +// <0x1=>Mode 1: RESULT above lower threshold +// <0x2=>Mode 2: RESULT beneath upper threshold +// <0x3=>Mode 3: RESULT inside lower and upper threshold +// <0x4=>Mode 4: RESULT outside lower and upper threshold +// These bits enable and define the window monitor mode. (WINMODE) +// adc_arch_winmode +#ifndef CONF_ADC_0_WINMODE +#define CONF_ADC_0_WINMODE 0x0 +#endif + +// Window Monitor Lower Threshold <0-65535> +// If the window monitor is enabled, these bits define the lower threshold value. (WINLT) +// adc_arch_winlt +#ifndef CONF_ADC_0_WINLT +#define CONF_ADC_0_WINLT 0 +#endif + +// Window Monitor Upper Threshold <0-65535> +// If the window monitor is enabled, these bits define the lower threshold value. (WINUT) +// adc_arch_winut +#ifndef CONF_ADC_0_WINUT +#define CONF_ADC_0_WINUT 0 +#endif + +// Bitmask for positive input sequence <0-4294967295> +// Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device). +// adc_arch_seqen +#ifndef CONF_ADC_0_SEQEN +#define CONF_ADC_0_SEQEN 0x0 +#endif + +// + +// Event Control +// adc_arch_event_settings +#ifndef CONF_ADC_0_EVENT_CONTROL +#define CONF_ADC_0_EVENT_CONTROL 0 +#endif + +// Window Monitor Event Out +// Enables event output on window event (WINMONEO) +// adc_arch_winmoneo +#ifndef CONF_ADC_0_WINMONEO +#define CONF_ADC_0_WINMONEO 0 +#endif + +// Result Ready Event Out +// Enables event output on result ready event (RESRDEO) +// adc_arch_resrdyeo +#ifndef CONF_ADC_0_RESRDYEO +#define CONF_ADC_0_RESRDYEO 0 +#endif + +// Invert flush Event Signal +// Invert the flush event input signal (FLUSHINV) +// adc_arch_flushinv +#ifndef CONF_ADC_0_FLUSHINV +#define CONF_ADC_0_FLUSHINV 0 +#endif + +// Trigger Flush On Event +// Trigger an ADC pipeline flush on event (FLUSHEI) +// adc_arch_flushei +#ifndef CONF_ADC_0_FLUSHEI +#define CONF_ADC_0_FLUSHEI 0 +#endif + +// Invert Start Conversion Event Signal +// Invert the start conversion event input signal (STARTINV) +// adc_arch_startinv +#ifndef CONF_ADC_0_STARTINV +#define CONF_ADC_0_STARTINV 0 +#endif + +// Trigger Conversion On Event +// Trigger a conversion on event. (STARTEI) +// adc_arch_startei +#ifndef CONF_ADC_0_STARTEI +#define CONF_ADC_0_STARTEI 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_ADC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_dac_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_dac_config.h new file mode 100644 index 0000000000..c46f99b7db --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_dac_config.h @@ -0,0 +1,169 @@ +/* Auto-generated config file hpl_dac_config.h */ +#ifndef HPL_DAC_CONFIG_H +#define HPL_DAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic configuration +// Reference Selection +// <0x00=> Unbuffered external voltage reference +// <0x01=> Voltage supply +// <0x02=> Buffered external voltage reference +// <0x03=> Internal bandgap reference +// dac_arch_refsel +#ifndef CONF_DAC_REFSEL +#define CONF_DAC_REFSEL 0 +#endif + +// Differential mode +// Indicates whether the differential mode is enabled or not +// dac_arch_diff +#ifndef CONF_DAC_DIFF +#define CONF_DAC_DIFF 0 +#endif +// + +// Advanced Configuration +// dac_advanced_settings +#ifndef CONF_DAC_ADVANCED_CONFIG +#define CONF_DAC_ADVANCED_CONFIG 0 +#endif + +// Debug Run +// Indicate whether running when CPU is halted +// adc_arch_dbgrun +#ifndef CONF_DAC_DBGRUN +#define CONF_DAC_DBGRUN 1 +#endif + +// Channel 0 configuration +// Left Adjusted Data +// Indicate how the data is adjusted in the Data and Data Buffer register +// dac0_arch_leftadj +#ifndef CONF_DAC0_LEFTADJ +#define CONF_DAC0_LEFTADJ 1 +#endif + +// Current control +// <0=> GCLK_DAC <= 1.2MHz (100kSPS) +// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) +// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) +// This defines the current in output buffer according to conversion rate +// dac0_arch_cctrl +#ifndef CONF_DAC0_CCTRL +#define CONF_DAC0_CCTRL 0 +#endif + +// Run in standby +// Indicates whether the DAC channel will continue running in standby sleep mode or not +// dac0_arch_runstdby +#ifndef CONF_DAC0_RUNSTDBY +#define CONF_DAC0_RUNSTDBY 0 +#endif + +// Dithering Mode +// Indicate whether dithering mode is enabled +// dac0_arch_ditrher +#ifndef CONF_DAC0_DITHER +#define CONF_DAC0_DITHER 0 +#endif + +// Refresh period <0x00-0xFF> +// This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us +// dac0_arch_refresh +#ifndef CONF_DAC0_REFRESH +#define CONF_DAC0_REFRESH 2 +#endif +// +// Channel 1 configuration +// Left Adjusted Data +// Indicate how the data is adjusted in the Data and Data Buffer register +// dac1_arch_leftadj +#ifndef CONF_DAC1_LEFTADJ +#define CONF_DAC1_LEFTADJ 1 +#endif + +// Current control +// <0=> GCLK_DAC <= 1.2MHz (100kSPS) +// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) +// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) +// This defines the current in output buffer according to conversion rate +// dac1_arch_cctrl +#ifndef CONF_DAC1_CCTRL +#define CONF_DAC1_CCTRL 0 +#endif + +// Run in standby +// Indicates whether the DAC channel will continue running in standby sleep mode or not +// dac1_arch_runstdby +#ifndef CONF_DAC1_RUNSTDBY +#define CONF_DAC1_RUNSTDBY 0 +#endif + +// Dithering Mode +// Indicate whether dithering mode is enabled +// dac1_arch_ditrher +#ifndef CONF_DAC1_DITHER +#define CONF_DAC1_DITHER 0 +#endif + +// Refresh period <0x00-0xFF> +// This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us +// dac1_arch_refresh +#ifndef CONF_DAC1_REFRESH +#define CONF_DAC1_REFRESH 2 +#endif +// + +// Event configuration +// Inversion of DAC 0 event +// <0=> Detection on rising edge pf the input event +// <1=> Detection on falling edge pf the input event +// This defines the edge detection of the input event +// dac_arch_invei0 +#ifndef CONF_DAC_INVEI0 +#define CONF_DAC_INVEI0 0 +#endif + +// Data Buffer of DAC 0 Empty Event Output +// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// dac_arch_emptyeo_0 +#ifndef CONF_DAC_EMPTYEO0 +#define CONF_DAC_EMPTYEO0 0 +#endif + +// Start Conversion Event Input DAC 0 +// Indicate whether Start input event is enabled +// dac_arch_startei_0 +#ifndef CONF_DAC_STARTEI0 +#define CONF_DAC_STARTEI0 0 +#endif +// Inversion of DAC 1 event +// <0=> Detection on rising edge pf the input event +// <1=> Detection on falling edge pf the input event +// This defines the edge detection of the input event +// dac_arch_invei1 +#ifndef CONF_DAC_INVEI1 +#define CONF_DAC_INVEI1 0 +#endif + +// Data Buffer of DAC 1 Empty Event Output +// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// dac_arch_emptyeo_1 +#ifndef CONF_DAC_EMPTYEO1 +#define CONF_DAC_EMPTYEO1 0 +#endif + +// Start Conversion Event Input DAC 1 +// Indicate whether Start input event is enabled +// dac_arch_startei_1 +#ifndef CONF_DAC_STARTEI1 +#define CONF_DAC_STARTEI1 0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_DAC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_dmac_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_dmac_config.h new file mode 100644 index 0000000000..90499fc27f --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_dmac_config.h @@ -0,0 +1,7277 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 1 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 1 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 16 is running in standby mode or not +// dmac_runstdby_16 +#ifndef CONF_DMAC_RUNSTDBY_16 +#define CONF_DMAC_RUNSTDBY_16 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_16 +#ifndef CONF_DMAC_TRIGACT_16 +#define CONF_DMAC_TRIGACT_16 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_16 +#ifndef CONF_DMAC_LVL_16 +#define CONF_DMAC_LVL_16 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_16 +#ifndef CONF_DMAC_EVOE_16 +#define CONF_DMAC_EVOE_16 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_16 +#ifndef CONF_DMAC_EVIE_16 +#define CONF_DMAC_EVIE_16 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_16 +#ifndef CONF_DMAC_EVACT_16 +#define CONF_DMAC_EVACT_16 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_16 +#ifndef CONF_DMAC_STEPSIZE_16 +#define CONF_DMAC_STEPSIZE_16 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_16 +#ifndef CONF_DMAC_STEPSEL_16 +#define CONF_DMAC_STEPSEL_16 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_16 +#ifndef CONF_DMAC_BLOCKACT_16 +#define CONF_DMAC_BLOCKACT_16 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_16 +#ifndef CONF_DMAC_EVOSEL_16 +#define CONF_DMAC_EVOSEL_16 0 +#endif +// + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 17 is running in standby mode or not +// dmac_runstdby_17 +#ifndef CONF_DMAC_RUNSTDBY_17 +#define CONF_DMAC_RUNSTDBY_17 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_17 +#ifndef CONF_DMAC_TRIGACT_17 +#define CONF_DMAC_TRIGACT_17 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_17 +#ifndef CONF_DMAC_LVL_17 +#define CONF_DMAC_LVL_17 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_17 +#ifndef CONF_DMAC_EVOE_17 +#define CONF_DMAC_EVOE_17 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_17 +#ifndef CONF_DMAC_EVIE_17 +#define CONF_DMAC_EVIE_17 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_17 +#ifndef CONF_DMAC_EVACT_17 +#define CONF_DMAC_EVACT_17 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_17 +#ifndef CONF_DMAC_STEPSIZE_17 +#define CONF_DMAC_STEPSIZE_17 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_17 +#ifndef CONF_DMAC_STEPSEL_17 +#define CONF_DMAC_STEPSEL_17 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_17 +#ifndef CONF_DMAC_BLOCKACT_17 +#define CONF_DMAC_BLOCKACT_17 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_17 +#ifndef CONF_DMAC_EVOSEL_17 +#define CONF_DMAC_EVOSEL_17 0 +#endif +// + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 18 is running in standby mode or not +// dmac_runstdby_18 +#ifndef CONF_DMAC_RUNSTDBY_18 +#define CONF_DMAC_RUNSTDBY_18 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_18 +#ifndef CONF_DMAC_TRIGACT_18 +#define CONF_DMAC_TRIGACT_18 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_18 +#ifndef CONF_DMAC_LVL_18 +#define CONF_DMAC_LVL_18 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_18 +#ifndef CONF_DMAC_EVOE_18 +#define CONF_DMAC_EVOE_18 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_18 +#ifndef CONF_DMAC_EVIE_18 +#define CONF_DMAC_EVIE_18 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_18 +#ifndef CONF_DMAC_EVACT_18 +#define CONF_DMAC_EVACT_18 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_18 +#ifndef CONF_DMAC_STEPSIZE_18 +#define CONF_DMAC_STEPSIZE_18 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_18 +#ifndef CONF_DMAC_STEPSEL_18 +#define CONF_DMAC_STEPSEL_18 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_18 +#ifndef CONF_DMAC_BLOCKACT_18 +#define CONF_DMAC_BLOCKACT_18 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_18 +#ifndef CONF_DMAC_EVOSEL_18 +#define CONF_DMAC_EVOSEL_18 0 +#endif +// + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 19 is running in standby mode or not +// dmac_runstdby_19 +#ifndef CONF_DMAC_RUNSTDBY_19 +#define CONF_DMAC_RUNSTDBY_19 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_19 +#ifndef CONF_DMAC_TRIGACT_19 +#define CONF_DMAC_TRIGACT_19 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_19 +#ifndef CONF_DMAC_LVL_19 +#define CONF_DMAC_LVL_19 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_19 +#ifndef CONF_DMAC_EVOE_19 +#define CONF_DMAC_EVOE_19 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_19 +#ifndef CONF_DMAC_EVIE_19 +#define CONF_DMAC_EVIE_19 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_19 +#ifndef CONF_DMAC_EVACT_19 +#define CONF_DMAC_EVACT_19 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_19 +#ifndef CONF_DMAC_STEPSIZE_19 +#define CONF_DMAC_STEPSIZE_19 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_19 +#ifndef CONF_DMAC_STEPSEL_19 +#define CONF_DMAC_STEPSEL_19 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_19 +#ifndef CONF_DMAC_BLOCKACT_19 +#define CONF_DMAC_BLOCKACT_19 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_19 +#ifndef CONF_DMAC_EVOSEL_19 +#define CONF_DMAC_EVOSEL_19 0 +#endif +// + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 20 is running in standby mode or not +// dmac_runstdby_20 +#ifndef CONF_DMAC_RUNSTDBY_20 +#define CONF_DMAC_RUNSTDBY_20 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_20 +#ifndef CONF_DMAC_TRIGACT_20 +#define CONF_DMAC_TRIGACT_20 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_20 +#ifndef CONF_DMAC_LVL_20 +#define CONF_DMAC_LVL_20 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_20 +#ifndef CONF_DMAC_EVOE_20 +#define CONF_DMAC_EVOE_20 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_20 +#ifndef CONF_DMAC_EVIE_20 +#define CONF_DMAC_EVIE_20 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_20 +#ifndef CONF_DMAC_EVACT_20 +#define CONF_DMAC_EVACT_20 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_20 +#ifndef CONF_DMAC_STEPSIZE_20 +#define CONF_DMAC_STEPSIZE_20 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_20 +#ifndef CONF_DMAC_STEPSEL_20 +#define CONF_DMAC_STEPSEL_20 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_20 +#ifndef CONF_DMAC_BLOCKACT_20 +#define CONF_DMAC_BLOCKACT_20 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_20 +#ifndef CONF_DMAC_EVOSEL_20 +#define CONF_DMAC_EVOSEL_20 0 +#endif +// + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 21 is running in standby mode or not +// dmac_runstdby_21 +#ifndef CONF_DMAC_RUNSTDBY_21 +#define CONF_DMAC_RUNSTDBY_21 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_21 +#ifndef CONF_DMAC_TRIGACT_21 +#define CONF_DMAC_TRIGACT_21 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_21 +#ifndef CONF_DMAC_LVL_21 +#define CONF_DMAC_LVL_21 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_21 +#ifndef CONF_DMAC_EVOE_21 +#define CONF_DMAC_EVOE_21 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_21 +#ifndef CONF_DMAC_EVIE_21 +#define CONF_DMAC_EVIE_21 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_21 +#ifndef CONF_DMAC_EVACT_21 +#define CONF_DMAC_EVACT_21 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_21 +#ifndef CONF_DMAC_STEPSIZE_21 +#define CONF_DMAC_STEPSIZE_21 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_21 +#ifndef CONF_DMAC_STEPSEL_21 +#define CONF_DMAC_STEPSEL_21 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_21 +#ifndef CONF_DMAC_BLOCKACT_21 +#define CONF_DMAC_BLOCKACT_21 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_21 +#ifndef CONF_DMAC_EVOSEL_21 +#define CONF_DMAC_EVOSEL_21 0 +#endif +// + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 22 is running in standby mode or not +// dmac_runstdby_22 +#ifndef CONF_DMAC_RUNSTDBY_22 +#define CONF_DMAC_RUNSTDBY_22 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_22 +#ifndef CONF_DMAC_TRIGACT_22 +#define CONF_DMAC_TRIGACT_22 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_22 +#ifndef CONF_DMAC_LVL_22 +#define CONF_DMAC_LVL_22 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_22 +#ifndef CONF_DMAC_EVOE_22 +#define CONF_DMAC_EVOE_22 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_22 +#ifndef CONF_DMAC_EVIE_22 +#define CONF_DMAC_EVIE_22 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_22 +#ifndef CONF_DMAC_EVACT_22 +#define CONF_DMAC_EVACT_22 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_22 +#ifndef CONF_DMAC_STEPSIZE_22 +#define CONF_DMAC_STEPSIZE_22 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_22 +#ifndef CONF_DMAC_STEPSEL_22 +#define CONF_DMAC_STEPSEL_22 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_22 +#ifndef CONF_DMAC_BLOCKACT_22 +#define CONF_DMAC_BLOCKACT_22 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_22 +#ifndef CONF_DMAC_EVOSEL_22 +#define CONF_DMAC_EVOSEL_22 0 +#endif +// + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 23 is running in standby mode or not +// dmac_runstdby_23 +#ifndef CONF_DMAC_RUNSTDBY_23 +#define CONF_DMAC_RUNSTDBY_23 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_23 +#ifndef CONF_DMAC_TRIGACT_23 +#define CONF_DMAC_TRIGACT_23 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_23 +#ifndef CONF_DMAC_LVL_23 +#define CONF_DMAC_LVL_23 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_23 +#ifndef CONF_DMAC_EVOE_23 +#define CONF_DMAC_EVOE_23 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_23 +#ifndef CONF_DMAC_EVIE_23 +#define CONF_DMAC_EVIE_23 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_23 +#ifndef CONF_DMAC_EVACT_23 +#define CONF_DMAC_EVACT_23 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_23 +#ifndef CONF_DMAC_STEPSIZE_23 +#define CONF_DMAC_STEPSIZE_23 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_23 +#ifndef CONF_DMAC_STEPSEL_23 +#define CONF_DMAC_STEPSEL_23 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_23 +#ifndef CONF_DMAC_BLOCKACT_23 +#define CONF_DMAC_BLOCKACT_23 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_23 +#ifndef CONF_DMAC_EVOSEL_23 +#define CONF_DMAC_EVOSEL_23 0 +#endif +// + +// Channel 24 settings +// dmac_channel_24_settings +#ifndef CONF_DMAC_CHANNEL_24_SETTINGS +#define CONF_DMAC_CHANNEL_24_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 24 is running in standby mode or not +// dmac_runstdby_24 +#ifndef CONF_DMAC_RUNSTDBY_24 +#define CONF_DMAC_RUNSTDBY_24 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_24 +#ifndef CONF_DMAC_TRIGACT_24 +#define CONF_DMAC_TRIGACT_24 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_24 +#ifndef CONF_DMAC_TRIGSRC_24 +#define CONF_DMAC_TRIGSRC_24 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_24 +#ifndef CONF_DMAC_LVL_24 +#define CONF_DMAC_LVL_24 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_24 +#ifndef CONF_DMAC_EVOE_24 +#define CONF_DMAC_EVOE_24 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_24 +#ifndef CONF_DMAC_EVIE_24 +#define CONF_DMAC_EVIE_24 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_24 +#ifndef CONF_DMAC_EVACT_24 +#define CONF_DMAC_EVACT_24 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_24 +#ifndef CONF_DMAC_STEPSIZE_24 +#define CONF_DMAC_STEPSIZE_24 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_24 +#ifndef CONF_DMAC_STEPSEL_24 +#define CONF_DMAC_STEPSEL_24 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_24 +#ifndef CONF_DMAC_SRCINC_24 +#define CONF_DMAC_SRCINC_24 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_24 +#ifndef CONF_DMAC_DSTINC_24 +#define CONF_DMAC_DSTINC_24 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_24 +#ifndef CONF_DMAC_BEATSIZE_24 +#define CONF_DMAC_BEATSIZE_24 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_24 +#ifndef CONF_DMAC_BLOCKACT_24 +#define CONF_DMAC_BLOCKACT_24 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_24 +#ifndef CONF_DMAC_EVOSEL_24 +#define CONF_DMAC_EVOSEL_24 0 +#endif +// + +// Channel 25 settings +// dmac_channel_25_settings +#ifndef CONF_DMAC_CHANNEL_25_SETTINGS +#define CONF_DMAC_CHANNEL_25_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 25 is running in standby mode or not +// dmac_runstdby_25 +#ifndef CONF_DMAC_RUNSTDBY_25 +#define CONF_DMAC_RUNSTDBY_25 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_25 +#ifndef CONF_DMAC_TRIGACT_25 +#define CONF_DMAC_TRIGACT_25 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_25 +#ifndef CONF_DMAC_TRIGSRC_25 +#define CONF_DMAC_TRIGSRC_25 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_25 +#ifndef CONF_DMAC_LVL_25 +#define CONF_DMAC_LVL_25 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_25 +#ifndef CONF_DMAC_EVOE_25 +#define CONF_DMAC_EVOE_25 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_25 +#ifndef CONF_DMAC_EVIE_25 +#define CONF_DMAC_EVIE_25 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_25 +#ifndef CONF_DMAC_EVACT_25 +#define CONF_DMAC_EVACT_25 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_25 +#ifndef CONF_DMAC_STEPSIZE_25 +#define CONF_DMAC_STEPSIZE_25 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_25 +#ifndef CONF_DMAC_STEPSEL_25 +#define CONF_DMAC_STEPSEL_25 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_25 +#ifndef CONF_DMAC_SRCINC_25 +#define CONF_DMAC_SRCINC_25 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_25 +#ifndef CONF_DMAC_DSTINC_25 +#define CONF_DMAC_DSTINC_25 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_25 +#ifndef CONF_DMAC_BEATSIZE_25 +#define CONF_DMAC_BEATSIZE_25 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_25 +#ifndef CONF_DMAC_BLOCKACT_25 +#define CONF_DMAC_BLOCKACT_25 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_25 +#ifndef CONF_DMAC_EVOSEL_25 +#define CONF_DMAC_EVOSEL_25 0 +#endif +// + +// Channel 26 settings +// dmac_channel_26_settings +#ifndef CONF_DMAC_CHANNEL_26_SETTINGS +#define CONF_DMAC_CHANNEL_26_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 26 is running in standby mode or not +// dmac_runstdby_26 +#ifndef CONF_DMAC_RUNSTDBY_26 +#define CONF_DMAC_RUNSTDBY_26 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_26 +#ifndef CONF_DMAC_TRIGACT_26 +#define CONF_DMAC_TRIGACT_26 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_26 +#ifndef CONF_DMAC_TRIGSRC_26 +#define CONF_DMAC_TRIGSRC_26 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_26 +#ifndef CONF_DMAC_LVL_26 +#define CONF_DMAC_LVL_26 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_26 +#ifndef CONF_DMAC_EVOE_26 +#define CONF_DMAC_EVOE_26 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_26 +#ifndef CONF_DMAC_EVIE_26 +#define CONF_DMAC_EVIE_26 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_26 +#ifndef CONF_DMAC_EVACT_26 +#define CONF_DMAC_EVACT_26 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_26 +#ifndef CONF_DMAC_STEPSIZE_26 +#define CONF_DMAC_STEPSIZE_26 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_26 +#ifndef CONF_DMAC_STEPSEL_26 +#define CONF_DMAC_STEPSEL_26 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_26 +#ifndef CONF_DMAC_SRCINC_26 +#define CONF_DMAC_SRCINC_26 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_26 +#ifndef CONF_DMAC_DSTINC_26 +#define CONF_DMAC_DSTINC_26 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_26 +#ifndef CONF_DMAC_BEATSIZE_26 +#define CONF_DMAC_BEATSIZE_26 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_26 +#ifndef CONF_DMAC_BLOCKACT_26 +#define CONF_DMAC_BLOCKACT_26 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_26 +#ifndef CONF_DMAC_EVOSEL_26 +#define CONF_DMAC_EVOSEL_26 0 +#endif +// + +// Channel 27 settings +// dmac_channel_27_settings +#ifndef CONF_DMAC_CHANNEL_27_SETTINGS +#define CONF_DMAC_CHANNEL_27_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 27 is running in standby mode or not +// dmac_runstdby_27 +#ifndef CONF_DMAC_RUNSTDBY_27 +#define CONF_DMAC_RUNSTDBY_27 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_27 +#ifndef CONF_DMAC_TRIGACT_27 +#define CONF_DMAC_TRIGACT_27 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_27 +#ifndef CONF_DMAC_TRIGSRC_27 +#define CONF_DMAC_TRIGSRC_27 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_27 +#ifndef CONF_DMAC_LVL_27 +#define CONF_DMAC_LVL_27 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_27 +#ifndef CONF_DMAC_EVOE_27 +#define CONF_DMAC_EVOE_27 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_27 +#ifndef CONF_DMAC_EVIE_27 +#define CONF_DMAC_EVIE_27 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_27 +#ifndef CONF_DMAC_EVACT_27 +#define CONF_DMAC_EVACT_27 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_27 +#ifndef CONF_DMAC_STEPSIZE_27 +#define CONF_DMAC_STEPSIZE_27 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_27 +#ifndef CONF_DMAC_STEPSEL_27 +#define CONF_DMAC_STEPSEL_27 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_27 +#ifndef CONF_DMAC_SRCINC_27 +#define CONF_DMAC_SRCINC_27 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_27 +#ifndef CONF_DMAC_DSTINC_27 +#define CONF_DMAC_DSTINC_27 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_27 +#ifndef CONF_DMAC_BEATSIZE_27 +#define CONF_DMAC_BEATSIZE_27 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_27 +#ifndef CONF_DMAC_BLOCKACT_27 +#define CONF_DMAC_BLOCKACT_27 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_27 +#ifndef CONF_DMAC_EVOSEL_27 +#define CONF_DMAC_EVOSEL_27 0 +#endif +// + +// Channel 28 settings +// dmac_channel_28_settings +#ifndef CONF_DMAC_CHANNEL_28_SETTINGS +#define CONF_DMAC_CHANNEL_28_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 28 is running in standby mode or not +// dmac_runstdby_28 +#ifndef CONF_DMAC_RUNSTDBY_28 +#define CONF_DMAC_RUNSTDBY_28 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_28 +#ifndef CONF_DMAC_TRIGACT_28 +#define CONF_DMAC_TRIGACT_28 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_28 +#ifndef CONF_DMAC_TRIGSRC_28 +#define CONF_DMAC_TRIGSRC_28 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_28 +#ifndef CONF_DMAC_LVL_28 +#define CONF_DMAC_LVL_28 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_28 +#ifndef CONF_DMAC_EVOE_28 +#define CONF_DMAC_EVOE_28 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_28 +#ifndef CONF_DMAC_EVIE_28 +#define CONF_DMAC_EVIE_28 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_28 +#ifndef CONF_DMAC_EVACT_28 +#define CONF_DMAC_EVACT_28 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_28 +#ifndef CONF_DMAC_STEPSIZE_28 +#define CONF_DMAC_STEPSIZE_28 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_28 +#ifndef CONF_DMAC_STEPSEL_28 +#define CONF_DMAC_STEPSEL_28 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_28 +#ifndef CONF_DMAC_SRCINC_28 +#define CONF_DMAC_SRCINC_28 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_28 +#ifndef CONF_DMAC_DSTINC_28 +#define CONF_DMAC_DSTINC_28 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_28 +#ifndef CONF_DMAC_BEATSIZE_28 +#define CONF_DMAC_BEATSIZE_28 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_28 +#ifndef CONF_DMAC_BLOCKACT_28 +#define CONF_DMAC_BLOCKACT_28 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_28 +#ifndef CONF_DMAC_EVOSEL_28 +#define CONF_DMAC_EVOSEL_28 0 +#endif +// + +// Channel 29 settings +// dmac_channel_29_settings +#ifndef CONF_DMAC_CHANNEL_29_SETTINGS +#define CONF_DMAC_CHANNEL_29_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 29 is running in standby mode or not +// dmac_runstdby_29 +#ifndef CONF_DMAC_RUNSTDBY_29 +#define CONF_DMAC_RUNSTDBY_29 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_29 +#ifndef CONF_DMAC_TRIGACT_29 +#define CONF_DMAC_TRIGACT_29 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_29 +#ifndef CONF_DMAC_TRIGSRC_29 +#define CONF_DMAC_TRIGSRC_29 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_29 +#ifndef CONF_DMAC_LVL_29 +#define CONF_DMAC_LVL_29 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_29 +#ifndef CONF_DMAC_EVOE_29 +#define CONF_DMAC_EVOE_29 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_29 +#ifndef CONF_DMAC_EVIE_29 +#define CONF_DMAC_EVIE_29 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_29 +#ifndef CONF_DMAC_EVACT_29 +#define CONF_DMAC_EVACT_29 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_29 +#ifndef CONF_DMAC_STEPSIZE_29 +#define CONF_DMAC_STEPSIZE_29 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_29 +#ifndef CONF_DMAC_STEPSEL_29 +#define CONF_DMAC_STEPSEL_29 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_29 +#ifndef CONF_DMAC_SRCINC_29 +#define CONF_DMAC_SRCINC_29 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_29 +#ifndef CONF_DMAC_DSTINC_29 +#define CONF_DMAC_DSTINC_29 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_29 +#ifndef CONF_DMAC_BEATSIZE_29 +#define CONF_DMAC_BEATSIZE_29 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_29 +#ifndef CONF_DMAC_BLOCKACT_29 +#define CONF_DMAC_BLOCKACT_29 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_29 +#ifndef CONF_DMAC_EVOSEL_29 +#define CONF_DMAC_EVOSEL_29 0 +#endif +// + +// Channel 30 settings +// dmac_channel_30_settings +#ifndef CONF_DMAC_CHANNEL_30_SETTINGS +#define CONF_DMAC_CHANNEL_30_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 30 is running in standby mode or not +// dmac_runstdby_30 +#ifndef CONF_DMAC_RUNSTDBY_30 +#define CONF_DMAC_RUNSTDBY_30 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_30 +#ifndef CONF_DMAC_TRIGACT_30 +#define CONF_DMAC_TRIGACT_30 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_30 +#ifndef CONF_DMAC_TRIGSRC_30 +#define CONF_DMAC_TRIGSRC_30 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_30 +#ifndef CONF_DMAC_LVL_30 +#define CONF_DMAC_LVL_30 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_30 +#ifndef CONF_DMAC_EVOE_30 +#define CONF_DMAC_EVOE_30 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_30 +#ifndef CONF_DMAC_EVIE_30 +#define CONF_DMAC_EVIE_30 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_30 +#ifndef CONF_DMAC_EVACT_30 +#define CONF_DMAC_EVACT_30 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_30 +#ifndef CONF_DMAC_STEPSIZE_30 +#define CONF_DMAC_STEPSIZE_30 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_30 +#ifndef CONF_DMAC_STEPSEL_30 +#define CONF_DMAC_STEPSEL_30 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_30 +#ifndef CONF_DMAC_SRCINC_30 +#define CONF_DMAC_SRCINC_30 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_30 +#ifndef CONF_DMAC_DSTINC_30 +#define CONF_DMAC_DSTINC_30 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_30 +#ifndef CONF_DMAC_BEATSIZE_30 +#define CONF_DMAC_BEATSIZE_30 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_30 +#ifndef CONF_DMAC_BLOCKACT_30 +#define CONF_DMAC_BLOCKACT_30 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_30 +#ifndef CONF_DMAC_EVOSEL_30 +#define CONF_DMAC_EVOSEL_30 0 +#endif +// + +// Channel 31 settings +// dmac_channel_31_settings +#ifndef CONF_DMAC_CHANNEL_31_SETTINGS +#define CONF_DMAC_CHANNEL_31_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 31 is running in standby mode or not +// dmac_runstdby_31 +#ifndef CONF_DMAC_RUNSTDBY_31 +#define CONF_DMAC_RUNSTDBY_31 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_31 +#ifndef CONF_DMAC_TRIGACT_31 +#define CONF_DMAC_TRIGACT_31 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_31 +#ifndef CONF_DMAC_TRIGSRC_31 +#define CONF_DMAC_TRIGSRC_31 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_31 +#ifndef CONF_DMAC_LVL_31 +#define CONF_DMAC_LVL_31 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_31 +#ifndef CONF_DMAC_EVOE_31 +#define CONF_DMAC_EVOE_31 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_31 +#ifndef CONF_DMAC_EVIE_31 +#define CONF_DMAC_EVIE_31 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_31 +#ifndef CONF_DMAC_EVACT_31 +#define CONF_DMAC_EVACT_31 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_31 +#ifndef CONF_DMAC_STEPSIZE_31 +#define CONF_DMAC_STEPSIZE_31 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_31 +#ifndef CONF_DMAC_STEPSEL_31 +#define CONF_DMAC_STEPSEL_31 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_31 +#ifndef CONF_DMAC_SRCINC_31 +#define CONF_DMAC_SRCINC_31 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_31 +#ifndef CONF_DMAC_DSTINC_31 +#define CONF_DMAC_DSTINC_31 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_31 +#ifndef CONF_DMAC_BEATSIZE_31 +#define CONF_DMAC_BEATSIZE_31 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_31 +#ifndef CONF_DMAC_BLOCKACT_31 +#define CONF_DMAC_BLOCKACT_31 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_31 +#ifndef CONF_DMAC_EVOSEL_31 +#define CONF_DMAC_EVOSEL_31 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h new file mode 100644 index 0000000000..6f4f01a7e6 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h @@ -0,0 +1,924 @@ +// Circuit Python SAMD51 clock tree: +// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5, GCLK6 +// GCLK1 (48MHz) -> 48 MHz peripherals +// GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0 +// DPLL0 (multiplied up to 120 MHz) -> GCLK0, GCLK4 (output for monitoring) +// GCLK6 (48 MHz divided down to 12 MHz) -> DAC + +// We'd like to use XOSC32K as a ref for DFLL48M on boards with a 32kHz crystal, +// but haven't figured that out yet. + +// Used in hpl/core/hpl_init.c to define which clocks should be initialized first. +// Not clear why all these need to be specified, but it doesn't work properly otherwise. + +//#define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5) +#define CIRCUITPY_GCLK_INIT_1ST 0xffff + +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 1 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 4 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 24 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 1 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 4 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// Generic clock generator 8 configuration +// Indicates whether generic clock 8 configuration is enabled or not +// enable_gclk_gen_8 +#ifndef CONF_GCLK_GENERATOR_8_CONFIG +#define CONF_GCLK_GENERATOR_8_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 8 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 8 +// gclk_gen_8_oscillator +#ifndef CONF_GCLK_GEN_8_SOURCE +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_8_runstdby +#ifndef CONF_GCLK_GEN_8_RUNSTDBY +#define CONF_GCLK_GEN_8_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_8_div_sel +#ifndef CONF_GCLK_GEN_8_DIVSEL +#define CONF_GCLK_GEN_8_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_8_oe +#ifndef CONF_GCLK_GEN_8_OE +#define CONF_GCLK_GEN_8_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_8_oov +#ifndef CONF_GCLK_GEN_8_OOV +#define CONF_GCLK_GEN_8_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_8_idc +#ifndef CONF_GCLK_GEN_8_IDC +#define CONF_GCLK_GEN_8_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_8_enable +#ifndef CONF_GCLK_GEN_8_GENEN +#define CONF_GCLK_GEN_8_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 8 division <0x0000-0xFFFF> +// gclk_gen_8_div +#ifndef CONF_GCLK_GEN_8_DIV +#define CONF_GCLK_GEN_8_DIV 1 +#endif +// +// + +// Generic clock generator 9 configuration +// Indicates whether generic clock 9 configuration is enabled or not +// enable_gclk_gen_9 +#ifndef CONF_GCLK_GENERATOR_9_CONFIG +#define CONF_GCLK_GENERATOR_9_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 9 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 9 +// gclk_gen_9_oscillator +#ifndef CONF_GCLK_GEN_9_SOURCE +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_9_runstdby +#ifndef CONF_GCLK_GEN_9_RUNSTDBY +#define CONF_GCLK_GEN_9_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_9_div_sel +#ifndef CONF_GCLK_GEN_9_DIVSEL +#define CONF_GCLK_GEN_9_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_9_oe +#ifndef CONF_GCLK_GEN_9_OE +#define CONF_GCLK_GEN_9_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_9_oov +#ifndef CONF_GCLK_GEN_9_OOV +#define CONF_GCLK_GEN_9_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_9_idc +#ifndef CONF_GCLK_GEN_9_IDC +#define CONF_GCLK_GEN_9_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_9_enable +#ifndef CONF_GCLK_GEN_9_GENEN +#define CONF_GCLK_GEN_9_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 9 division <0x0000-0xFFFF> +// gclk_gen_9_div +#ifndef CONF_GCLK_GEN_9_DIV +#define CONF_GCLK_GEN_9_DIV 1 +#endif +// +// + +// Generic clock generator 10 configuration +// Indicates whether generic clock 10 configuration is enabled or not +// enable_gclk_gen_10 +#ifndef CONF_GCLK_GENERATOR_10_CONFIG +#define CONF_GCLK_GENERATOR_10_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 10 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 10 +// gclk_gen_10_oscillator +#ifndef CONF_GCLK_GEN_10_SOURCE +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_10_runstdby +#ifndef CONF_GCLK_GEN_10_RUNSTDBY +#define CONF_GCLK_GEN_10_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_10_div_sel +#ifndef CONF_GCLK_GEN_10_DIVSEL +#define CONF_GCLK_GEN_10_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_10_oe +#ifndef CONF_GCLK_GEN_10_OE +#define CONF_GCLK_GEN_10_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_10_oov +#ifndef CONF_GCLK_GEN_10_OOV +#define CONF_GCLK_GEN_10_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_10_idc +#ifndef CONF_GCLK_GEN_10_IDC +#define CONF_GCLK_GEN_10_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_10_enable +#ifndef CONF_GCLK_GEN_10_GENEN +#define CONF_GCLK_GEN_10_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 10 division <0x0000-0xFFFF> +// gclk_gen_10_div +#ifndef CONF_GCLK_GEN_10_DIV +#define CONF_GCLK_GEN_10_DIV 1 +#endif +// +// + +// Generic clock generator 11 configuration +// Indicates whether generic clock 11 configuration is enabled or not +// enable_gclk_gen_11 +#ifndef CONF_GCLK_GENERATOR_11_CONFIG +#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 11 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 11 +// gclk_gen_11_oscillator +#ifndef CONF_GCLK_GEN_11_SOURCE +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_11_runstdby +#ifndef CONF_GCLK_GEN_11_RUNSTDBY +#define CONF_GCLK_GEN_11_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_11_div_sel +#ifndef CONF_GCLK_GEN_11_DIVSEL +#define CONF_GCLK_GEN_11_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_11_oe +#ifndef CONF_GCLK_GEN_11_OE +#define CONF_GCLK_GEN_11_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_11_oov +#ifndef CONF_GCLK_GEN_11_OOV +#define CONF_GCLK_GEN_11_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_11_idc +#ifndef CONF_GCLK_GEN_11_IDC +#define CONF_GCLK_GEN_11_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_11_enable +#ifndef CONF_GCLK_GEN_11_GENEN +#define CONF_GCLK_GEN_11_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 11 division <0x0000-0xFFFF> +// gclk_gen_11_div +#ifndef CONF_GCLK_GEN_11_DIV +#define CONF_GCLK_GEN_11_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_mclk_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_mclk_config.h new file mode 100644 index 0000000000..a5a7de53c2 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_mclk_config.h @@ -0,0 +1,104 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// High-Speed Clock Division +// Divide by 1 +// mclk_arch_hsdiv +#ifndef CONF_MCLK_HSDIV +#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_nvmctrl_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_nvmctrl_config.h new file mode 100644 index 0000000000..53fcb593ab --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_nvmctrl_config.h @@ -0,0 +1,36 @@ +/* Auto-generated config file hpl_nvmctrl_config.h */ +#ifndef HPL_NVMCTRL_CONFIG_H +#define HPL_NVMCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings + +// Power Reduction Mode During Sleep +// <0x00=> Wake On Access +// <0x01=> Wake Up Instant +// <0x03=> Disabled +// nvm_arch_sleepprm +#ifndef CONF_NVM_SLEEPPRM +#define CONF_NVM_SLEEPPRM 0 +#endif + +// AHB0 Cache Disable +// Indicate whether AHB0 cache is disable or not +// nvm_arch_cache0 +#ifndef CONF_NVM_CACHE0 +#define CONF_NVM_CACHE0 1 +#endif + +// AHB1 Cache Disable +// Indicate whether AHB1 cache is disable or not +// nvm_arch_cache1 +#ifndef CONF_NVM_CACHE1 +#define CONF_NVM_CACHE1 1 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_NVMCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_osc32kctrl_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_osc32kctrl_config.h new file mode 100644 index 0000000000..d93cbf922e --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_osc32kctrl_config.h @@ -0,0 +1,163 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ +#define CONF_RTCCTRL_1KHZ 1 +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 1 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 0 +#endif + +// Control Gain Mode +// <0x0=>Low Power mode +// <0x1=>Standard mode +// <0x2=>High Speed mode +// xosc32k_arch_cgm +#ifndef CONF_XOSC32K_CGM +#define CONF_XOSC32K_CGM 0x1 +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x3F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h new file mode 100644 index 0000000000..cd11866059 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h @@ -0,0 +1,634 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC0 is enabled or not +// enable_xosc0 +#ifndef CONF_XOSC0_CONFIG +#define CONF_XOSC0_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc0_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC0_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc0_arch_enable +#ifndef CONF_XOSC0_ENABLE +#define CONF_XOSC0_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc0_arch_startup +#ifndef CONF_XOSC0_STARTUP +#define CONF_XOSC0_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc0_arch_swben +#ifndef CONF_XOSC0_SWBEN +#define CONF_XOSC0_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc0_arch_cfden +#ifndef CONF_XOSC0_CFDEN +#define CONF_XOSC0_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc0_arch_enalc +#ifndef CONF_XOSC0_ENALC +#define CONF_XOSC0_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc0_arch_lowbufgain +#ifndef CONF_XOSC0_LOWBUFGAIN +#define CONF_XOSC0_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc0_arch_ondemand +#ifndef CONF_XOSC0_ONDEMAND +#define CONF_XOSC0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc0_arch_runstdby +#ifndef CONF_XOSC0_RUNSTDBY +#define CONF_XOSC0_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc0_arch_xtalen +#ifndef CONF_XOSC0_XTALEN +#define CONF_XOSC0_XTALEN 0 +#endif +// +// + +#if CONF_XOSC0_FREQUENCY >= 32000000 +#define CONF_XOSC0_CFDPRESC 0x0 +#define CONF_XOSC0_IMULT 0x7 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 24000000 +#define CONF_XOSC0_CFDPRESC 0x1 +#define CONF_XOSC0_IMULT 0x6 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 16000000 +#define CONF_XOSC0_CFDPRESC 0x2 +#define CONF_XOSC0_IMULT 0x5 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 8000000 +#define CONF_XOSC0_CFDPRESC 0x3 +#define CONF_XOSC0_IMULT 0x4 +#define CONF_XOSC0_IPTAT 0x3 +#endif + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC1 is enabled or not +// enable_xosc1 +#ifndef CONF_XOSC1_CONFIG +#define CONF_XOSC1_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc1_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC1_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc1_arch_enable +#ifndef CONF_XOSC1_ENABLE +#define CONF_XOSC1_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc1_arch_startup +#ifndef CONF_XOSC1_STARTUP +#define CONF_XOSC1_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc1_arch_swben +#ifndef CONF_XOSC1_SWBEN +#define CONF_XOSC1_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc1_arch_cfden +#ifndef CONF_XOSC1_CFDEN +#define CONF_XOSC1_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc1_arch_enalc +#ifndef CONF_XOSC1_ENALC +#define CONF_XOSC1_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc1_arch_lowbufgain +#ifndef CONF_XOSC1_LOWBUFGAIN +#define CONF_XOSC1_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc1_arch_ondemand +#ifndef CONF_XOSC1_ONDEMAND +#define CONF_XOSC1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc1_arch_runstdby +#ifndef CONF_XOSC1_RUNSTDBY +#define CONF_XOSC1_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc1_arch_xtalen +#ifndef CONF_XOSC1_XTALEN +#define CONF_XOSC1_XTALEN 0 +#endif +// +// + +#if CONF_XOSC1_FREQUENCY >= 32000000 +#define CONF_XOSC1_CFDPRESC 0x0 +#define CONF_XOSC1_IMULT 0x7 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 24000000 +#define CONF_XOSC1_CFDPRESC 0x1 +#define CONF_XOSC1_IMULT 0x6 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 16000000 +#define CONF_XOSC1_CFDPRESC 0x2 +#define CONF_XOSC1_IMULT 0x5 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 8000000 +#define CONF_XOSC1_CFDPRESC 0x3 +#define CONF_XOSC1_IMULT 0x4 +#define CONF_XOSC1_IPTAT 0x3 +#endif + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source +// dfll_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 1 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 1 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 1 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0x0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 0x1 +#endif + +// Fine Maximum Step <0x0-0xFF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 0x1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0x0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0xFF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x80) +#endif + +// + +// + +// + +// FDPLL0 Configuration +// Indicates whether configuration for FDPLL0 is enabled or not +// enable_fdpll0 +#ifndef CONF_FDPLL0_CONFIG +#define CONF_FDPLL0_CONFIG 1 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll0_ref_clock +#ifndef CONF_FDPLL0_GCLK +#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK5_Val +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll0_arch_enable +#ifndef CONF_FDPLL0_ENABLE +#define CONF_FDPLL0_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll0_arch_ondemand +#ifndef CONF_FDPLL0_ONDEMAND +#define CONF_FDPLL0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll0_arch_runstdby +#ifndef CONF_FDPLL0_RUNSTDBY +#define CONF_FDPLL0_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// fdpll0_ldrfrac +#ifndef CONF_FDPLL0_LDRFRAC +#define CONF_FDPLL0_LDRFRAC 0x0 +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// fdpll0_ldr +#ifndef CONF_FDPLL0_LDR +#define CONF_FDPLL0_LDR 59 +#endif + +// Clock Divider <0x0-0x7FF> +// fdpll0_clock_div +#ifndef CONF_FDPLL0_DIV +#define CONF_FDPLL0_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll0_arch_dcoen +#ifndef CONF_FDPLL0_DCOEN +#define CONF_FDPLL0_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll0_clock_dcofilter +#ifndef CONF_FDPLL0_DCOFILTER +#define CONF_FDPLL0_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll0_arch_lbypass +#ifndef CONF_FDPLL0_LBYPASS +#define CONF_FDPLL0_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll0_arch_ltime +#ifndef CONF_FDPLL0_LTIME +#define CONF_FDPLL0_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll0_arch_refclk +#ifndef CONF_FDPLL0_REFCLK +#define CONF_FDPLL0_REFCLK 0x0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll0_arch_wuf +#ifndef CONF_FDPLL0_WUF +#define CONF_FDPLL0_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll0_arch_filter +#ifndef CONF_FDPLL0_FILTER +#define CONF_FDPLL0_FILTER 0x0 +#endif + +// +// +// FDPLL1 Configuration +// Indicates whether configuration for FDPLL1 is enabled or not +// enable_fdpll1 +#ifndef CONF_FDPLL1_CONFIG +#define CONF_FDPLL1_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll1_ref_clock +#ifndef CONF_FDPLL1_GCLK +#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll1_arch_enable +#ifndef CONF_FDPLL1_ENABLE +#define CONF_FDPLL1_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll1_arch_ondemand +#ifndef CONF_FDPLL1_ONDEMAND +#define CONF_FDPLL1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll1_arch_runstdby +#ifndef CONF_FDPLL1_RUNSTDBY +#define CONF_FDPLL1_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// fdpll1_ldrfrac +#ifndef CONF_FDPLL1_LDRFRAC +#define CONF_FDPLL1_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// fdpll1_ldr +#ifndef CONF_FDPLL1_LDR +#define CONF_FDPLL1_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// fdpll1_clock_div +#ifndef CONF_FDPLL1_DIV +#define CONF_FDPLL1_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll1_arch_dcoen +#ifndef CONF_FDPLL1_DCOEN +#define CONF_FDPLL1_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll1_clock_dcofilter +#ifndef CONF_FDPLL1_DCOFILTER +#define CONF_FDPLL1_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll1_arch_lbypass +#ifndef CONF_FDPLL1_LBYPASS +#define CONF_FDPLL1_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll1_arch_ltime +#ifndef CONF_FDPLL1_LTIME +#define CONF_FDPLL1_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll1_arch_refclk +#ifndef CONF_FDPLL1_REFCLK +#define CONF_FDPLL1_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll1_arch_wuf +#ifndef CONF_FDPLL1_WUF +#define CONF_FDPLL1_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll1_arch_filter +#ifndef CONF_FDPLL1_FILTER +#define CONF_FDPLL1_FILTER 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_rtc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_rtc_config.h new file mode 100644 index 0000000000..2b0b6712e6 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_rtc_config.h @@ -0,0 +1,145 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// Force reset RTC on initialization +// Force RTC to reset on initialization. +// Note that the previous power down data in RTC is lost if it's enabled. +// rtc_arch_init_reset +#ifndef CONF_RTC_INIT_RESET +#define CONF_RTC_INIT_RESET 0 +#endif + +// Prescaler configuration +// <0x0=>OFF(Peripheral clock divided by 1) +// <0x1=>Peripheral clock divided by 1 +// <0x2=>Peripheral clock divided by 2 +// <0x3=>Peripheral clock divided by 4 +// <0x4=>Peripheral clock divided by 8 +// <0x5=>Peripheral clock divided by 16 +// <0x6=>Peripheral clock divided by 32 +// <0x7=>Peripheral clock divided by 64 +// <0x8=>Peripheral clock divided by 128 +// <0x9=>Peripheral clock divided by 256 +// <0xA=>Peripheral clock divided by 512 +// <0xB=>Peripheral clock divided by 1024 +// These bits define the RTC clock relative to the peripheral clock +// rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER +#define CONF_RTC_PRESCALER 0xb + +#endif + +// Compare Value <1-4294967295> +// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), +// by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms. +// rtc_arch_comp_val + +#ifndef CONF_RTC_COMP_VAL +#define CONF_RTC_COMP_VAL 1 + +#endif + +// Event control +// rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// Periodic Interval 0 Event Output +// This bit indicates whether Periodic interval 0 event is enabled and will be generated +// rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// Periodic Interval 1 Event Output +// This bit indicates whether Periodic interval 1 event is enabled and will be generated +// rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// Periodic Interval 2 Event Output +// This bit indicates whether Periodic interval 2 event is enabled and will be generated +// rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// Periodic Interval 3 Event Output +// This bit indicates whether Periodic interval 3 event is enabled and will be generated +// rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// Periodic Interval 4 Event Output +// This bit indicates whether Periodic interval 4 event is enabled and will be generated +// rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// Periodic Interval 5 Event Output +// This bit indicates whether Periodic interval 5 event is enabled and will be generated +// rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// Periodic Interval 6 Event Output +// This bit indicates whether Periodic interval 6 event is enabled and will be generated +// rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// Periodic Interval 7 Event Output +// This bit indicates whether Periodic interval 7 event is enabled and will be generated +// rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// Compare 0 Event Output +// This bit indicates whether Compare O event is enabled and will be generated +// rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// Compare 1 Event Output +// This bit indicates whether Compare 1 event is enabled and will be generated +// rtc_cmpeo1 +#ifndef CONF_RTC_COMPE1 +#define CONF_RTC_COMPE1 0 +#endif +// Overflow Event Output +// This bit indicates whether Overflow event is enabled and will be generated +// rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// Tamper Event Output +// This bit indicates whether Tamper event output is enabled and will be generated +// rtc_tampereo +#ifndef CONF_RTC_TAMPEREO +#define CONF_RTC_TAMPEREO 0 +#endif + +// Tamper Event Input +// This bit indicates whether Tamper event input is enabled and will be generated +// rtc_tampevei +#ifndef CONF_RTC_TAMPEVEI +#define CONF_RTC_TAMPEVEI 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_sdhc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_sdhc_config.h new file mode 100644 index 0000000000..daa6620517 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_sdhc_config.h @@ -0,0 +1,24 @@ +/* Auto-generated config file hpl_sdhc_config.h */ +#ifndef HPL_SDHC_CONFIG_H +#define HPL_SDHC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include "peripheral_clk_config.h" + +#ifndef CONF_BASE_FREQUENCY +#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY +#endif + +// Clock Generator Select +// <0=> Divided Clock mode +// <1=> Programmable Clock mode +// This defines the clock generator mode in the SDCLK Frequency Select field +// sdhc_clk_gsel +#ifndef CONF_SDHC0_CLK_GEN_SEL +#define CONF_SDHC0_CLK_GEN_SEL 0 +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SDHC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h new file mode 100644 index 0000000000..cd411154c7 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h @@ -0,0 +1,751 @@ +// For CircuitPython, use SERCOM settings as prototypes to set +// the default settings. This file defines these SERCOMs +// +// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous +// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous +// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous +// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA + +#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0 +#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY + +#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1 + +#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2 +#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY + +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_0_SPI_MODE +#define CONF_SERCOM_0_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_0_SPI_RXEN +#define CONF_SERCOM_0_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_0_SPI_CHSIZE +#define CONF_SERCOM_0_SPI_CHSIZE 0x0 +#endif + +// Baud rate <1-12000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_0_SPI_BAUD +#define CONF_SERCOM_0_SPI_BAUD 50000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_0_SPI_ADVANCED +#define CONF_SERCOM_0_SPI_ADVANCED 1 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE +#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_0_SPI_DORD +#define CONF_SERCOM_0_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_0_SPI_CPOL +#define CONF_SERCOM_0_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_0_SPI_CPHA +#define CONF_SERCOM_0_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_0_SPI_IBON +#define CONF_SERCOM_0_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_0_SPI_RUNSTDBY +#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_0_SPI_DBGSTOP +#define CONF_SERCOM_0_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_0_SPI_AMODE_EN +#define CONF_SERCOM_0_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_AMODE +#define CONF_SERCOM_0_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDR +#define CONF_SERCOM_0_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDRMASK +#define CONF_SERCOM_0_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_SSDE +#define CONF_SERCOM_0_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_MSSEN +#define CONF_SERCOM_0_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_0_SPI_PLOADEN +#define CONF_SERCOM_0_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_0_SPI_RXPO +#define CONF_SERCOM_0_SPI_RXPO 2 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_0_SPI_TXPO +#define CONF_SERCOM_0_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_0_SPI_BAUD_RATE +#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1 +#endif + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_1_I2CM_BAUD +#define CONF_SERCOM_1_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 1 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN +#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN +#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_1_I2CM_LOWTOUT +#define CONF_SERCOM_1_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_1_I2CM_INACTOUT +#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_1_I2CM_SDAHOLD +#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY +#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_1_I2CM_SPEED +#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10)) +#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE +#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_1_I2CM_BAUD_RATE \ + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include + +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 1 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x3=>3x +// How many over-sampling bits used when samling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_2_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_2_USART_INACK +#define CONF_SERCOM_2_USART_INACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_DSNACK +#define CONF_SERCOM_2_USART_DSNACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_MAXITER +#define CONF_SERCOM_2_USART_MAXITER 0x7 +#endif + +#ifndef CONF_SERCOM_2_USART_GTIME +#define CONF_SERCOM_2_USART_GTIME 0x2 +#endif + +#define CONF_SERCOM_2_USART_RXINV 0x0 +#define CONF_SERCOM_2_USART_TXINV 0x0 + +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA08 */ +#endif + +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA09 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 1 +#endif + +// SPI DMA TX Channel <0-32> +// This defines DMA channel to be used +// spi_master_dma_tx_channel +#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0 +#endif + +// SPI RX Channel Enable +// spi_master_rx_channel +#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL +#define CONF_SERCOM_3_SPI_RX_CHANNEL 1 +#endif + +// DMA Channel <0-32> +// This defines DMA channel to be used +// spi_master_dma_rx_channel +#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1 +#endif + +// + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_3_SPI_MODE +#define CONF_SERCOM_3_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_3_SPI_RXEN +#define CONF_SERCOM_3_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_3_SPI_CHSIZE +#define CONF_SERCOM_3_SPI_CHSIZE 0x0 +#endif + +// Baud rate <1-12000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_3_SPI_BAUD +#define CONF_SERCOM_3_SPI_BAUD 50000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_3_SPI_ADVANCED +#define CONF_SERCOM_3_SPI_ADVANCED 0 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE +#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_3_SPI_DORD +#define CONF_SERCOM_3_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_3_SPI_CPOL +#define CONF_SERCOM_3_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_3_SPI_CPHA +#define CONF_SERCOM_3_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_3_SPI_IBON +#define CONF_SERCOM_3_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_3_SPI_RUNSTDBY +#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_3_SPI_DBGSTOP +#define CONF_SERCOM_3_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_3_SPI_AMODE_EN +#define CONF_SERCOM_3_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_AMODE +#define CONF_SERCOM_3_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_ADDR +#define CONF_SERCOM_3_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_ADDRMASK +#define CONF_SERCOM_3_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_SSDE +#define CONF_SERCOM_3_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_MSSEN +#define CONF_SERCOM_3_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_3_SPI_PLOADEN +#define CONF_SERCOM_3_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_3_SPI_RXPO +#define CONF_SERCOM_3_SPI_RXPO 2 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_3_SPI_TXPO +#define CONF_SERCOM_3_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_3_SPI_BAUD_RATE +#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1 +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_systick_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_systick_config.h new file mode 100644 index 0000000000..a7f2f36208 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h new file mode 100644 index 0000000000..38d48e9b67 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h @@ -0,0 +1,209 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +// Basic settings +// Prescaler +// <0=> No division +// <1=> Divide by 2 +// <2=> Divide by 4 +// <3=> Divide by 8 +// <4=> Divide by 16 +// <5=> Divide by 64 +// <6=> Divide by 256 +// <7=> Divide by 1024 +// This defines the prescaler value +// tc_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0 +#endif +// + +// PWM Waveform Output settings +// Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// The unit of this value is us. +// tc_arch_wave_per_val +#ifndef CONF_TC0_WAVE_PER_VAL +#define CONF_TC0_WAVE_PER_VAL 0x3e8 +#endif + +// Waveform Duty Value (0.1%) <0x00-0x03E8> +// The unit of this value is 1/1000. +// tc_arch_wave_duty_val +#ifndef CONF_TC0_WAVE_DUTY_VAL +#define CONF_TC0_WAVE_DUTY_VAL 0x1f4 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 \ + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 64000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 256000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1024000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) +#endif + +// + +// Advanced settings +// Mode +// Counter in 16-bit mode +// Counter in 32-bit mode +// These bits mode +// tc_mode +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT16_Val +#endif + +// Period Value <0x00000000-0xFFFFFFFF> +// tc_per +#ifndef CONF_TC0_PER +#define CONF_TC0_PER 0x32 +#endif +// + +// Advanced settings +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the will continue running in standby sleep mode or not +// tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// On-Demand +// Indicates whether the TC0's on-demand mode is on or not +// tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// Auto Lock +// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event +// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event +// tc_arch_alock +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CAPTEN0 0 +//#define CONF_TC0_CAPTEN1 0 +//#define CONF_TC0_COPEN0 0 +//#define CONF_TC0_COPEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_DIR 0 +//#define CONF_TC0_ONESHOT 0 +//#define CONF_TC0_LUPD 0 + +// Debug Running Mode +// Indicates whether the Debug Running Mode is enabled or not +// tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// Event control +// timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 0 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_INVEN0 0 +//#define CONF_TC0_INVEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_PERBUF 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CCBUF0 0 +//#define CONF_TC0_CCBUF1 0 + +// + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_trng_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_trng_config.h new file mode 100644 index 0000000000..ba9014989a --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_trng_config.h @@ -0,0 +1,27 @@ +/* Auto-generated config file hpl_trng_config.h */ +#ifndef HPL_TRNG_CONFIG_H +#define HPL_TRNG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced configurations + +// Run In Standby +// Indicates whether the TRNG works in standby mode +// trng_runstdby +#ifndef CONF_TRNG_RUNSTDBY +#define CONF_TRNG_RUNSTDBY 0 +#endif + +// Data Ready Event Output Enable +// Indicates whether the TRNG generates event on Data Ready +// trng_datardyeo +#ifndef CONF_TRNG_DATARDYEO +#define CONF_TRNG_DATARDYEO 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_TRNG_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_usb_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_usb_config.h new file mode 100644 index 0000000000..d1bb42fe45 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/hpl_usb_config.h @@ -0,0 +1,413 @@ +/* Auto-generated config file hpl_usb_config.h */ +#ifndef HPL_USB_CONFIG_H +#define HPL_USB_CONFIG_H + +// CIRCUITPY: + +// Use 64-byte USB buffers for endpoint directions that are in use. They're set to 0 below otherwise. + +#include "genhdr/autogen_usb_descriptor.h" + +#if defined(USB_ENDPOINT_1_OUT_USED) && USB_ENDPOINT_1_OUT_USED +#define CONF_USB_EP1_CACHE 64 +#endif +#if defined(USB_ENDPOINT_1_IN_USED) && USB_ENDPOINT_1_IN_USED +#define CONF_USB_EP1_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_2_OUT_USED) && USB_ENDPOINT_2_OUT_USED +#define CONF_USB_EP2_CACHE 64 +#endif +#if defined(USB_ENDPOINT_2_IN_USED) && USB_ENDPOINT_2_IN_USED +#define CONF_USB_EP2_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_3_OUT_USED) && USB_ENDPOINT_3_OUT_USED +#define CONF_USB_EP3_CACHE 64 +#endif +#if defined(USB_ENDPOINT_3_IN_USED) && USB_ENDPOINT_3_IN_USED +#define CONF_USB_EP3_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_4_OUT_USED) && USB_ENDPOINT_4_OUT_USED +#define CONF_USB_EP4_CACHE 64 +#endif +#if defined(USB_ENDPOINT_4_IN_USED) && USB_ENDPOINT_4_IN_USED +#define CONF_USB_EP4_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_5_OUT_USED) && USB_ENDPOINT_5_OUT_USED +#define CONF_USB_EP5_CACHE 64 +#endif +#if defined(USB_ENDPOINT_5_IN_USED) && USB_ENDPOINT_5_IN_USED +#define CONF_USB_EP5_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_6_OUT_USED) && USB_ENDPOINT_6_OUT_USED +#define CONF_USB_EP6_CACHE 64 +#endif +#if defined(USB_ENDPOINT_6_IN_USED) && USB_ENDPOINT_6_IN_USED +#define CONF_USB_EP6_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_7_OUT_USED) && USB_ENDPOINT_7_OUT_USED +#define CONF_USB_EP7_CACHE 64 +#endif +#if defined(USB_ENDPOINT_7_IN_USED) && USB_ENDPOINT_7_IN_USED +#define CONF_USB_EP7_I_CACHE 64 +#endif + + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_USB_N_0 0 +#define CONF_USB_N_1 1 +#define CONF_USB_N_2 2 +#define CONF_USB_N_3 3 +#define CONF_USB_N_4 4 +#define CONF_USB_N_5 5 +#define CONF_USB_N_6 6 +#define CONF_USB_N_7 7 +#define CONF_USB_N_8 8 +#define CONF_USB_N_9 9 +#define CONF_USB_N_10 10 +#define CONF_USB_N_11 11 +#define CONF_USB_N_12 12 +#define CONF_USB_N_13 13 +#define CONF_USB_N_14 14 +#define CONF_USB_N_15 15 + +#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) +#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) + +// USB Device HAL Configuration + +// Max number of endpoints supported +// Limits the number of endpoints (described by EP address) can be used in app. +// NOTE(tannewt): This not only limits the number of endpoints but also the +// addresses. In other words, even if you use endpoint 6 you need to set this to 11. +// 1 (EP0 only) +// 2 (EP0 + 1 endpoint) +// 3 (EP0 + 2 endpoints) +// 4 (EP0 + 3 endpoints) +// 5 (EP0 + 4 endpoints) +// 6 (EP0 + 5 endpoints) +// 7 (EP0 + 6 endpoints) +// 8 (EP0 + 7 endpoints) +// Max possible (by "Max Endpoint Number" config) +// usbd_num_ep_sp +#ifndef CONF_USB_D_NUM_EP_SP +#define CONF_USB_D_NUM_EP_SP CONF_USB_D_N_EP_MAX +#endif + +// + +// Max Endpoint Number supported +// Limits the max endpoint number. +// USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. +// Reduce the value according to specific device design, to cut-off memory usage. +// 0 (only EP0) +// 1 (EP 0x81 or 0x01) +// 2 (EP 0x82 or 0x02) +// 3 (EP 0x83 or 0x03) +// 4 (EP 0x84 or 0x04) +// 5 (EP 0x85 or 0x05) +// 6 (EP 0x86 or 0x06) +// 7 (EP 0x87 or 0x07) +// Max possible (by HW) +// The number of physical endpoints - 1 +// usbd_arch_max_ep_n +#ifndef CONF_USB_D_MAX_EP_N +#define CONF_USB_D_MAX_EP_N CONF_USB_D_EP_N_MAX +#endif + +// USB Speed Limit +// Limits the working speed of the device. +// Full speed +// Low Speed +// usbd_arch_speed +#ifndef CONF_USB_D_SPEED +#define CONF_USB_D_SPEED USB_SPEED_FS +#endif + +// Cache buffer size for EP0 +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// usb_arch_ep0_cache +#ifndef CONF_USB_EP0_CACHE +#define CONF_USB_EP0_CACHE 64 +#endif + +// Cache configuration EP1 +// Cache buffer size for EP1 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep1_cache +#ifndef CONF_USB_EP1_CACHE +#define CONF_USB_EP1_CACHE 0 +#endif + +// Cache buffer size for EP1 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep1_I_CACHE +#ifndef CONF_USB_EP1_I_CACHE +#define CONF_USB_EP1_I_CACHE 0 +#endif +// + +// Cache configuration EP2 +// Cache buffer size for EP2 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep2_cache +#ifndef CONF_USB_EP2_CACHE +#define CONF_USB_EP2_CACHE 0 +#endif + +// Cache buffer size for EP2 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep2_I_CACHE +#ifndef CONF_USB_EP2_I_CACHE +#define CONF_USB_EP2_I_CACHE 0 +#endif +// + +// Cache configuration EP3 +// Cache buffer size for EP3 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep3_cache +#ifndef CONF_USB_EP3_CACHE +#define CONF_USB_EP3_CACHE 0 +#endif + +// Cache buffer size for EP3 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep3_I_CACHE +#ifndef CONF_USB_EP3_I_CACHE +#define CONF_USB_EP3_I_CACHE 0 +#endif +// + +// Cache configuration EP4 +// Cache buffer size for EP4 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep4_cache +#ifndef CONF_USB_EP4_CACHE +#define CONF_USB_EP4_CACHE 0 +#endif + +// Cache buffer size for EP4 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep4_I_CACHE +#ifndef CONF_USB_EP4_I_CACHE +#define CONF_USB_EP4_I_CACHE 0 +#endif +// + +// Cache configuration EP5 +// Cache buffer size for EP5 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep5_cache +#ifndef CONF_USB_EP5_CACHE +#define CONF_USB_EP5_CACHE 0 +#endif + +// Cache buffer size for EP5 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep5_I_CACHE +#ifndef CONF_USB_EP5_I_CACHE +#define CONF_USB_EP5_I_CACHE 0 +#endif +// + +// Cache configuration EP6 +// Cache buffer size for EP6 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep6_cache +#ifndef CONF_USB_EP6_CACHE +#define CONF_USB_EP6_CACHE 0 +#endif + +// Cache buffer size for EP6 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep6_I_CACHE +#ifndef CONF_USB_EP6_I_CACHE +#define CONF_USB_EP6_I_CACHE 0 +#endif +// + +// Cache configuration EP7 +// Cache buffer size for EP7 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep7_cache +#ifndef CONF_USB_EP7_CACHE +#define CONF_USB_EP7_CACHE 0 +#endif + +// Cache buffer size for EP7 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep7_I_CACHE +#ifndef CONF_USB_EP7_I_CACHE +#define CONF_USB_EP7_I_CACHE 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_USB_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h new file mode 100644 index 0000000000..59fe8730e6 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h @@ -0,0 +1,1170 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ADC Clock Source +// adc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for ADC. +#ifndef CONF_GCLK_ADC0_SRC +#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_ADC0_FREQUENCY + * \brief ADC0's Clock frequency + */ +#ifndef CONF_GCLK_ADC0_FREQUENCY +#define CONF_GCLK_ADC0_FREQUENCY 48000000 +#endif + +// DAC Clock Source + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// dac_gclk_selection +// Select the clock source for DAC. +#ifndef CONF_GCLK_DAC_SRC +#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK6_Val +#endif + +/** + * \def CONF_GCLK_DAC_FREQUENCY + * \brief DAC's Clock frequency + */ +#ifndef CONF_GCLK_DAC_FREQUENCY +#define CONF_GCLK_DAC_FREQUENCY 2000000 +#endif + +// EVSYS Channel 0 Clock Source +// evsys_clk_selection_0 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 0. +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC +#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 1 Clock Source +// evsys_clk_selection_1 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 1. +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC +#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 2 Clock Source +// evsys_clk_selection_2 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 2. +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC +#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 3 Clock Source +// evsys_clk_selection_3 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 3. +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC +#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 4 Clock Source +// evsys_clk_selection_4 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 4. +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC +#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 5 Clock Source +// evsys_clk_selection_5 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 5. +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC +#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 6 Clock Source +// evsys_clk_selection_6 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 6. +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC +#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 7 Clock Source +// evsys_clk_selection_7 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 7. +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC +#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 8 Clock Source +// evsys_clk_selection_8 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 8. +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC +#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 9 Clock Source +// evsys_clk_selection_9 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 9. +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC +#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 10 Clock Source +// evsys_clk_selection_10 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 10. +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC +#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 48000000.0 +#endif + +// EVSYS Channel 11 Clock Source +// evsys_clk_selection_11 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 11. +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC +#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 48000000.0 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 120000000 +#endif + +// RTC Clock Source +// rtc_clk_selection +// RTC source +// Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 1024 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC0_SRC +#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_TC0_FREQUENCY + * \brief TC0's Clock frequency + */ +#ifndef CONF_GCLK_TC0_FREQUENCY +#define CONF_GCLK_TC0_FREQUENCY 48000000 +#endif + +// USB Clock Source +// usb_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for USB. +#ifndef CONF_GCLK_USB_SRC +#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val + +#endif + +/** + * \def CONF_GCLK_USB_FREQUENCY + * \brief USB's Clock frequency + */ +#ifndef CONF_GCLK_USB_FREQUENCY +#define CONF_GCLK_USB_FREQUENCY 48000000 +#endif + +// SDHC Clock Settings +// SDHC Clock source + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for SDHC. +// sdhc_gclk_selection +#ifndef CONF_GCLK_SDHC0_SRC +#define CONF_GCLK_SDHC0_SRC GCLK_GENCTRL_SRC_DFLL_Val +#endif + +// SDHC clock slow source + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for SDHC. +// sdhc_slow_gclk_selection +#ifndef CONF_GCLK_SDHC0_SLOW_SRC +#define CONF_GCLK_SDHC0_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val +#endif +// + +/** + * \def SDHC FREQUENCY + * \brief SDHC's Clock frequency + */ +#ifndef CONF_SDHC0_FREQUENCY +#define CONF_SDHC0_FREQUENCY 12000000 +#endif + +/** + * \def SDHC FREQUENCY + * \brief SDHC's Clock slow frequency + */ +#ifndef CONF_SDHC0_SLOW_FREQUENCY +#define CONF_SDHC0_SLOW_FREQUENCY 12000000 +#endif + +// SDHC Clock Settings +// SDHC Clock source + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for SDHC. +// sdhc_gclk_selection +#ifndef CONF_GCLK_SDHC1_SRC +#define CONF_GCLK_SDHC1_SRC GCLK_GENCTRL_SRC_DFLL_Val +#endif + +// SDHC clock slow source + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for SDHC. +// sdhc_slow_gclk_selection +#ifndef CONF_GCLK_SDHC1_SLOW_SRC +#define CONF_GCLK_SDHC1_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val +#endif +// + +/** + * \def SDHC FREQUENCY + * \brief SDHC's Clock frequency + */ +#ifndef CONF_SDHC1_FREQUENCY +#define CONF_SDHC1_FREQUENCY 12000000 +#endif + +/** + * \def SDHC FREQUENCY + * \brief SDHC's Clock slow frequency + */ +#ifndef CONF_SDHC1_SLOW_FREQUENCY +#define CONF_SDHC1_SLOW_FREQUENCY 12000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same51/usbd_config.h b/ports/atmel-samd/asf4_conf/same51/usbd_config.h new file mode 100644 index 0000000000..be1fa3c9e0 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same51/usbd_config.h @@ -0,0 +1,850 @@ +/* Auto-generated config file usbd_config.h */ +#ifndef USBD_CONFIG_H +#define USBD_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ---- USB Device Stack Core Options ---- + +// High Speed Support +// Enable high speed specific descriptors support, e.g., DeviceQualifierDescriptor and OtherSpeedConfiguration Descriptor. +// High speed support require descriptors description array on start, for LS/FS and HS support in first and second place. +// usbd_hs_sp +#ifndef CONF_USBD_HS_SP +#define CONF_USBD_HS_SP 0 +#endif + +// ---- USB Device Stack Composite Options ---- + +// Enable String Descriptors +// usb_composite_str_en +#ifndef CONF_USB_COMPOSITE_STR_EN +#define CONF_USB_COMPOSITE_STR_EN 0 +#endif +// Language IDs +// Language IDs in c format, split by comma (E.g., 0x0409 ...) +// usb_composite_langid +#ifndef CONF_USB_COMPOSITE_LANGID +#define CONF_USB_COMPOSITE_LANGID "0x0409" +#endif + +#ifndef CONF_USB_COMPOSITE_LANGID_DESC +#define CONF_USB_COMPOSITE_LANGID_DESC +#endif +// + +// Composite Device Descriptor + +// bcdUSB +// <0x0200=> USB 2.0 version +// <0x0210=> USB 2.1 version +// usb_composite_bcdusb +#ifndef CONF_USB_COMPOSITE_BCDUSB +#define CONF_USB_COMPOSITE_BCDUSB 0x200 +#endif + +// bMaxPackeSize0 +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_bmaxpksz0 +#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 +#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 +#endif + +// idVender <0x0000-0xFFFF> +// usb_composite_idvender +#ifndef CONF_USB_COMPOSITE_IDVENDER +#define CONF_USB_COMPOSITE_IDVENDER 0x3eb +#endif + +// idProduct <0x0000-0xFFFF> +// usb_composite_idproduct +#ifndef CONF_USB_COMPOSITE_IDPRODUCT +#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421 +#endif + +// bcdDevice <0x0000-0xFFFF> +// usb_composite_bcddevice +#ifndef CONF_USB_COMPOSITE_BCDDEVICE +#define CONF_USB_COMPOSITE_BCDDEVICE 0x100 +#endif + +// Enable string descriptor of iManufact +// usb_composite_imanufact_en +#ifndef CONF_USB_COMPOSITE_IMANUFACT_EN +#define CONF_USB_COMPOSITE_IMANUFACT_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_IMANUFACT +#define CONF_USB_COMPOSITE_IMANUFACT (CONF_USB_COMPOSITE_IMANUFACT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN)) +#endif + +// Unicode string of iManufact +// usb_composite_imanufact_str +#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR +#define CONF_USB_COMPOSITE_IMANUFACT_STR "Atmel" +#endif + +#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR_DESC +#define CONF_USB_COMPOSITE_IMANUFACT_STR_DESC +#endif + +// + +// Enable string descriptor of iProduct +// usb_composite_iproduct_en +#ifndef CONF_USB_COMPOSITE_IPRODUCT_EN +#define CONF_USB_COMPOSITE_IPRODUCT_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_IPRODUCT +#define CONF_USB_COMPOSITE_IPRODUCT \ + (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) +#endif + +// Unicode string of iProduct +// usb_composite_iproduct_str +#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR +#define CONF_USB_COMPOSITE_IPRODUCT_STR "Composite Demo" +#endif + +#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR_DESC +#define CONF_USB_COMPOSITE_IPRODUCT_STR_DESC +#endif + +// + +// Enable string descriptor of iSerialNum +// usb_composite_iserialnum_en +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_EN +#define CONF_USB_COMPOSITE_ISERIALNUM_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_ISERIALNUM +#define CONF_USB_COMPOSITE_ISERIALNUM \ + (CONF_USB_COMPOSITE_ISERIALNUM_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) +#endif + +// Unicode string of iSerialNum +// usb_composite_iserialnum_str +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR +#define CONF_USB_COMPOSITE_ISERIALNUM_STR "123456789ABCDEF" +#endif + +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC +#define CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC +#endif + +// + +// bNumConfigurations <0x01-0xFF> +// usb_composite_bnumconfig +#ifndef CONF_USB_COMPOSITE_BNUMCONFIG +#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1 +#endif + +// + +// Composite Configuration Descriptor +// bConfigurationValue <0x01-0xFF> +// usb_composite_bconfigval +#ifndef CONF_USB_COMPOSITE_BCONFIGVAL +#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1 +#endif +// Enable string descriptor of iConfig +// usb_composite_iconfig_en +#ifndef CONF_USB_COMPOSITE_ICONFIG_EN +#define CONF_USB_COMPOSITE_ICONFIG_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_ICONFIG +#define CONF_USB_COMPOSITE_ICONFIG \ + (CONF_USB_COMPOSITE_ICONFIG_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ + + CONF_USB_COMPOSITE_ICONFIG_EN)) +#endif + +// Unicode string of iConfig +// usb_composite_iconfig_str +#ifndef CONF_USB_COMPOSITE_ICONFIG_STR +#define CONF_USB_COMPOSITE_ICONFIG_STR "" +#endif + +#ifndef CONF_USB_COMPOSITE_ICONFIG_STR_DESC +#define CONF_USB_COMPOSITE_ICONFIG_STR_DESC +#endif + +// + +// bmAttributes +// <0x80=> Bus power supply, not support for remote wakeup +// <0xA0=> Bus power supply, support for remote wakeup +// <0xC0=> Self powered, not support for remote wakeup +// <0xE0=> Self powered, support for remote wakeup +// usb_composite_bmattri +#ifndef CONF_USB_COMPOSITE_BMATTRI +#define CONF_USB_COMPOSITE_BMATTRI 0x80 +#endif + +// bMaxPower <0x00-0xFF> +// usb_composite_bmaxpower +#ifndef CONF_USB_COMPOSITE_BMAXPOWER +#define CONF_USB_COMPOSITE_BMAXPOWER 0x32 +#endif +// + +// CDC ACM Support +// usb_composite_cdc_acm_support +#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN +#define CONF_USB_COMPOSITE_CDC_ACM_EN 0 +#endif + +// CDC ACM Comm Interrupt IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_cdc_acm_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 +#endif + +// CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_cdc_acm_comm_int_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_cdc_acm_data_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 +#endif + +// CDC ACM Data BULK IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_cdc_acm_data_builin_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK IN Endpoint wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// usb_composite_cdc_acm_data_builin_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS 0x200 +#endif + +// CDC ACM Data BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_cdc_acm_data_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 +#endif + +// CDC ACM Data BULK OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_cdc_acm_data_buckout_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK OUT Endpoint wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// usb_composite_cdc_acm_data_buckout_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS 0x200 +#endif + +// CDC ACM Echo Demo generation +// conf_usb_composite_cdc_echo_demo +// Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo. +// Buf is packet buffer for data receive and echo back. +// The buffer is 4 byte aligned to support DMA. +#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO +#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0 +#endif + +// + +// HID Mouse Support +// usb_composite_hid_mouse_support +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN +#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0 +#endif + +// HID Mouse INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_hid_mouse_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83 +#endif + +// HID Mouse INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_hid_mouse_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 +#endif + +// HID Mouse Move Demo generation +// conf_usb_composite_hid_mouse_demo +// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// Button1 and button3 are the pins used for mouse moving left and right. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO +#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0 +#endif + +// + +// HID Keyboard Support +// usb_composite_hid_keyboard_support +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN +#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0 +#endif + +// HID Keyboard INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_hid_keyboard_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84 +#endif + +// HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_hid_keyboard_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8 +#endif + +// HID Keyboard INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_hid_keyboard_intout_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2 +#endif + +// HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_hid_keyboard_intout_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 +#endif + +// HID Keyboard Caps Lock Demo generation +// conf_usb_composite_hid_keyboard_demo +// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// Buffon2 is the pin used for keyboard CAPS LOCK simulation. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO +#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0 +#endif + +// + +// HID Generic Support +// usb_composite_hid_generic_support +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN +#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 +#endif + +// HID Generic INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_hid_generic_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85 +#endif + +// HID Generic INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_hid_generic_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40 +#endif + +// HID Generic INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_hid_generic_intout_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3 +#endif + +// HID Generic INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_generic_intout_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40 +#endif + +// + +// MSC Support +// usb_composite_msc_support +#ifndef CONF_USB_COMPOSITE_MSC_EN +#define CONF_USB_COMPOSITE_MSC_EN 0 +#endif + +// MSC BULK Endpoints wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_msc_bulk_maxpksz +#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ +#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x40 +#endif + +// MSC BULK Endpoints wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// usb_composite_msc_bulk_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS 0x200 +#endif + +// MSC BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_msc_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86 +#endif + +// MSC BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_msc_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x4 +#endif + +// Enable Demo code for Disk LUN handling +// usb_composite_msc_demo_en +#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO +#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1 +#endif + +// Disk access cache/buffer of sectors if non-RAM disk (e.g., SD/MMC) enabled <1-64> +// conf_usb_msc_lun_buf_sectors +#ifndef CONF_USB_MSC_LUN_BUF_SECTORS +#define CONF_USB_MSC_LUN_BUF_SECTORS 4 +#endif + +// Enable Demo for RAM Disk +// conf_usb_msc_lun0_enable +#ifndef CONF_USB_MSC_LUN0_ENABLE +#define CONF_USB_MSC_LUN0_ENABLE 1 +#endif + +#ifndef CONF_USB_MSC_LUN0_TYPE +#define CONF_USB_MSC_LUN0_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun0_rmb +#ifndef CONF_USB_MSC_LUN0_RMB +#define CONF_USB_MSC_LUN0_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN0_ISO +#define CONF_USB_MSC_LUN0_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ECMA +#define CONF_USB_MSC_LUN0_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ANSI +#define CONF_USB_MSC_LUN0_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_REPO +#define CONF_USB_MSC_LUN0_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN0_FACTORY +#define CONF_USB_MSC_LUN0_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT +#define CONF_USB_MSC_LUN0_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT_VERSION +#define CONF_USB_MSC_LUN0_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// Windows will not show disk less than 20K, so 22K is used to reserve more RAM for APP +// conf_usb_msc_lun0_capacity + +#ifndef CONF_USB_MSC_LUN0_CAPACITY +#define CONF_USB_MSC_LUN0_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN0_BLOCK_SIZE +#define CONF_USB_MSC_LUN0_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for SD/MMC Disk +// SD/MMC stack must be added before enable SD/MMC demo +// SD/MMC insert/eject not supported by this simple demo +// conf_usb_msc_lun1_enable +#ifndef CONF_USB_MSC_LUN1_ENABLE +#define CONF_USB_MSC_LUN1_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN1_TYPE +#define CONF_USB_MSC_LUN1_TYPE 0x00 +#endif + +// The disk is removable +// SD/MMC stack must be added before enable SD/MMC demo +// SD/MMC insert/eject not supported by this simple demo +// conf_usb_msc_lun1_rmb +#ifndef CONF_USB_MSC_LUN1_RMB +#define CONF_USB_MSC_LUN1_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN1_ISO +#define CONF_USB_MSC_LUN1_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ECMA +#define CONF_USB_MSC_LUN1_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ANSI +#define CONF_USB_MSC_LUN1_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_REPO +#define CONF_USB_MSC_LUN1_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN1_FACTORY +#define CONF_USB_MSC_LUN1_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT +#define CONF_USB_MSC_LUN1_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT_VERSION +#define CONF_USB_MSC_LUN1_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_CAPACITY +#define CONF_USB_MSC_LUN1_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN1_BLOCK_SIZE +#define CONF_USB_MSC_LUN1_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for LUN 2 +// conf_usb_msc_lun2_enable +#ifndef CONF_USB_MSC_LUN2_ENABLE +#define CONF_USB_MSC_LUN2_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN2_TYPE +#define CONF_USB_MSC_LUN2_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun2_rmb +#ifndef CONF_USB_MSC_LUN2_RMB +#define CONF_USB_MSC_LUN2_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN2_ISO +#define CONF_USB_MSC_LUN2_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_ECMA +#define CONF_USB_MSC_LUN2_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_ANSI +#define CONF_USB_MSC_LUN2_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_REPO +#define CONF_USB_MSC_LUN2_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN2_FACTORY +#define CONF_USB_MSC_LUN2_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_PRODUCT +#define CONF_USB_MSC_LUN2_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_PRODUCT_VERSION +#define CONF_USB_MSC_LUN2_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// conf_usb_msc_lun2_capacity + +#ifndef CONF_USB_MSC_LUN2_CAPACITY +#define CONF_USB_MSC_LUN2_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN2_BLOCK_SIZE +#define CONF_USB_MSC_LUN2_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for LUN 3 +// conf_usb_msc_lun3_enable +#ifndef CONF_USB_MSC_LUN3_ENABLE +#define CONF_USB_MSC_LUN3_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN3_TYPE +#define CONF_USB_MSC_LUN3_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun3_rmb +#ifndef CONF_USB_MSC_LUN3_RMB +#define CONF_USB_MSC_LUN3_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN3_ISO +#define CONF_USB_MSC_LUN3_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_ECMA +#define CONF_USB_MSC_LUN3_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_ANSI +#define CONF_USB_MSC_LUN3_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_REPO +#define CONF_USB_MSC_LUN3_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN3_FACTORY +#define CONF_USB_MSC_LUN3_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_PRODUCT +#define CONF_USB_MSC_LUN3_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_PRODUCT_VERSION +#define CONF_USB_MSC_LUN3_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// conf_usb_msc_lun3_capacity + +#ifndef CONF_USB_MSC_LUN3_CAPACITY +#define CONF_USB_MSC_LUN3_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN3_BLOCK_SIZE +#define CONF_USB_MSC_LUN3_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) +#endif + +// + +// +// + +// <<< end of configuration section >>> + +#endif // USBD_CONFIG_H diff --git a/ports/atmel-samd/boards/feather_m4_can/board.c b/ports/atmel-samd/boards/feather_m4_can/board.c new file mode 100644 index 0000000000..8096b9b8ea --- /dev/null +++ b/ports/atmel-samd/boards/feather_m4_can/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "mpconfigboard.h" + +void board_init(void) { +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.h b/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.h new file mode 100644 index 0000000000..20c4670e25 --- /dev/null +++ b/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.h @@ -0,0 +1,35 @@ +#define MICROPY_HW_BOARD_NAME "Adafruit Feather M4 CAN" +#define MICROPY_HW_MCU_NAME "same51j19a" + +#define CIRCUITPY_MCU_FAMILY samd51 + +// Rev E + +#define MICROPY_HW_LED_STATUS (&pin_PA23) +#define MICROPY_HW_NEOPIXEL (&pin_PB03) + +// These are pins not to reset. +// QSPI Data pins +#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) +// QSPI CS, QSPI SCK and NeoPixel pin +#define MICROPY_PORT_B (PORT_PB03 | PORT_PB10 | PORT_PB11) +#define MICROPY_PORT_C (0) +#define MICROPY_PORT_D (0) + +#define EXTERNAL_FLASH_QSPI_DUAL + +#define BOARD_HAS_CRYSTAL 1 + +#define DEFAULT_I2C_BUS_SCL (&pin_PA13) +#define DEFAULT_I2C_BUS_SDA (&pin_PA12) + +#define DEFAULT_SPI_BUS_SCK (&pin_PA17) +#define DEFAULT_SPI_BUS_MOSI (&pin_PB23) +#define DEFAULT_SPI_BUS_MISO (&pin_PB22) + +#define DEFAULT_UART_BUS_RX (&pin_PB17) +#define DEFAULT_UART_BUS_TX (&pin_PB16) + +// USB is always used internally so skip the pin objects for it. +#define IGNORE_PIN_PA24 1 +#define IGNORE_PIN_PA25 1 diff --git a/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.mk new file mode 100644 index 0000000000..306e7fe42b --- /dev/null +++ b/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.mk @@ -0,0 +1,14 @@ +USB_VID = 0x239A +USB_PID = 0x80CE +USB_PRODUCT = "Feather M4 CAN" +USB_MANUFACTURER = "Adafruit Industries LLC" + +CHIP_VARIANT = SAME51J19A +CHIP_FAMILY = same51 + +QSPI_FLASH_FILESYSTEM = 1 +EXTERNAL_FLASH_DEVICE_COUNT = 1 +EXTERNAL_FLASH_DEVICES = GD25Q16C +LONGINT_IMPL = MPZ + +CIRCUITPY_VECTORIO = 1 diff --git a/ports/atmel-samd/boards/feather_m4_can/pins.c b/ports/atmel-samd/boards/feather_m4_can/pins.c new file mode 100644 index 0000000000..2b67709f87 --- /dev/null +++ b/ports/atmel-samd/boards/feather_m4_can/pins.c @@ -0,0 +1,61 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PA02) }, + + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PA05) }, + + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PB08) }, + + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB09) }, + + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PA04) }, + + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PA06) }, + + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA17) }, + { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PA17) }, + + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB23) }, + { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PB23) }, + + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB22) }, + { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB22) }, + + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PB17) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB17) }, + + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PB16) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB16) }, + + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA20) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA21) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA23) }, + + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PB03) }, + + { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_BATTERY), MP_ROM_PTR(&pin_PB01) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_PB15) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_PB14) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_STANDBY), MP_ROM_PTR(&pin_PB13) }, + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/common-hal/neopixel_write/__init__.c b/ports/atmel-samd/common-hal/neopixel_write/__init__.c index 43c8575cb3..6f2090b983 100644 --- a/ports/atmel-samd/common-hal/neopixel_write/__init__.c +++ b/ports/atmel-samd/common-hal/neopixel_write/__init__.c @@ -34,6 +34,9 @@ #if defined(SAME54) #include "hri/hri_cmcc_e54.h" #include "hri/hri_nvmctrl_e54.h" +#elif defined(SAME51) +#include "hri/hri_cmcc_e51.h" +#include "hri/hri_nvmctrl_e51.h" #elif defined(SAMD51) #include "hri/hri_cmcc_d51.h" #include "hri/hri_nvmctrl_d51.h" diff --git a/ports/atmel-samd/peripherals b/ports/atmel-samd/peripherals index 0f5f1522d0..15fd96f4d8 160000 --- a/ports/atmel-samd/peripherals +++ b/ports/atmel-samd/peripherals @@ -1 +1 @@ -Subproject commit 0f5f1522d09c8fa7d858edec484a994c21c59668 +Subproject commit 15fd96f4d8c38d5490767ea09469b82a231a768d diff --git a/ports/atmel-samd/supervisor/internal_flash.c b/ports/atmel-samd/supervisor/internal_flash.c index ecb59f836e..4c7ca0dc76 100644 --- a/ports/atmel-samd/supervisor/internal_flash.c +++ b/ports/atmel-samd/supervisor/internal_flash.c @@ -39,6 +39,9 @@ #ifdef SAMD21 #include "hpl/pm/hpl_pm_base.h" #endif +#ifdef SAME51 +#include "hri/hri_mclk_e51.h" +#endif #ifdef SAME54 #include "hri/hri_mclk_e54.h" #endif diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 6352afb1d4..8d52c30c53 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -44,6 +44,9 @@ #include "hri/hri_pm_d21.h" #elif defined(SAME54) #include "hri/hri_rstc_e54.h" +#elif defined(SAME51) +#include "sam.h" +#include "hri/hri_rstc_e51.h" #elif defined(SAMD51) #include "hri/hri_rstc_d51.h" #else diff --git a/ports/atmel-samd/supervisor/same51_cpu.s b/ports/atmel-samd/supervisor/same51_cpu.s new file mode 100755 index 0000000000..9e6807a5e2 --- /dev/null +++ b/ports/atmel-samd/supervisor/same51_cpu.s @@ -0,0 +1,27 @@ +.syntax unified +.cpu cortex-m4 +.thumb +.text +.align 2 + +@ uint cpu_get_regs_and_sp(r0=uint regs[10]) +.global cpu_get_regs_and_sp +.thumb +.thumb_func +.type cpu_get_regs_and_sp, %function +cpu_get_regs_and_sp: +@ store registers into given array +str r4, [r0], #4 +str r5, [r0], #4 +str r6, [r0], #4 +str r7, [r0], #4 +str r8, [r0], #4 +str r9, [r0], #4 +str r10, [r0], #4 +str r11, [r0], #4 +str r12, [r0], #4 +str r13, [r0], #4 + +@ return the sp +mov r0, sp +bx lr From baa2d7fd56c65f0003f4a5b17849c6bc2f3d37a7 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Tue, 8 Sep 2020 14:08:52 -0500 Subject: [PATCH 20/91] add new board to CI --- .github/workflows/build.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 6bb9612f81..fef3da615c 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -208,6 +208,7 @@ jobs: - "feather_m0_rfm69" - "feather_m0_rfm9x" - "feather_m0_supersized" + - "feather_m4_can" - "feather_m4_express" - "feather_m7_1011" - "feather_mimxrt1011" From b49099c8f3dd957a3e7aa34a62cf68bcf4bd024b Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Tue, 8 Sep 2020 15:31:13 -0500 Subject: [PATCH 21/91] additional asf4 updates --- ports/atmel-samd/asf4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atmel-samd/asf4 b/ports/atmel-samd/asf4 index f99e36fb00..1b87f18f80 160000 --- a/ports/atmel-samd/asf4 +++ b/ports/atmel-samd/asf4 @@ -1 +1 @@ -Subproject commit f99e36fb008588bd9ff005099b3b89b7952fcfba +Subproject commit 1b87f18f8091f258e63f85cef54bcc7bafd44598 From f95ad7b27c040e54daeb4c71d6bb6c35844be66e Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Thu, 10 Sep 2020 15:37:43 -0400 Subject: [PATCH 22/91] Fix reset pin null reference, construct error null reference --- shared-module/displayio/FourWire.c | 4 +++- shared-module/displayio/I2CDisplay.c | 5 ++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/shared-module/displayio/FourWire.c b/shared-module/displayio/FourWire.c index 17e8cfa1d7..7261162089 100644 --- a/shared-module/displayio/FourWire.c +++ b/shared-module/displayio/FourWire.c @@ -76,7 +76,9 @@ void common_hal_displayio_fourwire_deinit(displayio_fourwire_obj_t* self) { common_hal_reset_pin(self->command.pin); common_hal_reset_pin(self->chip_select.pin); - common_hal_reset_pin(self->reset.pin); + if (self->reset.pin) { + common_hal_reset_pin(self->reset.pin); + } } bool common_hal_displayio_fourwire_reset(mp_obj_t obj) { diff --git a/shared-module/displayio/I2CDisplay.c b/shared-module/displayio/I2CDisplay.c index 0c8f2e69a9..9e9e178812 100644 --- a/shared-module/displayio/I2CDisplay.c +++ b/shared-module/displayio/I2CDisplay.c @@ -53,6 +53,7 @@ void common_hal_displayio_i2cdisplay_construct(displayio_i2cdisplay_obj_t* self, // Probe the bus to see if a device acknowledges the given address. if (!common_hal_busio_i2c_probe(i2c, device_address)) { + self->base.type = &mp_type_NoneType; mp_raise_ValueError_varg(translate("Unable to find I2C Display at %x"), device_address); } @@ -71,7 +72,9 @@ void common_hal_displayio_i2cdisplay_deinit(displayio_i2cdisplay_obj_t* self) { common_hal_busio_i2c_deinit(self->bus); } - common_hal_reset_pin(self->reset.pin); + if (self->reset.pin) { + common_hal_reset_pin(self->reset.pin); + } } bool common_hal_displayio_i2cdisplay_reset(mp_obj_t obj) { From c7c90f47b0986e0f8c4bcba574bccc2352bf700f Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Thu, 10 Sep 2020 17:32:20 -0700 Subject: [PATCH 23/91] Add non-DMA SPI support. This fixes SPI with PSRAM allocated buffers. DMA with SPI2 was attempted but produced junk output. This manual copy is less than 2x slower than DMA when not interrupted. Fixes #3339 --- ports/esp32s2/common-hal/busio/SPI.c | 41 ++++++++++++++++++++-------- ports/esp32s2/common-hal/busio/SPI.h | 4 --- 2 files changed, 29 insertions(+), 16 deletions(-) diff --git a/ports/esp32s2/common-hal/busio/SPI.c b/ports/esp32s2/common-hal/busio/SPI.c index a22075cd59..350580ea84 100644 --- a/ports/esp32s2/common-hal/busio/SPI.c +++ b/ports/esp32s2/common-hal/busio/SPI.c @@ -183,9 +183,6 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, // spi_hal_init clears the given hal context so set everything after. spi_hal_init(hal, host_id); - hal->dmadesc_tx = &self->tx_dma; - hal->dmadesc_rx = &self->rx_dma; - hal->dmadesc_n = 1; // We don't use native CS. // hal->cs_setup = 0; @@ -196,7 +193,6 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, hal->half_duplex = 0; // hal->tx_lsbfirst = 0; // hal->rx_lsbfirst = 0; - hal->dma_enabled = 1; hal->no_compensate = 1; // Ignore CS bits @@ -315,16 +311,34 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou hal->rcv_buffer = NULL; // Reset timing_conf in case we've moved since the last time we used it. hal->timing_conf = &self->timing_conf; + lldesc_t tx_dma __attribute__((aligned(16))); + lldesc_t rx_dma __attribute__((aligned(16))); + hal->dmadesc_tx = &tx_dma; + hal->dmadesc_rx = &rx_dma; + hal->dmadesc_n = 1; + + size_t burst_length; + // If both of the incoming pointers are DMA capable then use DMA. Otherwise, do + // bursts the size of the SPI data buffer without DMA. + if ((data_out == NULL || esp_ptr_dma_capable(data_out)) && + (data_in == NULL || esp_ptr_dma_capable(data_out))) { + hal->dma_enabled = 1; + burst_length = LLDESC_MAX_NUM_PER_DESC; + } else { + hal->dma_enabled = 0; + burst_length = sizeof(hal->hw->data_buf); + } + // This rounds up. - size_t dma_count = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC; - for (size_t i = 0; i < dma_count; i++) { - size_t offset = LLDESC_MAX_NUM_PER_DESC * i; - size_t dma_len = len - offset; - if (dma_len > LLDESC_MAX_NUM_PER_DESC) { - dma_len = LLDESC_MAX_NUM_PER_DESC; + size_t burst_count = (len + burst_length - 1) / burst_length; + for (size_t i = 0; i < burst_count; i++) { + size_t offset = burst_length * i; + size_t this_length = len - offset; + if (this_length > burst_length) { + this_length = burst_length; } - hal->tx_bitlen = dma_len * self->bits; - hal->rx_bitlen = dma_len * self->bits; + hal->tx_bitlen = this_length * self->bits; + hal->rx_bitlen = this_length * self->bits; if (data_out != NULL) { hal->send_buffer = (uint8_t*) data_out + offset; } @@ -341,6 +355,9 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou } spi_hal_fetch_result(hal); } + hal->dmadesc_tx = NULL; + hal->dmadesc_rx = NULL; + hal->dmadesc_n = 0; return true; } diff --git a/ports/esp32s2/common-hal/busio/SPI.h b/ports/esp32s2/common-hal/busio/SPI.h index 6d82038317..38fbe42ffc 100644 --- a/ports/esp32s2/common-hal/busio/SPI.h +++ b/ports/esp32s2/common-hal/busio/SPI.h @@ -44,10 +44,6 @@ typedef struct { spi_hal_context_t hal_context; spi_hal_timing_conf_t timing_conf; intr_handle_t interrupt; - // IDF allocates these in DMA accessible memory so they may need to move when - // we use external RAM for CircuitPython. - lldesc_t tx_dma; - lldesc_t rx_dma; uint32_t target_frequency; int32_t real_frequency; uint8_t polarity; From 40ab5c6b21ff93ad11ca51dc66d3613dcd77e5ef Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Sat, 12 Sep 2020 10:10:18 -0500 Subject: [PATCH 24/91] compression: Implement ciscorn's dictionary approach MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Massive savings. Thanks so much @ciscorn for providing the initial code for choosing the dictionary. This adds a bit of time to the build, both to find the dictionary but also because (for reasons I don't fully understand), the binary search in the compress() function no longer worked and had to be replaced with a linear search. I think this is because the intended invariant is that for codebook entries that encode to the same number of bits, the entries are ordered in ascending value. However, I mis-placed the transition from "words" to "byte/char values" so the codebook entries for words are in word-order rather than their code order. Because this price is only paid at build time, I didn't care to determine exactly where the correct fix was. I also commented out a line to produce the "estimated total memory size" -- at least on the unix build with TRANSLATION=ja, this led to a build time KeyError trying to compute the codebook size for all the strings. I think this occurs because some single unicode code point ('ァ') is no longer present as itself in the compressed strings, due to always being replaced by a word. As promised, this seems to save hundreds of bytes in the German translation on the trinket m0. Testing performed: - built trinket_m0 in several languages - built and ran unix port in several languages (en, de_DE, ja) and ran simple error-producing codes like ./micropython -c '1/0' --- py/makeqstrdata.py | 197 +++++++++++++++++++++++----------- supervisor/shared/translate.c | 21 ++-- 2 files changed, 152 insertions(+), 66 deletions(-) diff --git a/py/makeqstrdata.py b/py/makeqstrdata.py index 721fa83206..57635807dc 100644 --- a/py/makeqstrdata.py +++ b/py/makeqstrdata.py @@ -100,77 +100,153 @@ def translate(translation_file, i18ns): translations.append((original, translation)) return translations -def frequent_ngrams(corpus, sz, n): - return collections.Counter(corpus[i:i+sz] for i in range(len(corpus)-sz)).most_common(n) +class TextSplitter: + def __init__(self, words): + words.sort(key=lambda x: len(x), reverse=True) + self.words = set(words) + self.pat = re.compile("|".join(re.escape(w) for w in words) + "|.", flags=re.DOTALL) -def encode_ngrams(translation, ngrams): - if len(ngrams) > 32: - start = 0xe000 - else: - start = 0x80 - for i, g in enumerate(ngrams): - translation = translation.replace(g, chr(start + i)) - return translation + def iter_words(self, text): + s = [] + for m in self.pat.finditer(text): + t = m.group(0) + if t in self.words: + if s: + yield (False, "".join(s)) + s = [] + yield (True, t) + else: + s.append(t) + if s: + yield (False, "".join(s)) -def decode_ngrams(compressed, ngrams): - if len(ngrams) > 32: - start, end = 0xe000, 0xf8ff - else: - start, end = 0x80, 0x9f - return "".join(ngrams[ord(c) - start] if (start <= ord(c) <= end) else c for c in compressed) + def iter(self, text): + s = [] + for m in self.pat.finditer(text): + yield m.group(0) + +def iter_substrings(s, minlen, maxlen): + maxlen = min(len(s), maxlen) + for n in range(minlen, maxlen + 1): + for begin in range(0, len(s) - n + 1): + yield s[begin : begin + n] + +def compute_huffman_coding(translations, compression_filename): + texts = [t[1] for t in translations] + all_strings_concat = "".join(texts) + words = [] + max_ord = 0 + begin_unused = 128 + end_unused = 256 + for text in texts: + for c in text: + ord_c = ord(c) + max_ord = max(max_ord, ord_c) + if 128 <= ord_c < 256: + end_unused = min(ord_c, end_unused) + max_words = end_unused - begin_unused + char_size = 1 if max_ord < 256 else 2 + + sum_word_len = 0 + while True: + extractor = TextSplitter(words) + counter = collections.Counter() + for t in texts: + for (found, word) in extractor.iter_words(t): + if not found: + for substr in iter_substrings(word, minlen=2, maxlen=9): + counter[substr] += 1 + + scores = sorted( + ( + # I don't know why this works good. This could be better. + (s, (len(s) - 1) ** ((max(occ - 2, 1) + 0.5) ** 0.8), occ) + for (s, occ) in counter.items() + ), + key=lambda x: x[1], + reverse=True, + ) + + w = None + for (s, score, occ) in scores: + if score < 0: + break + if len(s) > 1: + w = s + break + + if not w: + break + if len(w) + sum_word_len > 256: + break + if len(words) == max_words: + break + words.append(w) + sum_word_len += len(w) + + extractor = TextSplitter(words) + counter = collections.Counter() + for t in texts: + for atom in extractor.iter(t): + counter[atom] += 1 + cb = huffman.codebook(counter.items()) + + word_start = begin_unused + word_end = word_start + len(words) - 1 + print("// # words", len(words)) + print("// words", words) -def compute_huffman_coding(translations, qstrs, compression_filename): - all_strings = [x[1] for x in translations] - all_strings_concat = "".join(all_strings) - ngrams = [i[0] for i in frequent_ngrams(all_strings_concat, 2, 32)] - all_strings_concat = encode_ngrams(all_strings_concat, ngrams) - counts = collections.Counter(all_strings_concat) - cb = huffman.codebook(counts.items()) values = [] length_count = {} renumbered = 0 last_l = None canonical = {} - for ch, code in sorted(cb.items(), key=lambda x: (len(x[1]), x[0])): - values.append(ch) + for atom, code in sorted(cb.items(), key=lambda x: (len(x[1]), x[0])): + values.append(atom) l = len(code) if l not in length_count: length_count[l] = 0 length_count[l] += 1 if last_l: renumbered <<= (l - last_l) - canonical[ch] = '{0:0{width}b}'.format(renumbered, width=l) - s = C_ESCAPES.get(ch, ch) - print("//", ord(ch), s, counts[ch], canonical[ch], renumbered) + canonical[atom] = '{0:0{width}b}'.format(renumbered, width=l) + #print(f"atom={repr(atom)} code={code}", file=sys.stderr) + if len(atom) > 1: + o = words.index(atom) + 0x80 + s = "".join(C_ESCAPES.get(ch1, ch1) for ch1 in atom) + else: + s = C_ESCAPES.get(atom, atom) + o = ord(atom) + print("//", o, s, counter[atom], canonical[atom], renumbered) renumbered += 1 last_l = l lengths = bytearray() print("// length count", length_count) - print("// bigrams", ngrams) + for i in range(1, max(length_count) + 2): lengths.append(length_count.get(i, 0)) print("// values", values, "lengths", len(lengths), lengths) - ngramdata = [ord(ni) for i in ngrams for ni in i] - print("// estimated total memory size", len(lengths) + 2*len(values) + 2 * len(ngramdata) + sum((len(cb[u]) + 7)//8 for u in all_strings_concat)) + maxord = max(ord(u) for u in values if len(u) == 1) + values_type = "uint16_t" if maxord > 255 else "uint8_t" + ch_size = 1 if maxord > 255 else 2 + print("//", values, lengths) + values = [(atom if len(atom) == 1 else chr(0x80 + words.index(atom))) for atom in values] print("//", values, lengths) - values_type = "uint16_t" if max(ord(u) for u in values) > 255 else "uint8_t" max_translation_encoded_length = max(len(translation.encode("utf-8")) for original,translation in translations) with open(compression_filename, "w") as f: f.write("const uint8_t lengths[] = {{ {} }};\n".format(", ".join(map(str, lengths)))) f.write("const {} values[] = {{ {} }};\n".format(values_type, ", ".join(str(ord(u)) for u in values))) f.write("#define compress_max_length_bits ({})\n".format(max_translation_encoded_length.bit_length())) - f.write("const {} bigrams[] = {{ {} }};\n".format(values_type, ", ".join(str(u) for u in ngramdata))) - if len(ngrams) > 32: - bigram_start = 0xe000 - else: - bigram_start = 0x80 - bigram_end = bigram_start + len(ngrams) - 1 # End is inclusive - f.write("#define bigram_start {}\n".format(bigram_start)) - f.write("#define bigram_end {}\n".format(bigram_end)) - return values, lengths, ngrams + f.write("const {} words[] = {{ {} }};\n".format(values_type, ", ".join(str(ord(c)) for w in words for c in w))) + f.write("const uint8_t wlen[] = {{ {} }};\n".format(", ".join(str(len(w)) for w in words))) + f.write("#define word_start {}\n".format(word_start)) + f.write("#define word_end {}\n".format(word_end)) + + extractor = TextSplitter(words) + return values, lengths, words, extractor def decompress(encoding_table, encoded, encoded_length_bits): - values, lengths, ngrams = encoding_table + values, lengths, words, extractor = encoding_table dec = [] this_byte = 0 this_bit = 7 @@ -218,7 +294,8 @@ def decompress(encoding_table, encoded, encoded_length_bits): searched_length += lengths[bit_length] v = values[searched_length + bits - max_code] - v = decode_ngrams(v, ngrams) + if v >= chr(0x80) and v < chr(0x80 + len(words)): + v = words[ord(v) - 0x80] i += len(v.encode('utf-8')) dec.append(v) return ''.join(dec) @@ -226,8 +303,8 @@ def decompress(encoding_table, encoded, encoded_length_bits): def compress(encoding_table, decompressed, encoded_length_bits, len_translation_encoded): if not isinstance(decompressed, str): raise TypeError() - values, lengths, ngrams = encoding_table - decompressed = encode_ngrams(decompressed, ngrams) + values, lengths, words, extractor = encoding_table + enc = bytearray(len(decompressed) * 3) #print(decompressed) #print(lengths) @@ -246,9 +323,15 @@ def compress(encoding_table, decompressed, encoded_length_bits, len_translation_ else: current_bit -= 1 - for c in decompressed: - #print() - #print("char", c, values.index(c)) + #print("values = ", values, file=sys.stderr) + for atom in extractor.iter(decompressed): + #print("", file=sys.stderr) + if len(atom) > 1: + c = chr(0x80 + words.index(atom)) + else: + c = atom + assert c in values + start = 0 end = lengths[0] bits = 1 @@ -258,18 +341,12 @@ def compress(encoding_table, decompressed, encoded_length_bits, len_translation_ s = start e = end #print("{0:0{width}b}".format(code, width=bits)) - # Binary search! - while e > s: - midpoint = (s + e) // 2 - #print(s, e, midpoint) - if values[midpoint] == c: - compressed = code + (midpoint - start) - #print("found {0:0{width}b}".format(compressed, width=bits)) + # Linear search! + for i in range(s, e): + if values[i] == c: + compressed = code + (i - start) + #print("found {0:0{width}b}".format(compressed, width=bits), file=sys.stderr) break - elif c < values[midpoint]: - e = midpoint - else: - s = midpoint + 1 code += end - start code <<= 1 start = end @@ -452,7 +529,7 @@ if __name__ == "__main__": if args.translation: i18ns = sorted(i18ns) translations = translate(args.translation, i18ns) - encoding_table = compute_huffman_coding(translations, qstrs, args.compression_filename) + encoding_table = compute_huffman_coding(translations, args.compression_filename) print_qstr_data(encoding_table, qcfgs, qstrs, translations) else: print_qstr_enums(qstrs) diff --git a/supervisor/shared/translate.c b/supervisor/shared/translate.c index 5cd7b8dd88..cc0de7f619 100644 --- a/supervisor/shared/translate.c +++ b/supervisor/shared/translate.c @@ -47,13 +47,22 @@ STATIC int put_utf8(char *buf, int u) { if(u <= 0x7f) { *buf = u; return 1; - } else if(bigram_start <= u && u <= bigram_end) { - int n = (u - 0x80) * 2; - // (note that at present, entries in the bigrams table are - // guaranteed not to represent bigrams themselves, so this adds + } else if(word_start <= u && u <= word_end) { + int n = (u - 0x80); + size_t off = 0; + for(int i=0; i> 6); *buf = 0b10000000 | (u & 0b00111111); From 15964a4750d9eb1a34317c166d9bde5f40c9878d Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Sat, 12 Sep 2020 19:39:35 -0500 Subject: [PATCH 25/91] makeqstrdata: Avoid encoding problems Most users and the CI system are running in configurations where Python configures stdout and stderr in UTF-8 mode. However, Windows is different, setting values like CP1252. This led to a build failure on Windows, because makeqstrdata printed Unicode strings to its stdout, expecting them to be encoded as UTF-8. This script is writing (stdout) to a compiler input file and potentially printing messages (stderr) to a log or console. Explicitly configure stdout to use utf-8 to get consistent behavior on all platforms, and configure stderr so that if any log/diagnostic messages are printed that cannot be displayed correctly, they are still displayed instead of creating an error while trying to print the diagnostic information. I considered setting the encodings both to ascii, but this would just be occasionally inconvenient to developers like me who want to show diagnostic info on stderr and in comments while working with the compression code. Closes: #3408 --- py/makeqstrdata.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/py/makeqstrdata.py b/py/makeqstrdata.py index 57635807dc..e30f120e61 100644 --- a/py/makeqstrdata.py +++ b/py/makeqstrdata.py @@ -16,6 +16,9 @@ import collections import gettext import os.path +sys.stdout.reconfigure(encoding='utf-8') +sys.stderr.reconfigure(errors='backslashreplace') + py = os.path.dirname(sys.argv[0]) top = os.path.dirname(py) From d18d79ac4709364c2371e2eaefd8f96bb20802e7 Mon Sep 17 00:00:00 2001 From: Taku Fukada Date: Mon, 14 Sep 2020 01:25:13 +0900 Subject: [PATCH 26/91] Small improvements to the dictionary compression --- py/makeqstrdata.py | 137 ++++++++++++++-------------------- supervisor/shared/translate.c | 12 +-- 2 files changed, 61 insertions(+), 88 deletions(-) diff --git a/py/makeqstrdata.py b/py/makeqstrdata.py index e30f120e61..0060217917 100644 --- a/py/makeqstrdata.py +++ b/py/makeqstrdata.py @@ -12,6 +12,7 @@ from __future__ import print_function import re import sys +from math import log import collections import gettext import os.path @@ -111,9 +112,10 @@ class TextSplitter: def iter_words(self, text): s = [] + words = self.words for m in self.pat.finditer(text): t = m.group(0) - if t in self.words: + if t in words: if s: yield (False, "".join(s)) s = [] @@ -124,33 +126,35 @@ class TextSplitter: yield (False, "".join(s)) def iter(self, text): - s = [] for m in self.pat.finditer(text): yield m.group(0) def iter_substrings(s, minlen, maxlen): - maxlen = min(len(s), maxlen) + len_s = len(s) + maxlen = min(len_s, maxlen) for n in range(minlen, maxlen + 1): - for begin in range(0, len(s) - n + 1): + for begin in range(0, len_s - n + 1): yield s[begin : begin + n] def compute_huffman_coding(translations, compression_filename): texts = [t[1] for t in translations] - all_strings_concat = "".join(texts) words = [] + + start_unused = 0x80 + end_unused = 0xff max_ord = 0 - begin_unused = 128 - end_unused = 256 for text in texts: for c in text: ord_c = ord(c) - max_ord = max(max_ord, ord_c) - if 128 <= ord_c < 256: + max_ord = max(ord_c, max_ord) + if 0x80 <= ord_c < 0xff: end_unused = min(ord_c, end_unused) - max_words = end_unused - begin_unused - char_size = 1 if max_ord < 256 else 2 + max_words = end_unused - 0x80 - sum_word_len = 0 + values_type = "uint16_t" if max_ord > 255 else "uint8_t" + max_words_len = 160 if max_ord > 255 else 255 + + sum_len = 0 while True: extractor = TextSplitter(words) counter = collections.Counter() @@ -162,30 +166,30 @@ def compute_huffman_coding(translations, compression_filename): scores = sorted( ( - # I don't know why this works good. This could be better. - (s, (len(s) - 1) ** ((max(occ - 2, 1) + 0.5) ** 0.8), occ) + (s, (len(s) - 1) ** log(max(occ - 2, 1)), occ) for (s, occ) in counter.items() ), key=lambda x: x[1], reverse=True, ) - w = None + word = None for (s, score, occ) in scores: - if score < 0: + if occ < 5: + continue + if score < 5: break - if len(s) > 1: - w = s - break - - if not w: + word = s break - if len(w) + sum_word_len > 256: + + if not word: + break + if sum_len + len(word) - 2 > max_words_len: break if len(words) == max_words: break - words.append(w) - sum_word_len += len(w) + words.append(word) + sum_len += len(word) - 2 extractor = TextSplitter(words) counter = collections.Counter() @@ -194,7 +198,7 @@ def compute_huffman_coding(translations, compression_filename): counter[atom] += 1 cb = huffman.codebook(counter.items()) - word_start = begin_unused + word_start = start_unused word_end = word_start + len(words) - 1 print("// # words", len(words)) print("// words", words) @@ -202,18 +206,18 @@ def compute_huffman_coding(translations, compression_filename): values = [] length_count = {} renumbered = 0 - last_l = None + last_length = None canonical = {} for atom, code in sorted(cb.items(), key=lambda x: (len(x[1]), x[0])): values.append(atom) - l = len(code) - if l not in length_count: - length_count[l] = 0 - length_count[l] += 1 - if last_l: - renumbered <<= (l - last_l) - canonical[atom] = '{0:0{width}b}'.format(renumbered, width=l) - #print(f"atom={repr(atom)} code={code}", file=sys.stderr) + length = len(code) + if length not in length_count: + length_count[length] = 0 + length_count[length] += 1 + if last_length: + renumbered <<= (length - last_length) + canonical[atom] = '{0:0{width}b}'.format(renumbered, width=length) + # print(f"atom={repr(atom)} code={code}", file=sys.stderr) if len(atom) > 1: o = words.index(atom) + 0x80 s = "".join(C_ESCAPES.get(ch1, ch1) for ch1 in atom) @@ -222,34 +226,37 @@ def compute_huffman_coding(translations, compression_filename): o = ord(atom) print("//", o, s, counter[atom], canonical[atom], renumbered) renumbered += 1 - last_l = l + last_length = length lengths = bytearray() print("// length count", length_count) for i in range(1, max(length_count) + 2): lengths.append(length_count.get(i, 0)) print("// values", values, "lengths", len(lengths), lengths) - maxord = max(ord(u) for u in values if len(u) == 1) - values_type = "uint16_t" if maxord > 255 else "uint8_t" - ch_size = 1 if maxord > 255 else 2 + print("//", values, lengths) values = [(atom if len(atom) == 1 else chr(0x80 + words.index(atom))) for atom in values] print("//", values, lengths) - max_translation_encoded_length = max(len(translation.encode("utf-8")) for original,translation in translations) + max_translation_encoded_length = max( + len(translation.encode("utf-8")) for (original, translation) in translations) + + wends = list(len(w) - 2 for w in words) + for i in range(1, len(wends)): + wends[i] += wends[i - 1] + with open(compression_filename, "w") as f: f.write("const uint8_t lengths[] = {{ {} }};\n".format(", ".join(map(str, lengths)))) f.write("const {} values[] = {{ {} }};\n".format(values_type, ", ".join(str(ord(u)) for u in values))) f.write("#define compress_max_length_bits ({})\n".format(max_translation_encoded_length.bit_length())) f.write("const {} words[] = {{ {} }};\n".format(values_type, ", ".join(str(ord(c)) for w in words for c in w))) - f.write("const uint8_t wlen[] = {{ {} }};\n".format(", ".join(str(len(w)) for w in words))) + f.write("const uint8_t wends[] = {{ {} }};\n".format(", ".join(str(p) for p in wends))) f.write("#define word_start {}\n".format(word_start)) f.write("#define word_end {}\n".format(word_end)) - extractor = TextSplitter(words) - return values, lengths, words, extractor + return (values, lengths, words, canonical, extractor) def decompress(encoding_table, encoded, encoded_length_bits): - values, lengths, words, extractor = encoding_table + (values, lengths, words, _, _) = encoding_table dec = [] this_byte = 0 this_bit = 7 @@ -306,66 +313,32 @@ def decompress(encoding_table, encoded, encoded_length_bits): def compress(encoding_table, decompressed, encoded_length_bits, len_translation_encoded): if not isinstance(decompressed, str): raise TypeError() - values, lengths, words, extractor = encoding_table + (_, _, _, canonical, extractor) = encoding_table enc = bytearray(len(decompressed) * 3) - #print(decompressed) - #print(lengths) current_bit = 7 current_byte = 0 - code = len_translation_encoded - bits = encoded_length_bits+1 + bits = encoded_length_bits + 1 for i in range(bits - 1, 0, -1): if len_translation_encoded & (1 << (i - 1)): enc[current_byte] |= 1 << current_bit if current_bit == 0: current_bit = 7 - #print("packed {0:0{width}b}".format(enc[current_byte], width=8)) current_byte += 1 else: current_bit -= 1 - #print("values = ", values, file=sys.stderr) for atom in extractor.iter(decompressed): - #print("", file=sys.stderr) - if len(atom) > 1: - c = chr(0x80 + words.index(atom)) - else: - c = atom - assert c in values - - start = 0 - end = lengths[0] - bits = 1 - compressed = None - code = 0 - while compressed is None: - s = start - e = end - #print("{0:0{width}b}".format(code, width=bits)) - # Linear search! - for i in range(s, e): - if values[i] == c: - compressed = code + (i - start) - #print("found {0:0{width}b}".format(compressed, width=bits), file=sys.stderr) - break - code += end - start - code <<= 1 - start = end - end += lengths[bits] - bits += 1 - #print("next bit", bits) - - for i in range(bits - 1, 0, -1): - if compressed & (1 << (i - 1)): + for b in canonical[atom]: + if b == "1": enc[current_byte] |= 1 << current_bit if current_bit == 0: current_bit = 7 - #print("packed {0:0{width}b}".format(enc[current_byte], width=8)) current_byte += 1 else: current_bit -= 1 + if current_bit != 7: current_byte += 1 return enc[:current_byte] diff --git a/supervisor/shared/translate.c b/supervisor/shared/translate.c index cc0de7f619..44544c98dd 100644 --- a/supervisor/shared/translate.c +++ b/supervisor/shared/translate.c @@ -48,17 +48,17 @@ STATIC int put_utf8(char *buf, int u) { *buf = u; return 1; } else if(word_start <= u && u <= word_end) { - int n = (u - 0x80); - size_t off = 0; - for(int i=0; i 0) { + pos = wends[n - 1] + (n * 2); } int ret = 0; // note that at present, entries in the words table are // guaranteed not to represent words themselves, so this adds // at most 1 level of recursive call - for(int i=0; i Date: Wed, 2 Sep 2020 15:42:57 +0200 Subject: [PATCH 27/91] camera: Implement new library for camera --- py/circuitpy_defns.mk | 6 + py/circuitpy_mpconfig.h | 8 ++ py/circuitpy_mpconfig.mk | 3 + shared-bindings/camera/Camera.c | 178 +++++++++++++++++++++++++++++ shared-bindings/camera/Camera.h | 45 ++++++++ shared-bindings/camera/ImageSize.c | 163 ++++++++++++++++++++++++++ shared-bindings/camera/ImageSize.h | 59 ++++++++++ shared-bindings/camera/__init__.c | 50 ++++++++ 8 files changed, 512 insertions(+) create mode 100644 shared-bindings/camera/Camera.c create mode 100644 shared-bindings/camera/Camera.h create mode 100644 shared-bindings/camera/ImageSize.c create mode 100644 shared-bindings/camera/ImageSize.h create mode 100644 shared-bindings/camera/__init__.c diff --git a/py/circuitpy_defns.mk b/py/circuitpy_defns.mk index 0e87287c13..f72c821e53 100644 --- a/py/circuitpy_defns.mk +++ b/py/circuitpy_defns.mk @@ -139,6 +139,9 @@ endif ifeq ($(CIRCUITPY_BUSIO),1) SRC_PATTERNS += busio/% bitbangio/OneWire.% endif +ifeq ($(CIRCUITPY_CAMERA),1) +SRC_PATTERNS += camera/% +endif ifeq ($(CIRCUITPY_COUNTIO),1) SRC_PATTERNS += countio/% endif @@ -310,6 +313,9 @@ SRC_COMMON_HAL_ALL = \ busio/SPI.c \ busio/UART.c \ busio/__init__.c \ + camera/__init__.c \ + camera/Camera.c \ + camera/ImageSize.c \ countio/Counter.c \ countio/__init__.c \ digitalio/DigitalInOut.c \ diff --git a/py/circuitpy_mpconfig.h b/py/circuitpy_mpconfig.h index 0fafbe876d..4272de2ec7 100644 --- a/py/circuitpy_mpconfig.h +++ b/py/circuitpy_mpconfig.h @@ -329,6 +329,13 @@ extern const struct _mp_obj_module_t busio_module; #define BUSIO_MODULE #endif +#if CIRCUITPY_CAMERA +extern const struct _mp_obj_module_t camera_module; +#define CAMERA_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_camera), (mp_obj_t)&camera_module }, +#else +#define CAMERA_MODULE +#endif + #if CIRCUITPY_COUNTIO extern const struct _mp_obj_module_t countio_module; #define COUNTIO_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_countio), (mp_obj_t)&countio_module }, @@ -758,6 +765,7 @@ extern const struct _mp_obj_module_t wifi_module; BLEIO_MODULE \ BOARD_MODULE \ BUSIO_MODULE \ + CAMERA_MODULE \ COUNTIO_MODULE \ DIGITALIO_MODULE \ DISPLAYIO_MODULE \ diff --git a/py/circuitpy_mpconfig.mk b/py/circuitpy_mpconfig.mk index a2da9c42f5..54bdefc6dd 100644 --- a/py/circuitpy_mpconfig.mk +++ b/py/circuitpy_mpconfig.mk @@ -90,6 +90,9 @@ CFLAGS += -DCIRCUITPY_BOARD=$(CIRCUITPY_BOARD) CIRCUITPY_BUSIO ?= 1 CFLAGS += -DCIRCUITPY_BUSIO=$(CIRCUITPY_BUSIO) +CIRCUITPY_CAMERA ?= 0 +CFLAGS += -DCIRCUITPY_CAMERA=$(CIRCUITPY_CAMERA) + CIRCUITPY_DIGITALIO ?= 1 CFLAGS += -DCIRCUITPY_DIGITALIO=$(CIRCUITPY_DIGITALIO) diff --git a/shared-bindings/camera/Camera.c b/shared-bindings/camera/Camera.c new file mode 100644 index 0000000000..3855fed3c7 --- /dev/null +++ b/shared-bindings/camera/Camera.c @@ -0,0 +1,178 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/objproperty.h" +#include "py/runtime.h" + +#include "shared-bindings/camera/Camera.h" +#include "shared-bindings/util.h" + +//| class Camera: +//| """The class to control camera. +//| +//| Usage:: +//| +//| import board +//| import sdioio +//| import storage +//| import camera +//| +//| sd = sdioio.SDCard( +//| clock=board.SDIO_CLOCK, +//| command=board.SDIO_COMMAND, +//| data=board.SDIO_DATA, +//| frequency=25000000) +//| vfs = storage.VfsFat(sd) +//| storage.mount(vfs, '/sd') +//| +//| cam = camera.Camera(camera.ImageSize.IMAGE_SIZE_1920x1080) +//| +//| file = open("/sd/image.jpg","wb") +//| cam.take_picture() +//| file.write(cam.picture) +//| file.close()""" +//| + +//| def __init__(self, ): +//| """Initialize camera. +//| +//| :param camera.ImageSize size: image size""" +//| ... +//| +STATIC mp_obj_t camera_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + camera_obj_t *self = m_new_obj(camera_obj_t); + self->base.type = &camera_type; + enum { ARG_size }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_size, MP_ARG_REQUIRED | MP_ARG_OBJ }, + }; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + camera_imagesize_t size = camera_imagesize_obj_to_type(args[ARG_size].u_obj); + + common_hal_camera_construct(self, size); + return MP_OBJ_FROM_PTR(self); +} + +//| def deinit(self, ) -> Any: +//| """De-initialize camera.""" +//| ... +//| +STATIC mp_obj_t camera_obj_deinit(mp_obj_t self_in) { + camera_obj_t *self = MP_OBJ_TO_PTR(self_in); + common_hal_camera_deinit(self); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_1(camera_deinit_obj, camera_obj_deinit); + +STATIC void check_for_deinit(camera_obj_t *self) { + if (common_hal_camera_deinited(self)) { + raise_deinited_error(); + } +} + +//| def take_picture(self, ) -> Any: +//| """Take picture.""" +//| ... +//| +STATIC mp_obj_t camera_obj_take_picture(mp_obj_t self_in) { + camera_obj_t *self = MP_OBJ_TO_PTR(self_in); + check_for_deinit(self); + + common_hal_camera_take_picture(self); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_1(camera_take_picture_obj, camera_obj_take_picture); + +//| picture: Any = ... +//| """Image buffer.""" +//| +STATIC mp_obj_t camera_obj_get_picture(mp_obj_t self_in) { + camera_obj_t *self = MP_OBJ_TO_PTR(self_in); + check_for_deinit(self); + + uint8_t *buffer = common_hal_camera_get_picture_buffer(self); + size_t size = common_hal_camera_get_picture_size(self); + + return mp_obj_new_bytearray_by_ref(size, buffer); +} +MP_DEFINE_CONST_FUN_OBJ_1(camera_get_picture_obj, camera_obj_get_picture); + +const mp_obj_property_t camera_picture_obj = { + .base.type = &mp_type_property, + .proxy = {(mp_obj_t)&camera_get_picture_obj, + (mp_obj_t)&mp_const_none_obj, + (mp_obj_t)&mp_const_none_obj}, +}; + +//| size: Any = ... +//| """Image size.""" +//| +STATIC mp_obj_t camera_obj_get_size(mp_obj_t self_in) { + camera_obj_t *self = MP_OBJ_TO_PTR(self_in); + check_for_deinit(self); + return camera_imagesize_type_to_obj(common_hal_camera_get_size(self)); +} +MP_DEFINE_CONST_FUN_OBJ_1(camera_get_size_obj, camera_obj_get_size); + +STATIC mp_obj_t camera_obj_set_size(mp_obj_t self_in, mp_obj_t value) { + camera_obj_t *self = MP_OBJ_TO_PTR(self_in); + check_for_deinit(self); + + camera_imagesize_t size = camera_imagesize_obj_to_type(value); + if (size == IMAGESIZE_NONE) { + mp_raise_ValueError(translate("Invalid image size.")); + } + + common_hal_camera_set_size(self, size); + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_2(camera_set_size_obj, camera_obj_set_size); + +const mp_obj_property_t camera_size_obj = { + .base.type = &mp_type_property, + .proxy = {(mp_obj_t)&camera_get_size_obj, + (mp_obj_t)&camera_set_size_obj, + (mp_obj_t)&mp_const_none_obj}, +}; + +STATIC const mp_rom_map_elem_t camera_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&camera_deinit_obj) }, + { MP_ROM_QSTR(MP_QSTR_take_picture), MP_ROM_PTR(&camera_take_picture_obj) }, + + { MP_ROM_QSTR(MP_QSTR_picture), MP_ROM_PTR(&camera_picture_obj) }, + { MP_ROM_QSTR(MP_QSTR_size), MP_ROM_PTR(&camera_size_obj) }, +}; +STATIC MP_DEFINE_CONST_DICT(camera_locals_dict, camera_locals_dict_table); + +const mp_obj_type_t camera_type = { + { &mp_type_type }, + .name = MP_QSTR_GNSS, + .make_new = camera_make_new, + .locals_dict = (mp_obj_dict_t*)&camera_locals_dict, +}; diff --git a/shared-bindings/camera/Camera.h b/shared-bindings/camera/Camera.h new file mode 100644 index 0000000000..e70d2493ec --- /dev/null +++ b/shared-bindings/camera/Camera.h @@ -0,0 +1,45 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_CAMERA_H +#define MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_CAMERA_H + +#include "common-hal/camera/Camera.h" +#include "shared-bindings/camera/ImageSize.h" + +extern const mp_obj_type_t camera_type; + +void common_hal_camera_construct(camera_obj_t *self, camera_imagesize_t size); +void common_hal_camera_deinit(camera_obj_t *self); +bool common_hal_camera_deinited(camera_obj_t *self); +void common_hal_camera_take_picture(camera_obj_t *self); + +uint8_t* common_hal_camera_get_picture_buffer(camera_obj_t *self); +size_t common_hal_camera_get_picture_size(camera_obj_t *self); +camera_imagesize_t common_hal_camera_get_size(camera_obj_t *self); +void common_hal_camera_set_size(camera_obj_t *self, camera_imagesize_t size); + +#endif // MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_CAMERA_H diff --git a/shared-bindings/camera/ImageSize.c b/shared-bindings/camera/ImageSize.c new file mode 100644 index 0000000000..bfa01814d9 --- /dev/null +++ b/shared-bindings/camera/ImageSize.c @@ -0,0 +1,163 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "shared-bindings/camera/ImageSize.h" + +//| class ImageSize: +//| """Image size""" +//| +//| def __init__(self) -> None: +//| """Enum-like class to define the image size.""" +//| +//| IMAGE_SIZE_320x240: ImageSize +//| """Image size 320x240.""" +//| +//| IMAGE_SIZE_640x480: ImageSize +//| """Image size 640x480.""" +//| +//| IMAGE_SIZE_1280x720: ImageSize +//| """Image size 1280x720.""" +//| +//| IMAGE_SIZE_1280x960: ImageSize +//| """Image size 1280x960.""" +//| +//| IMAGE_SIZE_1920x1080: ImageSize +//| """Image size 1920x1080.""" +//| +//| IMAGE_SIZE_2048x1536: ImageSize +//| """Image size 2048x1536.""" +//| +//| IMAGE_SIZE_2560x1920: ImageSize +//| """Image size 2560x1920.""" +//| +const mp_obj_type_t camera_imagesize_type; + +const camera_imagesize_obj_t camera_imagesize_320x240_obj = { + { &camera_imagesize_type }, +}; + +const camera_imagesize_obj_t camera_imagesize_640x320_obj = { + { &camera_imagesize_type }, +}; + +const camera_imagesize_obj_t camera_imagesize_1280x720_obj = { + { &camera_imagesize_type }, +}; + +const camera_imagesize_obj_t camera_imagesize_1280x960_obj = { + { &camera_imagesize_type }, +}; + +const camera_imagesize_obj_t camera_imagesize_1920x1080_obj = { + { &camera_imagesize_type }, +}; + +const camera_imagesize_obj_t camera_imagesize_2048x1536_obj = { + { &camera_imagesize_type }, +}; + +const camera_imagesize_obj_t camera_imagesize_2560x1920_obj = { + { &camera_imagesize_type }, +}; + +camera_imagesize_t camera_imagesize_obj_to_type(mp_obj_t obj) { + if (obj == MP_ROM_PTR(&camera_imagesize_320x240_obj)) { + return IMAGESIZE_320x240; + } else if (obj == MP_ROM_PTR(&camera_imagesize_640x320_obj)) { + return IMAGESIZE_640x320; + } else if (obj == MP_ROM_PTR(&camera_imagesize_1280x720_obj)) { + return IMAGESIZE_1280x720; + } else if (obj == MP_ROM_PTR(&camera_imagesize_1280x960_obj)) { + return IMAGESIZE_1280x960; + } else if (obj == MP_ROM_PTR(&camera_imagesize_1920x1080_obj)) { + return IMAGESIZE_1920x1080; + } else if (obj == MP_ROM_PTR(&camera_imagesize_2048x1536_obj)) { + return IMAGESIZE_2048x1536; + } else if (obj == MP_ROM_PTR(&camera_imagesize_2560x1920_obj)) { + return IMAGESIZE_2560x1920; + } + return IMAGESIZE_NONE; +} + +mp_obj_t camera_imagesize_type_to_obj(camera_imagesize_t size) { + switch (size) { + case IMAGESIZE_320x240: + return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_320x240_obj); + case IMAGESIZE_640x320: + return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_640x320_obj); + case IMAGESIZE_1280x720: + return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_1280x720_obj); + case IMAGESIZE_1280x960: + return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_1280x960_obj); + case IMAGESIZE_1920x1080: + return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_1920x1080_obj); + case IMAGESIZE_2048x1536: + return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_2048x1536_obj); + case IMAGESIZE_2560x1920: + return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_2560x1920_obj); + case IMAGESIZE_NONE: + default: + return (mp_obj_t)MP_ROM_PTR(&mp_const_none_obj); + } +} + +STATIC const mp_rom_map_elem_t camera_imagesize_locals_dict_table[] = { + {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_320x240), MP_ROM_PTR(&camera_imagesize_320x240_obj)}, + {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_640x320), MP_ROM_PTR(&camera_imagesize_640x320_obj)}, + {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_1280x720), MP_ROM_PTR(&camera_imagesize_1280x720_obj)}, + {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_1280x960), MP_ROM_PTR(&camera_imagesize_1280x960_obj)}, + {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_1920x1080), MP_ROM_PTR(&camera_imagesize_1920x1080_obj)}, + {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_2048x1536), MP_ROM_PTR(&camera_imagesize_2048x1536_obj)}, + {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_2560x1920), MP_ROM_PTR(&camera_imagesize_2560x1920_obj)}, +}; +STATIC MP_DEFINE_CONST_DICT(camera_imagesize_locals_dict, camera_imagesize_locals_dict_table); + +STATIC void camera_imagesize_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + qstr size = MP_QSTR_None; + if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_320x240_obj)) { + size = MP_QSTR_IMAGE_SIZE_320x240; + } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_640x320_obj)) { + size = MP_QSTR_IMAGE_SIZE_640x320; + } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_1280x720_obj)) { + size = MP_QSTR_IMAGE_SIZE_1280x720; + } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_1280x960_obj)) { + size = MP_QSTR_IMAGE_SIZE_1280x960; + } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_1920x1080_obj)) { + size = MP_QSTR_IMAGE_SIZE_1920x1080; + } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_2048x1536_obj)) { + size = MP_QSTR_IMAGE_SIZE_2048x1536; + } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_2560x1920_obj)) { + size = MP_QSTR_IMAGE_SIZE_2560x1920; + } + mp_printf(print, "%q.%q.%q", MP_QSTR_camera, MP_QSTR_ImageSize, size); +} + +const mp_obj_type_t camera_imagesize_type = { + { &mp_type_type }, + .name = MP_QSTR_ImageSize, + .print = camera_imagesize_print, + .locals_dict = (mp_obj_t)&camera_imagesize_locals_dict, +}; diff --git a/shared-bindings/camera/ImageSize.h b/shared-bindings/camera/ImageSize.h new file mode 100644 index 0000000000..3fe624e066 --- /dev/null +++ b/shared-bindings/camera/ImageSize.h @@ -0,0 +1,59 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGESIZE_H +#define MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGESIZE_H + +#include "py/obj.h" + +typedef enum { + IMAGESIZE_NONE, + IMAGESIZE_320x240, + IMAGESIZE_640x320, + IMAGESIZE_1280x720, + IMAGESIZE_1280x960, + IMAGESIZE_1920x1080, + IMAGESIZE_2048x1536, + IMAGESIZE_2560x1920, +} camera_imagesize_t; + +const mp_obj_type_t camera_imagesize_type; + +camera_imagesize_t camera_imagesize_obj_to_type(mp_obj_t obj); +mp_obj_t camera_imagesize_type_to_obj(camera_imagesize_t mode); + +typedef struct { + mp_obj_base_t base; +} camera_imagesize_obj_t; +extern const camera_imagesize_obj_t camera_imagesize_320x240_obj; +extern const camera_imagesize_obj_t camera_imagesize_640x320_obj; +extern const camera_imagesize_obj_t camera_imagesize_1280x720_obj; +extern const camera_imagesize_obj_t camera_imagesize_1280x960_obj; +extern const camera_imagesize_obj_t camera_imagesize_1920x1080_obj; +extern const camera_imagesize_obj_t camera_imagesize_2048x1536_obj; +extern const camera_imagesize_obj_t camera_imagesize_2560x1920_obj; + +#endif // MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGESIZE_H diff --git a/shared-bindings/camera/__init__.c b/shared-bindings/camera/__init__.c new file mode 100644 index 0000000000..3398d1ade6 --- /dev/null +++ b/shared-bindings/camera/__init__.c @@ -0,0 +1,50 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "shared-bindings/camera/Camera.h" +#include "shared-bindings/util.h" + +//| """Support for camera input +//| +//| The `camera` module contains classes to control the camera and take pictures.""" +//| +STATIC const mp_rom_map_elem_t camera_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_camera) }, + { MP_ROM_QSTR(MP_QSTR_Camera), MP_ROM_PTR(&camera_type) }, + + // Enum-like Classes. + { MP_ROM_QSTR(MP_QSTR_ImageSize), MP_ROM_PTR(&camera_imagesize_type) }, +}; + +STATIC MP_DEFINE_CONST_DICT(camera_module_globals, camera_module_globals_table); + +const mp_obj_module_t camera_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&camera_module_globals, +}; From 1fde8ef9bce14ceea241574f074ac446dca93055 Mon Sep 17 00:00:00 2001 From: Kamil Tomaszewski Date: Wed, 2 Sep 2020 15:43:37 +0200 Subject: [PATCH 28/91] spresense: Add support for camera --- ports/cxd56/Makefile | 2 +- ports/cxd56/common-hal/camera/Camera.c | 224 ++++++++++++++++++++++ ports/cxd56/common-hal/camera/Camera.h | 43 +++++ ports/cxd56/common-hal/camera/ImageSize.c | 0 ports/cxd56/common-hal/camera/__init__.c | 1 + ports/cxd56/mpconfigport.mk | 1 + 6 files changed, 270 insertions(+), 1 deletion(-) create mode 100644 ports/cxd56/common-hal/camera/Camera.c create mode 100644 ports/cxd56/common-hal/camera/Camera.h create mode 100644 ports/cxd56/common-hal/camera/ImageSize.c create mode 100644 ports/cxd56/common-hal/camera/__init__.c diff --git a/ports/cxd56/Makefile b/ports/cxd56/Makefile index bb3958af4f..7e145f5e2d 100644 --- a/ports/cxd56/Makefile +++ b/ports/cxd56/Makefile @@ -201,7 +201,7 @@ all: $(BUILD)/firmware.spk $(FIRMWARE): $(ECHO) "" $(ECHO) "Download the spresense binaries zip archive from:" - $(ECHO) "https://developer.sony.com/file/download/download-spresense-firmware-v1-4-000" + $(ECHO) "https://developer.sony.com/file/download/download-spresense-firmware-v2-0-000" $(ECHO) "Extract spresense binaries to $(FIRMWARE)" $(ECHO) "" $(ECHO) "run make flash-bootloader again to flash bootloader." diff --git a/ports/cxd56/common-hal/camera/Camera.c b/ports/cxd56/common-hal/camera/Camera.c new file mode 100644 index 0000000000..0c22525302 --- /dev/null +++ b/ports/cxd56/common-hal/camera/Camera.c @@ -0,0 +1,224 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include +#include +#include + +#include "py/runtime.h" + +#include "shared-bindings/camera/Camera.h" + +#define JPG_COMPRESS_RATIO (9) +#define SPRESENSE_CAMIMAGE_MEM_ALIGN (32) + +typedef struct { + const char* devpath; + int fd; +} camera_dev_t; + +STATIC camera_dev_t camera_dev = {"/dev/video", -1}; + +static void camera_size_to_width_and_height(camera_imagesize_t size, uint16_t *width, uint16_t *height) { + switch (size) { + case IMAGESIZE_320x240: + *height = VIDEO_VSIZE_QVGA; + *width = VIDEO_HSIZE_QVGA; + break; + case IMAGESIZE_640x320: + *height = VIDEO_VSIZE_VGA; + *width = VIDEO_HSIZE_VGA; + break; + case IMAGESIZE_1280x720: + *height = VIDEO_VSIZE_HD; + *width = VIDEO_HSIZE_HD; + break; + case IMAGESIZE_1280x960: + *height = VIDEO_VSIZE_QUADVGA; + *width = VIDEO_HSIZE_QUADVGA; + break; + case IMAGESIZE_1920x1080: + *height = VIDEO_VSIZE_FULLHD; + *width = VIDEO_HSIZE_FULLHD; + break; + case IMAGESIZE_2048x1536: + *height = VIDEO_VSIZE_3M; + *width = VIDEO_HSIZE_3M; + break; + case IMAGESIZE_2560x1920: + *height = VIDEO_VSIZE_5M; + *width = VIDEO_HSIZE_5M; + break; + default: + mp_raise_ValueError(translate("Size not supported")); + break; + } +} + +static void camera_set_format(enum v4l2_buf_type type, uint32_t pixformat, uint16_t width, uint16_t height) { + v4l2_requestbuffers_t req = {0}; + + // Set Buffer Mode. + req.type = type; + req.memory = V4L2_MEMORY_USERPTR; + req.count = 1; + req.mode = V4L2_BUF_MODE_RING; + ioctl(camera_dev.fd, VIDIOC_REQBUFS, (unsigned long)&req); + v4l2_format_t fmt = {0}; + + // Set Format. + fmt.type = type; + fmt.fmt.pix.width = width; + fmt.fmt.pix.height = height; + fmt.fmt.pix.field = V4L2_FIELD_ANY; + fmt.fmt.pix.pixelformat = pixformat; + ioctl(camera_dev.fd, VIDIOC_S_FMT, (unsigned long)&fmt); +} + +static void camera_start_streaming(enum v4l2_buf_type type) { + ioctl(camera_dev.fd, VIDIOC_STREAMON, (unsigned long)&type); +} + +static void camera_start_preview() { + camera_set_format(V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_PIX_FMT_UYVY, VIDEO_HSIZE_QVGA, VIDEO_VSIZE_QVGA); + + v4l2_buffer_t buf; + + memset(&buf, 0, sizeof(v4l2_buffer_t)); + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_USERPTR; + ioctl(camera_dev.fd, VIDIOC_QBUF, (unsigned long)&buf); + + camera_start_streaming(V4L2_BUF_TYPE_VIDEO_CAPTURE); +} + +void common_hal_camera_construct(camera_obj_t *self, camera_imagesize_t size) { + if (camera_dev.fd < 0) { + if (video_initialize(camera_dev.devpath) < 0) { + mp_raise_ValueError(translate("Could not initialize Camera")); + } + camera_dev.fd = open(camera_dev.devpath, 0); + if (camera_dev.fd < 0) { + mp_raise_ValueError(translate("Could not initialize Camera")); + } + } + + uint16_t width, height; + + camera_size_to_width_and_height(size, &width, &height); + + self->size = size; + + // In SPRESENSE SDK, JPEG compression quality=80 by default. + // In such setting, the maximum actual measured size of JPEG image + // is about width * height * 2 / 9. + self->buffer_size = (size_t)(width * height * 2 / JPG_COMPRESS_RATIO);; + self->buffer = m_malloc(self->buffer_size, true); + if (self->buffer == NULL) { + mp_raise_msg(&mp_type_MemoryError, translate("Couldn't allocate picture buffer")); + } + self->picture_buffer = self->buffer; + while ((uint32_t)self->picture_buffer % SPRESENSE_CAMIMAGE_MEM_ALIGN != 0) { + self->picture_buffer++; + } + + camera_start_preview(); + + camera_set_format(V4L2_BUF_TYPE_STILL_CAPTURE, V4L2_PIX_FMT_JPEG, width, height); + + camera_start_streaming(V4L2_BUF_TYPE_STILL_CAPTURE); + + sleep(1); +} + +void common_hal_camera_deinit(camera_obj_t *self) { + if (common_hal_camera_deinited(self)) { + return; + } + + video_uninitialize(); + + m_free(self->buffer); + + close(camera_dev.fd); + camera_dev.fd = -1; +} + +bool common_hal_camera_deinited(camera_obj_t *self) { + return camera_dev.fd < 0; +} + +void common_hal_camera_take_picture(camera_obj_t *self) { + v4l2_buffer_t buf; + + memset(&buf, 0, sizeof(v4l2_buffer_t)); + buf.type = V4L2_BUF_TYPE_STILL_CAPTURE; + buf.memory = V4L2_MEMORY_USERPTR; + buf.m.userptr = (unsigned long)self->picture_buffer; + buf.length = self->buffer_size - SPRESENSE_CAMIMAGE_MEM_ALIGN; + ioctl(camera_dev.fd, VIDIOC_QBUF, (unsigned long)&buf); + + ioctl(camera_dev.fd, VIDIOC_TAKEPICT_START, 0); + + ioctl(camera_dev.fd, VIDIOC_DQBUF, (unsigned long)&buf); + + ioctl(camera_dev.fd, VIDIOC_TAKEPICT_STOP, false); + + self->picture_size = (size_t)buf.bytesused; +} + +uint8_t *common_hal_camera_get_picture_buffer(camera_obj_t *self) { + return self->picture_buffer; +} + +size_t common_hal_camera_get_picture_size(camera_obj_t *self) { + return self->picture_size; +} + +camera_imagesize_t common_hal_camera_get_size(camera_obj_t *self) { + return self->size; +} + +void common_hal_camera_set_size(camera_obj_t *self, camera_imagesize_t size) { + uint16_t width, height; + + camera_size_to_width_and_height(size, &width, &height); + + self->buffer_size = (size_t)(width * height * 2 / JPG_COMPRESS_RATIO);; + self->buffer = m_realloc(self->buffer, self->buffer_size); + if (self->buffer == NULL) { + mp_raise_msg(&mp_type_MemoryError, translate("Couldn't allocate picture buffer")); + } + self->picture_buffer = self->buffer; + while ((uint32_t)self->picture_buffer % SPRESENSE_CAMIMAGE_MEM_ALIGN != 0) { + self->picture_buffer++; + } + + camera_set_format(V4L2_BUF_TYPE_STILL_CAPTURE, V4L2_PIX_FMT_JPEG, width, height); +} diff --git a/ports/cxd56/common-hal/camera/Camera.h b/ports/cxd56/common-hal/camera/Camera.h new file mode 100644 index 0000000000..1eb63ace11 --- /dev/null +++ b/ports/cxd56/common-hal/camera/Camera.h @@ -0,0 +1,43 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_CXD56_COMMON_HAL_CAMERA_CAMERA_H +#define MICROPY_INCLUDED_CXD56_COMMON_HAL_CAMERA_CAMERA_H + +#include "py/obj.h" + +#include "shared-bindings/camera/ImageSize.h" + +typedef struct { + mp_obj_base_t base; + uint8_t *buffer; + size_t buffer_size; + uint8_t *picture_buffer; + size_t picture_size; + camera_imagesize_t size; +} camera_obj_t; + +#endif // MICROPY_INCLUDED_CXD56_COMMON_HAL_CAMERA_CAMERA_H diff --git a/ports/cxd56/common-hal/camera/ImageSize.c b/ports/cxd56/common-hal/camera/ImageSize.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/ports/cxd56/common-hal/camera/__init__.c b/ports/cxd56/common-hal/camera/__init__.c new file mode 100644 index 0000000000..bf38b5f2bd --- /dev/null +++ b/ports/cxd56/common-hal/camera/__init__.c @@ -0,0 +1 @@ +// No camera module functions. diff --git a/ports/cxd56/mpconfigport.mk b/ports/cxd56/mpconfigport.mk index 914e0b37d5..e1ffc79d08 100644 --- a/ports/cxd56/mpconfigport.mk +++ b/ports/cxd56/mpconfigport.mk @@ -11,6 +11,7 @@ MPY_TOOL_LONGINT_IMPL = -mlongint-impl=mpz CIRCUITPY_AUDIOBUSIO = 0 CIRCUITPY_AUDIOIO = 0 +CIRCUITPY_CAMERA = 1 CIRCUITPY_COUNTIO = 0 CIRCUITPY_DISPLAYIO = 0 CIRCUITPY_FREQUENCYIO = 0 From fbf4431aa0f40859d0686308bda226a4880449e8 Mon Sep 17 00:00:00 2001 From: Kamil Tomaszewski Date: Wed, 2 Sep 2020 15:44:51 +0200 Subject: [PATCH 29/91] locale: make translate --- locale/circuitpython.pot | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 038cdacfc6..7bf2f851da 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -615,6 +615,10 @@ msgstr "" msgid "Corrupt raw code" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -672,6 +676,10 @@ msgstr "" msgid "Couldn't allocate input buffer" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Couldn't allocate picture buffer" +msgstr "" + #: shared-module/audiocore/WaveFile.c shared-module/audiomixer/Mixer.c #: shared-module/audiomp3/MP3Decoder.c msgid "Couldn't allocate second buffer" @@ -998,6 +1006,10 @@ msgstr "" msgid "Invalid frequency supplied" msgstr "" +#: shared-bindings/camera/Camera.c +msgid "Invalid image size." +msgstr "" + #: supervisor/shared/safe_mode.c msgid "Invalid memory access." msgstr "" @@ -1499,6 +1511,10 @@ msgstr "" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "" From 143a1ff94a5052465e3e65057b0ec4660120b2ed Mon Sep 17 00:00:00 2001 From: Kamil Tomaszewski Date: Fri, 11 Sep 2020 13:24:55 +0200 Subject: [PATCH 30/91] spresense: change the GC to do 32-byte blocks --- ports/cxd56/configs/circuitpython/defconfig | 1 - ports/cxd56/mpconfigport.h | 6 ++++-- ports/cxd56/spresense-exported-sdk | 2 +- ports/cxd56/supervisor/port.c | 12 ++++++++++-- 4 files changed, 15 insertions(+), 6 deletions(-) diff --git a/ports/cxd56/configs/circuitpython/defconfig b/ports/cxd56/configs/circuitpython/defconfig index 268f7a68e9..a97f821dfa 100644 --- a/ports/cxd56/configs/circuitpython/defconfig +++ b/ports/cxd56/configs/circuitpython/defconfig @@ -165,7 +165,6 @@ CONFIG_USBDEV=y CONFIG_USBDEV_DMA=y CONFIG_USBDEV_DUALSPEED=y CONFIG_USEC_PER_TICK=1000 -CONFIG_USERMAIN_STACKSIZE=1064960 CONFIG_USER_ENTRYPOINT="spresense_main" CONFIG_VIDEO_ISX012=y CONFIG_VIDEO_STREAM=y diff --git a/ports/cxd56/mpconfigport.h b/ports/cxd56/mpconfigport.h index df87946b95..27c82337bc 100644 --- a/ports/cxd56/mpconfigport.h +++ b/ports/cxd56/mpconfigport.h @@ -27,13 +27,15 @@ #ifndef __INCLUDED_MPCONFIGPORT_H #define __INCLUDED_MPCONFIGPORT_H -#define MICROPY_PY_SYS_PLATFORM "CXD56" +#define MICROPY_PY_SYS_PLATFORM "CXD56" // 64kiB stack -#define CIRCUITPY_DEFAULT_STACK_SIZE 0x10000 +#define CIRCUITPY_DEFAULT_STACK_SIZE (0x10000) #include "py/circuitpy_mpconfig.h" +#define MICROPY_BYTES_PER_GC_BLOCK (32) + #define MICROPY_PORT_ROOT_POINTERS \ CIRCUITPY_COMMON_ROOT_POINTERS \ diff --git a/ports/cxd56/spresense-exported-sdk b/ports/cxd56/spresense-exported-sdk index c991d439fa..752c4cd56d 160000 --- a/ports/cxd56/spresense-exported-sdk +++ b/ports/cxd56/spresense-exported-sdk @@ -1 +1 @@ -Subproject commit c991d439fac9c23cfcac0da16fe8055f818d40a4 +Subproject commit 752c4cd56dd0a270a559c28272ceb61ddcb7806c diff --git a/ports/cxd56/supervisor/port.c b/ports/cxd56/supervisor/port.c index 7038ca4782..6a32dc0f9e 100644 --- a/ports/cxd56/supervisor/port.c +++ b/ports/cxd56/supervisor/port.c @@ -46,12 +46,20 @@ #include "common-hal/pwmio/PWMOut.h" #include "common-hal/busio/UART.h" +#define HEAP_SIZE (1000 * 1024) + +uint32_t* heap; +uint32_t heap_size; + safe_mode_t port_init(void) { boardctl(BOARDIOC_INIT, 0); // Wait until RTC is available while (g_rtc_enabled == false); + heap = memalign(32, HEAP_SIZE); + heap_size = HEAP_SIZE / sizeof(uint32_t); + if (board_requests_safe_mode()) { return USER_SAFE_MODE; } @@ -100,11 +108,11 @@ uint32_t *port_stack_get_top(void) { } uint32_t *port_heap_get_bottom(void) { - return port_stack_get_limit(); + return heap; } uint32_t *port_heap_get_top(void) { - return port_stack_get_top(); + return heap + heap_size; } extern uint32_t _ebss; From c2fc592c2ca7ec42374a50f9e33ac551bf846596 Mon Sep 17 00:00:00 2001 From: Kamil Tomaszewski Date: Fri, 11 Sep 2020 13:27:11 +0200 Subject: [PATCH 31/91] camera: Change API --- ports/cxd56/common-hal/camera/Camera.c | 144 +++++++--------- ports/cxd56/common-hal/camera/Camera.h | 9 +- ports/cxd56/common-hal/camera/ImageSize.c | 0 py/circuitpy_defns.mk | 2 +- shared-bindings/camera/Camera.c | 120 +++++++------ shared-bindings/camera/Camera.h | 14 +- shared-bindings/camera/ImageFormat.c | 93 ++++++++++ .../camera/{ImageSize.h => ImageFormat.h} | 36 ++-- shared-bindings/camera/ImageSize.c | 163 ------------------ shared-bindings/camera/__init__.c | 2 +- 10 files changed, 247 insertions(+), 336 deletions(-) delete mode 100644 ports/cxd56/common-hal/camera/ImageSize.c create mode 100644 shared-bindings/camera/ImageFormat.c rename shared-bindings/camera/{ImageSize.h => ImageFormat.h} (55%) delete mode 100644 shared-bindings/camera/ImageSize.c diff --git a/ports/cxd56/common-hal/camera/Camera.c b/ports/cxd56/common-hal/camera/Camera.c index 0c22525302..9376822c8a 100644 --- a/ports/cxd56/common-hal/camera/Camera.c +++ b/ports/cxd56/common-hal/camera/Camera.c @@ -35,9 +35,6 @@ #include "shared-bindings/camera/Camera.h" -#define JPG_COMPRESS_RATIO (9) -#define SPRESENSE_CAMIMAGE_MEM_ALIGN (32) - typedef struct { const char* devpath; int fd; @@ -45,39 +42,36 @@ typedef struct { STATIC camera_dev_t camera_dev = {"/dev/video", -1}; -static void camera_size_to_width_and_height(camera_imagesize_t size, uint16_t *width, uint16_t *height) { - switch (size) { - case IMAGESIZE_320x240: - *height = VIDEO_VSIZE_QVGA; - *width = VIDEO_HSIZE_QVGA; - break; - case IMAGESIZE_640x320: - *height = VIDEO_VSIZE_VGA; - *width = VIDEO_HSIZE_VGA; - break; - case IMAGESIZE_1280x720: - *height = VIDEO_VSIZE_HD; - *width = VIDEO_HSIZE_HD; - break; - case IMAGESIZE_1280x960: - *height = VIDEO_VSIZE_QUADVGA; - *width = VIDEO_HSIZE_QUADVGA; - break; - case IMAGESIZE_1920x1080: - *height = VIDEO_VSIZE_FULLHD; - *width = VIDEO_HSIZE_FULLHD; - break; - case IMAGESIZE_2048x1536: - *height = VIDEO_VSIZE_3M; - *width = VIDEO_HSIZE_3M; - break; - case IMAGESIZE_2560x1920: - *height = VIDEO_VSIZE_5M; - *width = VIDEO_HSIZE_5M; - break; - default: - mp_raise_ValueError(translate("Size not supported")); - break; +static bool camera_check_width_and_height(uint16_t width, uint16_t height) { + if ((width == VIDEO_HSIZE_QVGA && height == VIDEO_VSIZE_QVGA) || + (width == VIDEO_HSIZE_VGA && height == VIDEO_VSIZE_VGA) || + (width == VIDEO_HSIZE_HD && height == VIDEO_VSIZE_HD) || + (width == VIDEO_HSIZE_QUADVGA && height == VIDEO_VSIZE_QUADVGA) || + (width == VIDEO_HSIZE_FULLHD && height == VIDEO_VSIZE_FULLHD) || + (width == VIDEO_HSIZE_3M && height == VIDEO_VSIZE_3M) || + (width == VIDEO_HSIZE_5M && height == VIDEO_VSIZE_5M)) { + return true; + } else { + return false; + } +} + +static bool camera_check_buffer_length(uint16_t width, uint16_t height, camera_imageformat_t format, size_t length) { + if (format == IMAGEFORMAT_JPG) { + // In SPRESENSE SDK, JPEG compression quality=80 by default. + // In such setting, the maximum actual measured size of JPEG image + // is about width * height * 2 / 9. + return length >= (size_t)(width * height * 2 / 9) ? true : false; + } else { + return false; + } +} + +static bool camera_check_format(camera_imageformat_t format) { + if (format == IMAGEFORMAT_JPG) { + return true; + } else { + return false; } } @@ -118,7 +112,9 @@ static void camera_start_preview() { camera_start_streaming(V4L2_BUF_TYPE_VIDEO_CAPTURE); } -void common_hal_camera_construct(camera_obj_t *self, camera_imagesize_t size) { +extern uint32_t _ebss; +extern uint32_t _stext; +void common_hal_camera_construct(camera_obj_t *self, uint16_t width, uint16_t height) { if (camera_dev.fd < 0) { if (video_initialize(camera_dev.devpath) < 0) { mp_raise_ValueError(translate("Could not initialize Camera")); @@ -129,25 +125,13 @@ void common_hal_camera_construct(camera_obj_t *self, camera_imagesize_t size) { } } - uint16_t width, height; - - camera_size_to_width_and_height(size, &width, &height); - - self->size = size; - - // In SPRESENSE SDK, JPEG compression quality=80 by default. - // In such setting, the maximum actual measured size of JPEG image - // is about width * height * 2 / 9. - self->buffer_size = (size_t)(width * height * 2 / JPG_COMPRESS_RATIO);; - self->buffer = m_malloc(self->buffer_size, true); - if (self->buffer == NULL) { - mp_raise_msg(&mp_type_MemoryError, translate("Couldn't allocate picture buffer")); - } - self->picture_buffer = self->buffer; - while ((uint32_t)self->picture_buffer % SPRESENSE_CAMIMAGE_MEM_ALIGN != 0) { - self->picture_buffer++; + if (!camera_check_width_and_height(width, height)) { + mp_raise_ValueError(translate("Size not supported")); } + self->width = width; + self->height = height; + camera_start_preview(); camera_set_format(V4L2_BUF_TYPE_STILL_CAPTURE, V4L2_PIX_FMT_JPEG, width, height); @@ -164,8 +148,6 @@ void common_hal_camera_deinit(camera_obj_t *self) { video_uninitialize(); - m_free(self->buffer); - close(camera_dev.fd); camera_dev.fd = -1; } @@ -174,14 +156,26 @@ bool common_hal_camera_deinited(camera_obj_t *self) { return camera_dev.fd < 0; } -void common_hal_camera_take_picture(camera_obj_t *self) { +size_t common_hal_camera_take_picture(camera_obj_t *self, uint8_t *buffer, size_t len, camera_imageformat_t format) { + if (!camera_check_width_and_height(self->width, self->height)) { + mp_raise_ValueError(translate("Size not supported")); + } + if (!camera_check_buffer_length(self->width, self->height, format, len)) { + mp_raise_ValueError(translate("Buffer is too small")); + } + if (!camera_check_format(format)) { + mp_raise_ValueError(translate("Format not supported")); + } + + camera_set_format(V4L2_BUF_TYPE_STILL_CAPTURE, V4L2_PIX_FMT_JPEG, self->width, self->height); + v4l2_buffer_t buf; memset(&buf, 0, sizeof(v4l2_buffer_t)); buf.type = V4L2_BUF_TYPE_STILL_CAPTURE; buf.memory = V4L2_MEMORY_USERPTR; - buf.m.userptr = (unsigned long)self->picture_buffer; - buf.length = self->buffer_size - SPRESENSE_CAMIMAGE_MEM_ALIGN; + buf.m.userptr = (unsigned long)buffer; + buf.length = len; ioctl(camera_dev.fd, VIDIOC_QBUF, (unsigned long)&buf); ioctl(camera_dev.fd, VIDIOC_TAKEPICT_START, 0); @@ -190,35 +184,21 @@ void common_hal_camera_take_picture(camera_obj_t *self) { ioctl(camera_dev.fd, VIDIOC_TAKEPICT_STOP, false); - self->picture_size = (size_t)buf.bytesused; + return (size_t)buf.bytesused; } -uint8_t *common_hal_camera_get_picture_buffer(camera_obj_t *self) { - return self->picture_buffer; +uint16_t common_hal_camera_get_width(camera_obj_t *self) { + return self->width; } -size_t common_hal_camera_get_picture_size(camera_obj_t *self) { - return self->picture_size; +void common_hal_camera_set_width(camera_obj_t *self, uint16_t width) { + self->width = width; } -camera_imagesize_t common_hal_camera_get_size(camera_obj_t *self) { - return self->size; +uint16_t common_hal_camera_get_height(camera_obj_t *self) { + return self->height; } -void common_hal_camera_set_size(camera_obj_t *self, camera_imagesize_t size) { - uint16_t width, height; - - camera_size_to_width_and_height(size, &width, &height); - - self->buffer_size = (size_t)(width * height * 2 / JPG_COMPRESS_RATIO);; - self->buffer = m_realloc(self->buffer, self->buffer_size); - if (self->buffer == NULL) { - mp_raise_msg(&mp_type_MemoryError, translate("Couldn't allocate picture buffer")); - } - self->picture_buffer = self->buffer; - while ((uint32_t)self->picture_buffer % SPRESENSE_CAMIMAGE_MEM_ALIGN != 0) { - self->picture_buffer++; - } - - camera_set_format(V4L2_BUF_TYPE_STILL_CAPTURE, V4L2_PIX_FMT_JPEG, width, height); +void common_hal_camera_set_height(camera_obj_t *self, uint16_t height) { + self->height = height; } diff --git a/ports/cxd56/common-hal/camera/Camera.h b/ports/cxd56/common-hal/camera/Camera.h index 1eb63ace11..11fc102085 100644 --- a/ports/cxd56/common-hal/camera/Camera.h +++ b/ports/cxd56/common-hal/camera/Camera.h @@ -29,15 +29,10 @@ #include "py/obj.h" -#include "shared-bindings/camera/ImageSize.h" - typedef struct { mp_obj_base_t base; - uint8_t *buffer; - size_t buffer_size; - uint8_t *picture_buffer; - size_t picture_size; - camera_imagesize_t size; + uint16_t width; + uint16_t height; } camera_obj_t; #endif // MICROPY_INCLUDED_CXD56_COMMON_HAL_CAMERA_CAMERA_H diff --git a/ports/cxd56/common-hal/camera/ImageSize.c b/ports/cxd56/common-hal/camera/ImageSize.c deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/py/circuitpy_defns.mk b/py/circuitpy_defns.mk index f72c821e53..6e98af8686 100644 --- a/py/circuitpy_defns.mk +++ b/py/circuitpy_defns.mk @@ -315,7 +315,6 @@ SRC_COMMON_HAL_ALL = \ busio/__init__.c \ camera/__init__.c \ camera/Camera.c \ - camera/ImageSize.c \ countio/Counter.c \ countio/__init__.c \ digitalio/DigitalInOut.c \ @@ -386,6 +385,7 @@ $(filter $(SRC_PATTERNS), \ _bleio/Attribute.c \ _bleio/ScanEntry.c \ _eve/__init__.c \ + camera/ImageFormat.c \ digitalio/Direction.c \ digitalio/DriveMode.c \ digitalio/Pull.c \ diff --git a/shared-bindings/camera/Camera.c b/shared-bindings/camera/Camera.c index 3855fed3c7..3b839d802f 100644 --- a/shared-bindings/camera/Camera.c +++ b/shared-bindings/camera/Camera.c @@ -48,37 +48,38 @@ //| vfs = storage.VfsFat(sd) //| storage.mount(vfs, '/sd') //| -//| cam = camera.Camera(camera.ImageSize.IMAGE_SIZE_1920x1080) +//| cam = camera.Camera(1920, 1080) //| +//| buffer = bytearray(512 * 1024) //| file = open("/sd/image.jpg","wb") -//| cam.take_picture() -//| file.write(cam.picture) +//| size = cam.take_picture() +//| file.write(buffer, size) //| file.close()""" //| -//| def __init__(self, ): +//| def __init__(self, width: int, height: int) -> None: //| """Initialize camera. //| -//| :param camera.ImageSize size: image size""" +//| :param int width: Width in pixels +//| :param int height: Height in pixels""" //| ... //| STATIC mp_obj_t camera_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { camera_obj_t *self = m_new_obj(camera_obj_t); self->base.type = &camera_type; - enum { ARG_size }; + enum { ARG_width, ARG_height }; static const mp_arg_t allowed_args[] = { - { MP_QSTR_size, MP_ARG_REQUIRED | MP_ARG_OBJ }, + { MP_QSTR_width, MP_ARG_REQUIRED | MP_ARG_INT }, + { MP_QSTR_height, MP_ARG_REQUIRED | MP_ARG_INT }, }; mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - camera_imagesize_t size = camera_imagesize_obj_to_type(args[ARG_size].u_obj); - - common_hal_camera_construct(self, size); + common_hal_camera_construct(self, args[ARG_width].u_int, args[ARG_height].u_int); return MP_OBJ_FROM_PTR(self); } -//| def deinit(self, ) -> Any: +//| def deinit(self) -> None: //| """De-initialize camera.""" //| ... //| @@ -95,69 +96,84 @@ STATIC void check_for_deinit(camera_obj_t *self) { } } -//| def take_picture(self, ) -> Any: -//| """Take picture.""" +//| def take_picture(self, buf: WriteableBuffer, format: ImageFormat) -> int: +//| """Take picture and save to ``buf`` in the given ``format`` +//| +//| :return: the size of the picture taken +//| :rtype: int""" //| ... //| -STATIC mp_obj_t camera_obj_take_picture(mp_obj_t self_in) { +STATIC mp_obj_t camera_obj_take_picture(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + enum { ARG_buffer, ARG_format }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_buffer, MP_ARG_REQUIRED | MP_ARG_OBJ }, + { MP_QSTR_format, MP_ARG_REQUIRED | MP_ARG_OBJ }, + }; + camera_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + check_for_deinit(self); + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[ARG_buffer].u_obj, &bufinfo, MP_BUFFER_WRITE); + + camera_imageformat_t format = camera_imageformat_obj_to_type(args[ARG_format].u_obj); + + return MP_OBJ_NEW_SMALL_INT(common_hal_camera_take_picture(self, (uint8_t *)bufinfo.buf, bufinfo.len, format)); +} +MP_DEFINE_CONST_FUN_OBJ_KW(camera_take_picture_obj, 3, camera_obj_take_picture); + +//| width: int +//| """Image width in pixels.""" +//| +STATIC mp_obj_t camera_obj_get_width(mp_obj_t self_in) { + camera_obj_t *self = MP_OBJ_TO_PTR(self_in); + check_for_deinit(self); + return MP_OBJ_NEW_SMALL_INT(common_hal_camera_get_width(self)); +} +MP_DEFINE_CONST_FUN_OBJ_1(camera_get_width_obj, camera_obj_get_width); + +STATIC mp_obj_t camera_obj_set_width(mp_obj_t self_in, mp_obj_t value) { camera_obj_t *self = MP_OBJ_TO_PTR(self_in); check_for_deinit(self); - common_hal_camera_take_picture(self); + common_hal_camera_set_width(self, mp_obj_get_int(value)); + return mp_const_none; } -MP_DEFINE_CONST_FUN_OBJ_1(camera_take_picture_obj, camera_obj_take_picture); +MP_DEFINE_CONST_FUN_OBJ_2(camera_set_width_obj, camera_obj_set_width); -//| picture: Any = ... -//| """Image buffer.""" -//| -STATIC mp_obj_t camera_obj_get_picture(mp_obj_t self_in) { - camera_obj_t *self = MP_OBJ_TO_PTR(self_in); - check_for_deinit(self); - - uint8_t *buffer = common_hal_camera_get_picture_buffer(self); - size_t size = common_hal_camera_get_picture_size(self); - - return mp_obj_new_bytearray_by_ref(size, buffer); -} -MP_DEFINE_CONST_FUN_OBJ_1(camera_get_picture_obj, camera_obj_get_picture); - -const mp_obj_property_t camera_picture_obj = { +const mp_obj_property_t camera_width_obj = { .base.type = &mp_type_property, - .proxy = {(mp_obj_t)&camera_get_picture_obj, - (mp_obj_t)&mp_const_none_obj, + .proxy = {(mp_obj_t)&camera_get_width_obj, + (mp_obj_t)&camera_set_width_obj, (mp_obj_t)&mp_const_none_obj}, }; -//| size: Any = ... -//| """Image size.""" +//| height: int +//| """Image height in pixels.""" //| -STATIC mp_obj_t camera_obj_get_size(mp_obj_t self_in) { +STATIC mp_obj_t camera_obj_get_height(mp_obj_t self_in) { camera_obj_t *self = MP_OBJ_TO_PTR(self_in); check_for_deinit(self); - return camera_imagesize_type_to_obj(common_hal_camera_get_size(self)); + return MP_OBJ_NEW_SMALL_INT(common_hal_camera_get_height(self)); } -MP_DEFINE_CONST_FUN_OBJ_1(camera_get_size_obj, camera_obj_get_size); +MP_DEFINE_CONST_FUN_OBJ_1(camera_get_height_obj, camera_obj_get_height); -STATIC mp_obj_t camera_obj_set_size(mp_obj_t self_in, mp_obj_t value) { +STATIC mp_obj_t camera_obj_set_height(mp_obj_t self_in, mp_obj_t value) { camera_obj_t *self = MP_OBJ_TO_PTR(self_in); check_for_deinit(self); - camera_imagesize_t size = camera_imagesize_obj_to_type(value); - if (size == IMAGESIZE_NONE) { - mp_raise_ValueError(translate("Invalid image size.")); - } - - common_hal_camera_set_size(self, size); + common_hal_camera_set_height(self, mp_obj_get_int(value)); return mp_const_none; } -MP_DEFINE_CONST_FUN_OBJ_2(camera_set_size_obj, camera_obj_set_size); +MP_DEFINE_CONST_FUN_OBJ_2(camera_set_height_obj, camera_obj_set_height); -const mp_obj_property_t camera_size_obj = { +const mp_obj_property_t camera_height_obj = { .base.type = &mp_type_property, - .proxy = {(mp_obj_t)&camera_get_size_obj, - (mp_obj_t)&camera_set_size_obj, + .proxy = {(mp_obj_t)&camera_get_height_obj, + (mp_obj_t)&camera_set_height_obj, (mp_obj_t)&mp_const_none_obj}, }; @@ -165,14 +181,14 @@ STATIC const mp_rom_map_elem_t camera_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&camera_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_take_picture), MP_ROM_PTR(&camera_take_picture_obj) }, - { MP_ROM_QSTR(MP_QSTR_picture), MP_ROM_PTR(&camera_picture_obj) }, - { MP_ROM_QSTR(MP_QSTR_size), MP_ROM_PTR(&camera_size_obj) }, + { MP_ROM_QSTR(MP_QSTR_width), MP_ROM_PTR(&camera_width_obj) }, + { MP_ROM_QSTR(MP_QSTR_height), MP_ROM_PTR(&camera_height_obj) }, }; STATIC MP_DEFINE_CONST_DICT(camera_locals_dict, camera_locals_dict_table); const mp_obj_type_t camera_type = { { &mp_type_type }, - .name = MP_QSTR_GNSS, + .name = MP_QSTR_Camera, .make_new = camera_make_new, .locals_dict = (mp_obj_dict_t*)&camera_locals_dict, }; diff --git a/shared-bindings/camera/Camera.h b/shared-bindings/camera/Camera.h index e70d2493ec..7ef13cd07e 100644 --- a/shared-bindings/camera/Camera.h +++ b/shared-bindings/camera/Camera.h @@ -28,18 +28,18 @@ #define MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_CAMERA_H #include "common-hal/camera/Camera.h" -#include "shared-bindings/camera/ImageSize.h" +#include "shared-bindings/camera/ImageFormat.h" extern const mp_obj_type_t camera_type; -void common_hal_camera_construct(camera_obj_t *self, camera_imagesize_t size); +void common_hal_camera_construct(camera_obj_t *self, uint16_t width, uint16_t height); void common_hal_camera_deinit(camera_obj_t *self); bool common_hal_camera_deinited(camera_obj_t *self); -void common_hal_camera_take_picture(camera_obj_t *self); +size_t common_hal_camera_take_picture(camera_obj_t *self, uint8_t *buffer, size_t len, camera_imageformat_t format); -uint8_t* common_hal_camera_get_picture_buffer(camera_obj_t *self); -size_t common_hal_camera_get_picture_size(camera_obj_t *self); -camera_imagesize_t common_hal_camera_get_size(camera_obj_t *self); -void common_hal_camera_set_size(camera_obj_t *self, camera_imagesize_t size); +uint16_t common_hal_camera_get_width(camera_obj_t *self); +void common_hal_camera_set_width(camera_obj_t *self, uint16_t width); +uint16_t common_hal_camera_get_height(camera_obj_t *self); +void common_hal_camera_set_height(camera_obj_t *self, uint16_t height); #endif // MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_CAMERA_H diff --git a/shared-bindings/camera/ImageFormat.c b/shared-bindings/camera/ImageFormat.c new file mode 100644 index 0000000000..d4bdddc562 --- /dev/null +++ b/shared-bindings/camera/ImageFormat.c @@ -0,0 +1,93 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "shared-bindings/camera/ImageFormat.h" + +//| class ImageFormat: +//| """Image format""" +//| +//| def __init__(self) -> None: +//| """Enum-like class to define the image format.""" +//| +//| JPG: ImageFormat +//| """JPG format.""" +//| +//| RGB565: ImageFormat +//| """RGB565 format.""" +//| +const mp_obj_type_t camera_imageformat_type; + +const camera_imageformat_obj_t camera_imageformat_jpg_obj = { + { &camera_imageformat_type }, +}; + +const camera_imageformat_obj_t camera_imageformat_rgb565_obj = { + { &camera_imageformat_type }, +}; + +camera_imageformat_t camera_imageformat_obj_to_type(mp_obj_t obj) { + if (obj == MP_ROM_PTR(&camera_imageformat_jpg_obj)) { + return IMAGEFORMAT_JPG; + } else if (obj == MP_ROM_PTR(&camera_imageformat_rgb565_obj)) { + return IMAGEFORMAT_RGB565; + } + return IMAGEFORMAT_NONE; +} + +mp_obj_t camera_imageformat_type_to_obj(camera_imageformat_t format) { + switch (format) { + case IMAGEFORMAT_JPG: + return (mp_obj_t)MP_ROM_PTR(&camera_imageformat_jpg_obj); + case IMAGEFORMAT_RGB565: + return (mp_obj_t)MP_ROM_PTR(&camera_imageformat_rgb565_obj); + case IMAGEFORMAT_NONE: + default: + return (mp_obj_t)MP_ROM_PTR(&mp_const_none_obj); + } +} + +STATIC const mp_rom_map_elem_t camera_imageformat_locals_dict_table[] = { + {MP_ROM_QSTR(MP_QSTR_JPG), MP_ROM_PTR(&camera_imageformat_jpg_obj)}, + {MP_ROM_QSTR(MP_QSTR_RGB565), MP_ROM_PTR(&camera_imageformat_rgb565_obj)}, +}; +STATIC MP_DEFINE_CONST_DICT(camera_imageformat_locals_dict, camera_imageformat_locals_dict_table); + +STATIC void camera_imageformat_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + qstr format = MP_QSTR_None; + if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imageformat_jpg_obj)) { + format = MP_QSTR_JPG; + } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imageformat_rgb565_obj)) { + format = MP_QSTR_RGB565; + } + mp_printf(print, "%q.%q.%q", MP_QSTR_camera, MP_QSTR_ImageSize, format); +} + +const mp_obj_type_t camera_imageformat_type = { + { &mp_type_type }, + .name = MP_QSTR_ImageFormat, + .print = camera_imageformat_print, + .locals_dict = (mp_obj_t)&camera_imageformat_locals_dict, +}; diff --git a/shared-bindings/camera/ImageSize.h b/shared-bindings/camera/ImageFormat.h similarity index 55% rename from shared-bindings/camera/ImageSize.h rename to shared-bindings/camera/ImageFormat.h index 3fe624e066..8abc88438d 100644 --- a/shared-bindings/camera/ImageSize.h +++ b/shared-bindings/camera/ImageFormat.h @@ -24,36 +24,26 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGESIZE_H -#define MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGESIZE_H +#ifndef MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGEFORMAT_H +#define MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGEFORMAT_H #include "py/obj.h" typedef enum { - IMAGESIZE_NONE, - IMAGESIZE_320x240, - IMAGESIZE_640x320, - IMAGESIZE_1280x720, - IMAGESIZE_1280x960, - IMAGESIZE_1920x1080, - IMAGESIZE_2048x1536, - IMAGESIZE_2560x1920, -} camera_imagesize_t; + IMAGEFORMAT_NONE, + IMAGEFORMAT_JPG, + IMAGEFORMAT_RGB565, +} camera_imageformat_t; -const mp_obj_type_t camera_imagesize_type; +const mp_obj_type_t camera_imageformat_type; -camera_imagesize_t camera_imagesize_obj_to_type(mp_obj_t obj); -mp_obj_t camera_imagesize_type_to_obj(camera_imagesize_t mode); +camera_imageformat_t camera_imageformat_obj_to_type(mp_obj_t obj); +mp_obj_t camera_imageformat_type_to_obj(camera_imageformat_t mode); typedef struct { mp_obj_base_t base; -} camera_imagesize_obj_t; -extern const camera_imagesize_obj_t camera_imagesize_320x240_obj; -extern const camera_imagesize_obj_t camera_imagesize_640x320_obj; -extern const camera_imagesize_obj_t camera_imagesize_1280x720_obj; -extern const camera_imagesize_obj_t camera_imagesize_1280x960_obj; -extern const camera_imagesize_obj_t camera_imagesize_1920x1080_obj; -extern const camera_imagesize_obj_t camera_imagesize_2048x1536_obj; -extern const camera_imagesize_obj_t camera_imagesize_2560x1920_obj; +} camera_imageformat_obj_t; +extern const camera_imageformat_obj_t camera_imageformat_jpg_obj; +extern const camera_imageformat_obj_t camera_imageformat_rgb565_obj; -#endif // MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGESIZE_H +#endif // MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_IMAGEFORMAT_H diff --git a/shared-bindings/camera/ImageSize.c b/shared-bindings/camera/ImageSize.c deleted file mode 100644 index bfa01814d9..0000000000 --- a/shared-bindings/camera/ImageSize.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright 2020 Sony Semiconductor Solutions Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "shared-bindings/camera/ImageSize.h" - -//| class ImageSize: -//| """Image size""" -//| -//| def __init__(self) -> None: -//| """Enum-like class to define the image size.""" -//| -//| IMAGE_SIZE_320x240: ImageSize -//| """Image size 320x240.""" -//| -//| IMAGE_SIZE_640x480: ImageSize -//| """Image size 640x480.""" -//| -//| IMAGE_SIZE_1280x720: ImageSize -//| """Image size 1280x720.""" -//| -//| IMAGE_SIZE_1280x960: ImageSize -//| """Image size 1280x960.""" -//| -//| IMAGE_SIZE_1920x1080: ImageSize -//| """Image size 1920x1080.""" -//| -//| IMAGE_SIZE_2048x1536: ImageSize -//| """Image size 2048x1536.""" -//| -//| IMAGE_SIZE_2560x1920: ImageSize -//| """Image size 2560x1920.""" -//| -const mp_obj_type_t camera_imagesize_type; - -const camera_imagesize_obj_t camera_imagesize_320x240_obj = { - { &camera_imagesize_type }, -}; - -const camera_imagesize_obj_t camera_imagesize_640x320_obj = { - { &camera_imagesize_type }, -}; - -const camera_imagesize_obj_t camera_imagesize_1280x720_obj = { - { &camera_imagesize_type }, -}; - -const camera_imagesize_obj_t camera_imagesize_1280x960_obj = { - { &camera_imagesize_type }, -}; - -const camera_imagesize_obj_t camera_imagesize_1920x1080_obj = { - { &camera_imagesize_type }, -}; - -const camera_imagesize_obj_t camera_imagesize_2048x1536_obj = { - { &camera_imagesize_type }, -}; - -const camera_imagesize_obj_t camera_imagesize_2560x1920_obj = { - { &camera_imagesize_type }, -}; - -camera_imagesize_t camera_imagesize_obj_to_type(mp_obj_t obj) { - if (obj == MP_ROM_PTR(&camera_imagesize_320x240_obj)) { - return IMAGESIZE_320x240; - } else if (obj == MP_ROM_PTR(&camera_imagesize_640x320_obj)) { - return IMAGESIZE_640x320; - } else if (obj == MP_ROM_PTR(&camera_imagesize_1280x720_obj)) { - return IMAGESIZE_1280x720; - } else if (obj == MP_ROM_PTR(&camera_imagesize_1280x960_obj)) { - return IMAGESIZE_1280x960; - } else if (obj == MP_ROM_PTR(&camera_imagesize_1920x1080_obj)) { - return IMAGESIZE_1920x1080; - } else if (obj == MP_ROM_PTR(&camera_imagesize_2048x1536_obj)) { - return IMAGESIZE_2048x1536; - } else if (obj == MP_ROM_PTR(&camera_imagesize_2560x1920_obj)) { - return IMAGESIZE_2560x1920; - } - return IMAGESIZE_NONE; -} - -mp_obj_t camera_imagesize_type_to_obj(camera_imagesize_t size) { - switch (size) { - case IMAGESIZE_320x240: - return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_320x240_obj); - case IMAGESIZE_640x320: - return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_640x320_obj); - case IMAGESIZE_1280x720: - return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_1280x720_obj); - case IMAGESIZE_1280x960: - return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_1280x960_obj); - case IMAGESIZE_1920x1080: - return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_1920x1080_obj); - case IMAGESIZE_2048x1536: - return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_2048x1536_obj); - case IMAGESIZE_2560x1920: - return (mp_obj_t)MP_ROM_PTR(&camera_imagesize_2560x1920_obj); - case IMAGESIZE_NONE: - default: - return (mp_obj_t)MP_ROM_PTR(&mp_const_none_obj); - } -} - -STATIC const mp_rom_map_elem_t camera_imagesize_locals_dict_table[] = { - {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_320x240), MP_ROM_PTR(&camera_imagesize_320x240_obj)}, - {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_640x320), MP_ROM_PTR(&camera_imagesize_640x320_obj)}, - {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_1280x720), MP_ROM_PTR(&camera_imagesize_1280x720_obj)}, - {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_1280x960), MP_ROM_PTR(&camera_imagesize_1280x960_obj)}, - {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_1920x1080), MP_ROM_PTR(&camera_imagesize_1920x1080_obj)}, - {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_2048x1536), MP_ROM_PTR(&camera_imagesize_2048x1536_obj)}, - {MP_ROM_QSTR(MP_QSTR_IMAGE_SIZE_2560x1920), MP_ROM_PTR(&camera_imagesize_2560x1920_obj)}, -}; -STATIC MP_DEFINE_CONST_DICT(camera_imagesize_locals_dict, camera_imagesize_locals_dict_table); - -STATIC void camera_imagesize_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { - qstr size = MP_QSTR_None; - if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_320x240_obj)) { - size = MP_QSTR_IMAGE_SIZE_320x240; - } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_640x320_obj)) { - size = MP_QSTR_IMAGE_SIZE_640x320; - } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_1280x720_obj)) { - size = MP_QSTR_IMAGE_SIZE_1280x720; - } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_1280x960_obj)) { - size = MP_QSTR_IMAGE_SIZE_1280x960; - } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_1920x1080_obj)) { - size = MP_QSTR_IMAGE_SIZE_1920x1080; - } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_2048x1536_obj)) { - size = MP_QSTR_IMAGE_SIZE_2048x1536; - } else if (MP_OBJ_TO_PTR(self_in) == MP_ROM_PTR(&camera_imagesize_2560x1920_obj)) { - size = MP_QSTR_IMAGE_SIZE_2560x1920; - } - mp_printf(print, "%q.%q.%q", MP_QSTR_camera, MP_QSTR_ImageSize, size); -} - -const mp_obj_type_t camera_imagesize_type = { - { &mp_type_type }, - .name = MP_QSTR_ImageSize, - .print = camera_imagesize_print, - .locals_dict = (mp_obj_t)&camera_imagesize_locals_dict, -}; diff --git a/shared-bindings/camera/__init__.c b/shared-bindings/camera/__init__.c index 3398d1ade6..28cf7df575 100644 --- a/shared-bindings/camera/__init__.c +++ b/shared-bindings/camera/__init__.c @@ -39,7 +39,7 @@ STATIC const mp_rom_map_elem_t camera_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_Camera), MP_ROM_PTR(&camera_type) }, // Enum-like Classes. - { MP_ROM_QSTR(MP_QSTR_ImageSize), MP_ROM_PTR(&camera_imagesize_type) }, + { MP_ROM_QSTR(MP_QSTR_ImageSize), MP_ROM_PTR(&camera_imageformat_type) }, }; STATIC MP_DEFINE_CONST_DICT(camera_module_globals, camera_module_globals_table); From a25e3c2858e565e465849669c96da560b4af228f Mon Sep 17 00:00:00 2001 From: Kamil Tomaszewski Date: Fri, 11 Sep 2020 13:31:34 +0200 Subject: [PATCH 32/91] locale: make translate --- locale/circuitpython.pot | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 7bf2f851da..20cf75264a 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -430,7 +430,7 @@ msgstr "" msgid "Buffer is not a bytearray." msgstr "" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "" @@ -676,10 +676,6 @@ msgstr "" msgid "Couldn't allocate input buffer" msgstr "" -#: ports/cxd56/common-hal/camera/Camera.c -msgid "Couldn't allocate picture buffer" -msgstr "" - #: shared-module/audiocore/WaveFile.c shared-module/audiomixer/Mixer.c #: shared-module/audiomp3/MP3Decoder.c msgid "Couldn't allocate second buffer" @@ -849,6 +845,10 @@ msgstr "" msgid "File exists" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1006,10 +1006,6 @@ msgstr "" msgid "Invalid frequency supplied" msgstr "" -#: shared-bindings/camera/Camera.c -msgid "Invalid image size." -msgstr "" - #: supervisor/shared/safe_mode.c msgid "Invalid memory access." msgstr "" From ce7ee58e92eca840f75c2fcf885fe862f1ebec13 Mon Sep 17 00:00:00 2001 From: Kamil Tomaszewski Date: Mon, 14 Sep 2020 12:55:53 +0200 Subject: [PATCH 33/91] camera: Update camera module --- ports/cxd56/common-hal/camera/Camera.c | 38 +++++++++++++++----------- ports/cxd56/supervisor/port.c | 8 ++++-- shared-bindings/camera/Camera.c | 4 +-- shared-bindings/camera/__init__.c | 2 +- 4 files changed, 30 insertions(+), 22 deletions(-) diff --git a/ports/cxd56/common-hal/camera/Camera.c b/ports/cxd56/common-hal/camera/Camera.c index 9376822c8a..a4e197bf33 100644 --- a/ports/cxd56/common-hal/camera/Camera.c +++ b/ports/cxd56/common-hal/camera/Camera.c @@ -42,18 +42,28 @@ typedef struct { STATIC camera_dev_t camera_dev = {"/dev/video", -1}; +typedef struct { + uint16_t width; + uint16_t height; +} image_size_t; + +STATIC const image_size_t image_size_table[] = { + { VIDEO_HSIZE_QVGA, VIDEO_VSIZE_QVGA }, + { VIDEO_HSIZE_VGA, VIDEO_VSIZE_VGA }, + { VIDEO_HSIZE_HD, VIDEO_VSIZE_HD }, + { VIDEO_HSIZE_QUADVGA, VIDEO_VSIZE_QUADVGA }, + { VIDEO_HSIZE_FULLHD, VIDEO_VSIZE_FULLHD }, + { VIDEO_HSIZE_3M, VIDEO_VSIZE_3M }, + { VIDEO_HSIZE_5M, VIDEO_VSIZE_5M }, +}; + static bool camera_check_width_and_height(uint16_t width, uint16_t height) { - if ((width == VIDEO_HSIZE_QVGA && height == VIDEO_VSIZE_QVGA) || - (width == VIDEO_HSIZE_VGA && height == VIDEO_VSIZE_VGA) || - (width == VIDEO_HSIZE_HD && height == VIDEO_VSIZE_HD) || - (width == VIDEO_HSIZE_QUADVGA && height == VIDEO_VSIZE_QUADVGA) || - (width == VIDEO_HSIZE_FULLHD && height == VIDEO_VSIZE_FULLHD) || - (width == VIDEO_HSIZE_3M && height == VIDEO_VSIZE_3M) || - (width == VIDEO_HSIZE_5M && height == VIDEO_VSIZE_5M)) { - return true; - } else { - return false; + for (int i = 0; i < MP_ARRAY_SIZE(image_size_table); i++) { + if (image_size_table[i].width == width && image_size_table[i].height == height) { + return true; + } } + return false; } static bool camera_check_buffer_length(uint16_t width, uint16_t height, camera_imageformat_t format, size_t length) { @@ -61,18 +71,14 @@ static bool camera_check_buffer_length(uint16_t width, uint16_t height, camera_i // In SPRESENSE SDK, JPEG compression quality=80 by default. // In such setting, the maximum actual measured size of JPEG image // is about width * height * 2 / 9. - return length >= (size_t)(width * height * 2 / 9) ? true : false; + return length >= (size_t)(width * height * 2 / 9); } else { return false; } } static bool camera_check_format(camera_imageformat_t format) { - if (format == IMAGEFORMAT_JPG) { - return true; - } else { - return false; - } + return format == IMAGEFORMAT_JPG; } static void camera_set_format(enum v4l2_buf_type type, uint32_t pixformat, uint16_t width, uint16_t height) { diff --git a/ports/cxd56/supervisor/port.c b/ports/cxd56/supervisor/port.c index 6a32dc0f9e..6164f74113 100644 --- a/ports/cxd56/supervisor/port.c +++ b/ports/cxd56/supervisor/port.c @@ -46,7 +46,7 @@ #include "common-hal/pwmio/PWMOut.h" #include "common-hal/busio/UART.h" -#define HEAP_SIZE (1000 * 1024) +#define SPRESENSE_MEM_ALIGN (32) uint32_t* heap; uint32_t heap_size; @@ -57,8 +57,10 @@ safe_mode_t port_init(void) { // Wait until RTC is available while (g_rtc_enabled == false); - heap = memalign(32, HEAP_SIZE); - heap_size = HEAP_SIZE / sizeof(uint32_t); + heap = memalign(SPRESENSE_MEM_ALIGN, 128 * 1024); + uint32_t size = CONFIG_RAM_START + CONFIG_RAM_SIZE - (uint32_t)heap - 2 * SPRESENSE_MEM_ALIGN; + heap = realloc(heap, size); + heap_size = size / sizeof(uint32_t); if (board_requests_safe_mode()) { return USER_SAFE_MODE; diff --git a/shared-bindings/camera/Camera.c b/shared-bindings/camera/Camera.c index 3b839d802f..5fe54e429d 100644 --- a/shared-bindings/camera/Camera.c +++ b/shared-bindings/camera/Camera.c @@ -52,7 +52,7 @@ //| //| buffer = bytearray(512 * 1024) //| file = open("/sd/image.jpg","wb") -//| size = cam.take_picture() +//| size = cam.take_picture(buffer, camera.ImageFormat.JPG) //| file.write(buffer, size) //| file.close()""" //| @@ -99,7 +99,7 @@ STATIC void check_for_deinit(camera_obj_t *self) { //| def take_picture(self, buf: WriteableBuffer, format: ImageFormat) -> int: //| """Take picture and save to ``buf`` in the given ``format`` //| -//| :return: the size of the picture taken +//| :return: the number of bytes written into buf //| :rtype: int""" //| ... //| diff --git a/shared-bindings/camera/__init__.c b/shared-bindings/camera/__init__.c index 28cf7df575..080516d51c 100644 --- a/shared-bindings/camera/__init__.c +++ b/shared-bindings/camera/__init__.c @@ -39,7 +39,7 @@ STATIC const mp_rom_map_elem_t camera_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_Camera), MP_ROM_PTR(&camera_type) }, // Enum-like Classes. - { MP_ROM_QSTR(MP_QSTR_ImageSize), MP_ROM_PTR(&camera_imageformat_type) }, + { MP_ROM_QSTR(MP_QSTR_ImageFormat), MP_ROM_PTR(&camera_imageformat_type) }, }; STATIC MP_DEFINE_CONST_DICT(camera_module_globals, camera_module_globals_table); From c68098777daab6454be82b9f9bd875473c31b566 Mon Sep 17 00:00:00 2001 From: DavePutz Date: Mon, 14 Sep 2020 10:50:57 -0500 Subject: [PATCH 34/91] Fixing up locale/circuitpython.pot date --- locale/circuitpython.pot | 147 +++++++++++++++++++++++++++++---------- 1 file changed, 109 insertions(+), 38 deletions(-) diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 0bf0cff1cf..351d30e651 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-08-18 11:19-0400\n" +"POT-Creation-Date: 2020-09-13 14:21-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -30,12 +30,6 @@ msgid "" "https://github.com/adafruit/circuitpython/issues\n" msgstr "" -#: supervisor/shared/safe_mode.c -msgid "" -"\n" -"To exit, please reset the board without " -msgstr "" - #: py/obj.c msgid " File \"%q\"" msgstr "" @@ -273,7 +267,7 @@ msgstr "" msgid "A hardware interrupt channel is already in use" msgstr "" -#: shared-bindings/_bleio/Address.c +#: shared-bindings/_bleio/Address.c shared-bindings/ipaddress/IPv4Address.c #, c-format msgid "Address must be %d bytes long" msgstr "" @@ -302,7 +296,7 @@ msgstr "" msgid "All sync event channels in use" msgstr "" -#: shared-bindings/pulseio/PWMOut.c +#: shared-bindings/pwmio/PWMOut.c msgid "All timers for this pin are in use" msgstr "" @@ -314,7 +308,7 @@ msgstr "" #: ports/cxd56/common-hal/pulseio/PulseOut.c #: ports/nrf/common-hal/audiopwmio/PWMAudioOut.c #: ports/nrf/common-hal/pulseio/PulseIn.c ports/nrf/peripherals/nrf/timers.c -#: ports/stm/peripherals/timers.c shared-bindings/pulseio/PWMOut.c +#: ports/stm/peripherals/timers.c shared-bindings/pwmio/PWMOut.c msgid "All timers in use" msgstr "" @@ -371,6 +365,10 @@ msgstr "" msgid "Attempted heap allocation when MicroPython VM not running." msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "Authentication failure" +msgstr "" + #: main.c msgid "Auto-reload is off.\n" msgstr "" @@ -490,6 +488,10 @@ msgstr "" msgid "Can't set CCCD on local Characteristic" msgstr "" +#: shared-bindings/_bleio/Adapter.c +msgid "Cannot create a new Adapter; use _bleio.adapter;" +msgstr "" + #: shared-bindings/displayio/Bitmap.c #: shared-bindings/memorymonitor/AllocationSize.c #: shared-bindings/pulseio/PulseIn.c @@ -552,7 +554,7 @@ msgstr "" msgid "Cannot unambiguously get sizeof scalar" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Cannot vary frequency on a timer that is already in use" msgstr "" @@ -574,6 +576,10 @@ msgid "" "boot. Press again to exit safe mode.\n" msgstr "" +#: supervisor/shared/safe_mode.c +msgid "CircuitPython was unable to allocate the heap.\n" +msgstr "" + #: shared-module/bitbangio/SPI.c msgid "Clock pin init failed." msgstr "" @@ -621,23 +627,23 @@ msgstr "" msgid "Could not initialize UART" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not initialize channel" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not initialize timer" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not re-init channel" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not re-init timer" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not restart PWM" msgstr "" @@ -645,7 +651,7 @@ msgstr "" msgid "Could not set address" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not start PWM" msgstr "" @@ -742,8 +748,8 @@ msgstr "" msgid "Error in regex" msgstr "" -#: shared-bindings/aesio/aes.c shared-bindings/busio/SPI.c -#: shared-bindings/microcontroller/Pin.c +#: shared-bindings/_bleio/__init__.c shared-bindings/aesio/aes.c +#: shared-bindings/busio/SPI.c shared-bindings/microcontroller/Pin.c #: shared-bindings/neopixel_write/__init__.c #: shared-bindings/terminalio/Terminal.c msgid "Expected a %q" @@ -754,10 +760,18 @@ msgstr "" msgid "Expected a Characteristic" msgstr "" +#: shared-bindings/_bleio/Adapter.c +msgid "Expected a DigitalInOut" +msgstr "" + #: shared-bindings/_bleio/Characteristic.c msgid "Expected a Service" msgstr "" +#: shared-bindings/_bleio/Adapter.c +msgid "Expected a UART" +msgstr "" + #: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c #: shared-bindings/_bleio/Service.c msgid "Expected a UUID" @@ -836,7 +850,7 @@ msgstr "" msgid "Frequency captured is above capability. Capture Paused." msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Frequency must match existing PWMOut using this timer" msgstr "" @@ -942,9 +956,9 @@ msgstr "" msgid "Invalid DAC pin supplied" msgstr "" -#: ports/atmel-samd/common-hal/pulseio/PWMOut.c -#: ports/cxd56/common-hal/pulseio/PWMOut.c -#: ports/nrf/common-hal/pulseio/PWMOut.c shared-bindings/pulseio/PWMOut.c +#: ports/atmel-samd/common-hal/pwmio/PWMOut.c +#: ports/cxd56/common-hal/pwmio/PWMOut.c ports/nrf/common-hal/pwmio/PWMOut.c +#: shared-bindings/pwmio/PWMOut.c msgid "Invalid PWM frequency" msgstr "" @@ -984,7 +998,7 @@ msgstr "" msgid "Invalid format chunk size" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Invalid frequency supplied" msgstr "" @@ -1002,8 +1016,8 @@ msgid "Invalid phase" msgstr "" #: ports/atmel-samd/common-hal/audioio/AudioOut.c -#: ports/atmel-samd/common-hal/touchio/TouchIn.c -#: shared-bindings/pulseio/PWMOut.c shared-module/rgbmatrix/RGBMatrix.c +#: ports/atmel-samd/common-hal/touchio/TouchIn.c shared-bindings/pwmio/PWMOut.c +#: shared-module/rgbmatrix/RGBMatrix.c msgid "Invalid pin" msgstr "" @@ -1027,7 +1041,7 @@ msgstr "" msgid "Invalid pins" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "Invalid pins for PWMOut" msgstr "" @@ -1209,10 +1223,14 @@ msgstr "" msgid "No long integer support" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "No more timers available on this pin." msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "No network with that ssid" +msgstr "" + #: shared-module/touchio/TouchIn.c msgid "No pulldown on pin; 1Mohm recommended" msgstr "" @@ -1233,6 +1251,10 @@ msgstr "" msgid "Nordic Soft Device failure assertion." msgstr "" +#: shared-bindings/ipaddress/IPv4Address.c shared-bindings/ipaddress/__init__.c +msgid "Not a valid IP string" +msgstr "" + #: ports/nrf/common-hal/_bleio/__init__.c #: shared-bindings/_bleio/CharacteristicBuffer.c msgid "Not connected" @@ -1247,6 +1269,10 @@ msgstr "" msgid "Not running saved code.\n" msgstr "" +#: shared-bindings/_bleio/__init__.c +msgid "Not settable" +msgstr "" + #: shared-bindings/util.c msgid "" "Object has been deinitialized and can no longer be used. Create a new object." @@ -1273,16 +1299,20 @@ msgid "" "%d bpp given" msgstr "" +#: shared-bindings/ipaddress/__init__.c +msgid "Only raw int supported for ip" +msgstr "" + #: shared-bindings/audiobusio/PDMIn.c msgid "Oversample must be multiple of 8." msgstr "" -#: shared-bindings/pulseio/PWMOut.c +#: shared-bindings/pwmio/PWMOut.c msgid "" "PWM duty_cycle must be between 0 and 65535 inclusive (16 bit resolution)" msgstr "" -#: shared-bindings/pulseio/PWMOut.c +#: shared-bindings/pwmio/PWMOut.c msgid "" "PWM frequency not writable when variable_frequency is False on construction." msgstr "" @@ -1337,8 +1367,8 @@ msgstr "" #: ports/nrf/common-hal/pulseio/PulseOut.c #: ports/stm/common-hal/pulseio/PulseOut.c msgid "" -"Port does not accept pins or frequency. " -"Construct and pass a PWMOut Carrier instead" +"Port does not accept pins or frequency. Construct and pass a PWMOut Carrier " +"instead" msgstr "" #: shared-bindings/_bleio/Adapter.c @@ -1353,10 +1383,6 @@ msgstr "" msgid "Pull not used when direction is output." msgstr "" -#: ports/stm/ref/pulseout-pre-timeralloc.c -msgid "PulseOut not supported on this chip" -msgstr "" - #: ports/stm/common-hal/os/__init__.c msgid "RNG DeInit Error" msgstr "" @@ -1473,6 +1499,10 @@ msgstr "" msgid "Serializer in use" msgstr "" +#: shared-bindings/ssl/SSLContext.c +msgid "Server side context cannot have hostname" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "" @@ -1568,11 +1598,15 @@ msgstr "" msgid "Timeout is too long: Maximum timeout length is %d seconds" msgstr "" -#: ports/stm/common-hal/pulseio/PWMOut.c +#: ports/stm/common-hal/pwmio/PWMOut.c msgid "" "Timer was reserved for internal use - declare PWM pins earlier in the program" msgstr "" +#: supervisor/shared/safe_mode.c +msgid "To exit, please reset the board without " +msgstr "" + #: ports/atmel-samd/common-hal/audiobusio/I2SOut.c msgid "Too many channels in sample." msgstr "" @@ -1668,6 +1702,10 @@ msgstr "" msgid "Unexpected nrfx uuid type" msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "Unknown failure" +msgstr "" + #: ports/nrf/common-hal/_bleio/__init__.c #, c-format msgid "Unknown gatt error: 0x%04x" @@ -1771,6 +1809,10 @@ msgid "" "To list built-in modules please do `help(\"modules\")`.\n" msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "WiFi password must be between 8 and 63 characters" +msgstr "" + #: ports/nrf/common-hal/_bleio/PacketBuffer.c msgid "Writes not supported on Characteristic" msgstr "" @@ -1885,7 +1927,7 @@ msgstr "" msgid "bad format string" msgstr "" -#: py/binary.c +#: py/binary.c py/objarray.c msgid "bad typecode" msgstr "" @@ -1938,6 +1980,10 @@ msgstr "" msgid "bytes > 8 bits not supported" msgstr "" +#: py/objarray.c +msgid "bytes length not a multiple of item size" +msgstr "" + #: py/objstr.c msgid "bytes value out of range" msgstr "" @@ -2457,6 +2503,10 @@ msgstr "" msgid "initial values must be iterable" msgstr "" +#: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c +msgid "initial_value length is wrong" +msgstr "" + #: py/compile.c msgid "inline assembler must be a function" msgstr "" @@ -2649,6 +2699,10 @@ msgstr "" msgid "max_length must be 0-%d when fixed_length is %s" msgstr "" +#: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c +msgid "max_length must be > 0" +msgstr "" + #: py/runtime.c msgid "maximum recursion depth exceeded" msgstr "" @@ -2883,10 +2937,23 @@ msgstr "" msgid "ord() expected a character, but string of length %d found" msgstr "" +#: shared-bindings/displayio/Bitmap.c +msgid "out of range of source" +msgstr "" + +#: shared-bindings/displayio/Bitmap.c +msgid "out of range of target" +msgstr "" + #: py/objint_mpz.c msgid "overflow converting long int to machine word" msgstr "" +#: py/modstruct.c +#, c-format +msgid "pack expected %d items for packing (got %d)" +msgstr "" + #: shared-bindings/_stage/Layer.c shared-bindings/_stage/Text.c msgid "palette must be 32 bytes long" msgstr "" @@ -3060,6 +3127,10 @@ msgstr "" msgid "sosfilt requires iterable arguments" msgstr "" +#: shared-bindings/displayio/Bitmap.c +msgid "source palette too large" +msgstr "" + #: py/objstr.c msgid "start/end indices" msgstr "" From 127346f7aeaddd724449c1c5beb71d5ad0c169a5 Mon Sep 17 00:00:00 2001 From: DavePutz Date: Mon, 14 Sep 2020 10:52:46 -0500 Subject: [PATCH 35/91] Removing some prior changes --- supervisor/background_callback.h | 4 ---- supervisor/port.h | 5 ++--- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/supervisor/background_callback.h b/supervisor/background_callback.h index e943830fd0..535dd656be 100644 --- a/supervisor/background_callback.h +++ b/supervisor/background_callback.h @@ -27,8 +27,6 @@ #ifndef CIRCUITPY_INCLUDED_SUPERVISOR_BACKGROUND_CALLBACK_H #define CIRCUITPY_INCLUDED_SUPERVISOR_BACKGROUND_CALLBACK_H -#include "supervisor/port.h" - /** Background callbacks are a linked list of tasks to call in the background. * * Include a member of type `background_callback_t` inside an object @@ -86,6 +84,4 @@ void background_callback_end_critical_section(void); */ void background_callback_gc_collect(void); -uint64_t background_get_ticks(void); - #endif diff --git a/supervisor/port.h b/supervisor/port.h index c95e43fd2e..ddb96bd524 100644 --- a/supervisor/port.h +++ b/supervisor/port.h @@ -69,13 +69,12 @@ uint32_t *port_heap_get_bottom(void); // Get heap top address uint32_t *port_heap_get_top(void); +supervisor_allocation* port_fixed_heap(void); + // Save and retrieve a word from memory that is preserved over reset. Used for safe mode. void port_set_saved_word(uint32_t); uint32_t port_get_saved_word(void); -// Used to keep track of last time background was run -uint64_t get_background_ticks(void); - // Get the raw tick count since start up. A tick is 1/1024 of a second, a common low frequency // clock rate. If subticks is not NULL then the port will fill in the number of subticks where each // tick is 32 subticks (for a resolution of 1/32768 or 30.5ish microseconds.) From 6b93f97de1e535b9b921b68c85360bfee5cc38c1 Mon Sep 17 00:00:00 2001 From: DavePutz Date: Mon, 14 Sep 2020 10:53:30 -0500 Subject: [PATCH 36/91] Removing some prior changes --- supervisor/shared/background_callback.c | 7 ------- supervisor/shared/tick.c | 21 +++++++-------------- 2 files changed, 7 insertions(+), 21 deletions(-) diff --git a/supervisor/shared/background_callback.c b/supervisor/shared/background_callback.c index 154618297e..8e12dd3625 100644 --- a/supervisor/shared/background_callback.c +++ b/supervisor/shared/background_callback.c @@ -37,14 +37,7 @@ STATIC volatile background_callback_t *callback_head, *callback_tail; #define CALLBACK_CRITICAL_BEGIN (common_hal_mcu_disable_interrupts()) #define CALLBACK_CRITICAL_END (common_hal_mcu_enable_interrupts()) -uint64_t last_background_tick = 0; - -uint64_t get_background_ticks(void) { - return last_background_tick; -} - void background_callback_add_core(background_callback_t *cb) { - last_background_tick = port_get_raw_ticks(NULL); CALLBACK_CRITICAL_BEGIN; if (cb->prev || callback_head == cb) { CALLBACK_CRITICAL_END; diff --git a/supervisor/shared/tick.c b/supervisor/shared/tick.c index eac5104a5c..012f2c80e8 100644 --- a/supervisor/shared/tick.c +++ b/supervisor/shared/tick.c @@ -27,6 +27,7 @@ #include "supervisor/shared/tick.h" #include "py/mpstate.h" +#include "py/runtime.h" #include "supervisor/linker.h" #include "supervisor/filesystem.h" #include "supervisor/background_callback.h" @@ -36,7 +37,7 @@ #if CIRCUITPY_BLEIO #include "supervisor/shared/bluetooth.h" -#include "common-hal/_bleio/bonding.h" +#include "common-hal/_bleio/__init__.h" #endif #if CIRCUITPY_DISPLAYIO @@ -68,6 +69,8 @@ static volatile uint64_t PLACE_IN_DTCM_BSS(background_ticks); static background_callback_t tick_callback; +volatile uint64_t last_finished_tick = 0; + void supervisor_background_tasks(void *unused) { port_start_background_task(); @@ -84,7 +87,7 @@ void supervisor_background_tasks(void *unused) { #if CIRCUITPY_BLEIO supervisor_bluetooth_background(); - bonding_background(); + bleio_background(); #endif port_background_task(); @@ -95,7 +98,7 @@ void supervisor_background_tasks(void *unused) { } bool supervisor_background_tasks_ok(void) { - return port_get_raw_ticks(NULL) - get_background_ticks() < 1024; + return port_get_raw_ticks(NULL) - last_finished_tick < 1024; } void supervisor_tick(void) { @@ -145,17 +148,7 @@ void mp_hal_delay_ms(mp_uint_t delay) { while (remaining > 0) { RUN_BACKGROUND_TASKS; // Check to see if we've been CTRL-Ced by autoreload or the user. - if(MP_STATE_VM(mp_pending_exception) == MP_OBJ_FROM_PTR(&MP_STATE_VM(mp_kbd_exception))) - { - // clear exception and generate stacktrace - MP_STATE_VM(mp_pending_exception) = MP_OBJ_NULL; - nlr_raise(&MP_STATE_VM(mp_kbd_exception)); - } - if( MP_STATE_VM(mp_pending_exception) == MP_OBJ_FROM_PTR(&MP_STATE_VM(mp_reload_exception)) || - WATCHDOG_EXCEPTION_CHECK()) { - // stop sleeping immediately - break; - } + mp_handle_pending(); remaining = end_tick - port_get_raw_ticks(NULL); // We break a bit early so we don't risk setting the alarm before the time when we call // sleep. From c014ac308903f6f0224c667624609f02a624bac0 Mon Sep 17 00:00:00 2001 From: DavePutz Date: Mon, 14 Sep 2020 10:54:57 -0500 Subject: [PATCH 37/91] Reworked check for input taking too long --- ports/atmel-samd/common-hal/pulseio/PulseIn.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c index 27bf842d56..9a9bf57a0d 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c @@ -51,6 +51,7 @@ static uint8_t refcount = 0; static uint8_t pulsein_tc_index = 0xff; volatile static uint32_t overflow_count = 0; +volatile static uint32_t start_overflow = 0; void pulsein_timer_interrupt_handler(uint8_t index) { if (index != pulsein_tc_index) return; @@ -91,6 +92,9 @@ void pulsein_interrupt_handler(uint8_t channel) { uint32_t current_count = tc->COUNT16.COUNT.reg; pulseio_pulsein_obj_t* self = get_eic_channel_data(channel); + if (self->len == 0 ) { + start_overflow = overflow_count; + } if (self->first_edge) { self->first_edge = false; pulsein_set_config(self, false); @@ -110,16 +114,21 @@ void pulsein_interrupt_handler(uint8_t channel) { if (total_diff < duration) { duration = total_diff; } + //check if the input is taking too long, 15 timer overflows is approx 1 second + if (current_overflow - start_overflow > 15) { + self->errored_too_fast = true; + common_hal_pulseio_pulsein_pause(self); + common_hal_mcu_enable_interrupts(); + return; + } uint16_t i = (self->start + self->len) % self->maxlen; + self->buffer[i] = duration; if (self->len < self->maxlen) { self->len++; } else { - self->errored_too_fast = true; - common_hal_mcu_enable_interrupts(); - return; + self->start++; } - self->buffer[i] = duration; } self->last_overflow = current_overflow; self->last_count = current_count; @@ -300,6 +309,7 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { mp_raise_IndexError(translate("pop from an empty PulseIn")); } if (self->errored_too_fast) { + self->errored_too_fast = 0; mp_raise_RuntimeError(translate("Input taking too long")); } common_hal_mcu_disable_interrupts(); From e504438fd223c9bb0b9d6950a699f1283ece137c Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Mon, 14 Sep 2020 11:58:13 -0400 Subject: [PATCH 38/91] Remove unlicensed file, fix reset pin type check --- ports/esp32s2/boards/esp32s2-saola-1.cfg | 41 ------------------------ shared-module/displayio/I2CDisplay.c | 4 +-- 2 files changed, 2 insertions(+), 43 deletions(-) delete mode 100644 ports/esp32s2/boards/esp32s2-saola-1.cfg diff --git a/ports/esp32s2/boards/esp32s2-saola-1.cfg b/ports/esp32s2/boards/esp32s2-saola-1.cfg deleted file mode 100644 index 6772907570..0000000000 --- a/ports/esp32s2/boards/esp32s2-saola-1.cfg +++ /dev/null @@ -1,41 +0,0 @@ -# The ESP32-S2 only supports JTAG. -transport select jtag -adapter_khz 1000 - -# Source the ESP common configuration file -source [find target/esp_common.cfg] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME esp32s2 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x120034e5 -} - -set _TARGETNAME $_CHIPNAME -set _CPUNAME cpu -set _TAPNAME $_CHIPNAME.$_CPUNAME - -jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID - -if { $_RTOS == "none" } { - target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME -} else { - target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME -rtos $_RTOS -} - -configure_esp_workarea $_TARGETNAME 0x40030000 0x3400 0x3FFE0000 0x6000 -configure_esp_flash_bank $_TARGETNAME $_TARGETNAME $_FLASH_SIZE - -xtensa maskisr on -if { $_SEMIHOST_BASEDIR != "" } { - esp semihost_basedir $_SEMIHOST_BASEDIR -} -if { $_FLASH_SIZE == 0 } { - gdb_breakpoint_override hard -} diff --git a/shared-module/displayio/I2CDisplay.c b/shared-module/displayio/I2CDisplay.c index 9e9e178812..5bd03dcd65 100644 --- a/shared-module/displayio/I2CDisplay.c +++ b/shared-module/displayio/I2CDisplay.c @@ -72,8 +72,8 @@ void common_hal_displayio_i2cdisplay_deinit(displayio_i2cdisplay_obj_t* self) { common_hal_busio_i2c_deinit(self->bus); } - if (self->reset.pin) { - common_hal_reset_pin(self->reset.pin); + if (self->reset.base.type == &digitalio_digitalinout_type) { + common_hal_digitalio_digitalinout_deinit(&self->reset); } } From 2eca4ee90244bc3c09999eb9efa5cd9ef611c3e3 Mon Sep 17 00:00:00 2001 From: DavePutz Date: Mon, 14 Sep 2020 11:04:45 -0500 Subject: [PATCH 39/91] Update PulseIn.c --- ports/atmel-samd/common-hal/pulseio/PulseIn.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c index 9a9bf57a0d..9930fe9c9f 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c @@ -115,11 +115,11 @@ void pulsein_interrupt_handler(uint8_t channel) { duration = total_diff; } //check if the input is taking too long, 15 timer overflows is approx 1 second - if (current_overflow - start_overflow > 15) { - self->errored_too_fast = true; - common_hal_pulseio_pulsein_pause(self); + if (current_overflow - start_overflow > 15) { + self->errored_too_fast = true; + common_hal_pulseio_pulsein_pause(self); common_hal_mcu_enable_interrupts(); - return; + return; } uint16_t i = (self->start + self->len) % self->maxlen; From da0a0f88f9d6bbaf0debfe93f01ed162cf38eae2 Mon Sep 17 00:00:00 2001 From: DavePutz Date: Mon, 14 Sep 2020 11:27:08 -0500 Subject: [PATCH 41/91] Reverting some prior changes --- supervisor/shared/tick.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/supervisor/shared/tick.c b/supervisor/shared/tick.c index 012f2c80e8..91ffa307d7 100644 --- a/supervisor/shared/tick.c +++ b/supervisor/shared/tick.c @@ -94,6 +94,8 @@ void supervisor_background_tasks(void *unused) { assert_heap_ok(); + last_finished_tick = port_get_raw_ticks(NULL); + port_finish_background_task(); } From 6ecfdda580a7d27b1aaeb7d37f63fdb7f10b3779 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Mon, 14 Sep 2020 13:18:51 -0400 Subject: [PATCH 43/91] Add Readme --- ports/esp32s2/README.md | 88 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 ports/esp32s2/README.md diff --git a/ports/esp32s2/README.md b/ports/esp32s2/README.md new file mode 100644 index 0000000000..86aa99a13a --- /dev/null +++ b/ports/esp32s2/README.md @@ -0,0 +1,88 @@ +# Circuitpython on ESP32-S2 # + +This port adds the ESP32-S2 line of modules from Espressif to Circuitpython. ESP32-S2 modules are low power, single-core Wi-Fi microcontroller SoCs designed for IoT applications. + +## How this port is organized: ## + +- **bindings/** contains some required bindings to the ESP-IDF for exceptions and memory. +- **boards/** contains the configuration files for each development board and breakout available on the port. +- **common-hal/** contains the port-specific module implementations, used by shared-module and shared-bindings. +- **esp-idf/** contains the Espressif IoT development framework installation, includign all the drivers for the port. +- **modules/** contains information specific to certain ESP32-S2 hardware modules, such as the pins used for flash and RAM on the WROVER and WROOM. +- **peripherals/** contains peripheral setup files and peripheral mapping information, sorted by family and sub-variant. Most files in this directory can be generated with the python scripts in **tools/**. +- **supervisor/** contains port-specific implementations of internal flash, serial and USB, as well as the **port.c** file, which initializes the port at startup. +- **tools/** includes useful python scripts for debugging and other purposes. + +At the root level, refer to **mpconfigboard.h** and **mpconfigport.mk** for port specific settings and a list of enabled circuitpython modules. + +## Connecting to the ESP32-S2 ## + +The USB port built into ESP32-S2 boards such as the Saola is not the native USB of the board, but a debugging and programming interface. The actual ESP32-S2 native USB which exposes the Circuitpython drive and CDC connection is located on IO pins 19 and 20: + +| GPIO | USB | +| ---- | ----------- | +| 20 | D+ (green) | +| 19 | D- (white) | +| GND | GND (black) | +| 5V | +5V (red) | + +Connect these pins using a [USB adapter](https://www.adafruit.com/product/4090) or [breakout cable](https://www.adafruit.com/product/4448) to access the Circuitpython drive. + +## Building and flashing ## + +Before building or flashing the ESP32-S2, you must [install the esp-idf](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/index.html). This must be re-done ever time the esp-idf is updated, but not every time you build. From the port root, run: + +``` +./esp-idf/install.sh +``` + +Additionally, any time you open a new bash environment for building or flashing, you must add the esp-idf tools to your path: + +``` +. esp-idf/export.sh +``` + +To build for a board such as the Saola 1 Wrover and flash it over the UART interface, run the following: + +``` +make BOARD=espressif_saola_1_wrover flash +``` + +On MacOS, you may need to directly specify the port. You can determine the correct port on your machine by running `ls /dev/tty.usb*` and selecting the one that appears only when your development board is plugged in. Example: + +``` +make BOARD=espressif_saola_1_wrover flash PORT=/dev/tty.usbserial-1421120 +``` + +## Debugging ## + +The ESP32-S2 supports JTAG debugging over OpenOCD using a JLink or other probe hardware. The official tutorials can be found on the Espressif website [here](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html), but they are mostly for the ESP32-S2 Kaluga, which has built-in debugging. + +OpenOCD is automatically installed and added to your bash environment during the esp-idf installation and setup process. You can double check that it is installed by using `openocd --version`, as per the tutorial. Attach the JTAG probe pins according to the [instructions](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/configure-other-jtag.html) for JTAG debugging on boards that do not contain an integrated debugger. + +Once the debugger is connected physically, you must run OpenOCD with attached configuration files specifying the **interface** (your debugger probe) and either a **target** or a **board** (targets are for SoCs only, and can be used when a full board configuration file doesn't exist). You can find the path location of these files by checking the `OPENOCD_SCRIPTS` environmental variable by running `echo $OPENOCD_SCRIPTS` in bash. Interfaces will be in the `interface/` directory, and targets and boards in the `target/` and `board/` directories, respectively. + +**Note:** Unfortunately, there are no board files for the esp32-s2 other than the Kaluga, and the included `target/esp32s2.cfg` target file will not work by default on the Jlink for boards like the Saola 1, as the default speed is incorrect. In addition, these files are covered under the GPL and cannot be included in Circuitpython. Thus, you must make a copy of the esp32s2.cfg file yourself and add the following line manually, under `transport select jtag` at the start of the file: + +``` +adapter_khz 1000 +``` + +Once this is complete, your final OpenOCD command may look something like this: + +`openocd -f interface/jlink.cfg -f SOMEPATH/copied-esp32s2-saola-1.cfg` + +Where `SOMEPATH` is the location of your copied configuration file (this can be placed in the port/boards director with a prefix to ignore it with `.gitignore`, for instance). Interface, target and board config files sourced from espressif only need their paths from the $OPENOCD_SCRIPTS location, you don't need to include their full path. Once OpenOCD is running, connect to GDB with: + +`xtensa-esp32s2-elf-gdb build-espressif_saola_1_wrover/firmware.elf` + +And follow the Espressif GDB tutorial [instructions](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/using-debugger.html) for connecting, or add them to your `gdbinit`: + +``` +target remote :3333 +set remote hardware-watchpoint-limit 2 +mon reset halt +flushregs +thb app_main +c +``` From 3640ef2b7f5cfa2c7938b7d0d23132a033756ba5 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Mon, 14 Sep 2020 17:37:55 -0400 Subject: [PATCH 45/91] Fix toctree, incorrect flash port assumptions --- docs/supported_ports.rst | 1 + ports/esp32s2/README.md | 8 +------- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/docs/supported_ports.rst b/docs/supported_ports.rst index 09571afb67..e74067e28f 100644 --- a/docs/supported_ports.rst +++ b/docs/supported_ports.rst @@ -17,3 +17,4 @@ is limited. ../ports/mimxrt10xx/README ../ports/nrf/README ../ports/stm/README + ../ports/esp32s2/README diff --git a/ports/esp32s2/README.md b/ports/esp32s2/README.md index 86aa99a13a..5b664df08c 100644 --- a/ports/esp32s2/README.md +++ b/ports/esp32s2/README.md @@ -42,13 +42,7 @@ Additionally, any time you open a new bash environment for building or flashing, . esp-idf/export.sh ``` -To build for a board such as the Saola 1 Wrover and flash it over the UART interface, run the following: - -``` -make BOARD=espressif_saola_1_wrover flash -``` - -On MacOS, you may need to directly specify the port. You can determine the correct port on your machine by running `ls /dev/tty.usb*` and selecting the one that appears only when your development board is plugged in. Example: +Building boards such as the Saola is typically done through `make flash`. The default port is `tty.SLAB_USBtoUART`, which will only work on certain Mac setups. On most machines, both Mac and Linux, you will need to set the port yourself by running `ls /dev/tty.usb*` and selecting the one that only appears when your development board is plugged in. An example make command with the port setting is as follows: ``` make BOARD=espressif_saola_1_wrover flash PORT=/dev/tty.usbserial-1421120 From 067a97587504521007a2031038b217cf151511f5 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Mon, 14 Sep 2020 17:22:30 -0500 Subject: [PATCH 46/91] update submodules to merge commits --- ports/atmel-samd/asf4 | 2 +- ports/atmel-samd/peripherals | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/atmel-samd/asf4 b/ports/atmel-samd/asf4 index 1b87f18f80..84f56af132 160000 --- a/ports/atmel-samd/asf4 +++ b/ports/atmel-samd/asf4 @@ -1 +1 @@ -Subproject commit 1b87f18f8091f258e63f85cef54bcc7bafd44598 +Subproject commit 84f56af13292d8f32c40acbd949bde698ddd4507 diff --git a/ports/atmel-samd/peripherals b/ports/atmel-samd/peripherals index 15fd96f4d8..2ff4ab0510 160000 --- a/ports/atmel-samd/peripherals +++ b/ports/atmel-samd/peripherals @@ -1 +1 @@ -Subproject commit 15fd96f4d8c38d5490767ea09469b82a231a768d +Subproject commit 2ff4ab05101ce7d3e105009cc6612df6e992123f From 8fcdc7da16a978d7c65bd3c82c46b11c5178714c Mon Sep 17 00:00:00 2001 From: askpatricw <4002194+askpatrickw@users.noreply.github.com> Date: Mon, 14 Sep 2020 23:24:44 -0700 Subject: [PATCH 47/91] RTC enabled --- ports/esp32s2/common-hal/rtc/RTC.c | 52 +++++++++++++++++++++++++ ports/esp32s2/common-hal/rtc/RTC.h | 34 ++++++++++++++++ ports/esp32s2/common-hal/rtc/__init__.c | 0 ports/esp32s2/mpconfigport.mk | 2 +- 4 files changed, 87 insertions(+), 1 deletion(-) create mode 100644 ports/esp32s2/common-hal/rtc/RTC.c create mode 100644 ports/esp32s2/common-hal/rtc/RTC.h create mode 100644 ports/esp32s2/common-hal/rtc/__init__.c diff --git a/ports/esp32s2/common-hal/rtc/RTC.c b/ports/esp32s2/common-hal/rtc/RTC.c new file mode 100644 index 0000000000..1218186a8c --- /dev/null +++ b/ports/esp32s2/common-hal/rtc/RTC.c @@ -0,0 +1,52 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright 2019 Sony Semiconductor Solutions Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/obj.h" +#include "py/runtime.h" +#include "soc/rtc_periph.h" +#include "shared-bindings/rtc/RTC.h" + +void common_hal_rtc_get_time(timeutils_struct_time_t *tm) { + struct timeval tv_now; + gettimeofday(&tv_now, NULL); + timeutils_seconds_since_2000_to_struct_time(tv_now.tv_sec, tm); +} + +void common_hal_rtc_set_time(timeutils_struct_time_t *tm) { + struct timeval tv_now = {0}; + tv_now.tv_sec = timeutils_seconds_since_2000(tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); + settimeofday(&tv_now, NULL); +} + +int common_hal_rtc_get_calibration(void) { + return 0; +} + +void common_hal_rtc_set_calibration(int calibration) { + mp_raise_NotImplementedError(translate("RTC calibration is not supported on this board")); +} diff --git a/ports/esp32s2/common-hal/rtc/RTC.h b/ports/esp32s2/common-hal/rtc/RTC.h new file mode 100644 index 0000000000..e51f1f7848 --- /dev/null +++ b/ports/esp32s2/common-hal/rtc/RTC.h @@ -0,0 +1,34 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Noralf Trønnes + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_NRF_COMMON_HAL_RTC_RTC_H +#define MICROPY_INCLUDED_NRF_COMMON_HAL_RTC_RTC_H + +extern void rtc_init(void); +extern void rtc_reset(void); +extern void common_hal_rtc_init(void); + +#endif // MICROPY_INCLUDED_NRF_COMMON_HAL_RTC_RTC_H diff --git a/ports/esp32s2/common-hal/rtc/__init__.c b/ports/esp32s2/common-hal/rtc/__init__.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/ports/esp32s2/mpconfigport.mk b/ports/esp32s2/mpconfigport.mk index ee98ce1f42..8f057784ac 100644 --- a/ports/esp32s2/mpconfigport.mk +++ b/ports/esp32s2/mpconfigport.mk @@ -21,7 +21,7 @@ CIRCUITPY_COUNTIO = 0 CIRCUITPY_FREQUENCYIO = 0 CIRCUITPY_I2CPERIPHERAL = 0 CIRCUITPY_ROTARYIO = 0 -CIRCUITPY_RTC = 0 +CIRCUITPY_RTC = 1 CIRCUITPY_NVM = 0 # We don't have enough endpoints to include MIDI. CIRCUITPY_USB_MIDI = 0 From d9e336d39f7a19c47cd98619049f5d8e29512947 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Tue, 15 Sep 2020 13:18:04 -0500 Subject: [PATCH 48/91] supervisor translate: explain the dictionary --- supervisor/shared/translate.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/supervisor/shared/translate.h b/supervisor/shared/translate.h index 731b26d123..16296a4161 100644 --- a/supervisor/shared/translate.h +++ b/supervisor/shared/translate.h @@ -43,6 +43,19 @@ // (building the huffman encoding on UTF-16 code points gave better // compression than building it on UTF-8 bytes) // +// - code points starting at 128 (word_start) and potentially extending +// to 255 (word_end) (but never interfering with the target +// language's used code points) stand for dictionary entries in a +// dictionary with size up to 256 code points. The dictionary entries +// are computed with a heuristic based on frequent substrings of 2 to +// 9 code points. These are called "words" but are not, grammatically +// speaking, words. They're just spans of code points that frequently +// occur together. +// +// - dictionary entries are non-overlapping, and the _ending_ index of each +// entry is stored in an array. Since the index given is the ending +// index, the array is called "wends". +// // The "data" / "tail" construct is so that the struct's last member is a // "flexible array". However, the _only_ member is not permitted to be // a flexible member, so we have to declare the first byte as a separte From f9f614b3a2878383cad845f72ffef034bd2be951 Mon Sep 17 00:00:00 2001 From: askpatricw <4002194+askpatrickw@users.noreply.github.com> Date: Tue, 15 Sep 2020 11:28:31 -0700 Subject: [PATCH 49/91] code review feedback --- ports/esp32s2/mpconfigport.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/esp32s2/mpconfigport.mk b/ports/esp32s2/mpconfigport.mk index 8f057784ac..95a845736f 100644 --- a/ports/esp32s2/mpconfigport.mk +++ b/ports/esp32s2/mpconfigport.mk @@ -13,7 +13,7 @@ USB_SERIAL_NUMBER_LENGTH = 12 LONGINT_IMPL = MPZ # These modules are implemented in ports//common-hal: -CIRCUITPY_FULL_BUILD = 1 +CIRCUITPY_FULL_BUILD = 0 CIRCUITPY_ANALOGIO = 0 CIRCUITPY_AUDIOBUSIO = 0 CIRCUITPY_AUDIOIO = 0 From bd381e434f00360a5089261b7ab108d6c0fd0ad9 Mon Sep 17 00:00:00 2001 From: askpatricw <4002194+askpatrickw@users.noreply.github.com> Date: Tue, 15 Sep 2020 13:02:26 -0700 Subject: [PATCH 50/91] Revert "code review feedback" This reverts commit f9f614b3a2878383cad845f72ffef034bd2be951. --- ports/esp32s2/mpconfigport.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/esp32s2/mpconfigport.mk b/ports/esp32s2/mpconfigport.mk index 95a845736f..8f057784ac 100644 --- a/ports/esp32s2/mpconfigport.mk +++ b/ports/esp32s2/mpconfigport.mk @@ -13,7 +13,7 @@ USB_SERIAL_NUMBER_LENGTH = 12 LONGINT_IMPL = MPZ # These modules are implemented in ports//common-hal: -CIRCUITPY_FULL_BUILD = 0 +CIRCUITPY_FULL_BUILD = 1 CIRCUITPY_ANALOGIO = 0 CIRCUITPY_AUDIOBUSIO = 0 CIRCUITPY_AUDIOIO = 0 From 95e27bb8bf3e0e3ab1f21e252dafe2c974f1ad30 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Tue, 15 Sep 2020 13:43:35 -0700 Subject: [PATCH 51/91] Add more PIDs for unique boards --- .../boards/feather_m0_adalogger/mpconfigboard.mk | 2 +- .../feather_m0_express_crickit/mpconfigboard.mk | 2 +- .../boards/feather_m0_rfm69/mpconfigboard.mk | 2 +- .../boards/feather_m0_rfm9x/mpconfigboard.mk | 2 +- .../feather_radiofruit_zigbee/mpconfigboard.mk | 2 +- ports/atmel-samd/boards/pewpew10/mpconfigboard.mk | 2 +- ports/atmel-samd/boards/ugame10/mpconfigboard.mk | 2 +- ports/nrf/boards/TG-Watch02A/mpconfigboard.mk | 2 +- .../boards/electronut_labs_blip/mpconfigboard.mk | 2 +- .../makerdiary_nrf52840_mdk/mpconfigboard.mk | 2 +- .../mpconfigboard.mk | 2 +- ports/nrf/boards/pca10056/mpconfigboard.mk | 2 +- ports/nrf/boards/pca10059/mpconfigboard.mk | 2 +- ports/nrf/boards/pca10100/mpconfigboard.mk | 2 +- ports/stm/boards/meowbit_v121/mpconfigboard.mk | 2 +- ports/stm/boards/thunderpack/mpconfigboard.mk | 2 +- tools/ci_check_duplicate_usb_vid_pid.py | 14 ++++++++++++-- 17 files changed, 28 insertions(+), 18 deletions(-) diff --git a/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk index 54c5bff6a0..143910318d 100644 --- a/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x8015 +USB_PID = 0x80D3 USB_PRODUCT = "Feather M0 Adalogger" USB_MANUFACTURER = "Adafruit Industries LLC" diff --git a/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.mk index d5e03b49d4..345722575a 100644 --- a/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x8023 +USB_PID = 0x80D1 USB_PRODUCT = "Feather M0 Express" USB_MANUFACTURER = "Adafruit Industries LLC" diff --git a/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk index 7556b9517f..30701f7286 100644 --- a/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x8015 +USB_PID = 0x80D2 USB_PRODUCT = "Feather M0 RFM69" USB_MANUFACTURER = "Adafruit Industries LLC" diff --git a/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk index de79638bd3..2d8010a360 100644 --- a/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x8015 +USB_PID = 0x80D4 USB_PRODUCT = "Feather M0 RFM9x" USB_MANUFACTURER = "Adafruit Industries LLC" diff --git a/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk b/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk index e9d94638af..ef571f9ab4 100755 --- a/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x8023 +USB_PID = 0x80D0 USB_PRODUCT = "Feather RadioFruit Zigbee" USB_MANUFACTURER = "Adafruit Industries LLC" diff --git a/ports/atmel-samd/boards/pewpew10/mpconfigboard.mk b/ports/atmel-samd/boards/pewpew10/mpconfigboard.mk index 7305abf73a..1cc91a8df6 100644 --- a/ports/atmel-samd/boards/pewpew10/mpconfigboard.mk +++ b/ports/atmel-samd/boards/pewpew10/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x801D +USB_PID = 0x80D5 USB_PRODUCT = "PewPew 10.2" USB_MANUFACTURER = "Radomir Dopieralski" diff --git a/ports/atmel-samd/boards/ugame10/mpconfigboard.mk b/ports/atmel-samd/boards/ugame10/mpconfigboard.mk index 1c43369076..f34655a959 100644 --- a/ports/atmel-samd/boards/ugame10/mpconfigboard.mk +++ b/ports/atmel-samd/boards/ugame10/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x801F +USB_PID = 0x80AF USB_PRODUCT = "uGame10" USB_MANUFACTURER = "Radomir Dopieralski" diff --git a/ports/nrf/boards/TG-Watch02A/mpconfigboard.mk b/ports/nrf/boards/TG-Watch02A/mpconfigboard.mk index 08915a19b9..4f5899fa7d 100644 --- a/ports/nrf/boards/TG-Watch02A/mpconfigboard.mk +++ b/ports/nrf/boards/TG-Watch02A/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x802A +USB_PID = 0x80DB USB_PRODUCT = "TG-Watch02A" USB_MANUFACTURER = "TG-Tech" diff --git a/ports/nrf/boards/electronut_labs_blip/mpconfigboard.mk b/ports/nrf/boards/electronut_labs_blip/mpconfigboard.mk index f30b308ecf..30946057c9 100644 --- a/ports/nrf/boards/electronut_labs_blip/mpconfigboard.mk +++ b/ports/nrf/boards/electronut_labs_blip/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x803C +USB_PID = 0x80D7 USB_PRODUCT = "Blip" USB_MANUFACTURER = "Electronut Labs" diff --git a/ports/nrf/boards/makerdiary_nrf52840_mdk/mpconfigboard.mk b/ports/nrf/boards/makerdiary_nrf52840_mdk/mpconfigboard.mk index 3395750496..d69bc82357 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_mdk/mpconfigboard.mk +++ b/ports/nrf/boards/makerdiary_nrf52840_mdk/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x802A +USB_PID = 0x80DC USB_PRODUCT = "nRF52840-MDK" USB_MANUFACTURER = "makerdiary" diff --git a/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/mpconfigboard.mk b/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/mpconfigboard.mk index 55ca410d9f..c4fa121744 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/mpconfigboard.mk +++ b/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x802A +USB_PID = 0x80DD USB_PRODUCT = "nRF52840-MDK-Dongle" USB_MANUFACTURER = "makerdiary" diff --git a/ports/nrf/boards/pca10056/mpconfigboard.mk b/ports/nrf/boards/pca10056/mpconfigboard.mk index 8fd1ef08d0..f24e6f6670 100644 --- a/ports/nrf/boards/pca10056/mpconfigboard.mk +++ b/ports/nrf/boards/pca10056/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x802A +USB_PID = 0x80DA USB_PRODUCT = "PCA10056" USB_MANUFACTURER = "Nordic Semiconductor" diff --git a/ports/nrf/boards/pca10059/mpconfigboard.mk b/ports/nrf/boards/pca10059/mpconfigboard.mk index 3f97b08218..9dc3cc71ed 100644 --- a/ports/nrf/boards/pca10059/mpconfigboard.mk +++ b/ports/nrf/boards/pca10059/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x802A +USB_PID = 0x80D9 USB_PRODUCT = "PCA10059" USB_MANUFACTURER = "Nordic Semiconductor" diff --git a/ports/nrf/boards/pca10100/mpconfigboard.mk b/ports/nrf/boards/pca10100/mpconfigboard.mk index 715b65e63e..fcac550996 100644 --- a/ports/nrf/boards/pca10100/mpconfigboard.mk +++ b/ports/nrf/boards/pca10100/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x802A +USB_PID = 0x80D8 USB_PRODUCT = "PCA10100" USB_MANUFACTURER = "Nordic Semiconductor" diff --git a/ports/stm/boards/meowbit_v121/mpconfigboard.mk b/ports/stm/boards/meowbit_v121/mpconfigboard.mk index cf60c89c26..69a6c65c85 100644 --- a/ports/stm/boards/meowbit_v121/mpconfigboard.mk +++ b/ports/stm/boards/meowbit_v121/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x805A +USB_PID = 0x80CF USB_PRODUCT = "Meowbit" USB_MANUFACTURER = "Kittenbot" USB_DEVICES = "CDC,MSC" diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index 007b00cdd1..02f28775ae 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x239A -USB_PID = 0x806A +USB_PID = 0x8069 USB_PRODUCT = "Thunderpack STM32F411" USB_MANUFACTURER = "Jeremy Gillick" USB_DEVICES = "CDC,MSC" diff --git a/tools/ci_check_duplicate_usb_vid_pid.py b/tools/ci_check_duplicate_usb_vid_pid.py index b05d56012f..dd6bf56709 100644 --- a/tools/ci_check_duplicate_usb_vid_pid.py +++ b/tools/ci_check_duplicate_usb_vid_pid.py @@ -38,7 +38,13 @@ DEFAULT_IGNORELIST = [ "pygamer", "pygamer_advance", "trinket_m0", - "trinket_m0_haxpress" + "trinket_m0_haxpress", + "sparkfun_qwiic_micro_with_flash", + "sparkfun_qwiic_micro_no_flash", + "feather_m0_express", + "feather_m0_supersized", + "cp32-m4", + "metro_m4_express" ] cli_parser = argparse.ArgumentParser(description="USB VID/PID Duplicate Checker") @@ -118,9 +124,13 @@ def check_vid_pid(files, ignorelist): ) duplicate_message = ( - f"Duplicate VID/PID usage found!\n{duplicates}" + f"Duplicate VID/PID usage found!\n{duplicates}\n" + f"If you are open source maker, then you can request a PID from http://pid.codes\n" + f"Otherwise, companies should pay the USB-IF for a vendor ID: https://www.usb.org/getting-vendor-id" ) sys.exit(duplicate_message) + else: + print("No USB PID duplicates found.") if __name__ == "__main__": From 2bd169ec327abd5af0cb34ea51a766341cdaae4a Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Tue, 15 Sep 2020 18:12:06 -0700 Subject: [PATCH 52/91] Add partition layouts for 8 and 16 MB as well. --- ports/esp32s2/Makefile | 2 +- ports/esp32s2/partitions-16MB.csv | 10 ++++++++++ ports/esp32s2/{partitions.csv => partitions-4MB.csv} | 0 ports/esp32s2/partitions-8MB.csv | 10 ++++++++++ ports/esp32s2/sdkconfig-16MB.defaults | 10 ++++++++++ ports/esp32s2/sdkconfig-4MB.defaults | 10 ++++++++++ ports/esp32s2/sdkconfig-8MB.defaults | 10 ++++++++++ ports/esp32s2/sdkconfig.defaults | 8 -------- 8 files changed, 51 insertions(+), 9 deletions(-) create mode 100644 ports/esp32s2/partitions-16MB.csv rename ports/esp32s2/{partitions.csv => partitions-4MB.csv} (100%) create mode 100644 ports/esp32s2/partitions-8MB.csv create mode 100644 ports/esp32s2/sdkconfig-16MB.defaults create mode 100644 ports/esp32s2/sdkconfig-4MB.defaults create mode 100644 ports/esp32s2/sdkconfig-8MB.defaults diff --git a/ports/esp32s2/Makefile b/ports/esp32s2/Makefile index 64068b02d6..229a3bf3ab 100644 --- a/ports/esp32s2/Makefile +++ b/ports/esp32s2/Makefile @@ -230,7 +230,7 @@ $(BUILD)/esp-idf: # create the config headers $(BUILD)/esp-idf/config/sdkconfig.h: boards/$(BOARD)/sdkconfig | $(BUILD)/esp-idf - IDF_PATH=$(IDF_PATH) cmake -S . -B $(BUILD)/esp-idf -DSDKCONFIG=$(BUILD)/esp-idf/sdkconfig -DSDKCONFIG_DEFAULTS="sdkconfig.defaults;boards/$(BOARD)/sdkconfig" -DCMAKE_TOOLCHAIN_FILE=$(IDF_PATH)/tools/cmake/toolchain-esp32s2.cmake -DIDF_TARGET=esp32s2 -GNinja + IDF_PATH=$(IDF_PATH) cmake -S . -B $(BUILD)/esp-idf -DSDKCONFIG=$(BUILD)/esp-idf/sdkconfig -DSDKCONFIG_DEFAULTS="sdkconfig.defaults;sdkconfig-$(CIRCUITPY_ESP_FLASH_SIZE).defaults;boards/$(BOARD)/sdkconfig" -DCMAKE_TOOLCHAIN_FILE=$(IDF_PATH)/tools/cmake/toolchain-esp32s2.cmake -DIDF_TARGET=esp32s2 -GNinja # build a lib # Adding -d explain -j 1 -v to the ninja line will output debug info diff --git a/ports/esp32s2/partitions-16MB.csv b/ports/esp32s2/partitions-16MB.csv new file mode 100644 index 0000000000..13ea81bea5 --- /dev/null +++ b/ports/esp32s2/partitions-16MB.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +user_fs, data, fat, 0x450000, 11968K, diff --git a/ports/esp32s2/partitions.csv b/ports/esp32s2/partitions-4MB.csv similarity index 100% rename from ports/esp32s2/partitions.csv rename to ports/esp32s2/partitions-4MB.csv diff --git a/ports/esp32s2/partitions-8MB.csv b/ports/esp32s2/partitions-8MB.csv new file mode 100644 index 0000000000..f4ba9b60a1 --- /dev/null +++ b/ports/esp32s2/partitions-8MB.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +user_fs, data, fat, 0x450000, 3776K, diff --git a/ports/esp32s2/sdkconfig-16MB.defaults b/ports/esp32s2/sdkconfig-16MB.defaults new file mode 100644 index 0000000000..af477999bd --- /dev/null +++ b/ports/esp32s2/sdkconfig-16MB.defaults @@ -0,0 +1,10 @@ + +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_16MB=y +CONFIG_ESPTOOLPY_FLASHSIZE="16MB" + +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions-16MB.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions-16MB.csv" diff --git a/ports/esp32s2/sdkconfig-4MB.defaults b/ports/esp32s2/sdkconfig-4MB.defaults new file mode 100644 index 0000000000..561f971c31 --- /dev/null +++ b/ports/esp32s2/sdkconfig-4MB.defaults @@ -0,0 +1,10 @@ + +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" + +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions-4MB.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions-4MB.csv" diff --git a/ports/esp32s2/sdkconfig-8MB.defaults b/ports/esp32s2/sdkconfig-8MB.defaults new file mode 100644 index 0000000000..fcff17f46f --- /dev/null +++ b/ports/esp32s2/sdkconfig-8MB.defaults @@ -0,0 +1,10 @@ + +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_8MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="8MB" + +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions-8MB.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions-8MB.csv" diff --git a/ports/esp32s2/sdkconfig.defaults b/ports/esp32s2/sdkconfig.defaults index c0a56c1432..4094367e0c 100644 --- a/ports/esp32s2/sdkconfig.defaults +++ b/ports/esp32s2/sdkconfig.defaults @@ -88,12 +88,6 @@ CONFIG_ESPTOOLPY_FLASHFREQ_40M=y # CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set CONFIG_ESPTOOLPY_FLASHFREQ="40m" -# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set -# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set -CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y -# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set -# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set -CONFIG_ESPTOOLPY_FLASHSIZE="4MB" CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y CONFIG_ESPTOOLPY_BEFORE_RESET=y # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set @@ -119,8 +113,6 @@ CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 # CONFIG_PARTITION_TABLE_SINGLE_APP is not set # CONFIG_PARTITION_TABLE_TWO_OTA is not set CONFIG_PARTITION_TABLE_CUSTOM=y -CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" -CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" CONFIG_PARTITION_TABLE_OFFSET=0x8000 CONFIG_PARTITION_TABLE_MD5=y # end of Partition Table From fead60d2d877073aad7d4303ff885781f3cff269 Mon Sep 17 00:00:00 2001 From: "Ryan T. Hamilton" Date: Tue, 15 Sep 2020 23:32:53 -0700 Subject: [PATCH 53/91] Add BSSID to Network --- ports/esp32s2/common-hal/wifi/Network.c | 6 ++++++ shared-bindings/wifi/Network.c | 18 ++++++++++++++++++ shared-bindings/wifi/Network.h | 1 + 3 files changed, 25 insertions(+) diff --git a/ports/esp32s2/common-hal/wifi/Network.c b/ports/esp32s2/common-hal/wifi/Network.c index 0320e8f92f..e90b3d552c 100644 --- a/ports/esp32s2/common-hal/wifi/Network.c +++ b/ports/esp32s2/common-hal/wifi/Network.c @@ -35,6 +35,12 @@ mp_obj_t common_hal_wifi_network_get_ssid(wifi_network_obj_t *self) { return mp_obj_new_str(cstr, strlen(cstr)); } +#define MAC_ADDRESS_LENGTH 6 + +mp_obj_t common_hal_wifi_network_get_bssid(wifi_network_obj_t *self) { + return mp_obj_new_bytes(self->record.bssid, MAC_ADDRESS_LENGTH); +} + mp_obj_t common_hal_wifi_network_get_rssi(wifi_network_obj_t *self) { return mp_obj_new_int(self->record.rssi); } diff --git a/shared-bindings/wifi/Network.c b/shared-bindings/wifi/Network.c index b6d5e0901e..bf970a9c0f 100644 --- a/shared-bindings/wifi/Network.c +++ b/shared-bindings/wifi/Network.c @@ -58,6 +58,23 @@ const mp_obj_property_t wifi_network_ssid_obj = { }; +//| bssid: bytes +//| """BSSID of the network (usually the AP's MAC address)""" +//| +STATIC mp_obj_t wifi_network_get_bssid(mp_obj_t self) { + return common_hal_wifi_network_get_bssid(self); + +} +MP_DEFINE_CONST_FUN_OBJ_1(wifi_network_get_bssid_obj, wifi_network_get_bssid); + +const mp_obj_property_t wifi_network_bssid_obj = { + .base.type = &mp_type_property, + .proxy = { (mp_obj_t)&wifi_network_get_bssid_obj, + (mp_obj_t)&mp_const_none_obj, + (mp_obj_t)&mp_const_none_obj }, +}; + + //| rssi: int //| """Signal strength of the network""" //| @@ -94,6 +111,7 @@ const mp_obj_property_t wifi_network_channel_obj = { STATIC const mp_rom_map_elem_t wifi_network_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_ssid), MP_ROM_PTR(&wifi_network_ssid_obj) }, + { MP_ROM_QSTR(MP_QSTR_bssid), MP_ROM_PTR(&wifi_network_bssid_obj) }, { MP_ROM_QSTR(MP_QSTR_rssi), MP_ROM_PTR(&wifi_network_rssi_obj) }, { MP_ROM_QSTR(MP_QSTR_channel), MP_ROM_PTR(&wifi_network_channel_obj) }, }; diff --git a/shared-bindings/wifi/Network.h b/shared-bindings/wifi/Network.h index 6a7f7be4a0..c9bbc685e6 100644 --- a/shared-bindings/wifi/Network.h +++ b/shared-bindings/wifi/Network.h @@ -36,6 +36,7 @@ const mp_obj_type_t wifi_network_type; extern mp_obj_t common_hal_wifi_network_get_ssid(wifi_network_obj_t *self); +extern mp_obj_t common_hal_wifi_network_get_bssid(wifi_network_obj_t *self); extern mp_obj_t common_hal_wifi_network_get_rssi(wifi_network_obj_t *self); extern mp_obj_t common_hal_wifi_network_get_channel(wifi_network_obj_t *self); From c06aeda399142b50d7fc049effc22db4e2da6830 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Sarrailh?= Date: Wed, 16 Sep 2020 13:10:01 +0200 Subject: [PATCH 54/91] Add Muselab nanoesp32 s2 definition --- .github/workflows/build.yml | 1 + .../boards/muselab_nanoesp32_s2/board.c | 47 ++++++++++++++++++ .../muselab_nanoesp32_s2/mpconfigboard.h | 34 +++++++++++++ .../muselab_nanoesp32_s2/mpconfigboard.mk | 17 +++++++ .../boards/muselab_nanoesp32_s2/pins.c | 48 +++++++++++++++++++ .../boards/muselab_nanoesp32_s2/sdkconfig | 0 6 files changed, 147 insertions(+) create mode 100644 ports/esp32s2/boards/muselab_nanoesp32_s2/board.c create mode 100644 ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h create mode 100644 ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.mk create mode 100644 ports/esp32s2/boards/muselab_nanoesp32_s2/pins.c create mode 100644 ports/esp32s2/boards/muselab_nanoesp32_s2/sdkconfig diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 513ef29304..49e52dbb2e 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -244,6 +244,7 @@ jobs: - "metro_nrf52840_express" - "mini_sam_m4" - "monster_m4sk" + - "muselabnanoesp32_s2" - "ndgarage_ndbit6" - "ndgarage_ndbit6_v2" - "nfc_copy_cat" diff --git a/ports/esp32s2/boards/muselab_nanoesp32_s2/board.c b/ports/esp32s2/boards/muselab_nanoesp32_s2/board.c new file mode 100644 index 0000000000..9f708874bf --- /dev/null +++ b/ports/esp32s2/boards/muselab_nanoesp32_s2/board.c @@ -0,0 +1,47 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "mpconfigboard.h" +#include "shared-bindings/microcontroller/Pin.h" + +void board_init(void) { + // USB + common_hal_never_reset_pin(&pin_GPIO19); + common_hal_never_reset_pin(&pin_GPIO20); + + // Debug UART + common_hal_never_reset_pin(&pin_GPIO43); + common_hal_never_reset_pin(&pin_GPIO44); +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { + +} diff --git a/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h b/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h new file mode 100644 index 0000000000..5a165deccd --- /dev/null +++ b/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +//Micropython setup + +#define MICROPY_HW_BOARD_NAME "nanoESP32-S2" +#define MICROPY_HW_MCU_NAME "ESP32S2" + +#define MICROPY_HW_NEOPIXEL (&pin_GPIO18) + +#define AUTORESET_DELAY_MS 500 diff --git a/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.mk b/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.mk new file mode 100644 index 0000000000..449676d380 --- /dev/null +++ b/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.mk @@ -0,0 +1,17 @@ +USB_VID = 0x239A +USB_PID = 0x80DE +USB_PRODUCT = "nanoESP32-S2" +USB_MANUFACTURER = "Muselab" + +INTERNAL_FLASH_FILESYSTEM = 1 +LONGINT_IMPL = MPZ + +# The default queue depth of 16 overflows on release builds, +# so increase it to 32. +CFLAGS += -DCFG_TUD_TASK_QUEUE_SZ=32 + +CIRCUITPY_ESP_FLASH_MODE=dio +CIRCUITPY_ESP_FLASH_FREQ=40m +CIRCUITPY_ESP_FLASH_SIZE=4MB + +CIRCUITPY_MODULE=wroom diff --git a/ports/esp32s2/boards/muselab_nanoesp32_s2/pins.c b/ports/esp32s2/boards/muselab_nanoesp32_s2/pins.c new file mode 100644 index 0000000000..0562d9331f --- /dev/null +++ b/ports/esp32s2/boards/muselab_nanoesp32_s2/pins.c @@ -0,0 +1,48 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_GPIO0) }, + { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_GPIO1) }, + { MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_GPIO2) }, + { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_GPIO3) }, + { MP_ROM_QSTR(MP_QSTR_IO4), MP_ROM_PTR(&pin_GPIO4) }, + { MP_ROM_QSTR(MP_QSTR_IO5), MP_ROM_PTR(&pin_GPIO5) }, + { MP_ROM_QSTR(MP_QSTR_IO6), MP_ROM_PTR(&pin_GPIO6) }, + { MP_ROM_QSTR(MP_QSTR_IO7), MP_ROM_PTR(&pin_GPIO7) }, + { MP_ROM_QSTR(MP_QSTR_IO8), MP_ROM_PTR(&pin_GPIO8) }, + { MP_ROM_QSTR(MP_QSTR_IO9), MP_ROM_PTR(&pin_GPIO9) }, + { MP_ROM_QSTR(MP_QSTR_IO10), MP_ROM_PTR(&pin_GPIO10) }, + { MP_ROM_QSTR(MP_QSTR_IO11), MP_ROM_PTR(&pin_GPIO11) }, + { MP_ROM_QSTR(MP_QSTR_IO12), MP_ROM_PTR(&pin_GPIO12) }, + { MP_ROM_QSTR(MP_QSTR_IO13), MP_ROM_PTR(&pin_GPIO13) }, + { MP_ROM_QSTR(MP_QSTR_IO14), MP_ROM_PTR(&pin_GPIO14) }, + { MP_ROM_QSTR(MP_QSTR_IO15), MP_ROM_PTR(&pin_GPIO15) }, + { MP_ROM_QSTR(MP_QSTR_IO16), MP_ROM_PTR(&pin_GPIO16) }, + { MP_ROM_QSTR(MP_QSTR_IO17), MP_ROM_PTR(&pin_GPIO17) }, + + + { MP_ROM_QSTR(MP_QSTR_IO18), MP_ROM_PTR(&pin_GPIO18) }, + { MP_ROM_QSTR(MP_QSTR_IO19), MP_ROM_PTR(&pin_GPIO19) }, + { MP_ROM_QSTR(MP_QSTR_IO20), MP_ROM_PTR(&pin_GPIO20) }, + { MP_ROM_QSTR(MP_QSTR_IO21), MP_ROM_PTR(&pin_GPIO21) }, + { MP_ROM_QSTR(MP_QSTR_IO26), MP_ROM_PTR(&pin_GPIO26) }, + { MP_ROM_QSTR(MP_QSTR_IO33), MP_ROM_PTR(&pin_GPIO33) }, + { MP_ROM_QSTR(MP_QSTR_IO34), MP_ROM_PTR(&pin_GPIO34) }, + { MP_ROM_QSTR(MP_QSTR_IO35), MP_ROM_PTR(&pin_GPIO35) }, + { MP_ROM_QSTR(MP_QSTR_IO36), MP_ROM_PTR(&pin_GPIO36) }, + { MP_ROM_QSTR(MP_QSTR_IO37), MP_ROM_PTR(&pin_GPIO37) }, + { MP_ROM_QSTR(MP_QSTR_IO38), MP_ROM_PTR(&pin_GPIO38) }, + { MP_ROM_QSTR(MP_QSTR_IO39), MP_ROM_PTR(&pin_GPIO39) }, + { MP_ROM_QSTR(MP_QSTR_IO40), MP_ROM_PTR(&pin_GPIO40) }, + { MP_ROM_QSTR(MP_QSTR_IO41), MP_ROM_PTR(&pin_GPIO41) }, + { MP_ROM_QSTR(MP_QSTR_IO42), MP_ROM_PTR(&pin_GPIO42) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO43) }, + { MP_ROM_QSTR(MP_QSTR_IO43), MP_ROM_PTR(&pin_GPIO43) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO44) }, + { MP_ROM_QSTR(MP_QSTR_IO44), MP_ROM_PTR(&pin_GPIO44) }, + { MP_ROM_QSTR(MP_QSTR_IO45), MP_ROM_PTR(&pin_GPIO45) }, + { MP_ROM_QSTR(MP_QSTR_IO46), MP_ROM_PTR(&pin_GPIO46) }, + + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO18) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/esp32s2/boards/muselab_nanoesp32_s2/sdkconfig b/ports/esp32s2/boards/muselab_nanoesp32_s2/sdkconfig new file mode 100644 index 0000000000..e69de29bb2 From 8be5d616e48828fa0220004aa3c0c1cf9dbc4761 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Sarrailh?= Date: Wed, 16 Sep 2020 13:44:09 +0200 Subject: [PATCH 55/91] Fix invalid indentation on build.yml --- .github/workflows/build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 49e52dbb2e..ef8c3c8a0e 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -244,7 +244,7 @@ jobs: - "metro_nrf52840_express" - "mini_sam_m4" - "monster_m4sk" - - "muselabnanoesp32_s2" + - "muselabnanoesp32_s2" - "ndgarage_ndbit6" - "ndgarage_ndbit6_v2" - "nfc_copy_cat" From 61687c81d82572ee5c014a9f167b2d73db73e2f4 Mon Sep 17 00:00:00 2001 From: Kamil Tomaszewski Date: Wed, 16 Sep 2020 13:55:57 +0200 Subject: [PATCH 56/91] camera: Pass width and height to take_picture() --- ports/cxd56/common-hal/camera/Camera.c | 37 ++--------- ports/cxd56/common-hal/camera/Camera.h | 2 - shared-bindings/camera/Camera.c | 92 +++++--------------------- shared-bindings/camera/Camera.h | 9 +-- 4 files changed, 22 insertions(+), 118 deletions(-) diff --git a/ports/cxd56/common-hal/camera/Camera.c b/ports/cxd56/common-hal/camera/Camera.c index a4e197bf33..35e2ab8822 100644 --- a/ports/cxd56/common-hal/camera/Camera.c +++ b/ports/cxd56/common-hal/camera/Camera.c @@ -118,9 +118,7 @@ static void camera_start_preview() { camera_start_streaming(V4L2_BUF_TYPE_VIDEO_CAPTURE); } -extern uint32_t _ebss; -extern uint32_t _stext; -void common_hal_camera_construct(camera_obj_t *self, uint16_t width, uint16_t height) { +void common_hal_camera_construct(camera_obj_t *self) { if (camera_dev.fd < 0) { if (video_initialize(camera_dev.devpath) < 0) { mp_raise_ValueError(translate("Could not initialize Camera")); @@ -131,17 +129,8 @@ void common_hal_camera_construct(camera_obj_t *self, uint16_t width, uint16_t he } } - if (!camera_check_width_and_height(width, height)) { - mp_raise_ValueError(translate("Size not supported")); - } - - self->width = width; - self->height = height; - camera_start_preview(); - camera_set_format(V4L2_BUF_TYPE_STILL_CAPTURE, V4L2_PIX_FMT_JPEG, width, height); - camera_start_streaming(V4L2_BUF_TYPE_STILL_CAPTURE); sleep(1); @@ -162,18 +151,18 @@ bool common_hal_camera_deinited(camera_obj_t *self) { return camera_dev.fd < 0; } -size_t common_hal_camera_take_picture(camera_obj_t *self, uint8_t *buffer, size_t len, camera_imageformat_t format) { - if (!camera_check_width_and_height(self->width, self->height)) { +size_t common_hal_camera_take_picture(camera_obj_t *self, uint8_t *buffer, size_t len, uint16_t width, uint16_t height, camera_imageformat_t format) { + if (!camera_check_width_and_height(width, height)) { mp_raise_ValueError(translate("Size not supported")); } - if (!camera_check_buffer_length(self->width, self->height, format, len)) { + if (!camera_check_buffer_length(width, height, format, len)) { mp_raise_ValueError(translate("Buffer is too small")); } if (!camera_check_format(format)) { mp_raise_ValueError(translate("Format not supported")); } - camera_set_format(V4L2_BUF_TYPE_STILL_CAPTURE, V4L2_PIX_FMT_JPEG, self->width, self->height); + camera_set_format(V4L2_BUF_TYPE_STILL_CAPTURE, V4L2_PIX_FMT_JPEG, width, height); v4l2_buffer_t buf; @@ -192,19 +181,3 @@ size_t common_hal_camera_take_picture(camera_obj_t *self, uint8_t *buffer, size_ return (size_t)buf.bytesused; } - -uint16_t common_hal_camera_get_width(camera_obj_t *self) { - return self->width; -} - -void common_hal_camera_set_width(camera_obj_t *self, uint16_t width) { - self->width = width; -} - -uint16_t common_hal_camera_get_height(camera_obj_t *self) { - return self->height; -} - -void common_hal_camera_set_height(camera_obj_t *self, uint16_t height) { - self->height = height; -} diff --git a/ports/cxd56/common-hal/camera/Camera.h b/ports/cxd56/common-hal/camera/Camera.h index 11fc102085..7056237d16 100644 --- a/ports/cxd56/common-hal/camera/Camera.h +++ b/ports/cxd56/common-hal/camera/Camera.h @@ -31,8 +31,6 @@ typedef struct { mp_obj_base_t base; - uint16_t width; - uint16_t height; } camera_obj_t; #endif // MICROPY_INCLUDED_CXD56_COMMON_HAL_CAMERA_CAMERA_H diff --git a/shared-bindings/camera/Camera.c b/shared-bindings/camera/Camera.c index 5fe54e429d..fd88ccab00 100644 --- a/shared-bindings/camera/Camera.c +++ b/shared-bindings/camera/Camera.c @@ -48,34 +48,26 @@ //| vfs = storage.VfsFat(sd) //| storage.mount(vfs, '/sd') //| -//| cam = camera.Camera(1920, 1080) +//| cam = camera.Camera() //| //| buffer = bytearray(512 * 1024) //| file = open("/sd/image.jpg","wb") -//| size = cam.take_picture(buffer, camera.ImageFormat.JPG) +//| size = cam.take_picture(buffer, width=1920, height=1080, format=camera.ImageFormat.JPG) //| file.write(buffer, size) //| file.close()""" //| -//| def __init__(self, width: int, height: int) -> None: -//| """Initialize camera. -//| -//| :param int width: Width in pixels -//| :param int height: Height in pixels""" +//| def __init__(self) -> None: +//| """Initialize camera.""" //| ... //| STATIC mp_obj_t camera_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { camera_obj_t *self = m_new_obj(camera_obj_t); self->base.type = &camera_type; - enum { ARG_width, ARG_height }; - static const mp_arg_t allowed_args[] = { - { MP_QSTR_width, MP_ARG_REQUIRED | MP_ARG_INT }, - { MP_QSTR_height, MP_ARG_REQUIRED | MP_ARG_INT }, - }; - mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; - mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + // No arguments + mp_arg_check_num(n_args, kw_args, 0, 0, false); - common_hal_camera_construct(self, args[ARG_width].u_int, args[ARG_height].u_int); + common_hal_camera_construct(self); return MP_OBJ_FROM_PTR(self); } @@ -97,17 +89,20 @@ STATIC void check_for_deinit(camera_obj_t *self) { } //| def take_picture(self, buf: WriteableBuffer, format: ImageFormat) -> int: -//| """Take picture and save to ``buf`` in the given ``format`` +//| """Take picture and save to ``buf`` in the given ``format``. The size of the picture +//| taken is ``width`` by ``height`` in pixels. //| //| :return: the number of bytes written into buf //| :rtype: int""" //| ... //| STATIC mp_obj_t camera_obj_take_picture(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { - enum { ARG_buffer, ARG_format }; + enum { ARG_buffer, ARG_width, ARG_height, ARG_format }; static const mp_arg_t allowed_args[] = { { MP_QSTR_buffer, MP_ARG_REQUIRED | MP_ARG_OBJ }, - { MP_QSTR_format, MP_ARG_REQUIRED | MP_ARG_OBJ }, + { MP_QSTR_width, MP_ARG_KW_ONLY | MP_ARG_REQUIRED | MP_ARG_INT }, + { MP_QSTR_height, MP_ARG_KW_ONLY | MP_ARG_REQUIRED | MP_ARG_INT }, + { MP_QSTR_format, MP_ARG_KW_ONLY | MP_ARG_REQUIRED | MP_ARG_OBJ }, }; camera_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); check_for_deinit(self); @@ -119,70 +114,13 @@ STATIC mp_obj_t camera_obj_take_picture(size_t n_args, const mp_obj_t *pos_args, camera_imageformat_t format = camera_imageformat_obj_to_type(args[ARG_format].u_obj); - return MP_OBJ_NEW_SMALL_INT(common_hal_camera_take_picture(self, (uint8_t *)bufinfo.buf, bufinfo.len, format)); + return MP_OBJ_NEW_SMALL_INT(common_hal_camera_take_picture(self, (uint8_t *)bufinfo.buf, bufinfo.len, args[ARG_width].u_int, args[ARG_height].u_int, format)); } -MP_DEFINE_CONST_FUN_OBJ_KW(camera_take_picture_obj, 3, camera_obj_take_picture); - -//| width: int -//| """Image width in pixels.""" -//| -STATIC mp_obj_t camera_obj_get_width(mp_obj_t self_in) { - camera_obj_t *self = MP_OBJ_TO_PTR(self_in); - check_for_deinit(self); - return MP_OBJ_NEW_SMALL_INT(common_hal_camera_get_width(self)); -} -MP_DEFINE_CONST_FUN_OBJ_1(camera_get_width_obj, camera_obj_get_width); - -STATIC mp_obj_t camera_obj_set_width(mp_obj_t self_in, mp_obj_t value) { - camera_obj_t *self = MP_OBJ_TO_PTR(self_in); - check_for_deinit(self); - - common_hal_camera_set_width(self, mp_obj_get_int(value)); - - return mp_const_none; -} -MP_DEFINE_CONST_FUN_OBJ_2(camera_set_width_obj, camera_obj_set_width); - -const mp_obj_property_t camera_width_obj = { - .base.type = &mp_type_property, - .proxy = {(mp_obj_t)&camera_get_width_obj, - (mp_obj_t)&camera_set_width_obj, - (mp_obj_t)&mp_const_none_obj}, -}; - -//| height: int -//| """Image height in pixels.""" -//| -STATIC mp_obj_t camera_obj_get_height(mp_obj_t self_in) { - camera_obj_t *self = MP_OBJ_TO_PTR(self_in); - check_for_deinit(self); - return MP_OBJ_NEW_SMALL_INT(common_hal_camera_get_height(self)); -} -MP_DEFINE_CONST_FUN_OBJ_1(camera_get_height_obj, camera_obj_get_height); - -STATIC mp_obj_t camera_obj_set_height(mp_obj_t self_in, mp_obj_t value) { - camera_obj_t *self = MP_OBJ_TO_PTR(self_in); - check_for_deinit(self); - - common_hal_camera_set_height(self, mp_obj_get_int(value)); - - return mp_const_none; -} -MP_DEFINE_CONST_FUN_OBJ_2(camera_set_height_obj, camera_obj_set_height); - -const mp_obj_property_t camera_height_obj = { - .base.type = &mp_type_property, - .proxy = {(mp_obj_t)&camera_get_height_obj, - (mp_obj_t)&camera_set_height_obj, - (mp_obj_t)&mp_const_none_obj}, -}; +MP_DEFINE_CONST_FUN_OBJ_KW(camera_take_picture_obj, 2, camera_obj_take_picture); STATIC const mp_rom_map_elem_t camera_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&camera_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_take_picture), MP_ROM_PTR(&camera_take_picture_obj) }, - - { MP_ROM_QSTR(MP_QSTR_width), MP_ROM_PTR(&camera_width_obj) }, - { MP_ROM_QSTR(MP_QSTR_height), MP_ROM_PTR(&camera_height_obj) }, }; STATIC MP_DEFINE_CONST_DICT(camera_locals_dict, camera_locals_dict_table); diff --git a/shared-bindings/camera/Camera.h b/shared-bindings/camera/Camera.h index 7ef13cd07e..8102672e49 100644 --- a/shared-bindings/camera/Camera.h +++ b/shared-bindings/camera/Camera.h @@ -32,14 +32,9 @@ extern const mp_obj_type_t camera_type; -void common_hal_camera_construct(camera_obj_t *self, uint16_t width, uint16_t height); +void common_hal_camera_construct(camera_obj_t *self); void common_hal_camera_deinit(camera_obj_t *self); bool common_hal_camera_deinited(camera_obj_t *self); -size_t common_hal_camera_take_picture(camera_obj_t *self, uint8_t *buffer, size_t len, camera_imageformat_t format); - -uint16_t common_hal_camera_get_width(camera_obj_t *self); -void common_hal_camera_set_width(camera_obj_t *self, uint16_t width); -uint16_t common_hal_camera_get_height(camera_obj_t *self); -void common_hal_camera_set_height(camera_obj_t *self, uint16_t height); +size_t common_hal_camera_take_picture(camera_obj_t *self, uint8_t *buffer, size_t len, uint16_t width, uint16_t height, camera_imageformat_t format); #endif // MICROPY_INCLUDED_SHARED_BINDINGS_CAMERA_CAMERA_H From d538918cfd0d24afffc800db4d07e7e269a13f45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Sarrailh?= Date: Wed, 16 Sep 2020 13:59:59 +0200 Subject: [PATCH 57/91] Fix name in build.yml --- .github/workflows/build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index ef8c3c8a0e..6d8dc5ba19 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -244,7 +244,7 @@ jobs: - "metro_nrf52840_express" - "mini_sam_m4" - "monster_m4sk" - - "muselabnanoesp32_s2" + - "muselab_nanoesp32_s2" - "ndgarage_ndbit6" - "ndgarage_ndbit6_v2" - "nfc_copy_cat" From 4225f8348ffc8cfd0bd0cd881d5896b12a16b324 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Sarrailh?= Date: Wed, 16 Sep 2020 14:59:35 +0200 Subject: [PATCH 58/91] Change build-arm to build-xtensa in build.yml --- .github/workflows/build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 6d8dc5ba19..8e7648e3e6 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -244,7 +244,6 @@ jobs: - "metro_nrf52840_express" - "mini_sam_m4" - "monster_m4sk" - - "muselab_nanoesp32_s2" - "ndgarage_ndbit6" - "ndgarage_ndbit6_v2" - "nfc_copy_cat" @@ -417,6 +416,7 @@ jobs: - "espressif_saola_1_wroom" - "espressif_saola_1_wrover" - "microdev_micro_s2" + - "muselab_nanoesp32_s2" - "unexpectedmaker_feathers2" steps: From a8e98cda83119b8716533ce24af6e3d691f7d2ca Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Wed, 16 Sep 2020 07:58:55 -0500 Subject: [PATCH 59/91] makeqstrdata: comment my understanding of @ciscorn's code --- py/makeqstrdata.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/py/makeqstrdata.py b/py/makeqstrdata.py index 0060217917..39d4a6840f 100644 --- a/py/makeqstrdata.py +++ b/py/makeqstrdata.py @@ -156,6 +156,14 @@ def compute_huffman_coding(translations, compression_filename): sum_len = 0 while True: + # Until the dictionary is filled to capacity, use a heuristic to find + # the best "word" (2- to 9-gram) to add to it. + # + # The TextSplitter allows us to avoid considering parts of the text + # that are already covered by a previously chosen word, for example + # if "the" is in words then not only will "the" not be considered + # again, neither will "there" or "wither", since they have "the" + # as substrings. extractor = TextSplitter(words) counter = collections.Counter() for t in texts: @@ -164,6 +172,8 @@ def compute_huffman_coding(translations, compression_filename): for substr in iter_substrings(word, minlen=2, maxlen=9): counter[substr] += 1 + # Score the candidates we found. This is an empirical formula only, + # chosen for its effectiveness. scores = sorted( ( (s, (len(s) - 1) ** log(max(occ - 2, 1)), occ) @@ -173,6 +183,8 @@ def compute_huffman_coding(translations, compression_filename): reverse=True, ) + # Do we have a "word" that occurred 5 times and got a score of at least + # 5? Horray. Pick the one with the highest score. word = None for (s, score, occ) in scores: if occ < 5: @@ -182,6 +194,8 @@ def compute_huffman_coding(translations, compression_filename): word = s break + # If we can successfully add it to the dictionary, do so. Otherwise, + # we've filled the dictionary to capacity and are done. if not word: break if sum_len + len(word) - 2 > max_words_len: From 478a4b6405df620f3c8933faae9b81a76dd5a87b Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 16 Sep 2020 10:51:08 -0400 Subject: [PATCH 60/91] Clarify location of port root --- ports/esp32s2/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/esp32s2/README.md b/ports/esp32s2/README.md index 5b664df08c..8a6dfbd2d8 100644 --- a/ports/esp32s2/README.md +++ b/ports/esp32s2/README.md @@ -30,7 +30,7 @@ Connect these pins using a [USB adapter](https://www.adafruit.com/product/4090) ## Building and flashing ## -Before building or flashing the ESP32-S2, you must [install the esp-idf](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/index.html). This must be re-done ever time the esp-idf is updated, but not every time you build. From the port root, run: +Before building or flashing the ESP32-S2, you must [install the esp-idf](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/index.html). This must be re-done ever time the esp-idf is updated, but not every time you build. Run `cd ports/esp32s2` from `circuitpython/` to move to the esp32s2 port root, and run: ``` ./esp-idf/install.sh From 18285f96e8a2600afcfcc1a63fa5df6388a8da19 Mon Sep 17 00:00:00 2001 From: askpatricw <4002194+askpatrickw@users.noreply.github.com> Date: Wed, 16 Sep 2020 10:13:07 -0700 Subject: [PATCH 61/91] RTC is pickd up automatically --- ports/esp32s2/mpconfigport.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/ports/esp32s2/mpconfigport.mk b/ports/esp32s2/mpconfigport.mk index 8f057784ac..bbaabb1c3d 100644 --- a/ports/esp32s2/mpconfigport.mk +++ b/ports/esp32s2/mpconfigport.mk @@ -21,7 +21,6 @@ CIRCUITPY_COUNTIO = 0 CIRCUITPY_FREQUENCYIO = 0 CIRCUITPY_I2CPERIPHERAL = 0 CIRCUITPY_ROTARYIO = 0 -CIRCUITPY_RTC = 1 CIRCUITPY_NVM = 0 # We don't have enough endpoints to include MIDI. CIRCUITPY_USB_MIDI = 0 From 00ee94d24b407768612a5f2a40c4099a7899aa0b Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 16 Sep 2020 14:05:15 -0400 Subject: [PATCH 62/91] Add SPI memset, optional flags --- ports/stm/Makefile | 3 ++- ports/stm/common-hal/busio/SPI.c | 13 ++++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/ports/stm/Makefile b/ports/stm/Makefile index dccc749ed8..9e1d10b998 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -102,7 +102,8 @@ CFLAGS += $(INC) -Werror -Wall -std=gnu11 -fshort-enums $(BASE_CFLAGS) $(C_DEFS) # Undo some warnings. # STM32 HAL uses undefined preprocessor variables, shadowed variables, casts that change alignment reqs -CFLAGS += -Wno-undef -Wno-shadow -Wno-cast-align +# You can add your own temporary suppression by setting ADD_CFLAGS in the make command +CFLAGS += -Wno-undef -Wno-shadow -Wno-cast-align $(ADD_CFLAGS) CFLAGS += -mthumb -mabi=aapcs-linux diff --git a/ports/stm/common-hal/busio/SPI.c b/ports/stm/common-hal/busio/SPI.c index 0354d64ad3..913385e962 100644 --- a/ports/stm/common-hal/busio/SPI.c +++ b/ports/stm/common-hal/busio/SPI.c @@ -25,6 +25,7 @@ * THE SOFTWARE. */ #include +#include #include "shared-bindings/busio/SPI.h" #include "py/mperrno.h" @@ -340,7 +341,7 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, if (self->mosi == NULL) { mp_raise_ValueError(translate("No MOSI Pin")); } - HAL_StatusTypeDef result = HAL_SPI_Transmit (&self->handle, (uint8_t *)data, (uint16_t)len, HAL_MAX_DELAY); + HAL_StatusTypeDef result = HAL_SPI_Transmit(&self->handle, (uint8_t *)data, (uint16_t)len, HAL_MAX_DELAY); return result == HAL_OK; } @@ -349,7 +350,13 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self, if (self->miso == NULL) { mp_raise_ValueError(translate("No MISO Pin")); } - HAL_StatusTypeDef result = HAL_SPI_Receive (&self->handle, data, (uint16_t)len, HAL_MAX_DELAY); + HAL_StatusTypeDef result = HAL_OK; + if (self->mosi == NULL) { + result = HAL_SPI_Receive(&self->handle, data, (uint16_t)len, HAL_MAX_DELAY); + } else { + memset(data, write_value, len); + result = HAL_SPI_TransmitReceive(&self->handle, data, data, (uint16_t)len, HAL_MAX_DELAY); + } return result == HAL_OK; } @@ -358,7 +365,7 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, if (self->miso == NULL || self->mosi == NULL) { mp_raise_ValueError(translate("Missing MISO or MOSI Pin")); } - HAL_StatusTypeDef result = HAL_SPI_TransmitReceive (&self->handle, + HAL_StatusTypeDef result = HAL_SPI_TransmitReceive(&self->handle, (uint8_t *) data_out, data_in, (uint16_t)len,HAL_MAX_DELAY); return result == HAL_OK; } From 847d609ddcab77ac0bba7f2bf50f847ec70ab1ed Mon Sep 17 00:00:00 2001 From: Brian Dean Date: Wed, 16 Sep 2020 16:27:24 -0400 Subject: [PATCH 63/91] rename board bdmicro_vina_m0 to bdmicro_vina_d21 and update boardfiles appropriately --- .github/workflows/build.yml | 2 +- .../board.c | 0 .../mpconfigboard.h | 37 +++++++++---------- .../mpconfigboard.mk | 13 ++++--- .../pins.c | 24 ++++++------ 5 files changed, 38 insertions(+), 38 deletions(-) rename ports/atmel-samd/boards/{bdmicro_vina_m0 => bdmicro_vina_d21}/board.c (100%) rename ports/atmel-samd/boards/{bdmicro_vina_m0 => bdmicro_vina_d21}/mpconfigboard.h (85%) rename ports/atmel-samd/boards/{bdmicro_vina_m0 => bdmicro_vina_d21}/mpconfigboard.mk (51%) rename ports/atmel-samd/boards/{bdmicro_vina_m0 => bdmicro_vina_d21}/pins.c (88%) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 8e7648e3e6..04b09f778e 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -177,7 +177,7 @@ jobs: - "arduino_nano_33_iot" - "arduino_zero" - "bast_pro_mini_m0" - - "bdmicro_vina_m0" + - "bdmicro_vina_d21" - "bless_dev_board_multi_sensor" - "blm_badge" - "capablerobot_usbhub" diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/board.c b/ports/atmel-samd/boards/bdmicro_vina_d21/board.c similarity index 100% rename from ports/atmel-samd/boards/bdmicro_vina_m0/board.c rename to ports/atmel-samd/boards/bdmicro_vina_d21/board.c diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h b/ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.h similarity index 85% rename from ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h rename to ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.h index 458b1e12a6..f2332bbe54 100644 --- a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h +++ b/ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.h @@ -1,34 +1,31 @@ -#define MICROPY_HW_BOARD_NAME "BDMICRO Vina M0" +#define MICROPY_HW_BOARD_NAME "BDMICRO VINA-D21" #define MICROPY_HW_MCU_NAME "samd21g18" -#define MICROPY_HW_LED_STATUS (&pin_PA28) -#define MICROPY_HW_LED_TX &pin_PA27 -#define MICROPY_HW_LED_RX &pin_PA31 - -// Clock rates are off: Salae reads 12MHz which is the limit even though we set it to the safer 8MHz. -#define SPI_FLASH_BAUDRATE (8000000) - -#define SPI_FLASH_MOSI_PIN &pin_PB22 -#define SPI_FLASH_MISO_PIN &pin_PB03 -#define SPI_FLASH_SCK_PIN &pin_PB23 -#define SPI_FLASH_CS_PIN &pin_PA13 - // These are pins not to reset. #define MICROPY_PORT_A (0) #define MICROPY_PORT_B (0) #define MICROPY_PORT_C (0) -#define BOARD_HAS_CRYSTAL 0 +#define SPI_FLASH_CS_PIN &pin_PA13 +#define SPI_FLASH_MISO_PIN &pin_PB03 +#define SPI_FLASH_MOSI_PIN &pin_PB22 +#define SPI_FLASH_SCK_PIN &pin_PB23 -#define DEFAULT_I2C_BUS_SCL (&pin_PA23) -#define DEFAULT_I2C_BUS_SDA (&pin_PA22) +// Clock rates are off: Salae reads 12MHz which is the limit even though we set it to the safer 8MHz. +#define SPI_FLASH_BAUDRATE (8000000) -#define DEFAULT_SPI_BUS_SCK (&pin_PB11) -#define DEFAULT_SPI_BUS_MOSI (&pin_PB10) -#define DEFAULT_SPI_BUS_MISO (&pin_PA12) +#define BOARD_HAS_CRYSTAL 1 -#define DEFAULT_UART_BUS_RX (&pin_PA11) #define DEFAULT_UART_BUS_TX (&pin_PA10) +#define DEFAULT_UART_BUS_RX (&pin_PA11) +#define DEFAULT_SPI_BUS_MISO (&pin_PA12) +#define DEFAULT_I2C_BUS_SDA (&pin_PA22) +#define DEFAULT_I2C_BUS_SCL (&pin_PA23) +#define MICROPY_HW_LED_TX (&pin_PA27) +#define MICROPY_HW_LED_STATUS (&pin_PA28) +#define MICROPY_HW_LED_RX (&pin_PA31) +#define DEFAULT_SPI_BUS_MOSI (&pin_PB10) +#define DEFAULT_SPI_BUS_SCK (&pin_PB11) // USB is always used internally so skip the pin objects for it. #define IGNORE_PIN_PA24 1 diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk b/ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.mk similarity index 51% rename from ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk rename to ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.mk index b7ad47ff2c..a9885d064b 100644 --- a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk +++ b/ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.mk @@ -1,19 +1,22 @@ USB_VID = 0x31e2 -USB_PID = 0x2002 -USB_PRODUCT = "Vina M0" +USB_PID = 0x2001 +USB_PRODUCT = "VINA-D21" USB_MANUFACTURER = "BDMICRO LLC" CHIP_VARIANT = SAMD21G18A CHIP_FAMILY = samd21 SPI_FLASH_FILESYSTEM = 1 -EXTERNAL_FLASH_DEVICE_COUNT = 1 -EXTERNAL_FLASH_DEVICES = "MX25L51245G" +EXTERNAL_FLASH_DEVICE_COUNT = 2 +EXTERNAL_FLASH_DEVICES = "MX25L51245G","GD25S512MD" LONGINT_IMPL = MPZ CIRCUITPY_BITBANGIO = 0 +CIRCUITPY_COUNTIO = 0 CIRCUITPY_I2CPERIPHERAL = 0 CIRCUITPY_VECTORIO = 0 -CFLAGS_INLINE_LIMIT = 50 +CFLAGS_INLINE_LIMIT = 60 SUPEROPT_GC = 0 + +CFLAGS_BOARD = --param max-inline-insns-auto=15 diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/pins.c b/ports/atmel-samd/boards/bdmicro_vina_d21/pins.c similarity index 88% rename from ports/atmel-samd/boards/bdmicro_vina_m0/pins.c rename to ports/atmel-samd/boards/bdmicro_vina_d21/pins.c index 0ebceb28dd..2e2f9ff4f1 100644 --- a/ports/atmel-samd/boards/bdmicro_vina_m0/pins.c +++ b/ports/atmel-samd/boards/bdmicro_vina_d21/pins.c @@ -1,8 +1,6 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_global_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR_RTC_INT), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_RTC_CLK), MP_ROM_PTR(&pin_PA01) }, { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) }, { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PB08) }, { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PB09) }, @@ -13,8 +11,11 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA11) }, { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA10) }, { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) }, { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_RTC_TS), MP_ROM_PTR(&pin_PA14) }, { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA09) }, { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA15) }, @@ -22,18 +23,17 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) }, { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, - { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, - { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) }, - { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) }, - { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) }, - { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) }, - { MP_ROM_QSTR(MP_QSTR_PGM_LED), MP_ROM_PTR(&pin_PA28) }, - { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB11) }, - { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_LED_STATUS), MP_ROM_PTR(&pin_PA28) }, + { MP_ROM_QSTR(MP_QSTR_LED_TX), MP_ROM_PTR(&pin_PA27) }, { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_LED_RX), MP_ROM_PTR(&pin_PA31) }, { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); + From 81ee8745319a4e2802db55eb2dae5adc8fe47b35 Mon Sep 17 00:00:00 2001 From: Brian Dean Date: Wed, 16 Sep 2020 16:40:04 -0400 Subject: [PATCH 64/91] pins.c: fix trailing whitespace --- ports/atmel-samd/boards/bdmicro_vina_d21/pins.c | 1 - 1 file changed, 1 deletion(-) diff --git a/ports/atmel-samd/boards/bdmicro_vina_d21/pins.c b/ports/atmel-samd/boards/bdmicro_vina_d21/pins.c index 2e2f9ff4f1..323f71dec2 100644 --- a/ports/atmel-samd/boards/bdmicro_vina_d21/pins.c +++ b/ports/atmel-samd/boards/bdmicro_vina_d21/pins.c @@ -36,4 +36,3 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); - From daa1dd278d3ee389be63723f4eabee1ab82c9a92 Mon Sep 17 00:00:00 2001 From: "Ryan T. Hamilton" Date: Wed, 16 Sep 2020 16:25:17 -0700 Subject: [PATCH 65/91] connect now accepts bssid --- ports/esp32s2/common-hal/wifi/Radio.c | 10 +++++++++- shared-bindings/wifi/Radio.c | 18 +++++++++++++++--- shared-bindings/wifi/Radio.h | 2 +- 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/ports/esp32s2/common-hal/wifi/Radio.c b/ports/esp32s2/common-hal/wifi/Radio.c index 3c6ab57570..9ba384ca18 100644 --- a/ports/esp32s2/common-hal/wifi/Radio.c +++ b/ports/esp32s2/common-hal/wifi/Radio.c @@ -104,7 +104,7 @@ void common_hal_wifi_radio_stop_scanning_networks(wifi_radio_obj_t *self) { self->current_scan = NULL; } -wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t* ssid, size_t ssid_len, uint8_t* password, size_t password_len, uint8_t channel, mp_float_t timeout) { +wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t* ssid, size_t ssid_len, uint8_t* password, size_t password_len, uint8_t channel, mp_float_t timeout, uint8_t* bssid, size_t bssid_len) { // check enabled wifi_config_t* config = &self->sta_config; memcpy(&config->sta.ssid, ssid, ssid_len); @@ -112,6 +112,14 @@ wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t memcpy(&config->sta.password, password, password_len); config->sta.password[password_len] = 0; config->sta.channel = channel; + // From esp_wifi_types.h: + // Generally, station_config.bssid_set needs to be 0; and it needs + // to be 1 only when users need to check the MAC address of the AP + if (bssid_len > 0){ + memcpy(&config->sta.bssid, bssid, bssid_len); + config->sta.bssid[bssid_len] = 0; + config->sta.bssid_set = 1; + } esp_wifi_set_config(ESP_IF_WIFI_STA, config); self->starting_retries = 5; self->retries_left = 5; diff --git a/shared-bindings/wifi/Radio.c b/shared-bindings/wifi/Radio.c index 329dcb1b5f..928f21da90 100644 --- a/shared-bindings/wifi/Radio.c +++ b/shared-bindings/wifi/Radio.c @@ -108,11 +108,12 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(wifi_radio_stop_scanning_networks_obj, wifi_rad //| ... //| STATIC mp_obj_t wifi_radio_connect(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { - enum { ARG_ssid, ARG_password, ARG_channel, ARG_timeout }; + enum { ARG_ssid, ARG_password, ARG_channel, ARG_bssid, ARG_timeout }; static const mp_arg_t allowed_args[] = { { MP_QSTR_ssid, MP_ARG_REQUIRED | MP_ARG_OBJ }, { MP_QSTR_password, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_channel, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_bssid, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, }; @@ -125,7 +126,6 @@ STATIC mp_obj_t wifi_radio_connect(size_t n_args, const mp_obj_t *pos_args, mp_m timeout = mp_obj_get_float(args[ARG_timeout].u_obj); } - mp_buffer_info_t ssid; mp_get_buffer_raise(args[ARG_ssid].u_obj, &ssid, MP_BUFFER_READ); @@ -138,7 +138,19 @@ STATIC mp_obj_t wifi_radio_connect(size_t n_args, const mp_obj_t *pos_args, mp_m } } - wifi_radio_error_t error = common_hal_wifi_radio_connect(self, ssid.buf, ssid.len, password.buf, password.len, args[ARG_channel].u_int, timeout); + #define MAC_ADDRESS_LENGTH 6 + + mp_buffer_info_t bssid; + bssid.len = 0; + // Should probably make sure bssid is just bytes and not something else too + if (args[ARG_bssid].u_obj != MP_OBJ_NULL) { + mp_get_buffer_raise(args[ARG_bssid].u_obj, &bssid, MP_BUFFER_READ); + if (bssid.len != MAC_ADDRESS_LENGTH) { + mp_raise_ValueError(translate("Invalid BSSID")); + } + } + + wifi_radio_error_t error = common_hal_wifi_radio_connect(self, ssid.buf, ssid.len, password.buf, password.len, args[ARG_channel].u_int, timeout, bssid.buf, bssid.len); if (error == WIFI_RADIO_ERROR_AUTH) { mp_raise_ConnectionError(translate("Authentication failure")); } else if (error == WIFI_RADIO_ERROR_NO_AP_FOUND) { diff --git a/shared-bindings/wifi/Radio.h b/shared-bindings/wifi/Radio.h index 812814f9ea..b5341d51c9 100644 --- a/shared-bindings/wifi/Radio.h +++ b/shared-bindings/wifi/Radio.h @@ -51,7 +51,7 @@ extern mp_obj_t common_hal_wifi_radio_get_mac_address(wifi_radio_obj_t *self); extern mp_obj_t common_hal_wifi_radio_start_scanning_networks(wifi_radio_obj_t *self); extern void common_hal_wifi_radio_stop_scanning_networks(wifi_radio_obj_t *self); -extern wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t* ssid, size_t ssid_len, uint8_t* password, size_t password_len, uint8_t channel, mp_float_t timeout); +extern wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t* ssid, size_t ssid_len, uint8_t* password, size_t password_len, uint8_t channel, mp_float_t timeout, uint8_t* bssid, size_t bssid_len); extern mp_obj_t common_hal_wifi_radio_get_ipv4_address(wifi_radio_obj_t *self); From 6a323a583f48b85e2762db8fc0468afa90501cb3 Mon Sep 17 00:00:00 2001 From: "Ryan T. Hamilton" Date: Wed, 16 Sep 2020 17:08:11 -0700 Subject: [PATCH 66/91] Add new error msg to translation --- locale/circuitpython.pot | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 038cdacfc6..078df08b23 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -948,6 +948,10 @@ msgstr "" msgid "Invalid BMP file" msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "" From 1805e92038a16d5bada953bdf52b7ae99524f2fa Mon Sep 17 00:00:00 2001 From: "Ryan T. Hamilton" Date: Thu, 17 Sep 2020 15:04:27 -0700 Subject: [PATCH 67/91] Add else case for non-bssid usage --- ports/esp32s2/common-hal/wifi/Radio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ports/esp32s2/common-hal/wifi/Radio.c b/ports/esp32s2/common-hal/wifi/Radio.c index 9ba384ca18..a0b8b6adc5 100644 --- a/ports/esp32s2/common-hal/wifi/Radio.c +++ b/ports/esp32s2/common-hal/wifi/Radio.c @@ -119,6 +119,8 @@ wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t memcpy(&config->sta.bssid, bssid, bssid_len); config->sta.bssid[bssid_len] = 0; config->sta.bssid_set = 1; + } else { + config->sta.bssid_set = 0; } esp_wifi_set_config(ESP_IF_WIFI_STA, config); self->starting_retries = 5; From 1b29ceaf1a7b9fd2e8e0ce832b24528a6591bef8 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Tue, 8 Sep 2020 09:10:31 -0500 Subject: [PATCH 68/91] sam e54: disable microcontroller.cpu.voltage This hangs, and the usual workarounds didn't work. --- ports/atmel-samd/common-hal/microcontroller/Processor.c | 6 ++++++ ports/atmel-samd/mpconfigport.h | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/ports/atmel-samd/common-hal/microcontroller/Processor.c b/ports/atmel-samd/common-hal/microcontroller/Processor.c index 199f19354b..ba8daf3fb0 100644 --- a/ports/atmel-samd/common-hal/microcontroller/Processor.c +++ b/ports/atmel-samd/common-hal/microcontroller/Processor.c @@ -61,6 +61,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include + #include "py/mphal.h" #include "common-hal/microcontroller/Processor.h" @@ -276,6 +278,9 @@ float common_hal_mcu_processor_get_temperature(void) { } float common_hal_mcu_processor_get_voltage(void) { +#if MICROCONTROLLER_VOLTAGE_DISABLE + return NAN; +#else struct adc_sync_descriptor adc; static Adc* adc_insts[] = ADC_INSTS; @@ -320,6 +325,7 @@ float common_hal_mcu_processor_get_voltage(void) { adc_sync_deinit(&adc); // Multiply by 4 to compensate for SCALEDIOVCC division by 4. return (reading / 4095.0f) * 4.0f; +#endif } uint32_t common_hal_mcu_processor_get_frequency(void) { diff --git a/ports/atmel-samd/mpconfigport.h b/ports/atmel-samd/mpconfigport.h index 2a2428d679..f185142e47 100644 --- a/ports/atmel-samd/mpconfigport.h +++ b/ports/atmel-samd/mpconfigport.h @@ -75,6 +75,9 @@ #define MICROPY_PY_SYS_PLATFORM "MicroChip SAMD51" #elif defined(SAME54) #define MICROPY_PY_SYS_PLATFORM "MicroChip SAME54" +#ifndef MICROCONTROLLER_VOLTAGE_DISABLE +#define MICROCONTROLLER_VOLTAGE_DISABLE (1) +#endif #endif #define SPI_FLASH_MAX_BAUDRATE 24000000 #define MICROPY_PY_BUILTINS_NOTIMPLEMENTED (1) @@ -246,4 +249,8 @@ CIRCUITPY_COMMON_ROOT_POINTERS \ mp_obj_t playing_audio[AUDIO_DMA_CHANNEL_COUNT]; +#ifndef MICROCONTROLLER_VOLTAGE_DISABLE +#define MICROCONTROLLER_VOLTAGE_DISABLE (0) +#endif + #endif // __INCLUDED_MPCONFIGPORT_H From c73182803d9ff5a0d270fa20a7649f61198ba5a0 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Tue, 25 Aug 2020 13:14:08 -0500 Subject: [PATCH 69/91] sdioio: fix code for the case where there is no SDHC1 .. it doesn't really make a difference (the old code created an empty else{} statement) but this is more correct. --- ports/atmel-samd/common-hal/sdioio/SDCard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atmel-samd/common-hal/sdioio/SDCard.c b/ports/atmel-samd/common-hal/sdioio/SDCard.c index 8cd077ecd7..1f555b6476 100644 --- a/ports/atmel-samd/common-hal/sdioio/SDCard.c +++ b/ports/atmel-samd/common-hal/sdioio/SDCard.c @@ -144,8 +144,8 @@ CLK PA21 PCC_D? (D32) BROWN hri_mclk_set_AHBMASK_SDHC0_bit(MCLK); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, CONF_GCLK_SDHC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, CONF_GCLK_SDHC0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - } else { #ifdef SDHC1_GCLK_ID + } else { hri_mclk_set_AHBMASK_SDHC1_bit(MCLK); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID, CONF_GCLK_SDHC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID_SLOW, CONF_GCLK_SDHC1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); From 45eec5b5a566f049edaff11e8457bc0befe79c60 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Thu, 3 Sep 2020 10:00:26 -0500 Subject: [PATCH 70/91] samd: SPI: improve conditional code I recently misdiagnosed a "maybe-uninitialized" diagnostic as a bug in asf4. However, the problem was in our SPI code. A special case for samr21 MCUs was being applied to same54p20a and possibly other D5x/E5x MCUs, since the check was simply for pin PC19 existing at all. Change the check to use the macro PIN_PC19F_SERCOM4_PAD0 which is only defined if special function F of pin PC19 is SERCOM4 PAD0. Reorganize the code a little bit so that brace-matching in editors is not confused by the conditionalized code, including an unrelated change for APA102_SCK's condition. Revert the change to the Makefile that incorrectly attempted to silence the diagnostic. --- ports/atmel-samd/Makefile | 2 - ports/atmel-samd/common-hal/busio/SPI.c | 106 ++++++++++++------------ 2 files changed, 53 insertions(+), 55 deletions(-) diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile index f115f9f666..aba630dbb3 100644 --- a/ports/atmel-samd/Makefile +++ b/ports/atmel-samd/Makefile @@ -286,8 +286,6 @@ SRC_ASF += \ $(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sdhc/hpl_sdhc.o: CFLAGS += -Wno-cast-align -Wno-implicit-fallthrough endif -$(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sercom/hpl_sercom.o: CFLAGS += -Wno-maybe-uninitialized - SRC_ASF := $(addprefix asf4/$(CHIP_FAMILY)/, $(SRC_ASF)) SRC_C += \ diff --git a/ports/atmel-samd/common-hal/busio/SPI.c b/ports/atmel-samd/common-hal/busio/SPI.c index 921713d690..189fd93b54 100644 --- a/ports/atmel-samd/common-hal/busio/SPI.c +++ b/ports/atmel-samd/common-hal/busio/SPI.c @@ -98,8 +98,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, uint8_t miso_pad = 0; uint8_t dopo = 255; - // Special case for SAMR boards. - #ifdef PIN_PC19 + // Special case for SAMR21 boards. (feather_radiofruit_zigbee) + #if defined(PIN_PC19F_SERCOM4_PAD0) if (miso == &pin_PC19) { if (mosi == &pin_PB30 && clock == &pin_PC18) { sercom = SERCOM4; @@ -113,67 +113,67 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, dopo = samd_peripherals_get_spi_dopo(clock_pad, mosi_pad); } // Error, leave SERCOM unset to throw an exception later. - } else { + } else #endif - for (int i = 0; i < NUM_SERCOMS_PER_PIN; i++) { - sercom_index = clock->sercom[i].index; // 2 for SERCOM2, etc. - if (sercom_index >= SERCOM_INST_NUM) { - continue; - } - Sercom* potential_sercom = sercom_insts[sercom_index]; - if ( - #if defined(MICROPY_HW_APA102_SCK) && defined(MICROPY_HW_APA102_MOSI) && !CIRCUITPY_BITBANG_APA102 - (potential_sercom->SPI.CTRLA.bit.ENABLE != 0 && - potential_sercom != status_apa102.spi_desc.dev.prvt && - !apa102_sck_in_use)) { - #else - potential_sercom->SPI.CTRLA.bit.ENABLE != 0) { - #endif - continue; - } - clock_pinmux = PINMUX(clock->number, (i == 0) ? MUX_C : MUX_D); - clock_pad = clock->sercom[i].pad; - if (!samd_peripherals_valid_spi_clock_pad(clock_pad)) { - continue; - } - for (int j = 0; j < NUM_SERCOMS_PER_PIN; j++) { - if (!mosi_none) { - if (sercom_index == mosi->sercom[j].index) { - mosi_pinmux = PINMUX(mosi->number, (j == 0) ? MUX_C : MUX_D); - mosi_pad = mosi->sercom[j].pad; - dopo = samd_peripherals_get_spi_dopo(clock_pad, mosi_pad); - if (dopo > 0x3) { - continue; // pad combination not possible - } - if (miso_none) { - sercom = potential_sercom; - break; - } - } else { - continue; - } + { + for (int i = 0; i < NUM_SERCOMS_PER_PIN; i++) { + sercom_index = clock->sercom[i].index; // 2 for SERCOM2, etc. + if (sercom_index >= SERCOM_INST_NUM) { + continue; } - if (!miso_none) { - for (int k = 0; k < NUM_SERCOMS_PER_PIN; k++) { - if (sercom_index == miso->sercom[k].index) { - miso_pinmux = PINMUX(miso->number, (k == 0) ? MUX_C : MUX_D); - miso_pad = miso->sercom[k].pad; - sercom = potential_sercom; - break; + Sercom* potential_sercom = sercom_insts[sercom_index]; + if ( + #if defined(MICROPY_HW_APA102_SCK) && defined(MICROPY_HW_APA102_MOSI) && !CIRCUITPY_BITBANG_APA102 + (potential_sercom->SPI.CTRLA.bit.ENABLE != 0 && + potential_sercom != status_apa102.spi_desc.dev.prvt && + !apa102_sck_in_use) + #else + potential_sercom->SPI.CTRLA.bit.ENABLE != 0 + #endif + ) { + continue; + } + clock_pinmux = PINMUX(clock->number, (i == 0) ? MUX_C : MUX_D); + clock_pad = clock->sercom[i].pad; + if (!samd_peripherals_valid_spi_clock_pad(clock_pad)) { + continue; + } + for (int j = 0; j < NUM_SERCOMS_PER_PIN; j++) { + if (!mosi_none) { + if (sercom_index == mosi->sercom[j].index) { + mosi_pinmux = PINMUX(mosi->number, (j == 0) ? MUX_C : MUX_D); + mosi_pad = mosi->sercom[j].pad; + dopo = samd_peripherals_get_spi_dopo(clock_pad, mosi_pad); + if (dopo > 0x3) { + continue; // pad combination not possible + } + if (miso_none) { + sercom = potential_sercom; + break; + } + } else { + continue; } } + if (!miso_none) { + for (int k = 0; k < NUM_SERCOMS_PER_PIN; k++) { + if (sercom_index == miso->sercom[k].index) { + miso_pinmux = PINMUX(miso->number, (k == 0) ? MUX_C : MUX_D); + miso_pad = miso->sercom[k].pad; + sercom = potential_sercom; + break; + } + } + } + if (sercom != NULL) { + break; + } } if (sercom != NULL) { break; } - } - if (sercom != NULL) { - break; - } } - #ifdef PIN_PC19 } - #endif if (sercom == NULL) { mp_raise_ValueError(translate("Invalid pins")); } From 28043c94b5ea5f3cce11fa57afa9f3f0141b8dce Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Thu, 3 Sep 2020 13:36:15 -0500 Subject: [PATCH 71/91] supervisor: Improve serial connection detection These changes remove the caveat from supervisor.runtime.serial_connected. It appears that _tud_cdc_connected() only tracks explicit changes to the "DTR" bit, which leads to disconnects not being registered. Instead: * when line state is changed explicitly, track the dtr value in _serial_connected * when the USB bus is suspended, set _serial_connected to False Testing performed (using sam e54 xplained): Run a program to show the state of `serial_connected` on the LED: ``` import digitalio import supervisor import board led = digitalio.DigitalInOut(board.LED) while True: led.switch_to_output(not supervisor.runtime.serial_connected) ``` Try all the following: * open, close serial terminal program - LED status tracks whether terminal is open * turn on/off data lines using the switchable charge-only cable - LED turns off when switch is in "charger" position - LED turns back on when switch is in Data position and terminal is opened (but doesn't turn back on just because switch position is changed) --- shared-bindings/supervisor/Runtime.c | 8 +------- supervisor/serial.h | 1 + supervisor/shared/serial.c | 4 +++- supervisor/shared/usb/usb.c | 4 ++++ 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/shared-bindings/supervisor/Runtime.c b/shared-bindings/supervisor/Runtime.c index 84d8370dd5..bfca6e7b1d 100755 --- a/shared-bindings/supervisor/Runtime.c +++ b/shared-bindings/supervisor/Runtime.c @@ -46,13 +46,7 @@ //| //| serial_connected: bool -//| """Returns the USB serial communication status (read-only). -//| -//| .. note:: -//| -//| SAMD: Will return ``True`` if the USB serial connection -//| has been established at any point. Will not reset if -//| USB is disconnected but power remains (e.g. battery connected)""" +//| """Returns the USB serial communication status (read-only).""" //| STATIC mp_obj_t supervisor_get_serial_connected(mp_obj_t self){ diff --git a/supervisor/serial.h b/supervisor/serial.h index 066886303e..9c2d44737a 100644 --- a/supervisor/serial.h +++ b/supervisor/serial.h @@ -47,4 +47,5 @@ char serial_read(void); bool serial_bytes_available(void); bool serial_connected(void); +extern volatile bool _serial_connected; #endif // MICROPY_INCLUDED_SUPERVISOR_SERIAL_H diff --git a/supervisor/shared/serial.c b/supervisor/shared/serial.c index 303f89e752..91e90671d2 100644 --- a/supervisor/shared/serial.c +++ b/supervisor/shared/serial.c @@ -47,6 +47,8 @@ busio_uart_obj_t debug_uart; byte buf_array[64]; #endif +volatile bool _serial_connected; + void serial_early_init(void) { #if defined(DEBUG_UART_TX) && defined(DEBUG_UART_RX) debug_uart.base.type = &busio_uart_type; @@ -69,7 +71,7 @@ bool serial_connected(void) { #if defined(DEBUG_UART_TX) && defined(DEBUG_UART_RX) return true; #else - return tud_cdc_connected(); + return _serial_connected; #endif } diff --git a/supervisor/shared/usb/usb.c b/supervisor/shared/usb/usb.c index e8541669ad..89fbf56f37 100644 --- a/supervisor/shared/usb/usb.c +++ b/supervisor/shared/usb/usb.c @@ -29,6 +29,7 @@ #include "shared-module/usb_midi/__init__.h" #include "supervisor/background_callback.h" #include "supervisor/port.h" +#include "supervisor/serial.h" #include "supervisor/usb.h" #include "lib/utils/interrupt_char.h" #include "lib/mp-readline/readline.h" @@ -115,6 +116,7 @@ void tud_umount_cb(void) { // remote_wakeup_en : if host allows us to perform remote wakeup // USB Specs: Within 7ms, device must draw an average current less than 2.5 mA from bus void tud_suspend_cb(bool remote_wakeup_en) { + _serial_connected = false; } // Invoked when usb bus is resumed @@ -126,6 +128,8 @@ void tud_resume_cb(void) { void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) { (void) itf; // interface ID, not used + _serial_connected = dtr; + // DTR = false is counted as disconnected if ( !dtr ) { From be3e478fceed9da87e569a0fa40c5797139d99bc Mon Sep 17 00:00:00 2001 From: Chris Dailey Date: Thu, 17 Sep 2020 20:46:59 -0400 Subject: [PATCH 72/91] Add SDA & SDL, RX & TX to pins.c Despite the [silk on the dock board](https://wiki.makerdiary.com/nrf52840-m2-devkit/resources/nrf52840_m2_devkit_hw_diagram_v1_0.pdf), the SDA/SCL pins weren't defined. Though, they were already defined in `mpconfigboard.h`. Same for RX/TX. It looks like it declared `TXD` and `RXD`, so I didn't want to remove those, but I think it makes sense to have the "standard" pin names, but I moved ithem to illustrate they were all referencing the same pins. I mimicked the whitespace I saw in the metro_nrf52840_express port. --- .../boards/makerdiary_nrf52840_m2_devkit/pins.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c index cb3bda35ab..d56fd35594 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c @@ -59,7 +59,13 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_P1_9), MP_ROM_PTR(&pin_P1_09) }, { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_RXD), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_TXD), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_P0_19) }, { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_P0_20) }, { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_P0_21) }, @@ -72,8 +78,12 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_P1_03) }, { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_P1_04) }, { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_P1_07) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_P1_05) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_P1_05) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_P1_06) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_P1_06) }, { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_P0_02) }, { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_P0_03) }, @@ -81,6 +91,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_P0_27) }, { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_P0_26) }, { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P0_11) }, { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_P0_12) }, @@ -91,9 +102,6 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_LCD_BL), MP_ROM_PTR(&pin_P0_20) }, { MP_ROM_QSTR(MP_QSTR_LCD_RST), MP_ROM_PTR(&pin_P1_09) }, - { MP_ROM_QSTR(MP_QSTR_TXD), MP_ROM_PTR(&pin_P0_16) }, - { MP_ROM_QSTR(MP_QSTR_RXD), MP_ROM_PTR(&pin_P0_15) }, - { MP_ROM_QSTR(MP_QSTR_LED_R), MP_ROM_PTR(&pin_P0_30) }, { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_P0_29) }, { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_P0_31) }, From db078922e4a0e77515fd2bddfb9ba0a4cfbde552 Mon Sep 17 00:00:00 2001 From: nitz Date: Thu, 17 Sep 2020 21:32:19 -0400 Subject: [PATCH 73/91] Removed TXD/RXD, fixed whitespace. --- ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c index d56fd35594..027cd9d8d7 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c @@ -60,12 +60,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_P0_15) }, { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_P0_15) }, - { MP_ROM_QSTR(MP_QSTR_RXD), MP_ROM_PTR(&pin_P0_15) }, - + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_P0_16) }, { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_P0_16) }, - { MP_ROM_QSTR(MP_QSTR_TXD), MP_ROM_PTR(&pin_P0_16) }, - + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_P0_19) }, { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_P0_20) }, { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_P0_21) }, @@ -78,10 +76,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_P1_03) }, { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_P1_04) }, { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_P1_07) }, - + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_P1_05) }, { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_P1_05) }, - + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_P1_06) }, { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_P1_06) }, @@ -91,7 +89,6 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_P0_27) }, { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_P0_26) }, { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P0_11) }, { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_P0_12) }, From c58bd4c04782efad04ffc08f77fda3efce83badb Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Fri, 18 Sep 2020 12:38:15 -0400 Subject: [PATCH 74/91] Add never_reset reservation to RGBMatrix init --- ports/stm/common-hal/rgbmatrix/RGBMatrix.c | 1 + 1 file changed, 1 insertion(+) diff --git a/ports/stm/common-hal/rgbmatrix/RGBMatrix.c b/ports/stm/common-hal/rgbmatrix/RGBMatrix.c index 3b42631adc..2826cf53e9 100644 --- a/ports/stm/common-hal/rgbmatrix/RGBMatrix.c +++ b/ports/stm/common-hal/rgbmatrix/RGBMatrix.c @@ -36,6 +36,7 @@ extern void _PM_IRQ_HANDLER(void); void *common_hal_rgbmatrix_timer_allocate() { TIM_TypeDef * timer = stm_peripherals_find_timer(); stm_peripherals_timer_reserve(timer); + stm_peripherals_timer_never_reset(timer); return timer; } From 3a59d30e1ae1a4d5159dadb5f34534b186cdf9fd Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Fri, 18 Sep 2020 12:48:15 -0400 Subject: [PATCH 75/91] Remove timer debug messages --- ports/stm/peripherals/timers.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/ports/stm/peripherals/timers.c b/ports/stm/peripherals/timers.c index baa81d2b5f..7bc5ea495a 100644 --- a/ports/stm/peripherals/timers.c +++ b/ports/stm/peripherals/timers.c @@ -195,9 +195,7 @@ TIM_TypeDef * stm_peripherals_find_timer(void) { // If no results are found, no unclaimed pins with this timer are in this package, // and it is safe to pick if (timer_in_package == false && mcu_tim_banks[i] != NULL) { - // DEBUG: print the timer return mcu_tim_banks[i]; - mp_printf(&mp_plat_print, "Timer: %d\n",i); } } //TODO: secondary search for timers outside the pins in the board profile @@ -205,8 +203,6 @@ TIM_TypeDef * stm_peripherals_find_timer(void) { // Work backwards - higher index timers have fewer pin allocations for (size_t i = (MP_ARRAY_SIZE(mcu_tim_banks) - 1); i >= 0; i--) { if ((!stm_timer_reserved[i]) && (mcu_tim_banks[i] != NULL)) { - // DEBUG: print the timer - mp_printf(&mp_plat_print, "Timer: %d\n",i); return mcu_tim_banks[i]; } } From 5249a228a011c737401a32ff76316bef161cc086 Mon Sep 17 00:00:00 2001 From: nitz Date: Fri, 18 Sep 2020 14:27:00 -0400 Subject: [PATCH 76/91] More pin names cleanup. --- ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c | 3 ++- ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c | 5 ++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c index 027cd9d8d7..2340885b50 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c @@ -103,7 +103,8 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_P0_29) }, { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_P0_31) }, - { MP_ROM_QSTR(MP_QSTR_USR_BTN), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_USR), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_P0_19) }, { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, diff --git a/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c b/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c index 006b247688..d46f369422 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c @@ -9,9 +9,8 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, // User must connect manually. { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, // User must connect manually. -// Not defining the NFC names until CircuitPython supports NFC. -// { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, -// { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, From 8d6a28a9ffcc3b8993b0ac261c81b8a619094cb2 Mon Sep 17 00:00:00 2001 From: nitz Date: Fri, 18 Sep 2020 17:01:44 -0400 Subject: [PATCH 77/91] Update user button names. --- ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c | 3 +-- ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c | 2 +- ports/nrf/boards/pitaya_go/pins.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c index 2340885b50..7dc6db18fa 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c @@ -103,8 +103,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_P0_29) }, { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_P0_31) }, - { MP_ROM_QSTR(MP_QSTR_USR), MP_ROM_PTR(&pin_P0_19) }, - { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_P0_19) }, { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, diff --git a/ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c b/ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c index 5284c24842..34f487b1de 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c @@ -55,7 +55,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_P0_22) }, { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_P0_24) }, - { MP_ROM_QSTR(MP_QSTR_USR_BTN), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_P1_00) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/nrf/boards/pitaya_go/pins.c b/ports/nrf/boards/pitaya_go/pins.c index 92411581bc..ba333fc2be 100644 --- a/ports/nrf/boards/pitaya_go/pins.c +++ b/ports/nrf/boards/pitaya_go/pins.c @@ -58,7 +58,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_P0_11) }, { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_P0_12) }, - { MP_ROM_QSTR(MP_QSTR_USR_BTN), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON_USER), MP_ROM_PTR(&pin_P1_00) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); From bfbbbd6c5ce58ba1bcb57323566209902e1000b0 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Sat, 19 Sep 2020 10:16:13 -0500 Subject: [PATCH 78/91] makeqstrdata: Work with older Python This construct (which I added without sufficient testing, apparently) is only supported in Python 3.7 and newer. Make it optional so that this script works on other Python versions. This means that if you have a system with non-UTF-8 encoding you will need to use Python 3.7. In particular, this affects a problem building circuitpython in github's ubuntu-18.04 virtual environment when Python 3.7 is not explicitly installed. cookie-cuttered libraries call for Python 3.6: ``` - name: Set up Python 3.6 uses: actions/setup-python@v1 with: python-version: 3.6 ``` Since CircuitPython's own build calls for 3.8, this problem was not detected. This problem was also encountered by discord user mdroberts1243. The failure I encountered was here: https://github.com/jepler/Jepler_CircuitPython_udecimal/runs/1138045020?check_suite_focus=true .. while my step of "clone and build circuitpython unix port" is unusual, I think the same problem would have affected "build assets" if that step had been reached. --- py/makeqstrdata.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/py/makeqstrdata.py b/py/makeqstrdata.py index 39d4a6840f..96e3956b42 100644 --- a/py/makeqstrdata.py +++ b/py/makeqstrdata.py @@ -17,8 +17,9 @@ import collections import gettext import os.path -sys.stdout.reconfigure(encoding='utf-8') -sys.stderr.reconfigure(errors='backslashreplace') +if hasattr(sys.stdout, 'reconfigure'): + sys.stdout.reconfigure(encoding='utf-8') + sys.stderr.reconfigure(errors='backslashreplace') py = os.path.dirname(sys.argv[0]) top = os.path.dirname(py) From 852bdd2137b98d77634eaa09773821a24684a780 Mon Sep 17 00:00:00 2001 From: Hugo Dahl Date: Wed, 16 Sep 2020 02:20:39 +0000 Subject: [PATCH 79/91] Translated using Weblate (French) Currently translated at 94.7% (753 of 795 strings) Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/fr/ --- locale/fr.po | 47 ++++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/locale/fr.po b/locale/fr.po index 1180648961..8f1965a6b8 100644 --- a/locale/fr.po +++ b/locale/fr.po @@ -8,14 +8,14 @@ msgstr "" "Project-Id-Version: 0.1\n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2020-09-13 14:21-0500\n" -"PO-Revision-Date: 2020-07-27 21:27+0000\n" -"Last-Translator: Nathan \n" +"PO-Revision-Date: 2020-09-16 13:47+0000\n" +"Last-Translator: Hugo Dahl \n" "Language: fr\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" "Plural-Forms: nplurals=2; plural=n > 1;\n" -"X-Generator: Weblate 4.2-dev\n" +"X-Generator: Weblate 4.3-dev\n" #: main.c msgid "" @@ -78,7 +78,7 @@ msgstr "index %q hors gamme" #: py/obj.c msgid "%q indices must be integers, not %q" -msgstr "" +msgstr "indices %q doivent être des chiffres entier, et non %q" #: shared-bindings/vectorio/Polygon.c msgid "%q list must be a list" @@ -118,39 +118,39 @@ msgstr "'%q' argument requis" #: py/runtime.c msgid "'%q' object cannot assign attribute '%q'" -msgstr "" +msgstr "object '%q' ne peut assigner l'attribut '%q'" #: py/proto.c msgid "'%q' object does not support '%q'" -msgstr "" +msgstr "object '%q' ne supporte pas '%q'" #: py/obj.c msgid "'%q' object does not support item assignment" -msgstr "" +msgstr "objet '%q' ne supporte pas l'assignement d'objets" #: py/obj.c msgid "'%q' object does not support item deletion" -msgstr "" +msgstr "object '%q' ne supported pas la suppression d'objet" #: py/runtime.c msgid "'%q' object has no attribute '%q'" -msgstr "" +msgstr "object '%q' n'as pas d'attribut '%q'" #: py/runtime.c msgid "'%q' object is not an iterator" -msgstr "" +msgstr "object '%q' n'est pas un itérateur" #: py/objtype.c py/runtime.c msgid "'%q' object is not callable" -msgstr "" +msgstr "object '%q' ne peut pas être appelé" #: py/runtime.c msgid "'%q' object is not iterable" -msgstr "" +msgstr "objet '%q' n'est pas iterable" #: py/obj.c msgid "'%q' object is not subscriptable" -msgstr "" +msgstr "objet '%q' n'est pas souscriptable" #: py/emitinlinethumb.c py/emitinlinextensa.c #, c-format @@ -220,7 +220,7 @@ msgstr "'await' en dehors d'une fonction" #: py/compile.c msgid "'await', 'async for' or 'async with' outside async function" -msgstr "" +msgstr "'await', 'async for' ou 'async with' au dehors d'une fonction async" #: py/compile.c msgid "'break' outside loop" @@ -378,7 +378,7 @@ msgstr "" #: shared-bindings/wifi/Radio.c msgid "Authentication failure" -msgstr "" +msgstr "Échec d'authentification" #: main.c msgid "Auto-reload is off.\n" @@ -460,7 +460,7 @@ msgstr "La longueur de la mémoire tampon doit être un multiple de 512" #: ports/stm/common-hal/sdioio/SDCard.c msgid "Buffer must be a multiple of 512 bytes" -msgstr "" +msgstr "La mémoire tampon doit être un multiple de 512" #: shared-bindings/bitbangio/I2C.c shared-bindings/busio/I2C.c msgid "Buffer must be at least length 1" @@ -504,6 +504,7 @@ msgstr "Impossible de définir CCCD sur une caractéristique locale" #: shared-bindings/_bleio/Adapter.c msgid "Cannot create a new Adapter; use _bleio.adapter;" msgstr "" +"Un nouveau Adapter ne peut être créé ; Adapter; utilisez _bleio.adapter;" #: shared-bindings/displayio/Bitmap.c #: shared-bindings/memorymonitor/AllocationSize.c @@ -598,7 +599,7 @@ msgstr "" #: supervisor/shared/safe_mode.c msgid "CircuitPython was unable to allocate the heap.\n" -msgstr "" +msgstr "CircuitPython n'as pu faire l'allocation de la pile\n" #: shared-module/bitbangio/SPI.c msgid "Clock pin init failed." @@ -784,7 +785,7 @@ msgstr "Une 'Characteristic' est attendue" #: shared-bindings/_bleio/Adapter.c msgid "Expected a DigitalInOut" -msgstr "" +msgstr "Un 'DigitalInOut' est attendu" #: shared-bindings/_bleio/Characteristic.c msgid "Expected a Service" @@ -792,7 +793,7 @@ msgstr "Attendu un service" #: shared-bindings/_bleio/Adapter.c msgid "Expected a UART" -msgstr "" +msgstr "Un 'UART' est attendu" #: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c #: shared-bindings/_bleio/Service.c @@ -3391,7 +3392,7 @@ msgstr "spécification %c de conversion inconnue" #: py/objstr.c msgid "unknown format code '%c' for object of type '%q'" -msgstr "" +msgstr "code de formatage inconnu '%c' pour objet de type '%q'" #: py/compile.c msgid "unknown type" @@ -3431,7 +3432,7 @@ msgstr "caractère de format '%c' (0x%x) non supporté à l'index %d" #: py/runtime.c msgid "unsupported type for %q: '%q'" -msgstr "" +msgstr "type non supporté pour %q: '%q'" #: py/runtime.c msgid "unsupported type for operator" @@ -3439,7 +3440,7 @@ msgstr "type non supporté pour l'opérateur" #: py/runtime.c msgid "unsupported types for %q: '%q', '%q'" -msgstr "" +msgstr "types non supportés pour %q: '%q', '%q'" #: py/objint.c #, c-format @@ -3452,7 +3453,7 @@ msgstr "'value_count' doit être > 0" #: extmod/ulab/code/linalg/linalg.c msgid "vectors must have same lengths" -msgstr "" +msgstr "les vecteurs doivent avoir la même longueur" #: shared-bindings/watchdog/WatchDogTimer.c msgid "watchdog timeout must be greater than 0" From aeec662fef2ec47384be9f3f87ed0cd8a3a56e87 Mon Sep 17 00:00:00 2001 From: Maciej Stankiewicz Date: Wed, 16 Sep 2020 10:41:07 +0000 Subject: [PATCH 80/91] Translated using Weblate (Polish) Currently translated at 71.3% (567 of 795 strings) Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/pl/ --- locale/pl.po | 199 +++++++++++++++++++++++++++------------------------ 1 file changed, 105 insertions(+), 94 deletions(-) diff --git a/locale/pl.po b/locale/pl.po index 8b4fceee4a..d616378fbf 100644 --- a/locale/pl.po +++ b/locale/pl.po @@ -7,13 +7,16 @@ msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2020-09-13 14:21-0500\n" -"PO-Revision-Date: 2019-03-19 18:37-0700\n" -"Last-Translator: Radomir Dopieralski \n" +"PO-Revision-Date: 2020-09-16 13:47+0000\n" +"Last-Translator: Maciej Stankiewicz \n" "Language-Team: pl\n" "Language: pl\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=UTF-8\n" "Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=3; plural=n==1 ? 0 : n%10>=2 && n%10<=4 && (n%100<10 " +"|| n%100>=20) ? 1 : 2;\n" +"X-Generator: Weblate 4.3-dev\n" #: main.c msgid "" @@ -78,7 +81,7 @@ msgstr "" #: shared-bindings/memorymonitor/AllocationAlarm.c msgid "%q must be >= 0" -msgstr "" +msgstr "%q musi być >= 0" #: shared-bindings/_bleio/CharacteristicBuffer.c #: shared-bindings/_bleio/PacketBuffer.c shared-bindings/displayio/Group.c @@ -90,7 +93,7 @@ msgstr "%q musi być >= 1" #: shared-module/vectorio/Polygon.c msgid "%q must be a tuple of length 2" -msgstr "" +msgstr "%q musi być krotką o długości 2" #: ports/atmel-samd/common-hal/sdioio/SDCard.c msgid "%q pin invalid" @@ -114,7 +117,7 @@ msgstr "" #: py/proto.c msgid "'%q' object does not support '%q'" -msgstr "" +msgstr "Obiekt '%q' nie wspiera '%q'" #: py/obj.c msgid "'%q' object does not support item assignment" @@ -126,19 +129,19 @@ msgstr "" #: py/runtime.c msgid "'%q' object has no attribute '%q'" -msgstr "" +msgstr "Obiekt '%q' nie ma atrybutu '%q'" #: py/runtime.c msgid "'%q' object is not an iterator" -msgstr "" +msgstr "Obiekt '%q' nie jest iteratorem" #: py/objtype.c py/runtime.c msgid "'%q' object is not callable" -msgstr "" +msgstr "Obiekt '%q' nie jest wywoływalny" #: py/runtime.c msgid "'%q' object is not iterable" -msgstr "" +msgstr "Obiekt '%q' nie jest iterowalny" #: py/obj.c msgid "'%q' object is not subscriptable" @@ -212,7 +215,7 @@ msgstr "'await' poza funkcją" #: py/compile.c msgid "'await', 'async for' or 'async with' outside async function" -msgstr "" +msgstr "'await', 'async for' lub 'async with' poza funkcją asynchroniczną" #: py/compile.c msgid "'break' outside loop" @@ -359,7 +362,7 @@ msgstr "" #: shared-module/memorymonitor/AllocationAlarm.c #, c-format msgid "Attempt to allocate %d blocks" -msgstr "" +msgstr "Próba przydzielenia %d bloków" #: supervisor/shared/safe_mode.c msgid "Attempted heap allocation when MicroPython VM not running." @@ -367,7 +370,7 @@ msgstr "" #: shared-bindings/wifi/Radio.c msgid "Authentication failure" -msgstr "" +msgstr "Błąd autoryzacji" #: main.c msgid "Auto-reload is off.\n" @@ -396,7 +399,7 @@ msgstr "Głębia musi być wielokrotnością 8." #: ports/mimxrt10xx/common-hal/busio/UART.c msgid "Both RX and TX required for flow control" -msgstr "" +msgstr "Do kontroli przepływu wymagane są zarówno RX, jak i TX" #: ports/atmel-samd/common-hal/rotaryio/IncrementalEncoder.c msgid "Both pins must support hardware interrupts" @@ -406,7 +409,7 @@ msgstr "Obie nóżki muszą wspierać przerwania sprzętowe" #: shared-bindings/framebufferio/FramebufferDisplay.c #: shared-bindings/rgbmatrix/RGBMatrix.c msgid "Brightness must be 0-1.0" -msgstr "" +msgstr "Jasność musi wynosić 0-1,0" #: shared-bindings/supervisor/__init__.c msgid "Brightness must be between 0 and 255" @@ -435,21 +438,21 @@ msgstr "" #: shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" -msgstr "" +msgstr "Bufor jest za mały" #: ports/nrf/common-hal/audiopwmio/PWMAudioOut.c #, c-format msgid "Buffer length %d too big. It must be less than %d" -msgstr "" +msgstr "Długość %d bufora jest za duża. Musi być ona mniejsza niż %d" #: ports/atmel-samd/common-hal/sdioio/SDCard.c #: ports/cxd56/common-hal/sdioio/SDCard.c shared-module/sdcardio/SDCard.c msgid "Buffer length must be a multiple of 512" -msgstr "" +msgstr "Długość bufora musi być wielokrotnością 512" #: ports/stm/common-hal/sdioio/SDCard.c msgid "Buffer must be a multiple of 512 bytes" -msgstr "" +msgstr "Bufor musi być wielokrotnością 512 bajtów" #: shared-bindings/bitbangio/I2C.c shared-bindings/busio/I2C.c msgid "Buffer must be at least length 1" @@ -457,12 +460,12 @@ msgstr "Bufor musi mieć długość 1 lub więcej" #: ports/nrf/common-hal/_bleio/PacketBuffer.c msgid "Buffer too large and unable to allocate" -msgstr "" +msgstr "Bufor jest zbyt duży i nie można go przydzielić" #: shared-bindings/_bleio/PacketBuffer.c #, c-format msgid "Buffer too short by %d bytes" -msgstr "" +msgstr "Bufor za krótki o %d bajtów" #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c @@ -480,7 +483,7 @@ msgstr "Bytes musi być między 0 a 255." #: shared-bindings/aesio/aes.c msgid "CBC blocks must be multiples of 16 bytes" -msgstr "" +msgstr "Bloki CBC muszą być wielokrotnościami 16 bajtów" #: py/objtype.c msgid "Call super().__init__() before accessing native object." @@ -520,7 +523,7 @@ msgstr "Nie można mieć obu kanałów na tej samej nóżce" #: shared-module/bitbangio/SPI.c msgid "Cannot read without MISO pin." -msgstr "Nie można czytać bez nóżki MISO" +msgstr "Nie można czytać bez nóżki MISO." #: shared-bindings/audiobusio/PDMIn.c msgid "Cannot record to a file" @@ -538,11 +541,11 @@ msgstr "Nie można zrestartować -- nie ma bootloadera." #: shared-bindings/digitalio/DigitalInOut.c msgid "Cannot set value when direction is input." -msgstr "Nie można ustawić wartości w trybie wejścia" +msgstr "Nie można ustawić wartości w trybie wejścia." #: ports/mimxrt10xx/common-hal/busio/UART.c msgid "Cannot specify RTS or CTS in RS485 mode" -msgstr "" +msgstr "Nie można określić RTS ani CTS w trybie RS485" #: py/objslice.c msgid "Cannot subclass slice" @@ -558,7 +561,7 @@ msgstr "Wielkość skalara jest niejednoznaczna" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Cannot vary frequency on a timer that is already in use" -msgstr "" +msgstr "Nie można zmieniać częstotliwości timera, który jest już używany" #: shared-module/bitbangio/SPI.c msgid "Cannot write without MOSI pin." @@ -577,14 +580,16 @@ msgid "" "CircuitPython is in safe mode because you pressed the reset button during " "boot. Press again to exit safe mode.\n" msgstr "" +"CircuitPython jest w trybie awaryjnym, ponieważ podczas rozruchu naciśnięto " +"przycisk resetowania. Naciśnij ponownie, aby wyjść z trybu awaryjnego.\n" #: supervisor/shared/safe_mode.c msgid "CircuitPython was unable to allocate the heap.\n" -msgstr "" +msgstr "CircuitPython nie mógł przydzielić sterty.\n" #: shared-module/bitbangio/SPI.c msgid "Clock pin init failed." -msgstr "Nie powiodło się ustawienie nóżki zegara" +msgstr "Inicjalizacja nóżki zegara nie powiodła się." #: shared-module/bitbangio/I2C.c msgid "Clock stretch too long" @@ -608,10 +613,12 @@ msgid "" "Connection has been disconnected and can no longer be used. Create a new " "connection." msgstr "" +"Połączenie zostało rozłączone i nie można go już używać. Utwórz nowe " +"połączenie." #: py/persistentcode.c msgid "Corrupt .mpy file" -msgstr "" +msgstr "Uszkodzony plik .mpy" #: py/emitglue.c msgid "Corrupt raw code" @@ -619,11 +626,11 @@ msgstr "" #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" -msgstr "" +msgstr "Nie można zainicjować GNSS" #: ports/cxd56/common-hal/sdioio/SDCard.c msgid "Could not initialize SDCard" -msgstr "" +msgstr "Nie można zainicjować SDCard" #: ports/atmel-samd/common-hal/busio/UART.c ports/cxd56/common-hal/busio/UART.c msgid "Could not initialize UART" @@ -647,15 +654,15 @@ msgstr "" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not restart PWM" -msgstr "" +msgstr "Nie można zrestartować PWM" #: shared-bindings/_bleio/Adapter.c msgid "Could not set address" -msgstr "" +msgstr "Nie można ustawić adresu" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not start PWM" -msgstr "" +msgstr "Nie można wystartować PWM" #: ports/stm/common-hal/busio/UART.c msgid "Could not start interrupt, RX busy" @@ -714,7 +721,7 @@ msgstr "Pojemność celu mniejsza od destination_length." #: ports/nrf/common-hal/audiobusio/I2SOut.c msgid "Device in use" -msgstr "" +msgstr "Urządzenie w użyciu" #: ports/cxd56/common-hal/digitalio/DigitalInOut.c msgid "DigitalInOut not supported on given pin" @@ -798,12 +805,12 @@ msgstr "" #: shared-bindings/ps2io/Ps2.c msgid "Failed sending command." -msgstr "" +msgstr "Nie udało się wysłać polecenia." #: ports/nrf/sd_mutex.c -#, fuzzy, c-format +#, c-format msgid "Failed to acquire mutex, err 0x%04x" -msgstr "Nie udało się uzyskać blokady, błąd 0x$04x" +msgstr "Nie udało się uzyskać blokady, błąd 0x%04x" #: ports/mimxrt10xx/common-hal/busio/UART.c ports/nrf/common-hal/busio/UART.c msgid "Failed to allocate RX buffer" @@ -820,11 +827,11 @@ msgstr "Nie udała się alokacja %d bajtów na bufor RX" #: ports/nrf/common-hal/_bleio/Adapter.c msgid "Failed to connect: internal error" -msgstr "" +msgstr "Nie udało się połączyć: błąd wewnętrzny" #: ports/nrf/common-hal/_bleio/Adapter.c msgid "Failed to connect: timeout" -msgstr "" +msgstr "Nie udało się połączyć: upłynął limit czasu" #: shared-module/audiomp3/MP3Decoder.c msgid "Failed to parse MP3 file" @@ -837,7 +844,7 @@ msgstr "Nie udało się zwolnić blokady, błąd 0x%04x" #: supervisor/shared/safe_mode.c msgid "Failed to write internal flash." -msgstr "" +msgstr "Nie udało się zapisać wewnętrznej pamięci flash." #: py/moduerrno.c msgid "File exists" @@ -846,7 +853,7 @@ msgstr "Plik istnieje" #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" -msgstr "" +msgstr "Bufor ramki wymaga %d bajtów" #: ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c msgid "Frequency captured is above capability. Capture Paused." @@ -865,7 +872,7 @@ msgstr "Funkcja wymaga blokady" #: shared-bindings/displayio/EPaperDisplay.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Group already used" -msgstr "" +msgstr "Grupa już używana" #: shared-module/displayio/Group.c msgid "Group full" @@ -886,7 +893,7 @@ msgstr "Operacja I/O na zamkniętym pliku" #: ports/stm/common-hal/busio/I2C.c msgid "I2C Init Error" -msgstr "" +msgstr "Błąd inicjalizacji I2C" #: shared-bindings/audiobusio/I2SOut.c msgid "I2SOut not available" @@ -915,11 +922,11 @@ msgstr "Błąd I/O" #: ports/nrf/common-hal/_bleio/__init__.c msgid "Insufficient authentication" -msgstr "" +msgstr "Niewystarczające uwierzytelnienie" #: ports/nrf/common-hal/_bleio/__init__.c msgid "Insufficient encryption" -msgstr "" +msgstr "Niewystarczające szyfrowanie" #: ports/stm/common-hal/busio/UART.c msgid "Internal define error" @@ -928,7 +935,7 @@ msgstr "" #: shared-module/rgbmatrix/RGBMatrix.c #, c-format msgid "Internal error #%d" -msgstr "" +msgstr "Błąd wewnętrzny #%d" #: shared-bindings/sdioio/SDCard.c msgid "Invalid %q" @@ -988,7 +995,7 @@ msgstr "Zła liczba kanałów" #: shared-bindings/digitalio/DigitalInOut.c msgid "Invalid direction." -msgstr "Zły tryb" +msgstr "Nieprawidłowy kierunek." #: shared-module/audiocore/WaveFile.c msgid "Invalid file" @@ -1000,11 +1007,11 @@ msgstr "Zła wielkość fragmentu formatu" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Invalid frequency supplied" -msgstr "" +msgstr "Podano nieprawidłową częstotliwość" #: supervisor/shared/safe_mode.c msgid "Invalid memory access." -msgstr "" +msgstr "Nieprawidłowy dostęp do pamięci." #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c msgid "Invalid number of bits" @@ -1043,7 +1050,7 @@ msgstr "Złe nóżki" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Invalid pins for PWMOut" -msgstr "" +msgstr "Nieprawidłowe piny dla PWMOut" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c #: shared-bindings/displayio/FourWire.c @@ -1052,11 +1059,11 @@ msgstr "Zła polaryzacja" #: shared-bindings/_bleio/Characteristic.c msgid "Invalid properties" -msgstr "" +msgstr "Nieprawidłowe właściwości" #: shared-bindings/microcontroller/__init__.c msgid "Invalid run mode." -msgstr "Zły tryb uruchomienia" +msgstr "Zły tryb uruchomienia." #: shared-module/_bleio/Attribute.c msgid "Invalid security_mode" @@ -1076,11 +1083,11 @@ msgstr "Zły plik wave" #: ports/stm/common-hal/busio/UART.c msgid "Invalid word/bit length" -msgstr "" +msgstr "Niepoprawna długość słowa/bitu" #: shared-bindings/aesio/aes.c msgid "Key must be 16, 24, or 32 bytes long" -msgstr "" +msgstr "Klucz musi mieć długość 16, 24 lub 32 bajtów" #: py/compile.c msgid "LHS of keyword arg must be an id" @@ -1108,7 +1115,7 @@ msgstr "Nie powiodło się ustawienie nóżki MISO." #: shared-module/bitbangio/SPI.c msgid "MOSI pin init failed." -msgstr "Nie powiodło się ustawienie nóżki MOSI" +msgstr "Nie powiodło się ustawienie nóżki MOSI." #: shared-module/displayio/Shape.c #, c-format @@ -1118,10 +1125,11 @@ msgstr "Największa wartość x przy odwróceniu to %d" #: supervisor/shared/safe_mode.c msgid "MicroPython NLR jump failed. Likely memory corruption." msgstr "" +"Skok MicroRython NLR nie powiódł się. Prawdopodobne uszkodzenie pamięci." #: supervisor/shared/safe_mode.c msgid "MicroPython fatal error." -msgstr "" +msgstr "Błąd krytyczny MicroPython." #: shared-bindings/audiobusio/PDMIn.c msgid "Microphone startup delay must be in range 0.0 to 1.0" @@ -1137,11 +1145,11 @@ msgstr "" #: ports/mimxrt10xx/common-hal/busio/SPI.c ports/stm/common-hal/busio/SPI.c msgid "Must provide MISO or MOSI pin" -msgstr "" +msgstr "Należy podać pin MISO lub MOSI" #: ports/stm/common-hal/busio/SPI.c msgid "Must provide SCK pin" -msgstr "" +msgstr "Należy podać pin SCK" #: shared-bindings/rgbmatrix/RGBMatrix.c #, c-format @@ -1150,7 +1158,7 @@ msgstr "" #: py/parse.c msgid "Name too long" -msgstr "" +msgstr "Za długa nazwa" #: ports/nrf/common-hal/_bleio/Characteristic.c msgid "No CCCD for this Characteristic" @@ -1192,7 +1200,7 @@ msgstr "Brak wolnych zegarów" #: shared-bindings/_bleio/PacketBuffer.c msgid "No connection: length cannot be determined" -msgstr "" +msgstr "Brak połączenia: nie można ustalić długości" #: shared-bindings/board/__init__.c msgid "No default %q bus" @@ -1217,7 +1225,7 @@ msgstr "Brak sprzętowej obsługi na nóżce" #: shared-bindings/aesio/aes.c msgid "No key was specified" -msgstr "" +msgstr "Nie określono klucza" #: shared-bindings/time/__init__.c msgid "No long integer support" @@ -1320,7 +1328,7 @@ msgstr "Nie można zmienić częstotliwości PWM gdy variable_frequency=False." #: ports/mimxrt10xx/common-hal/displayio/ParallelBus.c #: ports/stm/common-hal/displayio/ParallelBus.c msgid "ParallelBus not yet supported" -msgstr "" +msgstr "ParallelBus nie jest jeszcze obsługiwany" #: py/moduerrno.c msgid "Permission denied" @@ -1340,7 +1348,7 @@ msgstr "" #: ports/atmel-samd/common-hal/countio/Counter.c msgid "Pin must support hardware interrupts" -msgstr "" +msgstr "Pin musi obsługiwać przerwania sprzętowe" #: ports/stm/common-hal/pulseio/PulseIn.c msgid "Pin number already reserved by EXTI" @@ -1428,11 +1436,11 @@ msgstr "Obiekt tylko do odczytu" #: shared-bindings/displayio/EPaperDisplay.c msgid "Refresh too soon" -msgstr "" +msgstr "Zbyt wczesne odświeżenie" #: shared-bindings/aesio/aes.c msgid "Requested AES mode is unsupported" -msgstr "" +msgstr "Żądany tryb AES nie jest obsługiwany" #: ports/atmel-samd/common-hal/audioio/AudioOut.c msgid "Right channel unsupported" @@ -1467,11 +1475,11 @@ msgstr "" #: ports/stm/common-hal/busio/SPI.c msgid "SPI Init Error" -msgstr "" +msgstr "Błąd inicjowania SPI" #: ports/stm/common-hal/busio/SPI.c msgid "SPI Re-initialization error" -msgstr "" +msgstr "Błąd ponownej inicjalizacji SPI" #: shared-bindings/audiomixer/Mixer.c msgid "Sample rate must be positive" @@ -1484,7 +1492,7 @@ msgstr "Zbyt wysoka częstotliwość próbkowania. Musi być mniejsza niż %d" #: ports/nrf/common-hal/_bleio/Adapter.c msgid "Scan already in progess. Stop with stop_scan." -msgstr "" +msgstr "Skanuj już w toku. Zatrzymaj za pomocą stop_scan." #: ports/mimxrt10xx/common-hal/busio/UART.c msgid "Selected CTS pin not valid" @@ -1516,7 +1524,7 @@ msgstr "Fragmenty nieobsługiwane" #: shared-bindings/aesio/aes.c msgid "Source and destination buffers must be the same length" -msgstr "" +msgstr "Bufory źródłowy i docelowy muszą mieć taką samą długość" #: extmod/modure.c msgid "Splitting with sub-captures" @@ -1567,7 +1575,7 @@ msgstr "Wartość bits_per_sample nie pasuje do miksera" #: shared-module/audiomixer/MixerVoice.c msgid "The sample's channel count does not match the mixer's" -msgstr "Liczba kanałów nie pasuje do miksera " +msgstr "Liczba kanałów nie pasuje do miksera" #: shared-module/audiomixer/MixerVoice.c msgid "The sample's sample rate does not match the mixer's" @@ -1633,7 +1641,7 @@ msgstr "Wymagana krotka lub struct_time" #: ports/stm/common-hal/busio/UART.c msgid "UART Buffer allocation error" -msgstr "" +msgstr "Błąd alokacji bufora UART" #: ports/stm/common-hal/busio/UART.c msgid "UART De-init error" @@ -1700,7 +1708,7 @@ msgstr "Błąd zapisu do NVM." #: ports/nrf/common-hal/_bleio/UUID.c msgid "Unexpected nrfx uuid type" -msgstr "Nieoczekiwany typ nrfx uuid." +msgstr "Nieoczekiwany typ nrfx uuid" #: shared-bindings/wifi/Radio.c msgid "Unknown failure" @@ -1793,7 +1801,7 @@ msgstr "" #: shared-bindings/watchdog/WatchDogTimer.c msgid "WatchDogTimer.timeout must be greater than 0" -msgstr "" +msgstr "WatchDogTimer.timeout musi być większe od 0" #: supervisor/shared/safe_mode.c msgid "Watchdog timer expired." @@ -1808,9 +1816,12 @@ msgid "" "\n" "To list built-in modules please do `help(\"modules\")`.\n" msgstr "" -"Witamy w CircuitPythonie Adafruita %s!\n" -"Podręczniki dostępne na learn.adafruit.com/category/circuitpyhon.\n" -"Aby zobaczyć wbudowane moduły, wpisz `help(\"modules\")`.\n" +"Witamy w Adafruit CircuitPython %s!\n" +"\n" +"Aby zapoznać się z przewodnikami do projektu, odwiedź stronę learn.adafruit." +"com/category/circuitpython.\n" +"\n" +"Aby wyświetlić listę wbudowanych modułów, wpisz `help(\"modules\")`.\n" #: shared-bindings/wifi/Radio.c msgid "WiFi password must be between 8 and 63 characters" @@ -2026,7 +2037,7 @@ msgstr "przypisanie do wyrażenia" #: py/obj.c py/objint.c shared-bindings/i2cperipheral/I2CPeripheral.c #: shared-module/_pixelbuf/PixelBuf.c msgid "can't convert %q to %q" -msgstr "" +msgstr "nie można dokonać konwersji %q na %q" #: py/objstr.c msgid "can't convert '%q' object to %q implicitly" @@ -2216,7 +2227,7 @@ msgstr "" #: shared-module/sdcardio/SDCard.c msgid "couldn't determine SD card version" -msgstr "" +msgstr "nie można określić wersji karty SD" #: extmod/ulab/code/approx/approx.c msgid "data must be iterable" @@ -2365,11 +2376,11 @@ msgstr "" #: extmod/ulab/code/approx/approx.c msgid "first argument must be a function" -msgstr "" +msgstr "pierwszy argument musi być funkcją" #: extmod/ulab/code/ndarray.c msgid "first argument must be an iterable" -msgstr "" +msgstr "pierwszy argument musi być iterowalny" #: extmod/ulab/code/vector/vectorise.c msgid "first argument must be an ndarray" @@ -2489,7 +2500,7 @@ msgstr "złe wypełnienie" #: extmod/ulab/code/ndarray.c msgid "index is out of bounds" -msgstr "" +msgstr "indeks jest poza zakresem" #: py/obj.c msgid "index out of range" @@ -2505,11 +2516,11 @@ msgstr "" #: extmod/ulab/code/approx/approx.c msgid "initial values must be iterable" -msgstr "" +msgstr "wartości początkowe muszą być iterowalne" #: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c msgid "initial_value length is wrong" -msgstr "" +msgstr "długość initial_value jest nieprawidłowa" #: py/compile.c msgid "inline assembler must be a function" @@ -2521,7 +2532,7 @@ msgstr "" #: extmod/ulab/code/fft/fft.c msgid "input array length must be power of 2" -msgstr "" +msgstr "długość tablicy wejściowej musi być potęgą 2" #: extmod/ulab/code/poly/poly.c msgid "input data must be an iterable" @@ -2537,7 +2548,7 @@ msgstr "" #: extmod/ulab/code/linalg/linalg.c msgid "input must be square matrix" -msgstr "" +msgstr "wejście musi być macierzą kwadratową" #: extmod/ulab/code/numerical/numerical.c msgid "input must be tuple, list, range, or ndarray" @@ -2545,7 +2556,7 @@ msgstr "" #: extmod/ulab/code/poly/poly.c msgid "input vectors must be of equal length" -msgstr "" +msgstr "wektory wejściowe muszą być równej długości" #: py/parsenum.c msgid "int() arg 2 must be >= 2 and <= 36" @@ -2562,7 +2573,7 @@ msgstr "" #: shared-bindings/_bleio/Adapter.c #, c-format msgid "interval must be in range %s-%s" -msgstr "" +msgstr "interwał musi mieścić się w zakresie %s-%s" #: lib/netutils/netutils.c msgid "invalid arguments" @@ -2705,7 +2716,7 @@ msgstr "" #: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c msgid "max_length must be > 0" -msgstr "" +msgstr "max_length musi być > 0" #: py/runtime.c msgid "maximum recursion depth exceeded" @@ -2930,7 +2941,7 @@ msgstr "" #: extmod/ulab/code/ndarray.c msgid "operation is not supported for given type" -msgstr "" +msgstr "operacja nie jest obsługiwana dla danego typu" #: py/modbuiltins.c msgid "ord expects a character" @@ -3021,7 +3032,7 @@ msgstr "" #: extmod/ulab/code/fft/fft.c msgid "real and imaginary parts must be of equal length" -msgstr "" +msgstr "rzeczywiste i urojone części muszą mieć jednakową długość" #: py/builtinimport.c msgid "relative import" @@ -3231,7 +3242,7 @@ msgstr "zbyt wiele argumentów podanych dla tego formatu" #: extmod/ulab/code/ndarray.c msgid "too many indices" -msgstr "" +msgstr "zbyt wiele indeksów" #: py/runtime.c #, c-format @@ -3367,7 +3378,7 @@ msgstr "value_count musi być > 0" #: extmod/ulab/code/linalg/linalg.c msgid "vectors must have same lengths" -msgstr "" +msgstr "wektory muszą mieć identyczną długość" #: shared-bindings/watchdog/WatchDogTimer.c msgid "watchdog timeout must be greater than 0" @@ -3379,11 +3390,11 @@ msgstr "" #: extmod/ulab/code/linalg/linalg.c msgid "wrong argument type" -msgstr "" +msgstr "zły typ argumentu" #: extmod/ulab/code/ndarray.c msgid "wrong index type" -msgstr "" +msgstr "zły typ indeksu" #: extmod/ulab/code/vector/vectorise.c msgid "wrong input type" From e1071bb14ab269e2dfea95f3419e77ed53bb3c05 Mon Sep 17 00:00:00 2001 From: Hosted Weblate Date: Wed, 16 Sep 2020 15:47:44 +0200 Subject: [PATCH 81/91] Update translation files Updated by "Update PO files to match POT (msgmerge)" hook in Weblate. Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/ --- locale/ID.po | 4 ++++ locale/cs.po | 4 ++++ locale/de_DE.po | 4 ++++ locale/el.po | 4 ++++ locale/es.po | 4 ++++ locale/fil.po | 4 ++++ locale/fr.po | 4 ++++ locale/hi.po | 4 ++++ locale/it_IT.po | 4 ++++ locale/ja.po | 4 ++++ locale/ko.po | 4 ++++ locale/nl.po | 4 ++++ locale/pl.po | 4 ++++ locale/pt_BR.po | 4 ++++ locale/sv.po | 4 ++++ locale/zh_Latn_pinyin.po | 4 ++++ 16 files changed, 64 insertions(+) diff --git a/locale/ID.po b/locale/ID.po index 5fd0647a14..5b9354b5a9 100644 --- a/locale/ID.po +++ b/locale/ID.po @@ -926,6 +926,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "Ukuran penyangga salah" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Kesalahan input/output" diff --git a/locale/cs.po b/locale/cs.po index 8dcf08cf2a..33fa668c50 100644 --- a/locale/cs.po +++ b/locale/cs.po @@ -909,6 +909,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "" diff --git a/locale/de_DE.po b/locale/de_DE.po index d9f80769ea..83cb537fa0 100644 --- a/locale/de_DE.po +++ b/locale/de_DE.po @@ -926,6 +926,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "Inkorrekte Puffergröße" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Eingabe-/Ausgabefehler" diff --git a/locale/el.po b/locale/el.po index 6f5ae88e04..4aee93220d 100644 --- a/locale/el.po +++ b/locale/el.po @@ -904,6 +904,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "" diff --git a/locale/es.po b/locale/es.po index 85b4e758df..e6d321c31e 100644 --- a/locale/es.po +++ b/locale/es.po @@ -927,6 +927,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "Tamaño incorrecto del buffer" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "error Input/output" diff --git a/locale/fil.po b/locale/fil.po index e630fddee3..7e8ee19907 100644 --- a/locale/fil.po +++ b/locale/fil.po @@ -919,6 +919,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "May mali sa Input/Output" diff --git a/locale/fr.po b/locale/fr.po index 8f1965a6b8..d59eec51d4 100644 --- a/locale/fr.po +++ b/locale/fr.po @@ -932,6 +932,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "Taille de tampon incorrecte" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Erreur d'entrée/sortie" diff --git a/locale/hi.po b/locale/hi.po index c06eff81d9..34014d120b 100644 --- a/locale/hi.po +++ b/locale/hi.po @@ -904,6 +904,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "" diff --git a/locale/it_IT.po b/locale/it_IT.po index 5ff22f8a63..128958c22b 100644 --- a/locale/it_IT.po +++ b/locale/it_IT.po @@ -919,6 +919,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Errore input/output" diff --git a/locale/ja.po b/locale/ja.po index db3839b402..91e4d46368 100644 --- a/locale/ja.po +++ b/locale/ja.po @@ -920,6 +920,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "バッファサイズが正しくありません" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "入力/出力エラー" diff --git a/locale/ko.po b/locale/ko.po index 70b7985867..d371c9bbdc 100644 --- a/locale/ko.po +++ b/locale/ko.po @@ -907,6 +907,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "" diff --git a/locale/nl.po b/locale/nl.po index 04d0ede837..f5fe492b67 100644 --- a/locale/nl.po +++ b/locale/nl.po @@ -921,6 +921,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "Incorrecte buffer grootte" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Input/Output fout" diff --git a/locale/pl.po b/locale/pl.po index d616378fbf..ff9f6e4b3d 100644 --- a/locale/pl.po +++ b/locale/pl.po @@ -916,6 +916,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "Niewłaściwa wielkość bufora" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Błąd I/O" diff --git a/locale/pt_BR.po b/locale/pt_BR.po index 70cecc395c..26392c8043 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -930,6 +930,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "O tamanho do buffer está incorreto" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Erro de entrada/saída" diff --git a/locale/sv.po b/locale/sv.po index cc3cd4593e..94e4d4f330 100644 --- a/locale/sv.po +++ b/locale/sv.po @@ -919,6 +919,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "Fel buffertstorlek" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Indata-/utdatafel" diff --git a/locale/zh_Latn_pinyin.po b/locale/zh_Latn_pinyin.po index 9b9c1414ac..c3f0a7e0d8 100644 --- a/locale/zh_Latn_pinyin.po +++ b/locale/zh_Latn_pinyin.po @@ -916,6 +916,10 @@ msgstr "" msgid "Incorrect buffer size" msgstr "Huǎnchōng qū dàxiǎo bù zhèngquè" +#: ports/atmel-samd/common-hal/pulseio/PulseIn.c +msgid "Input taking too long" +msgstr "" + #: py/moduerrno.c msgid "Input/output error" msgstr "Shūrù/shūchū cuòwù" From 07f944bf6732646a2020f4ccdb803a428539bf39 Mon Sep 17 00:00:00 2001 From: Wellington Terumi Uemura Date: Wed, 16 Sep 2020 15:54:08 +0000 Subject: [PATCH 82/91] Translated using Weblate (Portuguese (Brazil)) Currently translated at 100.0% (796 of 796 strings) Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/pt_BR/ --- locale/pt_BR.po | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/locale/pt_BR.po b/locale/pt_BR.po index 26392c8043..0cef2c6360 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -6,7 +6,7 @@ msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2020-09-13 14:21-0500\n" -"PO-Revision-Date: 2020-09-14 13:47+0000\n" +"PO-Revision-Date: 2020-09-16 16:30+0000\n" "Last-Translator: Wellington Terumi Uemura \n" "Language-Team: \n" "Language: pt_BR\n" @@ -932,7 +932,7 @@ msgstr "O tamanho do buffer está incorreto" #: ports/atmel-samd/common-hal/pulseio/PulseIn.c msgid "Input taking too long" -msgstr "" +msgstr "A entrada está demorando demais" #: py/moduerrno.c msgid "Input/output error" From 22becafde9c012a374c29c11bcb8cd0fc2d7b5c4 Mon Sep 17 00:00:00 2001 From: Hosted Weblate Date: Wed, 16 Sep 2020 18:30:09 +0200 Subject: [PATCH 83/91] Update translation files Updated by "Update PO files to match POT (msgmerge)" hook in Weblate. Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/ --- locale/ID.po | 16 ++++++++++++++-- locale/cs.po | 16 ++++++++++++++-- locale/de_DE.po | 16 ++++++++++++++-- locale/el.po | 16 ++++++++++++++-- locale/es.po | 16 ++++++++++++++-- locale/fil.po | 16 ++++++++++++++-- locale/fr.po | 16 ++++++++++++++-- locale/hi.po | 16 ++++++++++++++-- locale/it_IT.po | 16 ++++++++++++++-- locale/ja.po | 16 ++++++++++++++-- locale/ko.po | 16 ++++++++++++++-- locale/nl.po | 16 ++++++++++++++-- locale/pl.po | 16 ++++++++++++++-- locale/pt_BR.po | 16 ++++++++++++++-- locale/sv.po | 16 ++++++++++++++-- locale/zh_Latn_pinyin.po | 16 ++++++++++++++-- 16 files changed, 224 insertions(+), 32 deletions(-) diff --git a/locale/ID.po b/locale/ID.po index 5b9354b5a9..cbf59dc8c6 100644 --- a/locale/ID.po +++ b/locale/ID.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-07-06 18:10+0000\n" "Last-Translator: oon arfiandwi \n" "Language-Team: LANGUAGE \n" @@ -436,7 +436,7 @@ msgstr "Ukuran buffer salah. Seharusnya %d byte." msgid "Buffer is not a bytearray." msgstr "Buffer bukan bytearray." -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "Buffer terlalu kecil" @@ -632,6 +632,10 @@ msgstr "File .mpy rusak" msgid "Corrupt raw code" msgstr "Kode raw rusak" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -859,6 +863,10 @@ msgstr "Gagal menulis flash internal." msgid "File exists" msgstr "File sudah ada" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1528,6 +1536,10 @@ msgstr "Serializer sedang digunakan" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "" diff --git a/locale/cs.po b/locale/cs.po index 33fa668c50..5f6a46a3bb 100644 --- a/locale/cs.po +++ b/locale/cs.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-05-24 03:22+0000\n" "Last-Translator: dronecz \n" "Language-Team: LANGUAGE \n" @@ -434,7 +434,7 @@ msgstr "" msgid "Buffer is not a bytearray." msgstr "" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "" @@ -619,6 +619,10 @@ msgstr "" msgid "Corrupt raw code" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -845,6 +849,10 @@ msgstr "" msgid "File exists" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1507,6 +1515,10 @@ msgstr "" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "" diff --git a/locale/de_DE.po b/locale/de_DE.po index 83cb537fa0..0e9511f125 100644 --- a/locale/de_DE.po +++ b/locale/de_DE.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-06-16 18:24+0000\n" "Last-Translator: Andreas Buchen \n" "Language: de_DE\n" @@ -437,7 +437,7 @@ msgstr "Der Puffergröße ist inkorrekt. Sie sollte %d bytes haben." msgid "Buffer is not a bytearray." msgstr "Der Buffer ist kein Byte-Array." -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "Der Puffer ist zu klein" @@ -629,6 +629,10 @@ msgstr "Beschädigte .mpy Datei" msgid "Corrupt raw code" msgstr "Beschädigter raw code" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -856,6 +860,10 @@ msgstr "Interner Flash konnte nicht geschrieben werden." msgid "File exists" msgstr "Datei existiert" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1537,6 +1545,10 @@ msgstr "Serializer wird benutzt" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Slice und Wert (value) haben unterschiedliche Längen." diff --git a/locale/el.po b/locale/el.po index 4aee93220d..10efe96a7c 100644 --- a/locale/el.po +++ b/locale/el.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: Automatically generated\n" "Language-Team: none\n" @@ -429,7 +429,7 @@ msgstr "" msgid "Buffer is not a bytearray." msgstr "" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "" @@ -614,6 +614,10 @@ msgstr "" msgid "Corrupt raw code" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -840,6 +844,10 @@ msgstr "" msgid "File exists" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1502,6 +1510,10 @@ msgstr "" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "" diff --git a/locale/es.po b/locale/es.po index e6d321c31e..1e312d7c8e 100644 --- a/locale/es.po +++ b/locale/es.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-08-17 21:11+0000\n" "Last-Translator: Alvaro Figueroa \n" "Language-Team: \n" @@ -443,7 +443,7 @@ msgstr "Tamaño de buffer incorrecto. Debe ser de %d bytes." msgid "Buffer is not a bytearray." msgstr "Buffer no es un bytearray." -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "El buffer es muy pequeño" @@ -634,6 +634,10 @@ msgstr "Archivo .mpy corrupto" msgid "Corrupt raw code" msgstr "Código crudo corrupto" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "No se pudo inicializar el GNSS" @@ -860,6 +864,10 @@ msgstr "Error al escribir al flash interno." msgid "File exists" msgstr "El archivo ya existe" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1536,6 +1544,10 @@ msgstr "Serializer está siendo utilizado" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Slice y value tienen tamaños diferentes." diff --git a/locale/fil.po b/locale/fil.po index 7e8ee19907..09efc42440 100644 --- a/locale/fil.po +++ b/locale/fil.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2018-12-20 22:15-0800\n" "Last-Translator: Timothy \n" "Language-Team: fil\n" @@ -434,7 +434,7 @@ msgstr "Mali ang size ng buffer. Dapat %d bytes." msgid "Buffer is not a bytearray." msgstr "" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "" @@ -622,6 +622,10 @@ msgstr "" msgid "Corrupt raw code" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -853,6 +857,10 @@ msgstr "" msgid "File exists" msgstr "Mayroong file" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1524,6 +1532,10 @@ msgstr "Serializer ginagamit" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Slice at value iba't ibang haba." diff --git a/locale/fr.po b/locale/fr.po index d59eec51d4..e602facaf2 100644 --- a/locale/fr.po +++ b/locale/fr.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: 0.1\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-09-16 13:47+0000\n" "Last-Translator: Hugo Dahl \n" "Language: fr\n" @@ -443,7 +443,7 @@ msgstr "Tampon de taille incorrect. Devrait être de %d octets." msgid "Buffer is not a bytearray." msgstr "Le tampon n'est pas un 'bytearray'." -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "Le tampon est trop petit" @@ -638,6 +638,10 @@ msgstr "Fichier .mpy corrompu" msgid "Corrupt raw code" msgstr "Code brut corrompu" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "Impossible d'initialiser GNSS" @@ -865,6 +869,10 @@ msgstr "Échec de l'écriture du flash interne." msgid "File exists" msgstr "Le fichier existe" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1543,6 +1551,10 @@ msgstr "Sérialiseur en cours d'utilisation" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Tranche et valeur de tailles différentes." diff --git a/locale/hi.po b/locale/hi.po index 34014d120b..17048b1a6d 100644 --- a/locale/hi.po +++ b/locale/hi.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: Automatically generated\n" "Language-Team: none\n" @@ -429,7 +429,7 @@ msgstr "" msgid "Buffer is not a bytearray." msgstr "" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "" @@ -614,6 +614,10 @@ msgstr "" msgid "Corrupt raw code" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -840,6 +844,10 @@ msgstr "" msgid "File exists" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1502,6 +1510,10 @@ msgstr "" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "" diff --git a/locale/it_IT.po b/locale/it_IT.po index 128958c22b..b190f976b6 100644 --- a/locale/it_IT.po +++ b/locale/it_IT.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2018-10-02 16:27+0200\n" "Last-Translator: Enrico Paganin \n" "Language-Team: \n" @@ -434,7 +434,7 @@ msgstr "Buffer di lunghezza non valida. Dovrebbe essere di %d bytes." msgid "Buffer is not a bytearray." msgstr "" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "" @@ -623,6 +623,10 @@ msgstr "" msgid "Corrupt raw code" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -853,6 +857,10 @@ msgstr "" msgid "File exists" msgstr "File esistente" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1535,6 +1543,10 @@ msgstr "Serializer in uso" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "" diff --git a/locale/ja.po b/locale/ja.po index 91e4d46368..0f9bd3be60 100644 --- a/locale/ja.po +++ b/locale/ja.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-09-01 18:44+0000\n" "Last-Translator: Jeff Epler \n" "Language-Team: none\n" @@ -439,7 +439,7 @@ msgstr "バッファサイズが正しくありません。%dバイトでなけ msgid "Buffer is not a bytearray." msgstr "バッファが bytearray ではありません" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "バッファが小さすぎます" @@ -628,6 +628,10 @@ msgstr "破損した .mpy ファイル" msgid "Corrupt raw code" msgstr "破損したraw code" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "GNSSを初期化できません" @@ -854,6 +858,10 @@ msgstr "内部フラッシュの書き込みに失敗" msgid "File exists" msgstr "ファイルが存在します" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1522,6 +1530,10 @@ msgstr "シリアライザは使用中" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "スライスと値の長さが一致しません" diff --git a/locale/ko.po b/locale/ko.po index d371c9bbdc..0bdf7c742d 100644 --- a/locale/ko.po +++ b/locale/ko.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2019-05-06 14:22-0700\n" "Last-Translator: \n" "Language-Team: LANGUAGE \n" @@ -432,7 +432,7 @@ msgstr "잘못된 크기의 버퍼. %d 바이트 여야합니다." msgid "Buffer is not a bytearray." msgstr "" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "" @@ -617,6 +617,10 @@ msgstr "" msgid "Corrupt raw code" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "" @@ -843,6 +847,10 @@ msgstr "" msgid "File exists" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1505,6 +1513,10 @@ msgstr "" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "" diff --git a/locale/nl.po b/locale/nl.po index f5fe492b67..e0b4d8793a 100644 --- a/locale/nl.po +++ b/locale/nl.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-09-09 16:05+0000\n" "Last-Translator: Jelle Jager \n" "Language-Team: none\n" @@ -436,7 +436,7 @@ msgstr "Buffer heeft incorrect grootte. Moet %d bytes zijn." msgid "Buffer is not a bytearray." msgstr "Buffer is geen bytearray." -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "Buffer is te klein" @@ -627,6 +627,10 @@ msgstr "Corrupt .mpy bestand" msgid "Corrupt raw code" msgstr "Corrupt raw code" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "Kan GNSS niet initialiseren" @@ -853,6 +857,10 @@ msgstr "Schrijven naar interne flash mislukt." msgid "File exists" msgstr "Bestand bestaat" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1533,6 +1541,10 @@ msgstr "Serializer in gebruik" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Slice en waarde hebben verschillende lengtes." diff --git a/locale/pl.po b/locale/pl.po index ff9f6e4b3d..afecdaf4fb 100644 --- a/locale/pl.po +++ b/locale/pl.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-09-16 13:47+0000\n" "Last-Translator: Maciej Stankiewicz \n" "Language-Team: pl\n" @@ -435,7 +435,7 @@ msgstr "Zła wielkość bufora. Powinno być %d bajtów." msgid "Buffer is not a bytearray." msgstr "" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "Bufor jest za mały" @@ -624,6 +624,10 @@ msgstr "Uszkodzony plik .mpy" msgid "Corrupt raw code" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "Nie można zainicjować GNSS" @@ -850,6 +854,10 @@ msgstr "Nie udało się zapisać wewnętrznej pamięci flash." msgid "File exists" msgstr "Plik istnieje" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1515,6 +1523,10 @@ msgstr "Serializator w użyciu" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Fragment i wartość są różnych długości." diff --git a/locale/pt_BR.po b/locale/pt_BR.po index 0cef2c6360..89fd302163 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-09-16 16:30+0000\n" "Last-Translator: Wellington Terumi Uemura \n" "Language-Team: \n" @@ -444,7 +444,7 @@ msgstr "Buffer de tamanho incorreto. Deve ser %d bytes." msgid "Buffer is not a bytearray." msgstr "O buffer não é um bytearray." -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "O buffer é muito pequeno" @@ -636,6 +636,10 @@ msgstr "Arquivo .mpy corrompido" msgid "Corrupt raw code" msgstr "Código bruto corrompido" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "Não foi possível inicializar o GNSS" @@ -862,6 +866,10 @@ msgstr "Falha ao gravar o flash interno." msgid "File exists" msgstr "Arquivo já existe" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1545,6 +1553,10 @@ msgstr "Serializer em uso" msgid "Server side context cannot have hostname" msgstr "O contexto do lado do servidor não pode ter nome de host" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Fatie e avalie os diferentes comprimentos." diff --git a/locale/sv.po b/locale/sv.po index 94e4d4f330..8774e0734c 100644 --- a/locale/sv.po +++ b/locale/sv.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2020-09-07 19:36+0000\n" "Last-Translator: Jonny Bergdahl \n" "Language-Team: LANGUAGE \n" @@ -436,7 +436,7 @@ msgstr "Buffert har felaktig storlek. Ska vara %d byte." msgid "Buffer is not a bytearray." msgstr "Buffert är inte en bytearray." -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "Bufferten är för liten" @@ -627,6 +627,10 @@ msgstr "Skadad .mpy-fil" msgid "Corrupt raw code" msgstr "Korrupt rå kod" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "Kan inte initiera GNSS" @@ -853,6 +857,10 @@ msgstr "Det gick inte att skriva till intern flash." msgid "File exists" msgstr "Filen finns redan" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1531,6 +1539,10 @@ msgstr "Serializern används redan" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Slice och värde har olika längd." diff --git a/locale/zh_Latn_pinyin.po b/locale/zh_Latn_pinyin.po index c3f0a7e0d8..fe49abaf25 100644 --- a/locale/zh_Latn_pinyin.po +++ b/locale/zh_Latn_pinyin.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: circuitpython-cn\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-13 14:21-0500\n" +"POT-Creation-Date: 2020-09-11 13:30+0200\n" "PO-Revision-Date: 2019-04-13 10:10-0700\n" "Last-Translator: hexthat\n" "Language-Team: Chinese Hanyu Pinyin\n" @@ -437,7 +437,7 @@ msgstr "Huǎnchōng qū dàxiǎo bù zhèngquè. Yīnggāi shì %d zì jié." msgid "Buffer is not a bytearray." msgstr "Huǎnchōng qū bùshì bytearray" -#: shared-bindings/displayio/Display.c +#: ports/cxd56/common-hal/camera/Camera.c shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Buffer is too small" msgstr "Huǎnchōng qū tài xiǎo" @@ -624,6 +624,10 @@ msgstr "Fǔbài de .mpy wénjiàn" msgid "Corrupt raw code" msgstr "Sǔnhuài de yuánshǐ dàimǎ" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Could not initialize Camera" +msgstr "" + #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" msgstr "wú fǎ chū shǐ huà GNSS" @@ -850,6 +854,10 @@ msgstr "Wúfǎ xiě rù nèibù shǎncún." msgid "File exists" msgstr "Wénjiàn cúnzài" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Format not supported" +msgstr "" + #: shared-module/framebufferio/FramebufferDisplay.c #, c-format msgid "Framebuffer requires %d bytes" @@ -1523,6 +1531,10 @@ msgstr "Xùliè huà yǐjīng shǐyòngguò" msgid "Server side context cannot have hostname" msgstr "" +#: ports/cxd56/common-hal/camera/Camera.c +msgid "Size not supported" +msgstr "" + #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." msgstr "Qiēpiàn hé zhí bùtóng chángdù." From 63ac3a5a435c011faa31055e0eb40fe5cf71cab4 Mon Sep 17 00:00:00 2001 From: Maciej Stankiewicz Date: Thu, 17 Sep 2020 07:54:17 +0000 Subject: [PATCH 84/91] Translated using Weblate (Polish) Currently translated at 73.2% (585 of 799 strings) Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/pl/ --- locale/pl.po | 50 +++++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/locale/pl.po b/locale/pl.po index afecdaf4fb..1dc55ad825 100644 --- a/locale/pl.po +++ b/locale/pl.po @@ -7,7 +7,7 @@ msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2020-09-11 13:30+0200\n" -"PO-Revision-Date: 2020-09-16 13:47+0000\n" +"PO-Revision-Date: 2020-09-17 17:58+0000\n" "Last-Translator: Maciej Stankiewicz \n" "Language-Team: pl\n" "Language: pl\n" @@ -326,7 +326,7 @@ msgstr "" #: ports/cxd56/common-hal/analogio/AnalogIn.c msgid "AnalogIn not supported on given pin" -msgstr "" +msgstr "AnalogIn nie jest obsługiwany na danym pinie" #: ports/cxd56/common-hal/analogio/AnalogOut.c #: ports/mimxrt10xx/common-hal/analogio/AnalogOut.c @@ -443,7 +443,7 @@ msgstr "Bufor jest za mały" #: ports/nrf/common-hal/audiopwmio/PWMAudioOut.c #, c-format msgid "Buffer length %d too big. It must be less than %d" -msgstr "Długość %d bufora jest za duża. Musi być ona mniejsza niż %d" +msgstr "Długość %d bufora jest za duża. Musi być mniejsza niż %d" #: ports/atmel-samd/common-hal/sdioio/SDCard.c #: ports/cxd56/common-hal/sdioio/SDCard.c shared-module/sdcardio/SDCard.c @@ -465,7 +465,7 @@ msgstr "Bufor jest zbyt duży i nie można go przydzielić" #: shared-bindings/_bleio/PacketBuffer.c #, c-format msgid "Buffer too short by %d bytes" -msgstr "Bufor za krótki o %d bajtów" +msgstr "Bufor za krótki o% d bajtów" #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c @@ -642,23 +642,23 @@ msgstr "Ustawienie UART nie powiodło się" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not initialize channel" -msgstr "" +msgstr "Nie można zainicjować kanału" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not initialize timer" -msgstr "" +msgstr "Nie można zainicjować timera" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not re-init channel" -msgstr "" +msgstr "Nie można ponownie zainicjować kanału" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not re-init timer" -msgstr "" +msgstr "Nie można ponownie zainicjować timera" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not restart PWM" -msgstr "Nie można zrestartować PWM" +msgstr "Nie można ponownie uruchomić PWM" #: shared-bindings/_bleio/Adapter.c msgid "Could not set address" @@ -666,11 +666,11 @@ msgstr "Nie można ustawić adresu" #: ports/stm/common-hal/pwmio/PWMOut.c msgid "Could not start PWM" -msgstr "Nie można wystartować PWM" +msgstr "Nie można uruchomić PWM" #: ports/stm/common-hal/busio/UART.c msgid "Could not start interrupt, RX busy" -msgstr "" +msgstr "Nie można rozpocząć przerwania, RX jest zajęty" #: shared-module/audiomp3/MP3Decoder.c msgid "Couldn't allocate decoder" @@ -683,7 +683,7 @@ msgstr "Nie udała się alokacja pierwszego bufora" #: shared-module/audiomp3/MP3Decoder.c msgid "Couldn't allocate input buffer" -msgstr "" +msgstr "Nie można przydzielić bufora wejściowego" #: shared-module/audiocore/WaveFile.c shared-module/audiomixer/Mixer.c #: shared-module/audiomp3/MP3Decoder.c @@ -696,11 +696,11 @@ msgstr "" #: ports/stm/common-hal/analogio/AnalogOut.c msgid "DAC Channel Init Error" -msgstr "" +msgstr "Błąd inicjalizacji kanału DAC" #: ports/stm/common-hal/analogio/AnalogOut.c msgid "DAC Device Init Error" -msgstr "" +msgstr "Błąd inicjowania urządzenia DAC" #: ports/atmel-samd/common-hal/audioio/AudioOut.c msgid "DAC already in use" @@ -729,12 +729,12 @@ msgstr "Urządzenie w użyciu" #: ports/cxd56/common-hal/digitalio/DigitalInOut.c msgid "DigitalInOut not supported on given pin" -msgstr "" +msgstr "DigitalInOut nie jest obsługiwany na podanym pinie" #: shared-bindings/displayio/Display.c #: shared-bindings/framebufferio/FramebufferDisplay.c msgid "Display must have a 16 bit colorspace." -msgstr "" +msgstr "Wyświetlacz musi mieć 16-bitową przestrzeń kolorów." #: shared-bindings/displayio/Display.c #: shared-bindings/displayio/EPaperDisplay.c @@ -748,7 +748,7 @@ msgstr "Tryb sterowania nieużywany w trybie wejścia." #: shared-bindings/aesio/aes.c msgid "ECB only operates on 16 bytes at a time" -msgstr "" +msgstr "ECB działa tylko na 16 bajtach naraz" #: ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c #: ports/atmel-samd/common-hal/ps2io/Ps2.c @@ -792,7 +792,7 @@ msgstr "Oczekiwano UUID" #: shared-bindings/_bleio/Adapter.c msgid "Expected an Address" -msgstr "" +msgstr "Oczekiwano adresu" #: shared-module/_pixelbuf/PixelBuf.c #, c-format @@ -839,7 +839,7 @@ msgstr "Nie udało się połączyć: upłynął limit czasu" #: shared-module/audiomp3/MP3Decoder.c msgid "Failed to parse MP3 file" -msgstr "" +msgstr "Nie można przeanalizować pliku MP3" #: ports/nrf/sd_mutex.c #, c-format @@ -889,11 +889,11 @@ msgstr "Grupa pełna" #: ports/mimxrt10xx/common-hal/busio/SPI.c ports/stm/common-hal/busio/I2C.c #: ports/stm/common-hal/busio/SPI.c ports/stm/common-hal/sdioio/SDCard.c msgid "Hardware busy, try alternative pins" -msgstr "" +msgstr "Sprzęt zajęty, wypróbuj alternatywne piny" #: ports/mimxrt10xx/common-hal/busio/UART.c ports/stm/common-hal/busio/UART.c msgid "Hardware in use, try alternative pins" -msgstr "" +msgstr "Sprzęt w użyciu, wypróbuj alternatywne piny" #: extmod/vfs_posix_file.c py/objstringio.c msgid "I/O operation on closed file" @@ -910,7 +910,7 @@ msgstr "" #: shared-bindings/aesio/aes.c #, c-format msgid "IV must be %d bytes long" -msgstr "" +msgstr "IV musi mieć długość %d bajtów" #: py/persistentcode.c msgid "" @@ -1123,11 +1123,11 @@ msgstr "Długość musi być nieujemna" #: shared-module/bitbangio/SPI.c msgid "MISO pin init failed." -msgstr "Nie powiodło się ustawienie nóżki MISO." +msgstr "Nie powiodło się ustawienie pinu MISO." #: shared-module/bitbangio/SPI.c msgid "MOSI pin init failed." -msgstr "Nie powiodło się ustawienie nóżki MOSI." +msgstr "Nie powiodło się ustawienie pinu MOSI." #: shared-module/displayio/Shape.c #, c-format @@ -1188,7 +1188,7 @@ msgstr "Nie znaleziono kanału DMA" #: ports/mimxrt10xx/common-hal/busio/SPI.c ports/stm/common-hal/busio/SPI.c msgid "No MISO Pin" -msgstr "" +msgstr "Brak pinu MISO" #: ports/mimxrt10xx/common-hal/busio/SPI.c ports/stm/common-hal/busio/SPI.c msgid "No MOSI Pin" From dd0f5f1b21f2a7919a1ec90c83214c1a39317706 Mon Sep 17 00:00:00 2001 From: Wellington Terumi Uemura Date: Wed, 16 Sep 2020 19:26:42 +0000 Subject: [PATCH 85/91] Translated using Weblate (Portuguese (Brazil)) Currently translated at 100.0% (799 of 799 strings) Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/pt_BR/ --- locale/pt_BR.po | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/locale/pt_BR.po b/locale/pt_BR.po index 89fd302163..e3f8fee72b 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -6,7 +6,7 @@ msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2020-09-11 13:30+0200\n" -"PO-Revision-Date: 2020-09-16 16:30+0000\n" +"PO-Revision-Date: 2020-09-17 17:58+0000\n" "Last-Translator: Wellington Terumi Uemura \n" "Language-Team: \n" "Language: pt_BR\n" @@ -638,7 +638,7 @@ msgstr "Código bruto corrompido" #: ports/cxd56/common-hal/camera/Camera.c msgid "Could not initialize Camera" -msgstr "" +msgstr "Não foi possível inicializar a Câmera" #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" @@ -868,7 +868,7 @@ msgstr "Arquivo já existe" #: ports/cxd56/common-hal/camera/Camera.c msgid "Format not supported" -msgstr "" +msgstr "O formato não é suportado" #: shared-module/framebufferio/FramebufferDisplay.c #, c-format @@ -1555,7 +1555,7 @@ msgstr "O contexto do lado do servidor não pode ter nome de host" #: ports/cxd56/common-hal/camera/Camera.c msgid "Size not supported" -msgstr "" +msgstr "O tamanho não é suportado" #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." From fb123cebf2d4e60166516d72010db29e45d2e072 Mon Sep 17 00:00:00 2001 From: Alvaro Figueroa Date: Fri, 18 Sep 2020 21:41:03 +0000 Subject: [PATCH 86/91] Translated using Weblate (Spanish) Currently translated at 100.0% (799 of 799 strings) Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/es/ --- locale/es.po | 52 +++++++++++++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/locale/es.po b/locale/es.po index 1e312d7c8e..354311e8d2 100644 --- a/locale/es.po +++ b/locale/es.po @@ -8,7 +8,7 @@ msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2020-09-11 13:30+0200\n" -"PO-Revision-Date: 2020-08-17 21:11+0000\n" +"PO-Revision-Date: 2020-09-18 23:14+0000\n" "Last-Translator: Alvaro Figueroa \n" "Language-Team: \n" "Language: es\n" @@ -16,7 +16,7 @@ msgstr "" "Content-Type: text/plain; charset=UTF-8\n" "Content-Transfer-Encoding: 8bit\n" "Plural-Forms: nplurals=2; plural=n != 1;\n" -"X-Generator: Weblate 4.2-dev\n" +"X-Generator: Weblate 4.3-dev\n" #: main.c msgid "" @@ -378,7 +378,7 @@ msgstr "" #: shared-bindings/wifi/Radio.c msgid "Authentication failure" -msgstr "" +msgstr "Fallo de autenticación" #: main.c msgid "Auto-reload is off.\n" @@ -503,7 +503,7 @@ msgstr "No se puede configurar CCCD en la característica local" #: shared-bindings/_bleio/Adapter.c msgid "Cannot create a new Adapter; use _bleio.adapter;" -msgstr "" +msgstr "No se puede crear nuevo Adapter; use _bleio.adapter;" #: shared-bindings/displayio/Bitmap.c #: shared-bindings/memorymonitor/AllocationSize.c @@ -595,7 +595,7 @@ msgstr "" #: supervisor/shared/safe_mode.c msgid "CircuitPython was unable to allocate the heap.\n" -msgstr "" +msgstr "CircuitPython no puedo encontrar el montículo.\n" #: shared-module/bitbangio/SPI.c msgid "Clock pin init failed." @@ -636,7 +636,7 @@ msgstr "Código crudo corrupto" #: ports/cxd56/common-hal/camera/Camera.c msgid "Could not initialize Camera" -msgstr "" +msgstr "No se puede inicializar Camera" #: ports/cxd56/common-hal/gnss/GNSS.c msgid "Could not initialize GNSS" @@ -785,7 +785,7 @@ msgstr "Se esperaba una Característica" #: shared-bindings/_bleio/Adapter.c msgid "Expected a DigitalInOut" -msgstr "" +msgstr "Se espera un DigitalInOut" #: shared-bindings/_bleio/Characteristic.c msgid "Expected a Service" @@ -793,7 +793,7 @@ msgstr "Se esperaba un servicio" #: shared-bindings/_bleio/Adapter.c msgid "Expected a UART" -msgstr "" +msgstr "Se espera un UART" #: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c #: shared-bindings/_bleio/Service.c @@ -866,7 +866,7 @@ msgstr "El archivo ya existe" #: ports/cxd56/common-hal/camera/Camera.c msgid "Format not supported" -msgstr "" +msgstr "Sin capacidades para el formato" #: shared-module/framebufferio/FramebufferDisplay.c #, c-format @@ -937,7 +937,7 @@ msgstr "Tamaño incorrecto del buffer" #: ports/atmel-samd/common-hal/pulseio/PulseIn.c msgid "Input taking too long" -msgstr "" +msgstr "La entrada está durando mucho tiempo" #: py/moduerrno.c msgid "Input/output error" @@ -1259,7 +1259,7 @@ msgstr "No hay más temporizadores disponibles en este pin." #: shared-bindings/wifi/Radio.c msgid "No network with that ssid" -msgstr "" +msgstr "No hay una red con ese ssid" #: shared-module/touchio/TouchIn.c msgid "No pulldown on pin; 1Mohm recommended" @@ -1283,7 +1283,7 @@ msgstr "fallo de aserción de dispositivo Nordic Soft." #: shared-bindings/ipaddress/IPv4Address.c shared-bindings/ipaddress/__init__.c msgid "Not a valid IP string" -msgstr "" +msgstr "No es una cadena de IP válida" #: ports/nrf/common-hal/_bleio/__init__.c #: shared-bindings/_bleio/CharacteristicBuffer.c @@ -1301,7 +1301,7 @@ msgstr "No ejecutando el código almacenado.\n" #: shared-bindings/_bleio/__init__.c msgid "Not settable" -msgstr "" +msgstr "No configurable" #: shared-bindings/util.c msgid "" @@ -1337,7 +1337,7 @@ msgstr "" #: shared-bindings/ipaddress/__init__.c msgid "Only raw int supported for ip" -msgstr "" +msgstr "Solo se aceptan enteros crudos para ip" #: shared-bindings/audiobusio/PDMIn.c msgid "Oversample must be multiple of 8." @@ -1410,6 +1410,8 @@ msgid "" "Port does not accept pins or frequency. Construct and pass a PWMOut Carrier " "instead" msgstr "" +"Port no acepta los pines o la frecuencia. Construya y pase en su lugar un " +"Carrier de PWMOut" #: shared-bindings/_bleio/Adapter.c msgid "Prefix buffer must be on the heap" @@ -1542,11 +1544,11 @@ msgstr "Serializer está siendo utilizado" #: shared-bindings/ssl/SSLContext.c msgid "Server side context cannot have hostname" -msgstr "" +msgstr "El contexto del lado del servidor no puede tener un hostname" #: ports/cxd56/common-hal/camera/Camera.c msgid "Size not supported" -msgstr "" +msgstr "Sin capacidades para el tamaño" #: shared-bindings/nvm/ByteArray.c msgid "Slice and value different lengths." @@ -1763,7 +1765,7 @@ msgstr "Tipo de uuid nrfx inesperado" #: shared-bindings/wifi/Radio.c msgid "Unknown failure" -msgstr "" +msgstr "Fallo desconocido" #: ports/nrf/common-hal/_bleio/__init__.c #, c-format @@ -1881,7 +1883,7 @@ msgstr "" #: shared-bindings/wifi/Radio.c msgid "WiFi password must be between 8 and 63 characters" -msgstr "" +msgstr "La clave de WiFi debe ser entre 8 y 63 caracteres" #: ports/nrf/common-hal/_bleio/PacketBuffer.c msgid "Writes not supported on Characteristic" @@ -2052,7 +2054,7 @@ msgstr "bytes > 8 bits no soportados" #: py/objarray.c msgid "bytes length not a multiple of item size" -msgstr "" +msgstr "el tamaño en bytes no es un múltiplo del tamaño del item" #: py/objstr.c msgid "bytes value out of range" @@ -2582,7 +2584,7 @@ msgstr "los valores iniciales deben permitir iteración" #: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c msgid "initial_value length is wrong" -msgstr "" +msgstr "el tamaño de initial_value es incorrecto" #: py/compile.c msgid "inline assembler must be a function" @@ -2781,7 +2783,7 @@ msgstr "max_length debe ser 0-%d cuando fixed_length es %s" #: shared-bindings/_bleio/Characteristic.c shared-bindings/_bleio/Descriptor.c msgid "max_length must be > 0" -msgstr "" +msgstr "max_lenght debe ser > 0" #: py/runtime.c msgid "maximum recursion depth exceeded" @@ -3022,11 +3024,11 @@ msgstr "ord() espera un carácter, pero encontró un string de longitud %d" #: shared-bindings/displayio/Bitmap.c msgid "out of range of source" -msgstr "" +msgstr "fuera de rango de fuente" #: shared-bindings/displayio/Bitmap.c msgid "out of range of target" -msgstr "" +msgstr "fuera de rango del objetivo" #: py/objint_mpz.c msgid "overflow converting long int to machine word" @@ -3035,7 +3037,7 @@ msgstr "desbordamiento convirtiendo long int a palabra de máquina" #: py/modstruct.c #, c-format msgid "pack expected %d items for packing (got %d)" -msgstr "" +msgstr "pack espera %d items para empaquetado (se recibió %d)" #: shared-bindings/_stage/Layer.c shared-bindings/_stage/Text.c msgid "palette must be 32 bytes long" @@ -3214,7 +3216,7 @@ msgstr "sosfilt requiere argumentos iterables" #: shared-bindings/displayio/Bitmap.c msgid "source palette too large" -msgstr "" +msgstr "paleta fuente muy larga" #: py/objstr.c msgid "start/end indices" From ed9173498f3d2e091aa576ff88a43a28f21fc29b Mon Sep 17 00:00:00 2001 From: Hosted Weblate Date: Sat, 19 Sep 2020 03:31:34 +0200 Subject: [PATCH 87/91] Update translation files Updated by "Update PO files to match POT (msgmerge)" hook in Weblate. Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/ --- locale/ID.po | 6 +++++- locale/cs.po | 6 +++++- locale/de_DE.po | 6 +++++- locale/el.po | 6 +++++- locale/es.po | 6 +++++- locale/fil.po | 6 +++++- locale/fr.po | 6 +++++- locale/hi.po | 6 +++++- locale/it_IT.po | 6 +++++- locale/ja.po | 6 +++++- locale/ko.po | 6 +++++- locale/nl.po | 6 +++++- locale/pl.po | 6 +++++- locale/pt_BR.po | 6 +++++- locale/sv.po | 6 +++++- locale/zh_Latn_pinyin.po | 6 +++++- 16 files changed, 80 insertions(+), 16 deletions(-) diff --git a/locale/ID.po b/locale/ID.po index cbf59dc8c6..a13d97f9ec 100644 --- a/locale/ID.po +++ b/locale/ID.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-07-06 18:10+0000\n" "Last-Translator: oon arfiandwi \n" "Language-Team: LANGUAGE \n" @@ -981,6 +981,10 @@ msgstr "Nilai Unit ADC tidak valid" msgid "Invalid BMP file" msgstr "File BMP tidak valid" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "Pin DAC yang diberikan tidak valid" diff --git a/locale/cs.po b/locale/cs.po index 5f6a46a3bb..8d0827b9a1 100644 --- a/locale/cs.po +++ b/locale/cs.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-05-24 03:22+0000\n" "Last-Translator: dronecz \n" "Language-Team: LANGUAGE \n" @@ -964,6 +964,10 @@ msgstr "" msgid "Invalid BMP file" msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "" diff --git a/locale/de_DE.po b/locale/de_DE.po index 0e9511f125..b1eefc98e8 100644 --- a/locale/de_DE.po +++ b/locale/de_DE.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-06-16 18:24+0000\n" "Last-Translator: Andreas Buchen \n" "Language: de_DE\n" @@ -981,6 +981,10 @@ msgstr "Ungültiger ADC-Einheitenwert" msgid "Invalid BMP file" msgstr "Ungültige BMP-Datei" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "Ungültiger DAC-Pin angegeben" diff --git a/locale/el.po b/locale/el.po index 10efe96a7c..acdb64d5a5 100644 --- a/locale/el.po +++ b/locale/el.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: Automatically generated\n" "Language-Team: none\n" @@ -959,6 +959,10 @@ msgstr "" msgid "Invalid BMP file" msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "" diff --git a/locale/es.po b/locale/es.po index 354311e8d2..990908b7c3 100644 --- a/locale/es.po +++ b/locale/es.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-09-18 23:14+0000\n" "Last-Translator: Alvaro Figueroa \n" "Language-Team: \n" @@ -982,6 +982,10 @@ msgstr "Valor de unidad de ADC no válido" msgid "Invalid BMP file" msgstr "Archivo BMP inválido" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "Pin suministrado inválido para DAC" diff --git a/locale/fil.po b/locale/fil.po index 09efc42440..6ef8829981 100644 --- a/locale/fil.po +++ b/locale/fil.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2018-12-20 22:15-0800\n" "Last-Translator: Timothy \n" "Language-Team: fil\n" @@ -974,6 +974,10 @@ msgstr "" msgid "Invalid BMP file" msgstr "Mali ang BMP file" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "" diff --git a/locale/fr.po b/locale/fr.po index e602facaf2..d4a68c3f48 100644 --- a/locale/fr.po +++ b/locale/fr.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: 0.1\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-09-16 13:47+0000\n" "Last-Translator: Hugo Dahl \n" "Language: fr\n" @@ -987,6 +987,10 @@ msgstr "Valeur d'unité ADC non valide" msgid "Invalid BMP file" msgstr "Fichier BMP invalide" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "Broche DAC non valide fournie" diff --git a/locale/hi.po b/locale/hi.po index 17048b1a6d..b2a4bccafe 100644 --- a/locale/hi.po +++ b/locale/hi.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: Automatically generated\n" "Language-Team: none\n" @@ -959,6 +959,10 @@ msgstr "" msgid "Invalid BMP file" msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "" diff --git a/locale/it_IT.po b/locale/it_IT.po index b190f976b6..146e4ced14 100644 --- a/locale/it_IT.po +++ b/locale/it_IT.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2018-10-02 16:27+0200\n" "Last-Translator: Enrico Paganin \n" "Language-Team: \n" @@ -974,6 +974,10 @@ msgstr "" msgid "Invalid BMP file" msgstr "File BMP non valido" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "" diff --git a/locale/ja.po b/locale/ja.po index 0f9bd3be60..cd0ae7b50f 100644 --- a/locale/ja.po +++ b/locale/ja.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-09-01 18:44+0000\n" "Last-Translator: Jeff Epler \n" "Language-Team: none\n" @@ -975,6 +975,10 @@ msgstr "不正なADCユニット値" msgid "Invalid BMP file" msgstr "不正なBMPファイル" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "不正なDACピンが与えられました" diff --git a/locale/ko.po b/locale/ko.po index 0bdf7c742d..4072553a60 100644 --- a/locale/ko.po +++ b/locale/ko.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2019-05-06 14:22-0700\n" "Last-Translator: \n" "Language-Team: LANGUAGE \n" @@ -962,6 +962,10 @@ msgstr "" msgid "Invalid BMP file" msgstr "" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "" diff --git a/locale/nl.po b/locale/nl.po index e0b4d8793a..d74a2e07d0 100644 --- a/locale/nl.po +++ b/locale/nl.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-09-09 16:05+0000\n" "Last-Translator: Jelle Jager \n" "Language-Team: none\n" @@ -976,6 +976,10 @@ msgstr "Ongeldige ADC Unit waarde" msgid "Invalid BMP file" msgstr "Ongeldig BMP bestand" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "Ongeldige DAC pin opgegeven" diff --git a/locale/pl.po b/locale/pl.po index 1dc55ad825..2528b25e6f 100644 --- a/locale/pl.po +++ b/locale/pl.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-09-17 17:58+0000\n" "Last-Translator: Maciej Stankiewicz \n" "Language-Team: pl\n" @@ -971,6 +971,10 @@ msgstr "" msgid "Invalid BMP file" msgstr "Zły BMP" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "" diff --git a/locale/pt_BR.po b/locale/pt_BR.po index e3f8fee72b..bff8ff948f 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-09-17 17:58+0000\n" "Last-Translator: Wellington Terumi Uemura \n" "Language-Team: \n" @@ -985,6 +985,10 @@ msgstr "Valor inválido da unidade ADC" msgid "Invalid BMP file" msgstr "Arquivo BMP inválido" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "O pino DAC informado é inválido" diff --git a/locale/sv.po b/locale/sv.po index 8774e0734c..a88c91b532 100644 --- a/locale/sv.po +++ b/locale/sv.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2020-09-07 19:36+0000\n" "Last-Translator: Jonny Bergdahl \n" "Language-Team: LANGUAGE \n" @@ -974,6 +974,10 @@ msgstr "Ogiltigt ADC-enhetsvärde" msgid "Invalid BMP file" msgstr "Ogiltig BMP-fil" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "Ogiltig DAC-pinne angiven" diff --git a/locale/zh_Latn_pinyin.po b/locale/zh_Latn_pinyin.po index fe49abaf25..de19d2b602 100644 --- a/locale/zh_Latn_pinyin.po +++ b/locale/zh_Latn_pinyin.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: circuitpython-cn\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-09-11 13:30+0200\n" +"POT-Creation-Date: 2020-09-16 17:07-0700\n" "PO-Revision-Date: 2019-04-13 10:10-0700\n" "Last-Translator: hexthat\n" "Language-Team: Chinese Hanyu Pinyin\n" @@ -971,6 +971,10 @@ msgstr "Wúxiào de ADC dānwèi zhí" msgid "Invalid BMP file" msgstr "Wúxiào de BMP wénjiàn" +#: shared-bindings/wifi/Radio.c +msgid "Invalid BSSID" +msgstr "" + #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" msgstr "Tí gōng liǎo wúxiào de DAC yǐn jiǎo" From 54001079f7872047f06e1363b8b82436c172eb8a Mon Sep 17 00:00:00 2001 From: Wellington Terumi Uemura Date: Sat, 19 Sep 2020 05:02:16 +0000 Subject: [PATCH 88/91] Translated using Weblate (Portuguese (Brazil)) Currently translated at 100.0% (800 of 800 strings) Translation: CircuitPython/main Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/pt_BR/ --- locale/pt_BR.po | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/locale/pt_BR.po b/locale/pt_BR.po index bff8ff948f..2574786db8 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -6,7 +6,7 @@ msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2020-09-16 17:07-0700\n" -"PO-Revision-Date: 2020-09-17 17:58+0000\n" +"PO-Revision-Date: 2020-09-19 17:41+0000\n" "Last-Translator: Wellington Terumi Uemura \n" "Language-Team: \n" "Language: pt_BR\n" @@ -987,7 +987,7 @@ msgstr "Arquivo BMP inválido" #: shared-bindings/wifi/Radio.c msgid "Invalid BSSID" -msgstr "" +msgstr "BSSID Inválido" #: ports/stm/common-hal/analogio/AnalogOut.c msgid "Invalid DAC pin supplied" From 40ec7a66e424c37da7556bdea303a4e5da30985c Mon Sep 17 00:00:00 2001 From: microDev <70126934+microDev1@users.noreply.github.com> Date: Mon, 21 Sep 2020 14:39:31 +0530 Subject: [PATCH 89/91] Update microS2 config files --- .../boards/microdev_micro_s2/mpconfigboard.h | 3 ++- .../boards/microdev_micro_s2/mpconfigboard.mk | 1 + ports/esp32s2/boards/microdev_micro_s2/pins.c | 21 ++++++++++++++++++- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h b/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h index 1a1ef7a6c7..c138c8ed15 100644 --- a/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h +++ b/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h @@ -26,10 +26,11 @@ //Micropython setup -#define MICROPY_HW_BOARD_NAME "microDev microS2" +#define MICROPY_HW_BOARD_NAME "microS2" #define MICROPY_HW_MCU_NAME "ESP32S2" #define MICROPY_HW_LED (&pin_GPIO21) +#define MICROPY_HW_BUTTON (&pin_GPIO0) #define MICROPY_HW_NEOPIXEL (&pin_GPIO33) #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0) diff --git a/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.mk b/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.mk index 783e7ad4c7..5156170957 100644 --- a/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.mk +++ b/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.mk @@ -2,6 +2,7 @@ USB_VID = 0x239A USB_PID = 0x80C6 USB_PRODUCT = "microS2" USB_MANUFACTURER = "microDev" +USB_DEVICES = "CDC,MSC,HID" INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = MPZ diff --git a/ports/esp32s2/boards/microdev_micro_s2/pins.c b/ports/esp32s2/boards/microdev_micro_s2/pins.c index 25300b5c3c..bd230ed38f 100644 --- a/ports/esp32s2/boards/microdev_micro_s2/pins.c +++ b/ports/esp32s2/boards/microdev_micro_s2/pins.c @@ -42,8 +42,27 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO43) }, { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO44) }, - { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO21) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO1) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO2) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO36) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO35) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO37) }, + + { MP_ROM_QSTR(MP_QSTR_MTCK), MP_ROM_PTR(&pin_GPIO39) }, + { MP_ROM_QSTR(MP_QSTR_MTDO), MP_ROM_PTR(&pin_GPIO40) }, + { MP_ROM_QSTR(MP_QSTR_MTDI), MP_ROM_PTR(&pin_GPIO41) }, + { MP_ROM_QSTR(MP_QSTR_MTMS), MP_ROM_PTR(&pin_GPIO42) }, + + { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_GPIO17) }, + { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_GPIO18) }, + + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO21) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_GPIO0) }, { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO33) }, + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); From 0318eb359fbeb91c6b37ed2050e57711ec2740bc Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Mon, 21 Sep 2020 10:02:27 -0500 Subject: [PATCH 90/91] makeqstrdata: Work around python3.6 compatibility problem Discord user Folknology encountered a problem building with Python 3.6.9, `TypeError: ord() expected a character, but string of length 0 found`. I was able to reproduce the problem using Python3.5*, and discovered that the meaning of the regular expression `"|."` had changed in 3.7. Before, ``` >>> [m.group(0) for m in re.finditer("|.", "hello")] ['', '', '', '', '', ''] ``` After: ``` >>> [m.group(0) for m in re.finditer("|.", "hello")] ['', 'h', '', 'e', '', 'l', '', 'l', '', 'o', ''] ``` Check if `words` is empty and if so use `"."` as the regular expression instead. This gives the same result on both versions: ``` ['h', 'e', 'l', 'l', 'o'] ``` and fixes the generation of the huffman dictionary. Folknology verified that this fix worked for them. * I could easily install 3.5 but not 3.6. 3.5 reproduced the same problem --- py/makeqstrdata.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/py/makeqstrdata.py b/py/makeqstrdata.py index 96e3956b42..b4f4f1b035 100644 --- a/py/makeqstrdata.py +++ b/py/makeqstrdata.py @@ -109,7 +109,11 @@ class TextSplitter: def __init__(self, words): words.sort(key=lambda x: len(x), reverse=True) self.words = set(words) - self.pat = re.compile("|".join(re.escape(w) for w in words) + "|.", flags=re.DOTALL) + if words: + pat = "|".join(re.escape(w) for w in words) + "|." + else: + pat = "." + self.pat = re.compile(pat, flags=re.DOTALL) def iter_words(self, text): s = [] From add230b4da7c32c1b6fee3a328ccb8eebede42c5 Mon Sep 17 00:00:00 2001 From: microDev <70126934+microDev1@users.noreply.github.com> Date: Tue, 22 Sep 2020 11:37:12 +0530 Subject: [PATCH 91/91] Update port.c --- ports/esp32s2/supervisor/port.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/ports/esp32s2/supervisor/port.c b/ports/esp32s2/supervisor/port.c index e52b7f3762..3de63278dc 100644 --- a/ports/esp32s2/supervisor/port.c +++ b/ports/esp32s2/supervisor/port.c @@ -43,6 +43,7 @@ #include "common-hal/wifi/__init__.h" #include "supervisor/memory.h" #include "supervisor/shared/tick.h" +#include "shared-bindings/rtc/__init__.h" #include "peripherals/rmt.h" #include "esp-idf/components/heap/include/esp_heap_caps.h" @@ -106,6 +107,11 @@ void reset_port(void) { spi_reset(); uart_reset(); #endif + +#if CIRCUITPY_RTC + rtc_reset(); +#endif + #if CIRCUITPY_WIFI wifi_reset(); #endif