lcd_ev: add timings; rename TFT -> TFT_PINS
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4c682262e6
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@ -39,7 +39,7 @@ STATIC const mp_rom_obj_tuple_t tft_b_pins = {
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}
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};
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STATIC const mp_rom_map_elem_t tft_table[] = {
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STATIC const mp_rom_map_elem_t tft_pins_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_de), MP_ROM_PTR(&pin_GPIO17) },
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{ MP_ROM_QSTR(MP_QSTR_vsync), MP_ROM_PTR(&pin_GPIO3) },
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{ MP_ROM_QSTR(MP_QSTR_hsync), MP_ROM_PTR(&pin_GPIO46) },
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@ -48,12 +48,31 @@ STATIC const mp_rom_map_elem_t tft_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_green), MP_ROM_PTR(&tft_g_pins) },
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{ MP_ROM_QSTR(MP_QSTR_blue), MP_ROM_PTR(&tft_b_pins) },
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};
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MP_DEFINE_CONST_DICT(tft_dict, tft_table);
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MP_DEFINE_CONST_DICT(tft_pins_dict, tft_pins_table);
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STATIC const mp_rom_map_elem_t tft_timings_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_frequency), MP_ROM_INT(6500000) }, // nominal 16MHz, but display is unstable/tears at that frequency
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{ MP_ROM_QSTR(MP_QSTR_width), MP_ROM_INT(480) },
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{ MP_ROM_QSTR(MP_QSTR_height), MP_ROM_INT(480) },
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{ MP_ROM_QSTR(MP_QSTR_hsync_pulse_width), MP_ROM_INT(13) },
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{ MP_ROM_QSTR(MP_QSTR_hsync_front_porch), MP_ROM_INT(20) },
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{ MP_ROM_QSTR(MP_QSTR_hsync_back_porch), MP_ROM_INT(40) },
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{ MP_ROM_QSTR(MP_QSTR_hsync_idle_low), MP_ROM_FALSE },
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{ MP_ROM_QSTR(MP_QSTR_vsync_pulse_width), MP_ROM_INT(15) },
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{ MP_ROM_QSTR(MP_QSTR_vsync_front_porch), MP_ROM_INT(20) },
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{ MP_ROM_QSTR(MP_QSTR_vsync_back_porch), MP_ROM_INT(40) },
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{ MP_ROM_QSTR(MP_QSTR_vsync_idle_low), MP_ROM_FALSE },
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{ MP_ROM_QSTR(MP_QSTR_de_idle_high), MP_ROM_FALSE },
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{ MP_ROM_QSTR(MP_QSTR_pclk_active_high), MP_ROM_FALSE },
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{ MP_ROM_QSTR(MP_QSTR_pclk_idle_high), MP_ROM_FALSE },
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};
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MP_DEFINE_CONST_DICT(tft_timings_dict, tft_timings_table);
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STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
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CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
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{ MP_ROM_QSTR(MP_QSTR_TFT), MP_ROM_PTR(&tft_dict) },
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{ MP_ROM_QSTR(MP_QSTR_TFT_PINS), MP_ROM_PTR(&tft_pins_dict) },
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{ MP_ROM_QSTR(MP_QSTR_TFT_TIMINGS), MP_ROM_PTR(&tft_timings_dict) },
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{ MP_ROM_QSTR(MP_QSTR_I2S_SCK), MP_ROM_PTR(&pin_GPIO16) },
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{ MP_ROM_QSTR(MP_QSTR_I2S_MCLK), MP_ROM_PTR(&pin_GPIO5) },
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