djsundog
/
circuitpython
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

stm32/boards/NUCLEO_F767ZI: Fix up comments about HCLK computation.

This commit is contained in:
Damien George 2019-02-22 21:53:07 +11:00
parent 9521399044
commit 75a35448e1
1 changed files with 2 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
ports/stm32/boards/NUCLEO_F767ZI/mpconfigboard.h
View File

@ -16,20 +16,12 @@
#define MICROPY_BOARD_EARLY_INIT NUCLEO_F767ZI_board_early_init #define MICROPY_BOARD_EARLY_INIT NUCLEO_F767ZI_board_early_init
void NUCLEO_F767ZI_board_early_init(void); void NUCLEO_F767ZI_board_early_init(void);
// HSE is 25MHz // HSE is 8MHz
// VCOClock = HSE * PLLN / PLLM = 25 MHz * 432 / 25 = 432 MHz
// SYSCLK = VCOClock / PLLP = 432 MHz / 2 = 216 MHz
// USB/SDMMC/RNG Clock = VCOClock / PLLQ = 432 MHz / 9 = 48 MHz
#define MICROPY_HW_CLK_PLLM (4) #define MICROPY_HW_CLK_PLLM (4)
#define MICROPY_HW_CLK_PLLN (216) #define MICROPY_HW_CLK_PLLN (216)
#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2) #define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
#define MICROPY_HW_CLK_PLLQ (9) #define MICROPY_HW_CLK_PLLQ (9)
#define MICROPY_HW_FLASH_LATENCY (FLASH_LATENCY_7) // 210-216 MHz needs 7 wait states
// From the reference manual, for 2.7V to 3.6V
// 151-180 MHz => 5 wait states
// 181-210 MHz => 6 wait states
// 211-216 MHz => 7 wait states
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_7 // 210-216 MHz needs 7 wait states
// UART config // UART config
#define MICROPY_HW_UART2_TX (pin_D5) #define MICROPY_HW_UART2_TX (pin_D5)