From 73299ae48c49c71592337e7fddcb3979e5015611 Mon Sep 17 00:00:00 2001 From: Christopher Hoover Date: Sun, 21 May 2023 17:42:30 -0700 Subject: [PATCH] Adds new board for MIMRT1060-EVKB (not to be confused with MIMRT1060-EVK). --- .../mimxrt10xx/boards/imxrt1060_evkb/board.c | 58 +++++++ .../boards/imxrt1060_evkb/flash_config.c | 143 ++++++++++++++++++ .../boards/imxrt1060_evkb/mpconfigboard.h | 25 +++ .../boards/imxrt1060_evkb/mpconfigboard.mk | 10 ++ ports/mimxrt10xx/boards/imxrt1060_evkb/pins.c | 140 +++++++++++++++++ 5 files changed, 376 insertions(+) create mode 100644 ports/mimxrt10xx/boards/imxrt1060_evkb/board.c create mode 100644 ports/mimxrt10xx/boards/imxrt1060_evkb/flash_config.c create mode 100644 ports/mimxrt10xx/boards/imxrt1060_evkb/mpconfigboard.h create mode 100644 ports/mimxrt10xx/boards/imxrt1060_evkb/mpconfigboard.mk create mode 100644 ports/mimxrt10xx/boards/imxrt1060_evkb/pins.c diff --git a/ports/mimxrt10xx/boards/imxrt1060_evkb/board.c b/ports/mimxrt10xx/boards/imxrt1060_evkb/board.c new file mode 100644 index 0000000000..4a2e6e0913 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evkb/board.c @@ -0,0 +1,58 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2019 Artur Pacholec + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "supervisor/board.h" +#include "shared-bindings/microcontroller/Pin.h" + +// These pins should never ever be reset; doing so could interfere with basic operation. +// Used in common-hal/microcontroller/Pin.c +const mcu_pin_obj_t *mimxrt10xx_reset_forbidden_pins[] = { + // SWD Pins + &pin_GPIO_AD_B0_06, // SWDIO + &pin_GPIO_AD_B0_07, // SWCLK + + // FLEX flash + &pin_GPIO_SD_B1_00, + &pin_GPIO_SD_B1_01, + &pin_GPIO_SD_B1_02, + &pin_GPIO_SD_B1_03, + &pin_GPIO_SD_B1_04, + &pin_GPIO_SD_B1_05, + &pin_GPIO_SD_B1_06, + &pin_GPIO_SD_B1_07, + &pin_GPIO_SD_B1_08, + &pin_GPIO_SD_B1_09, + &pin_GPIO_SD_B1_10, + &pin_GPIO_SD_B1_11, + + // USB Pins + &pin_GPIO_AD_B0_01, // ID Pin + &pin_GPIO_AD_B0_03, // OC/Fault Pin + NULL, // Must end in NULL. +}; + +// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here. diff --git a/ports/mimxrt10xx/boards/imxrt1060_evkb/flash_config.c b/ports/mimxrt10xx/boards/imxrt1060_evkb/flash_config.c new file mode 100644 index 0000000000..c75174d1c4 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evkb/flash_config.c @@ -0,0 +1,143 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "boards/flash_config.h" + +#include "xip/fsl_flexspi_nor_boot.h" + +// Config for IS25WP064A with QSPI routed. +__attribute__((section(".boot_hdr.conf"))) +const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x40, + .deviceType = kFLEXSPIDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFLEXSPISerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + { + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE + }, + }, +}; diff --git a/ports/mimxrt10xx/boards/imxrt1060_evkb/mpconfigboard.h b/ports/mimxrt10xx/boards/imxrt1060_evkb/mpconfigboard.h new file mode 100644 index 0000000000..8f439080cb --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evkb/mpconfigboard.h @@ -0,0 +1,25 @@ +#define MICROPY_HW_BOARD_NAME "iMX RT 1060 EVKB" +#define MICROPY_HW_MCU_NAME "IMXRT1062DVJ6A" + +// If you change this, then make sure to update the linker scripts as well to +// make sure you don't overwrite code +#define CIRCUITPY_INTERNAL_NVM_SIZE 0 + +#define BOARD_FLASH_SIZE (8 * 1024 * 1024) + +#define MICROPY_HW_LED_STATUS (&pin_GPIO_AD_B0_08) +#define MICROPY_HW_LED_STATUS_INVERTED (1) + +#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_00) +#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_01) + +#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B1_07) +#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B1_06) + +#define CIRCUITPY_CONSOLE_UART_TX (&pin_GPIO_AD_B0_12) +#define CIRCUITPY_CONSOLE_UART_RX (&pin_GPIO_AD_B0_13) + +// Put host on the first USB so that right angle OTG adapters can fit. This is +// the right port when looking at the board. +#define CIRCUITPY_USB_DEVICE_INSTANCE 1 +#define CIRCUITPY_USB_HOST_INSTANCE 0 diff --git a/ports/mimxrt10xx/boards/imxrt1060_evkb/mpconfigboard.mk b/ports/mimxrt10xx/boards/imxrt1060_evkb/mpconfigboard.mk new file mode 100644 index 0000000000..c70865ebd6 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evkb/mpconfigboard.mk @@ -0,0 +1,10 @@ +USB_VID = 0x239A +USB_PID = 0x8084 +USB_PRODUCT = "iMX RT 1060 EVKB" +USB_MANUFACTURER = "NXP" + +CHIP_VARIANT = MIMXRT1062DVJ6A +CHIP_FAMILY = MIMXRT1062 +FLASH = IS25WP064A + +CIRCUITPY_USB_HOST = 1 diff --git a/ports/mimxrt10xx/boards/imxrt1060_evkb/pins.c b/ports/mimxrt10xx/boards/imxrt1060_evkb/pins.c new file mode 100644 index 0000000000..f19b24db37 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evkb/pins.c @@ -0,0 +1,140 @@ +#include "shared-bindings/board/__init__.h" + +#include "supervisor/board.h" + +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { + CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS + + { MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B1_07) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B1_07) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B1_06) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B1_06) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_B0_11) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_B1_08) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_AD_B0_09) }, // Connected to audio codec + { MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_AD_B0_10) }, // Connected to audio codec + { MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_03) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_AD_B0_03) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_AD_B0_02) }, // Connected to audio codec + { MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_SD_B0_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_SD_B0_02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_SD_B0_03) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_SD_B0_00) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_00) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00) }, + + // i2c sensor is on I2C1_SCL/SDA + + { MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_10) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_11) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_04) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_05) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_00) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_08) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_08) }, + + // Camera Sensor Interface + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_VSYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_06) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_PWDN), MP_ROM_PTR(&pin_GPIO_AD_B1_02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_HSYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_07) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D9), MP_ROM_PTR(&pin_GPIO_AD_B1_08) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_05) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D8), MP_ROM_PTR(&pin_GPIO_AD_B1_09) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_10) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_PIXCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_04) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_11) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D2), MP_ROM_PTR(&pin_GPIO_AD_B1_15) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D5), MP_ROM_PTR(&pin_GPIO_AD_B1_12) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D3), MP_ROM_PTR(&pin_GPIO_AD_B1_14) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D4), MP_ROM_PTR(&pin_GPIO_AD_B1_13) }, + + // SD Card + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_GPIO_B1_12) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_GPIO_SD_B0_02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_GPIO_SD_B0_03) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_GPIO_SD_B0_04) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_GPIO_SD_B0_05) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_PWREN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) }, + + // LCD Interface + { MP_ROM_QSTR(MP_QSTR_LCD_BACKLIGHT), MP_ROM_PTR(&pin_GPIO_B1_15) }, + { MP_ROM_QSTR(MP_QSTR_LCD_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_02) }, + { MP_ROM_QSTR(MP_QSTR_LCD_ENABLE), MP_ROM_PTR(&pin_GPIO_B0_01) }, + { MP_ROM_QSTR(MP_QSTR_LCD_VSYNC), MP_ROM_PTR(&pin_GPIO_B0_03) }, + { MP_ROM_QSTR(MP_QSTR_LCD_HSYNC), MP_ROM_PTR(&pin_GPIO_B0_02) }, + { MP_ROM_QSTR(MP_QSTR_LCD_CLK), MP_ROM_PTR(&pin_GPIO_B0_00) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D0), MP_ROM_PTR(&pin_GPIO_B0_04) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D1), MP_ROM_PTR(&pin_GPIO_B0_05) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D2), MP_ROM_PTR(&pin_GPIO_B0_06) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D3), MP_ROM_PTR(&pin_GPIO_B0_07) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D4), MP_ROM_PTR(&pin_GPIO_B0_08) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D5), MP_ROM_PTR(&pin_GPIO_B0_09) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D6), MP_ROM_PTR(&pin_GPIO_B0_10) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D7), MP_ROM_PTR(&pin_GPIO_B0_11) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D8), MP_ROM_PTR(&pin_GPIO_B0_12) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D9), MP_ROM_PTR(&pin_GPIO_B0_13) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D10), MP_ROM_PTR(&pin_GPIO_B0_14) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D11), MP_ROM_PTR(&pin_GPIO_B0_15) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D12), MP_ROM_PTR(&pin_GPIO_B1_00) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D13), MP_ROM_PTR(&pin_GPIO_B1_01) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D14), MP_ROM_PTR(&pin_GPIO_B1_02) }, + { MP_ROM_QSTR(MP_QSTR_LCD_D15), MP_ROM_PTR(&pin_GPIO_B1_03) }, + + // Touch Interface + { MP_ROM_QSTR(MP_QSTR_LCD_TOUCH_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_11) }, + + // Audio Interface + { MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_AD_B1_08) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_SYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_15) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_14) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_AD_B1_12) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_AD_B1_13) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_09) }, + + // SPDIF + { MP_ROM_QSTR(MP_QSTR_SPDIF_IN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) }, + { MP_ROM_QSTR(MP_QSTR_SPDIF_OUT), MP_ROM_PTR(&pin_GPIO_AD_B1_02) }, + + // Ethernet + { MP_ROM_QSTR(MP_QSTR_ETHERNET_MDIO), MP_ROM_PTR(&pin_GPIO_EMC_41) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_MDC), MP_ROM_PTR(&pin_GPIO_EMC_40) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD0), MP_ROM_PTR(&pin_GPIO_B1_04) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD1), MP_ROM_PTR(&pin_GPIO_B1_05) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_CRS_DV), MP_ROM_PTR(&pin_GPIO_B1_06) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD0), MP_ROM_PTR(&pin_GPIO_B1_07) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD1), MP_ROM_PTR(&pin_GPIO_B1_08) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_TXEN), MP_ROM_PTR(&pin_GPIO_B1_09) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_10) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_09) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_CLK), MP_ROM_PTR(&pin_GPIO_B1_10) }, + { MP_ROM_QSTR(MP_QSTR_ETHERNET_RXER), MP_ROM_PTR(&pin_GPIO_B1_11) }, + + // Freelink UART + { MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_12) }, + { MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_13) }, + + // CAN + { MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_14) }, + { MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_15) }, + { MP_ROM_QSTR(MP_QSTR_CAN_STBY), MP_ROM_PTR(&pin_GPIO_AD_B0_05) }, + + // USB + #if CIRCUITPY_USB_HOST_INSTANCE == 0 + { MP_ROM_QSTR(MP_QSTR_USB_HOST_DP), MP_ROM_PTR(&pin_USB_OTG1_DP) }, + { MP_ROM_QSTR(MP_QSTR_USB_HOST_DM), MP_ROM_PTR(&pin_USB_OTG1_DN) }, + #elif CIRCUITPY_USB_HOST_INSTANCE == 1 + { MP_ROM_QSTR(MP_QSTR_USB_HOST_DP), MP_ROM_PTR(&pin_USB_OTG2_DP) }, + { MP_ROM_QSTR(MP_QSTR_USB_HOST_DM), MP_ROM_PTR(&pin_USB_OTG2_DN) }, + #endif + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);