corrected pre-commit errors
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60e330fb0d
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716497c132
@ -2149,6 +2149,10 @@ msgstr ""
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msgid "Set pin count must be between 1 and 5"
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msgstr ""
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#: shared-bindings/microcontroller/Processor.c
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msgid "Settable Clock Not Implemented for Your Board"
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msgstr ""
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#: ports/raspberrypi/bindings/rp2pio/StateMachine.c
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msgid "Side set pin count must be between 1 and 5"
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msgstr ""
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@ -3019,7 +3023,7 @@ msgstr ""
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msgid "complex values not supported"
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msgstr ""
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#: extmod/moduzlib.c shared-module/zlib/DecompIO.c
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#: extmod/moduzlib.c
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msgid "compression header"
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msgstr ""
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@ -25,7 +25,7 @@
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* THE SOFTWARE.
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*/
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//https://raw.githubusercontent.com/adafruit/circuitpython/main/ports/mimxrt10xx/common-hal/microcontroller/Processor.c
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// https://raw.githubusercontent.com/adafruit/circuitpython/main/ports/mimxrt10xx/common-hal/microcontroller/Processor.c
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#include <math.h>
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@ -359,7 +359,7 @@ void clocks_init(void) {
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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//Note setarmclock is a port from Teensyduino for the Teensy 4.x written by Paul Stroffgren,
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// Note setarmclock is a port from Teensyduino for the Teensy 4.x written by Paul Stroffgren,
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// A brief explanation of F_CPU_ACTUAL vs F_CPU
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// https://forum.pjrc.com/threads/57236?p=212642&viewfull=1#post212642
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volatile uint32_t F_CPU_ACTUAL = 396000000;
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@ -375,20 +375,20 @@ volatile uint32_t F_BUS_ACTUAL = 132000000;
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#define DCDC_REG3 0x40080012
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#define DCDC_REG0 0x40080000
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#define DCDC_REG0_STS_DC_OK_L ((uint32_t)(1<<31))
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#define CCM_ANALOG_PLL_USB1_ENABLE_L ((uint32_t)(1<<13))
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#define CCM_ANALOG_PLL_USB1_POWER_L ((uint32_t)(1<<12))
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#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_L ((uint32_t)(1<<6))
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#define CCM_ANALOG_PLL_USB1_LOCK_L ((uint32_t)(1<<31))
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#define DCDC_REG0_STS_DC_OK_L ((uint32_t)(1 << 31))
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#define CCM_ANALOG_PLL_USB1_ENABLE_L ((uint32_t)(1 << 13))
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#define CCM_ANALOG_PLL_USB1_POWER_L ((uint32_t)(1 << 12))
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#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_L ((uint32_t)(1 << 6))
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#define CCM_ANALOG_PLL_USB1_LOCK_L ((uint32_t)(1 << 31))
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#define CCM_CCGR6_DCDC(n) ((uint32_t)(((n) & 0x03) << 6))
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#define CCM_ANALOG_PLL_ARM_LOCK_L ((uint32_t)(1<<31))
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#define CCM_ANALOG_PLL_ARM_BYPASS_L ((uint32_t)(1<<16))
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#define CCM_ANALOG_PLL_ARM_ENABLE_L ((uint32_t)(1<<13))
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#define CCM_ANALOG_PLL_ARM_POWERDOWN_L ((uint32_t)(1<<12))
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#define CCM_CDHIPR_ARM_PODF_BUSY_L ((uint32_t)(1<<16))
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#define CCM_CDHIPR_AHB_PODF_BUSY_L ((uint32_t)(1<<1))
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#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L ((uint32_t)(1<<5))
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#define CCM_CBCDR_PERIPH_CLK_SEL_L ((uint32_t)(1<<25))
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#define CCM_ANALOG_PLL_ARM_LOCK_L ((uint32_t)(1 << 31))
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#define CCM_ANALOG_PLL_ARM_BYPASS_L ((uint32_t)(1 << 16))
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#define CCM_ANALOG_PLL_ARM_ENABLE_L ((uint32_t)(1 << 13))
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#define CCM_ANALOG_PLL_ARM_POWERDOWN_L ((uint32_t)(1 << 12))
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#define CCM_CDHIPR_ARM_PODF_BUSY_L ((uint32_t)(1 << 16))
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#define CCM_CDHIPR_AHB_PODF_BUSY_L ((uint32_t)(1 << 1))
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#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L ((uint32_t)(1 << 5))
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#define CCM_CBCDR_PERIPH_CLK_SEL_L ((uint32_t)(1 << 25))
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#define CCM_CCGR_OFF 0
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#define CCM_CCGR_ON_RUNONLY 1
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#define CCM_CCGR_ON 3
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@ -423,7 +423,7 @@ volatile uint32_t F_BUS_ACTUAL = 132000000;
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* SOFTWARE.
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*/
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//uint32_t set_arm_clock(uint32_t frequency);
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// uint32_t set_arm_clock(uint32_t frequency);
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// stuff needing wait handshake:
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// CCM_CACRR ARM_PODF
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@ -432,8 +432,7 @@ volatile uint32_t F_BUS_ACTUAL = 132000000;
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// CCM_CBCDR AHB_PODF
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// CCM_CBCDR SEMC_PODF
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uint32_t setarmclock(uint32_t frequency)
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{
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uint32_t setarmclock(uint32_t frequency) {
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uint32_t cbcdr = CCM->CBCDR; // pg 1021
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uint32_t cbcmr = CCM->CBCMR; // pg 1023
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uint32_t dcdc = DCDC->REG3;
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@ -442,12 +441,14 @@ uint32_t setarmclock(uint32_t frequency)
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uint32_t voltage = 1150; // default = 1.15V
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if (frequency > 528000000) {
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voltage = 1250; // 1.25V
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#if defined(OVERCLOCK_STEPSIZE) && defined(OVERCLOCK_MAX_VOLT)
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#if defined(OVERCLOCK_STEPSIZE) && defined(OVERCLOCK_MAX_VOLT)
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if (frequency > 600000000) {
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voltage += ((frequency - 600000000) / OVERCLOCK_STEPSIZE) * 25;
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if (voltage > OVERCLOCK_MAX_VOLT) voltage = OVERCLOCK_MAX_VOLT;
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if (voltage > OVERCLOCK_MAX_VOLT) {
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voltage = OVERCLOCK_MAX_VOLT;
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}
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#endif
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}
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#endif
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} else if (frequency <= 24000000) {
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voltage = 950; // 0.95
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}
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@ -455,24 +456,26 @@ uint32_t setarmclock(uint32_t frequency)
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// if voltage needs to increase, do it before switch clock speed
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CCM->CCGR6 |= CCM_CCGR6_DCDC(CCM_CCGR_ON);
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if ((dcdc & ((uint32_t)(0x1F << 0))) < ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0)) {
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//printf("Increasing voltage to %u mV\n", voltage);
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// printf("Increasing voltage to %u mV\n", voltage);
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dcdc &= ~((uint32_t)(0x1F << 0));
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dcdc |= ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0);
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DCDC->REG3 = dcdc;
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while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) ; // wait voltage settling
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while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) {
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; // wait voltage settling
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}
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}
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if (!(cbcdr & CCM_CBCDR_PERIPH_CLK_SEL_L)) {
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//printf("need to switch to alternate clock during reconfigure of ARM PLL\n");
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// printf("need to switch to alternate clock during reconfigure of ARM PLL\n");
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const uint32_t need1s = CCM_ANALOG_PLL_USB1_ENABLE_L | CCM_ANALOG_PLL_USB1_POWER_L |
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CCM_ANALOG_PLL_USB1_LOCK_L | CCM_ANALOG_PLL_USB1_EN_USB_CLKS_L;
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uint32_t sel, div;
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if ((CCM_ANALOG->PLL_USB1 & need1s) == need1s) {
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//printf("USB PLL is running, so we can use 120 MHz\n");
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// printf("USB PLL is running, so we can use 120 MHz\n");
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sel = 0;
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div = 3; // divide down to 120 MHz, so IPG is ok even if IPG_PODF=0
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} else {
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//printf("USB PLL is off, use 24 MHz crystal\n");
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// printf("USB PLL is off, use 24 MHz crystal\n");
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sel = 1;
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div = 0;
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}
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@ -487,14 +490,18 @@ uint32_t setarmclock(uint32_t frequency)
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cbcmr &= ~((uint32_t)(0x03 << 12));
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cbcmr |= CCM_CBCMR_PERIPH_CLK2_SEL(sel);
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CCM->CBCMR = cbcmr;
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while (CCM->CDHIPR & ((uint32_t)(1<<3))) ; // wait
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while (CCM->CDHIPR & ((uint32_t)(1 << 3))) {
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; // wait
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}
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}
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// switch over to PERIPH_CLK2
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cbcdr |= ((uint32_t)(1<<25));
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cbcdr |= ((uint32_t)(1 << 25));
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CCM->CBCDR = cbcdr;
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while (CCM->CDHIPR & ((uint32_t)(1<<5))) ; // wait
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while (CCM->CDHIPR & ((uint32_t)(1 << 5))) {
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; // wait
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}
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} else {
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//printf("already running from PERIPH_CLK2, safe to mess with ARM PLL\n");
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// printf("already running from PERIPH_CLK2, safe to mess with ARM PLL\n");
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}
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// TODO: check if PLL2 running, can 352, 396 or 528 can work? (no need for ARM PLL)
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@ -515,42 +522,54 @@ uint32_t setarmclock(uint32_t frequency)
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}
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}
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uint32_t mult = (frequency * div_arm * div_ahb + 6000000) / 12000000;
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if (mult > 108) mult = 108;
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if (mult < 54) mult = 54;
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//printf("Freq: 12 MHz * %u / %u / %u\n", mult, div_arm, div_ahb);
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if (mult > 108) {
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mult = 108;
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}
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if (mult < 54) {
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mult = 54;
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}
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// printf("Freq: 12 MHz * %u / %u / %u\n", mult, div_arm, div_ahb);
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frequency = mult * 12000000 / div_arm / div_ahb;
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//printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM);
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// printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM);
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const uint32_t arm_pll_mask = CCM_ANALOG_PLL_ARM_LOCK_L | CCM_ANALOG_PLL_ARM_BYPASS_L |
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CCM_ANALOG_PLL_ARM_ENABLE_L | CCM_ANALOG_PLL_ARM_POWERDOWN_L |
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CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK;
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if ((CCM_ANALOG->PLL_ARM & arm_pll_mask) != (CCM_ANALOG_PLL_ARM_LOCK_L
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| CCM_ANALOG_PLL_ARM_ENABLE_L | CCM_ANALOG_PLL_ARM_DIV_SELECT(mult))) {
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//printf("ARM PLL needs reconfigure\n");
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// printf("ARM PLL needs reconfigure\n");
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CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_L;
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// TODO: delay needed?
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CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_L
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| CCM_ANALOG_PLL_ARM_DIV_SELECT(mult);
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while (!(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_L)) ; // wait for lock
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//printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM);
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while (!(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_L)) {
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; // wait for lock
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}
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// printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM);
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} else {
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//printf("ARM PLL already running at required frequency\n");
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// printf("ARM PLL already running at required frequency\n");
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}
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if ((CCM->CACRR & ((uint32_t)(0x07 << 0))) != (div_arm - 1)) {
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CCM->CACRR = CCM_CACRR_ARM_PODF(div_arm - 1);
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while (CCM->CDHIPR & CCM_CDHIPR_ARM_PODF_BUSY_L) ; // wait
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while (CCM->CDHIPR & CCM_CDHIPR_ARM_PODF_BUSY_L) {
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; // wait
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}
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}
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if ((cbcdr & ((uint32_t)(0x07 << 10))) != CCM_CBCDR_AHB_PODF(div_ahb - 1)) {
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cbcdr &= ~((uint32_t)(0x07 << 10));
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cbcdr |= CCM_CBCDR_AHB_PODF(div_ahb - 1);
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CCM->CBCDR = cbcdr;
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while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_L); // wait
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while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_L) {
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; // wait
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}
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}
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uint32_t div_ipg = (frequency + 149999999) / 150000000;
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if (div_ipg > 4) div_ipg = 4;
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if (div_ipg > 4) {
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div_ipg = 4;
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}
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if ((cbcdr & ((uint32_t)(0x03 << 8))) != (CCM_CBCDR_IPG_PODF(div_ipg - 1))) {
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cbcdr &= ~((uint32_t)(0x03 << 8));
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cbcdr |= CCM_CBCDR_IPG_PODF(div_ipg - 1);
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@ -558,24 +577,28 @@ uint32_t setarmclock(uint32_t frequency)
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CCM->CBCDR = cbcdr;
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}
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//cbcdr &= ~CCM_CBCDR_PERIPH_CLK_SEL;
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//CCM_CBCDR = cbcdr; // why does this not work at 24 MHz?
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CCM->CBCDR &= ~((uint32_t)(1<<25));
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while (CCM->CDHIPR & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L) ; // wait
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// cbcdr &= ~CCM_CBCDR_PERIPH_CLK_SEL;
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// CCM_CBCDR = cbcdr; // why does this not work at 24 MHz?
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CCM->CBCDR &= ~((uint32_t)(1 << 25));
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while (CCM->CDHIPR & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L) {
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; // wait
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}
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F_CPU_ACTUAL = frequency;
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F_BUS_ACTUAL = frequency / div_ipg;
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//scale_cpu_cycles_to_microseconds = 0xFFFFFFFFu / (uint32_t)(frequency / 1000000u);
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// scale_cpu_cycles_to_microseconds = 0xFFFFFFFFu / (uint32_t)(frequency / 1000000u);
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//printf("New Frequency: ARM=%u, IPG=%u\n", frequency, frequency / div_ipg);
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// printf("New Frequency: ARM=%u, IPG=%u\n", frequency, frequency / div_ipg);
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// if voltage needs to decrease, do it after switch clock speed
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if ((dcdc & ((uint32_t)(0x1F << 0))) > ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0)) {
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//printf("Decreasing voltage to %u mV\n", voltage);
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// printf("Decreasing voltage to %u mV\n", voltage);
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dcdc &= ~((uint32_t)(0x1F << 0));
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dcdc |= ((uint32_t)(0x1F << 0));
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DCDC->REG3 = dcdc;
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while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) ; // wait voltage settling
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while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) {
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; // wait voltage settling
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}
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}
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return frequency;
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@ -30,9 +30,9 @@
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#include <math.h>
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#include <stdint.h>
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//#include "py/objproperty.h"
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// #include "py/objproperty.h"
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//#include "py/runtime.h"
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// #include "py/runtime.h"
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#include "shared-bindings/util.h"
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