djsundog
/
circuitpython
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

corrected pre-commit errors

This commit is contained in:
root 2022-04-13 12:04:28 -04:00
parent 60e330fb0d
commit 716497c132
10 changed files with 203 additions and 176 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
locale/circuitpython.pot
View File

@ -2149,6 +2149,10 @@ msgstr ""
msgid "Set pin count must be between 1 and 5"
msgstr ""
#: shared-bindings/microcontroller/Processor.c
msgid "Settable Clock Not Implemented for Your Board"
msgstr ""
#: ports/raspberrypi/bindings/rp2pio/StateMachine.c
msgid "Side set pin count must be between 1 and 5"
msgstr ""
@ -3019,7 +3023,7 @@ msgstr ""
msgid "complex values not supported"
msgstr ""
#: extmod/moduzlib.c shared-module/zlib/DecompIO.c
#: extmod/moduzlib.c
msgid "compression header"
msgstr ""

51
ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c
View File

@ -432,8 +432,7 @@ volatile uint32_t F_BUS_ACTUAL = 132000000;
// CCM_CBCDR AHB_PODF
// CCM_CBCDR SEMC_PODF
uint32_t setarmclock(uint32_t frequency)
{
uint32_t setarmclock(uint32_t frequency) {
uint32_t cbcdr = CCM->CBCDR; // pg 1021
uint32_t cbcmr = CCM->CBCMR; // pg 1023
uint32_t dcdc = DCDC->REG3;
@ -445,7 +444,9 @@ uint32_t setarmclock(uint32_t frequency)
#if defined(OVERCLOCK_STEPSIZE) && defined(OVERCLOCK_MAX_VOLT)
if (frequency > 600000000) {
voltage += ((frequency - 600000000) / OVERCLOCK_STEPSIZE) * 25;
if (voltage > OVERCLOCK_MAX_VOLT) voltage = OVERCLOCK_MAX_VOLT;
if (voltage > OVERCLOCK_MAX_VOLT) {
voltage = OVERCLOCK_MAX_VOLT;
}
}
#endif
} else if (frequency <= 24000000) {
@ -459,7 +460,9 @@ uint32_t setarmclock(uint32_t frequency)
dcdc &= ~((uint32_t)(0x1F << 0));
dcdc |= ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0);
DCDC->REG3 = dcdc;
while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) ; // wait voltage settling
while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) {
; // wait voltage settling
}
}
if (!(cbcdr & CCM_CBCDR_PERIPH_CLK_SEL_L)) {
@ -487,12 +490,16 @@ uint32_t setarmclock(uint32_t frequency)
cbcmr &= ~((uint32_t)(0x03 << 12));
cbcmr |= CCM_CBCMR_PERIPH_CLK2_SEL(sel);
CCM->CBCMR = cbcmr;
while (CCM->CDHIPR & ((uint32_t)(1<<3))) ; // wait
while (CCM->CDHIPR & ((uint32_t)(1 << 3))) {
; // wait
}
}
// switch over to PERIPH_CLK2
cbcdr |= ((uint32_t)(1 << 25));
CCM->CBCDR = cbcdr;
while (CCM->CDHIPR & ((uint32_t)(1<<5))) ; // wait
while (CCM->CDHIPR & ((uint32_t)(1 << 5))) {
; // wait
}
} else {
// printf("already running from PERIPH_CLK2, safe to mess with ARM PLL\n");
}
@ -515,8 +522,12 @@ uint32_t setarmclock(uint32_t frequency)
}
}
uint32_t mult = (frequency * div_arm * div_ahb + 6000000) / 12000000;
if (mult > 108) mult = 108;
if (mult < 54) mult = 54;
if (mult > 108) {
mult = 108;
}
if (mult < 54) {
mult = 54;
}
// printf("Freq: 12 MHz * %u / %u / %u\n", mult, div_arm, div_ahb);
frequency = mult * 12000000 / div_arm / div_ahb;
@ -531,7 +542,9 @@ uint32_t setarmclock(uint32_t frequency)
// TODO: delay needed?
CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_L
| CCM_ANALOG_PLL_ARM_DIV_SELECT(mult);
while (!(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_L)) ; // wait for lock
while (!(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_L)) {
; // wait for lock
}
// printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM);
} else {
// printf("ARM PLL already running at required frequency\n");
@ -539,18 +552,24 @@ uint32_t setarmclock(uint32_t frequency)
if ((CCM->CACRR & ((uint32_t)(0x07 << 0))) != (div_arm - 1)) {
CCM->CACRR = CCM_CACRR_ARM_PODF(div_arm - 1);
while (CCM->CDHIPR & CCM_CDHIPR_ARM_PODF_BUSY_L) ; // wait
while (CCM->CDHIPR & CCM_CDHIPR_ARM_PODF_BUSY_L) {
; // wait
}
}
if ((cbcdr & ((uint32_t)(0x07 << 10))) != CCM_CBCDR_AHB_PODF(div_ahb - 1)) {
cbcdr &= ~((uint32_t)(0x07 << 10));
cbcdr |= CCM_CBCDR_AHB_PODF(div_ahb - 1);
CCM->CBCDR = cbcdr;
while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_L); // wait
while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_L) {
; // wait
}
}
uint32_t div_ipg = (frequency + 149999999) / 150000000;
if (div_ipg > 4) div_ipg = 4;
if (div_ipg > 4) {
div_ipg = 4;
}
if ((cbcdr & ((uint32_t)(0x03 << 8))) != (CCM_CBCDR_IPG_PODF(div_ipg - 1))) {
cbcdr &= ~((uint32_t)(0x03 << 8));
cbcdr |= CCM_CBCDR_IPG_PODF(div_ipg - 1);
@ -561,8 +580,10 @@ uint32_t setarmclock(uint32_t frequency)
// cbcdr &= ~CCM_CBCDR_PERIPH_CLK_SEL;
// CCM_CBCDR = cbcdr; // why does this not work at 24 MHz?
CCM->CBCDR &= ~((uint32_t)(1 << 25));
while (CCM->CDHIPR & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L) ; // wait
while (CCM->CDHIPR & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L) {
; // wait
}
F_CPU_ACTUAL = frequency;
F_BUS_ACTUAL = frequency / div_ipg;
// scale_cpu_cycles_to_microseconds = 0xFFFFFFFFu / (uint32_t)(frequency / 1000000u);
@ -575,7 +596,9 @@ uint32_t setarmclock(uint32_t frequency)
dcdc &= ~((uint32_t)(0x1F << 0));
dcdc |= ((uint32_t)(0x1F << 0));
DCDC->REG3 = dcdc;
while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) ; // wait voltage settling
while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) {
; // wait voltage settling
}
}
return frequency;