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corrected pre-commit errors

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This commit is contained in:
root 2022-04-13 12:04:28 -04:00
parent 60e330fb0d
commit 716497c132
10 changed files with 203 additions and 176 deletions
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6
locale/circuitpython.pot
View File

@ -2149,6 +2149,10 @@ msgstr ""
msgid "Set pin count must be between 1 and 5" msgid "Set pin count must be between 1 and 5"
msgstr "" msgstr ""
#: shared-bindings/microcontroller/Processor.c
msgid "Settable Clock Not Implemented for Your Board"
msgstr ""
#: ports/raspberrypi/bindings/rp2pio/StateMachine.c #: ports/raspberrypi/bindings/rp2pio/StateMachine.c
msgid "Side set pin count must be between 1 and 5" msgid "Side set pin count must be between 1 and 5"
msgstr "" msgstr ""
@ -3019,7 +3023,7 @@ msgstr ""
msgid "complex values not supported" msgid "complex values not supported"
msgstr "" msgstr ""
#: extmod/moduzlib.c shared-module/zlib/DecompIO.c #: extmod/moduzlib.c
msgid "compression header" msgid "compression header"
msgstr "" msgstr ""

2
ports/mimxrt10xx/common-hal/microcontroller/Processor.c
View File

@ -25,7 +25,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
//https://raw.githubusercontent.com/adafruit/circuitpython/main/ports/mimxrt10xx/common-hal/microcontroller/Processor.c // https://raw.githubusercontent.com/adafruit/circuitpython/main/ports/mimxrt10xx/common-hal/microcontroller/Processor.c
#include <math.h> #include <math.h>

119
ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c
View File

@ -359,7 +359,7 @@ void clocks_init(void) {
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE. * THE SOFTWARE.
*/ */
//Note setarmclock is a port from Teensyduino for the Teensy 4.x written by Paul Stroffgren, // Note setarmclock is a port from Teensyduino for the Teensy 4.x written by Paul Stroffgren,
// A brief explanation of F_CPU_ACTUAL vs F_CPU // A brief explanation of F_CPU_ACTUAL vs F_CPU
// https://forum.pjrc.com/threads/57236?p=212642&viewfull=1#post212642 // https://forum.pjrc.com/threads/57236?p=212642&viewfull=1#post212642
volatile uint32_t F_CPU_ACTUAL = 396000000; volatile uint32_t F_CPU_ACTUAL = 396000000;
@ -375,20 +375,20 @@ volatile uint32_t F_BUS_ACTUAL = 132000000;
#define DCDC_REG3 0x40080012 #define DCDC_REG3 0x40080012
#define DCDC_REG0 0x40080000 #define DCDC_REG0 0x40080000
#define DCDC_REG0_STS_DC_OK_L ((uint32_t)(1<<31)) #define DCDC_REG0_STS_DC_OK_L ((uint32_t)(1 << 31))
#define CCM_ANALOG_PLL_USB1_ENABLE_L ((uint32_t)(1<<13)) #define CCM_ANALOG_PLL_USB1_ENABLE_L ((uint32_t)(1 << 13))
#define CCM_ANALOG_PLL_USB1_POWER_L ((uint32_t)(1<<12)) #define CCM_ANALOG_PLL_USB1_POWER_L ((uint32_t)(1 << 12))
#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_L ((uint32_t)(1<<6)) #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_L ((uint32_t)(1 << 6))
#define CCM_ANALOG_PLL_USB1_LOCK_L ((uint32_t)(1<<31)) #define CCM_ANALOG_PLL_USB1_LOCK_L ((uint32_t)(1 << 31))
#define CCM_CCGR6_DCDC(n) ((uint32_t)(((n) & 0x03) << 6)) #define CCM_CCGR6_DCDC(n) ((uint32_t)(((n) & 0x03) << 6))
#define CCM_ANALOG_PLL_ARM_LOCK_L ((uint32_t)(1<<31)) #define CCM_ANALOG_PLL_ARM_LOCK_L ((uint32_t)(1 << 31))
#define CCM_ANALOG_PLL_ARM_BYPASS_L ((uint32_t)(1<<16)) #define CCM_ANALOG_PLL_ARM_BYPASS_L ((uint32_t)(1 << 16))
#define CCM_ANALOG_PLL_ARM_ENABLE_L ((uint32_t)(1<<13)) #define CCM_ANALOG_PLL_ARM_ENABLE_L ((uint32_t)(1 << 13))
#define CCM_ANALOG_PLL_ARM_POWERDOWN_L ((uint32_t)(1<<12)) #define CCM_ANALOG_PLL_ARM_POWERDOWN_L ((uint32_t)(1 << 12))
#define CCM_CDHIPR_ARM_PODF_BUSY_L ((uint32_t)(1<<16)) #define CCM_CDHIPR_ARM_PODF_BUSY_L ((uint32_t)(1 << 16))
#define CCM_CDHIPR_AHB_PODF_BUSY_L ((uint32_t)(1<<1)) #define CCM_CDHIPR_AHB_PODF_BUSY_L ((uint32_t)(1 << 1))
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L ((uint32_t)(1<<5)) #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L ((uint32_t)(1 << 5))
#define CCM_CBCDR_PERIPH_CLK_SEL_L ((uint32_t)(1<<25)) #define CCM_CBCDR_PERIPH_CLK_SEL_L ((uint32_t)(1 << 25))
#define CCM_CCGR_OFF 0 #define CCM_CCGR_OFF 0
#define CCM_CCGR_ON_RUNONLY 1 #define CCM_CCGR_ON_RUNONLY 1
#define CCM_CCGR_ON 3 #define CCM_CCGR_ON 3
@ -423,7 +423,7 @@ volatile uint32_t F_BUS_ACTUAL = 132000000;
* SOFTWARE. * SOFTWARE.
*/ */
//uint32_t set_arm_clock(uint32_t frequency); // uint32_t set_arm_clock(uint32_t frequency);
// stuff needing wait handshake: // stuff needing wait handshake:
// CCM_CACRR ARM_PODF // CCM_CACRR ARM_PODF
@ -432,8 +432,7 @@ volatile uint32_t F_BUS_ACTUAL = 132000000;
// CCM_CBCDR AHB_PODF // CCM_CBCDR AHB_PODF
// CCM_CBCDR SEMC_PODF // CCM_CBCDR SEMC_PODF
uint32_t setarmclock(uint32_t frequency) uint32_t setarmclock(uint32_t frequency) {
{
uint32_t cbcdr = CCM->CBCDR; // pg 1021 uint32_t cbcdr = CCM->CBCDR; // pg 1021
uint32_t cbcmr = CCM->CBCMR; // pg 1023 uint32_t cbcmr = CCM->CBCMR; // pg 1023
uint32_t dcdc = DCDC->REG3; uint32_t dcdc = DCDC->REG3;
@ -442,12 +441,14 @@ uint32_t setarmclock(uint32_t frequency)
uint32_t voltage = 1150; // default = 1.15V uint32_t voltage = 1150; // default = 1.15V
if (frequency > 528000000) { if (frequency > 528000000) {
voltage = 1250; // 1.25V voltage = 1250; // 1.25V
#if defined(OVERCLOCK_STEPSIZE) && defined(OVERCLOCK_MAX_VOLT) #if defined(OVERCLOCK_STEPSIZE) && defined(OVERCLOCK_MAX_VOLT)
if (frequency > 600000000) { if (frequency > 600000000) {
voltage += ((frequency - 600000000) / OVERCLOCK_STEPSIZE) * 25; voltage += ((frequency - 600000000) / OVERCLOCK_STEPSIZE) * 25;
if (voltage > OVERCLOCK_MAX_VOLT) voltage = OVERCLOCK_MAX_VOLT; if (voltage > OVERCLOCK_MAX_VOLT) {
voltage = OVERCLOCK_MAX_VOLT;
} }
#endif }
#endif
} else if (frequency <= 24000000) { } else if (frequency <= 24000000) {
voltage = 950; // 0.95 voltage = 950; // 0.95
} }
@ -455,24 +456,26 @@ uint32_t setarmclock(uint32_t frequency)
// if voltage needs to increase, do it before switch clock speed // if voltage needs to increase, do it before switch clock speed
CCM->CCGR6 |= CCM_CCGR6_DCDC(CCM_CCGR_ON); CCM->CCGR6 |= CCM_CCGR6_DCDC(CCM_CCGR_ON);
if ((dcdc & ((uint32_t)(0x1F << 0))) < ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0)) { if ((dcdc & ((uint32_t)(0x1F << 0))) < ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0)) {
//printf("Increasing voltage to %u mV\n", voltage); // printf("Increasing voltage to %u mV\n", voltage);
dcdc &= ~((uint32_t)(0x1F << 0)); dcdc &= ~((uint32_t)(0x1F << 0));
dcdc |= ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0); dcdc |= ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0);
DCDC->REG3 = dcdc; DCDC->REG3 = dcdc;
while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) ; // wait voltage settling while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) {
; // wait voltage settling
}
} }
if (!(cbcdr & CCM_CBCDR_PERIPH_CLK_SEL_L)) { if (!(cbcdr & CCM_CBCDR_PERIPH_CLK_SEL_L)) {
//printf("need to switch to alternate clock during reconfigure of ARM PLL\n"); // printf("need to switch to alternate clock during reconfigure of ARM PLL\n");
const uint32_t need1s = CCM_ANALOG_PLL_USB1_ENABLE_L | CCM_ANALOG_PLL_USB1_POWER_L | const uint32_t need1s = CCM_ANALOG_PLL_USB1_ENABLE_L | CCM_ANALOG_PLL_USB1_POWER_L |
CCM_ANALOG_PLL_USB1_LOCK_L | CCM_ANALOG_PLL_USB1_EN_USB_CLKS_L; CCM_ANALOG_PLL_USB1_LOCK_L | CCM_ANALOG_PLL_USB1_EN_USB_CLKS_L;
uint32_t sel, div; uint32_t sel, div;
if ((CCM_ANALOG->PLL_USB1 & need1s) == need1s) { if ((CCM_ANALOG->PLL_USB1 & need1s) == need1s) {
//printf("USB PLL is running, so we can use 120 MHz\n"); // printf("USB PLL is running, so we can use 120 MHz\n");
sel = 0; sel = 0;
div = 3; // divide down to 120 MHz, so IPG is ok even if IPG_PODF=0 div = 3; // divide down to 120 MHz, so IPG is ok even if IPG_PODF=0
} else { } else {
//printf("USB PLL is off, use 24 MHz crystal\n"); // printf("USB PLL is off, use 24 MHz crystal\n");
sel = 1; sel = 1;
div = 0; div = 0;
} }
@ -487,14 +490,18 @@ uint32_t setarmclock(uint32_t frequency)
cbcmr &= ~((uint32_t)(0x03 << 12)); cbcmr &= ~((uint32_t)(0x03 << 12));
cbcmr |= CCM_CBCMR_PERIPH_CLK2_SEL(sel); cbcmr |= CCM_CBCMR_PERIPH_CLK2_SEL(sel);
CCM->CBCMR = cbcmr; CCM->CBCMR = cbcmr;
while (CCM->CDHIPR & ((uint32_t)(1<<3))) ; // wait while (CCM->CDHIPR & ((uint32_t)(1 << 3))) {
; // wait
}
} }
// switch over to PERIPH_CLK2 // switch over to PERIPH_CLK2
cbcdr |= ((uint32_t)(1<<25)); cbcdr |= ((uint32_t)(1 << 25));
CCM->CBCDR = cbcdr; CCM->CBCDR = cbcdr;
while (CCM->CDHIPR & ((uint32_t)(1<<5))) ; // wait while (CCM->CDHIPR & ((uint32_t)(1 << 5))) {
; // wait
}
} else { } else {
//printf("already running from PERIPH_CLK2, safe to mess with ARM PLL\n"); // printf("already running from PERIPH_CLK2, safe to mess with ARM PLL\n");
} }
// TODO: check if PLL2 running, can 352, 396 or 528 can work? (no need for ARM PLL) // TODO: check if PLL2 running, can 352, 396 or 528 can work? (no need for ARM PLL)
@ -515,42 +522,54 @@ uint32_t setarmclock(uint32_t frequency)
} }
} }
uint32_t mult = (frequency * div_arm * div_ahb + 6000000) / 12000000; uint32_t mult = (frequency * div_arm * div_ahb + 6000000) / 12000000;
if (mult > 108) mult = 108; if (mult > 108) {
if (mult < 54) mult = 54; mult = 108;
//printf("Freq: 12 MHz * %u / %u / %u\n", mult, div_arm, div_ahb); }
if (mult < 54) {
mult = 54;
}
// printf("Freq: 12 MHz * %u / %u / %u\n", mult, div_arm, div_ahb);
frequency = mult * 12000000 / div_arm / div_ahb; frequency = mult * 12000000 / div_arm / div_ahb;
//printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM); // printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM);
const uint32_t arm_pll_mask = CCM_ANALOG_PLL_ARM_LOCK_L | CCM_ANALOG_PLL_ARM_BYPASS_L | const uint32_t arm_pll_mask = CCM_ANALOG_PLL_ARM_LOCK_L | CCM_ANALOG_PLL_ARM_BYPASS_L |
CCM_ANALOG_PLL_ARM_ENABLE_L | CCM_ANALOG_PLL_ARM_POWERDOWN_L | CCM_ANALOG_PLL_ARM_ENABLE_L | CCM_ANALOG_PLL_ARM_POWERDOWN_L |
CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK; CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK;
if ((CCM_ANALOG->PLL_ARM & arm_pll_mask) != (CCM_ANALOG_PLL_ARM_LOCK_L if ((CCM_ANALOG->PLL_ARM & arm_pll_mask) != (CCM_ANALOG_PLL_ARM_LOCK_L
| CCM_ANALOG_PLL_ARM_ENABLE_L | CCM_ANALOG_PLL_ARM_DIV_SELECT(mult))) { | CCM_ANALOG_PLL_ARM_ENABLE_L | CCM_ANALOG_PLL_ARM_DIV_SELECT(mult))) {
//printf("ARM PLL needs reconfigure\n"); // printf("ARM PLL needs reconfigure\n");
CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_L; CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_L;
// TODO: delay needed? // TODO: delay needed?
CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_L CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_L
| CCM_ANALOG_PLL_ARM_DIV_SELECT(mult); | CCM_ANALOG_PLL_ARM_DIV_SELECT(mult);
while (!(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_L)) ; // wait for lock while (!(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_L)) {
//printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM); ; // wait for lock
}
// printf("ARM PLL=%x\n", CCM_ANALOG->PLL_ARM);
} else { } else {
//printf("ARM PLL already running at required frequency\n"); // printf("ARM PLL already running at required frequency\n");
} }
if ((CCM->CACRR & ((uint32_t)(0x07 << 0))) != (div_arm - 1)) { if ((CCM->CACRR & ((uint32_t)(0x07 << 0))) != (div_arm - 1)) {
CCM->CACRR = CCM_CACRR_ARM_PODF(div_arm - 1); CCM->CACRR = CCM_CACRR_ARM_PODF(div_arm - 1);
while (CCM->CDHIPR & CCM_CDHIPR_ARM_PODF_BUSY_L) ; // wait while (CCM->CDHIPR & CCM_CDHIPR_ARM_PODF_BUSY_L) {
; // wait
}
} }
if ((cbcdr & ((uint32_t)(0x07 << 10))) != CCM_CBCDR_AHB_PODF(div_ahb - 1)) { if ((cbcdr & ((uint32_t)(0x07 << 10))) != CCM_CBCDR_AHB_PODF(div_ahb - 1)) {
cbcdr &= ~((uint32_t)(0x07 << 10)); cbcdr &= ~((uint32_t)(0x07 << 10));
cbcdr |= CCM_CBCDR_AHB_PODF(div_ahb - 1); cbcdr |= CCM_CBCDR_AHB_PODF(div_ahb - 1);
CCM->CBCDR = cbcdr; CCM->CBCDR = cbcdr;
while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_L); // wait while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_L) {
; // wait
}
} }
uint32_t div_ipg = (frequency + 149999999) / 150000000; uint32_t div_ipg = (frequency + 149999999) / 150000000;
if (div_ipg > 4) div_ipg = 4; if (div_ipg > 4) {
div_ipg = 4;
}
if ((cbcdr & ((uint32_t)(0x03 << 8))) != (CCM_CBCDR_IPG_PODF(div_ipg - 1))) { if ((cbcdr & ((uint32_t)(0x03 << 8))) != (CCM_CBCDR_IPG_PODF(div_ipg - 1))) {
cbcdr &= ~((uint32_t)(0x03 << 8)); cbcdr &= ~((uint32_t)(0x03 << 8));
cbcdr |= CCM_CBCDR_IPG_PODF(div_ipg - 1); cbcdr |= CCM_CBCDR_IPG_PODF(div_ipg - 1);
@ -558,24 +577,28 @@ uint32_t setarmclock(uint32_t frequency)
CCM->CBCDR = cbcdr; CCM->CBCDR = cbcdr;
} }
//cbcdr &= ~CCM_CBCDR_PERIPH_CLK_SEL; // cbcdr &= ~CCM_CBCDR_PERIPH_CLK_SEL;
//CCM_CBCDR = cbcdr; // why does this not work at 24 MHz? // CCM_CBCDR = cbcdr; // why does this not work at 24 MHz?
CCM->CBCDR &= ~((uint32_t)(1<<25)); CCM->CBCDR &= ~((uint32_t)(1 << 25));
while (CCM->CDHIPR & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L) ; // wait while (CCM->CDHIPR & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_L) {
; // wait
}
F_CPU_ACTUAL = frequency; F_CPU_ACTUAL = frequency;
F_BUS_ACTUAL = frequency / div_ipg; F_BUS_ACTUAL = frequency / div_ipg;
//scale_cpu_cycles_to_microseconds = 0xFFFFFFFFu / (uint32_t)(frequency / 1000000u); // scale_cpu_cycles_to_microseconds = 0xFFFFFFFFu / (uint32_t)(frequency / 1000000u);
//printf("New Frequency: ARM=%u, IPG=%u\n", frequency, frequency / div_ipg); // printf("New Frequency: ARM=%u, IPG=%u\n", frequency, frequency / div_ipg);
// if voltage needs to decrease, do it after switch clock speed // if voltage needs to decrease, do it after switch clock speed
if ((dcdc & ((uint32_t)(0x1F << 0))) > ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0)) { if ((dcdc & ((uint32_t)(0x1F << 0))) > ((uint32_t)(((voltage - 800) / 25) & 0x1F) << 0)) {
//printf("Decreasing voltage to %u mV\n", voltage); // printf("Decreasing voltage to %u mV\n", voltage);
dcdc &= ~((uint32_t)(0x1F << 0)); dcdc &= ~((uint32_t)(0x1F << 0));
dcdc |= ((uint32_t)(0x1F << 0)); dcdc |= ((uint32_t)(0x1F << 0));
DCDC->REG3 = dcdc; DCDC->REG3 = dcdc;
while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) ; // wait voltage settling while (!(DCDC->REG0 & DCDC_REG0_STS_DC_OK_L)) {
; // wait voltage settling
}
} }
return frequency; return frequency;

4
shared-bindings/microcontroller/Processor.c
View File

@ -30,9 +30,9 @@
#include <math.h> #include <math.h>
#include <stdint.h> #include <stdint.h>
//#include "py/objproperty.h" // #include "py/objproperty.h"
//#include "py/runtime.h" // #include "py/runtime.h"
#include "shared-bindings/util.h" #include "shared-bindings/util.h"