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stm32/boards: Fix typos in stm32f767_af.csv table.

This commit is contained in:
Damien George 2017-10-06 14:32:42 +11:00
parent ca2427c313
commit 6f1a615427
1 changed files with 4 additions and 4 deletions
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8
ports/stm32/boards/stm32f767_af.csv
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@ -15,9 +15,9 @@ PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT
PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT
PortA,PA13,JTMS,SWDIO,,,,,,,,,,,,,,EVENTOUT
PortA,PA14,JTCK,SWCLK,,,,,,,,,,,,,,EVENTOUT
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,HDMICE,CSPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT
PortB,PB0,,TIM1_CH2N,TIM3_CH3T,IM8_CH2N,,,,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT
PortB,PB1,,TIM1_CH3N,TIM3_CH4T,IM8_CH3N,,,,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,HDMICEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT
PortB,PB0,,TIM1_CH2N,TIM3_CH3T,TIM8_CH2N,,,,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT
PortB,PB1,,TIM1_CH3N,TIM3_CH4T,TIM8_CH3N,,,,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT
PortB,PB2,,,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,,,,,,EVENTOUT
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,SDMMC2_D2,,,,,EVENTOUT
PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,SDMMC2_D3,,,,,EVENTOUT
@ -41,7 +41,7 @@ PortC,PC5,,,,,,,,,SPDIFRX_IN3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT
PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,SDMMC2_D6,,SDMMC1_D6,DCMI_D0,LCD_HSYNC,EVENTOUT
PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,SDMMC2_D7,,SDMMC1_D7,DCMI_D1,LCD_G6,EVENTOUT
PortC,PC8,TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,,,,SDMMC1_D0,DCMI_D2,,EVENTOUT
PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,,,SDMMC1_D1,DCMI_D3,,EVENTOUT
PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S2_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,,,SDMMC1_D1,DCMI_D3,,EVENTOUT
PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC1_D2,DCMI_D8,LCD_R2,EVENTOUT
PortC,PC11,,,,,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC1_D3,DCMI_D4,,EVENTOUT
PortC,PC12,TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC1_CK,DCMI_D9,,EVENTOUT

1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
15 PortA PA12 TIM1_ETR USART1_RTS SAI2_FS_B CAN1_TX OTG_FS_DP LCD_R5 EVENTOUT
16 PortA PA13 JTMS SWDIO EVENTOUT
17 PortA PA14 JTCK SWCLK EVENTOUT
18 PortA PA15 JTDI TIM2_CH1/TIM2_ETR HDMICE HDMICEC CSPI1_NSS/I2S1_WS SPI1_NSS/I2S1_WS SPI3_NSS/I2S3_WS UART4_RTS EVENTOUT
19 PortB PB0 TIM1_CH2N TIM3_CH3T IM8_CH2N TIM8_CH2N UART4_CTS LCD_R3 OTG_HS_ULPI_D1 ETH_MII_RXD2 EVENTOUT
20 PortB PB1 TIM1_CH3N TIM3_CH4T IM8_CH3N TIM8_CH3N LCD_R6 OTG_HS_ULPI_D2 ETH_MII_RXD3 EVENTOUT
21 PortB PB2 SAI1_SD_A SPI3_MOSI/I2S3_SD QUADSPI_CLK EVENTOUT
22 PortB PB3 JTDO/TRACESWO TIM2_CH2 SPI1_SCK/I2S1_CK SPI3_SCK/I2S3_CK SDMMC2_D2 EVENTOUT
23 PortB PB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO SPI2_NSS/I2S2_WS SDMMC2_D3 EVENTOUT
41 PortC PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDMMC2_D6 SDMMC1_D6 DCMI_D0 LCD_HSYNC EVENTOUT
42 PortC PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDMMC2_D7 SDMMC1_D7 DCMI_D1 LCD_G6 EVENTOUT
43 PortC PC8 TRACED1 TIM3_CH3 TIM8_CH3 UART5_RTS USART6_CK SDMMC1_D0 DCMI_D2 EVENTOUT
44 PortC PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN I2S2_CKIN UART5_CTS QUADSPI_BK1_IO0 SDMMC1_D1 DCMI_D3 EVENTOUT
45 PortC PC10 SPI3_SCK/I2S3_CK USART3_TX UART4_TX QUADSPI_BK1_IO1 SDMMC1_D2 DCMI_D8 LCD_R2 EVENTOUT
46 PortC PC11 SPI3_MISO USART3_RX UART4_RX QUADSPI_BK2_NCS SDMMC1_D3 DCMI_D4 EVENTOUT
47 PortC PC12 TRACED3 SPI3_MOSI/I2S3_SD USART3_CK UART5_TX SDMMC1_CK DCMI_D9 EVENTOUT