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Merge pull request #1418 from dhalbert/feather52840-rgb-qspi-fixes 

Don't check for corrupt heap too early; Fix QSPI timing
This commit is contained in:
Dan Halbert 2018-12-26 17:53:06 -05:00 committed by GitHub
parent 60a509bea1 0dfe2dbff0
commit 6d60b817f3
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 15 additions and 15 deletions
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28
ports/nrf/supervisor/qspi_flash.c
View File

@ -40,15 +40,13 @@
bool spi_flash_command(uint8_t command) {
nrf_qspi_cinstr_conf_t cinstr_cfg = {
.opcode = 0,
.length = 0,
.opcode = command,
.length = 1,
.io2_level = true,
.io3_level = true,
.wipwait = false,
.wren = false
};
cinstr_cfg.opcode = command;
cinstr_cfg.length = 1;
nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
return true;
}
@ -62,8 +60,8 @@ bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length)
.wipwait = false,
.wren = false
};
nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, response);
return true;
return nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, response) == NRFX_SUCCESS;
}
bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
@ -75,8 +73,7 @@ bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
.wipwait = false,
.wren = false // We do this manually.
};
nrfx_qspi_cinstr_xfer(&cinstr_cfg, data, NULL);
return true;
return nrfx_qspi_cinstr_xfer(&cinstr_cfg, data, NULL) == NRFX_SUCCESS;
}
bool spi_flash_sector_command(uint8_t command, uint32_t address) {
@ -91,8 +88,7 @@ bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) {
}
bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
nrfx_qspi_read(data, length, address);
return true;
return nrfx_qspi_read(data, length, address) == NRFX_SUCCESS;
}
void spi_flash_init(void) {
@ -115,7 +111,7 @@ void spi_flash_init(void) {
.dpmconfig = false
},
.phy_if = {
.sck_freq = NRF_QSPI_FREQ_32MDIV16, // Start at a slow 2mhz and speed up once we know what we're talking to.
.sck_freq = NRF_QSPI_FREQ_32MDIV16, // Start at a slow 2MHz and speed up once we know what we're talking to.
.sck_delay = 10, // min time CS must stay high before going low again. in unit of 62.5 ns
.spi_mode = NRF_QSPI_MODE_0,
.dpmen = false
@ -145,14 +141,18 @@ void spi_flash_init_device(const external_flash_device* device) {
// Switch to single output line if the device doesn't support quad programs.
if (!device->supports_qspi_writes) {
NRF_QSPI->IFCONFIG0 &= ~QSPI_IFCONFIG0_WRITEOC_Msk;
NRF_QSPI->IFCONFIG0 |= QSPI_IFCONFIG0_WRITEOC_PP;
NRF_QSPI->IFCONFIG0 |= QSPI_IFCONFIG0_WRITEOC_PP << QSPI_IFCONFIG0_WRITEOC_Pos;
}
// Speed up as much as we can.
uint8_t sckfreq = 0;
// Start at 16 MHz and go down.
// At 32 MHz GD25Q16C doesn't work reliably on Feather 52840, even though it should work up to 104 MHz.
// sckfreq = 0 is 32 Mhz
// sckfreq = 1 is 16 MHz, etc.
uint8_t sckfreq = 1;
while (32000000 / (sckfreq + 1) > device->max_clock_speed_mhz * 1000000 && sckfreq < 16) {
sckfreq += 1;
}
NRF_QSPI->IFCONFIG1 &= ~QSPI_IFCONFIG1_SCKFREQ_Msk;
NRF_QSPI->IFCONFIG1 |= sckfreq << QSPI_IFCONFIG1_SCKDELAY_Pos;
NRF_QSPI->IFCONFIG1 |= sckfreq << QSPI_IFCONFIG1_SCKFREQ_Pos;
}

2
supervisor/shared/stack.c
View File

@ -56,7 +56,7 @@ void allocate_stack(void) {
}
inline bool stack_ok(void) {
return *stack_alloc->ptr == STACK_CANARY_VALUE;
return stack_alloc == NULL || *stack_alloc->ptr == STACK_CANARY_VALUE;
}
inline void assert_heap_ok(void) {