djsundog/circuitpython
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

esp8266: Cache Xtensa-built libaxtls.a in local build dir.

Browse Source 
Allows to build the library variant for other archs in parallel.
This commit is contained in:
Paul Sokolovsky 2016-07-16 04:53:33 +03:00
parent bcd0e9a7fa
commit 6aa7c805cc
2 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
esp8266/Makefile
View File

@ -154,7 +154,7 @@ SRC_QSTR += $(SRC_C) $(STM_SRC_C) $(EXTMOD_SRC_C) $(DRIVERS_SRC_C)
# Append any auto-generated sources that are needed by sources listed in SRC_QSTR
SRC_QSTR_AUTO_DEPS +=
all: $(BUILD)/firmware-combined.bin
all: $(BUILD)/libaxtls.a $(BUILD)/firmware-combined.bin
CONFVARS_FILE = $(BUILD)/confvars
@ -230,8 +230,11 @@ $(BUILD)/firmware.elf: $(OBJ)
include ../py/mkrules.mk
axtls:
axtls: $(BUILD)/libaxtls.a
$(BUILD)/libaxtls.a:
cd ../lib/axtls; cp config/upyconfig config/.config
cd ../lib/axtls; make oldconfig -B
cd ../lib/axtls; make clean
cd ../lib/axtls; make all CC="$(CC)" LD="$(LD)" AR="$(AR)" CFLAGS_EXTRA="$(CFLAGS_XTENSA) -Dabort=abort_ -DRT_MAX_PLAIN_LENGTH=1024 -DRT_EXTRA=3072"
cp ../lib/axtls/_stage/libaxtls.a $@

2
py/py.mk
View File

@ -23,7 +23,7 @@ ifeq ($(MICROPY_PY_USSL),1)
CFLAGS_MOD += -DMICROPY_PY_USSL=1
ifeq ($(MICROPY_SSL_AXTLS),1)
CFLAGS_MOD += -DMICROPY_SSL_AXTLS=1 -I../lib/axtls/ssl -I../lib/axtls/crypto -I../lib/axtls/config
LDFLAGS_MOD += -L../lib/axtls/_stage -laxtls
LDFLAGS_MOD += -Lbuild -laxtls
endif
endif