8334: RP2040 lacks raw memory map access

This commit is contained in:
Bob Abeles 2023-08-31 20:25:20 -07:00
parent 3605d891de
commit 66b3eccaf6
13 changed files with 245 additions and 33 deletions

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@ -89,13 +89,17 @@ msgid ""
msgstr ""
#: ports/atmel-samd/common-hal/alarm/__init__.c
#: ports/atmel-samd/common-hal/audiobusio/I2SOut.c
#: ports/cxd56/common-hal/analogio/AnalogOut.c ports/cxd56/common-hal/rtc/RTC.c
#: ports/espressif/common-hal/audiobusio/I2SOut.c
#: ports/espressif/common-hal/rtc/RTC.c
#: ports/mimxrt10xx/common-hal/analogio/AnalogOut.c
#: ports/mimxrt10xx/common-hal/rtc/RTC.c ports/nrf/common-hal/alarm/__init__.c
#: ports/nrf/common-hal/analogio/AnalogOut.c ports/nrf/common-hal/rtc/RTC.c
#: ports/nrf/common-hal/analogio/AnalogOut.c
#: ports/nrf/common-hal/audiobusio/I2SOut.c ports/nrf/common-hal/rtc/RTC.c
#: ports/raspberrypi/common-hal/alarm/__init__.c
#: ports/raspberrypi/common-hal/analogio/AnalogOut.c
#: ports/raspberrypi/common-hal/audiobusio/I2SOut.c
#: ports/raspberrypi/common-hal/rtc/RTC.c ports/stm/common-hal/alarm/__init__.c
#: ports/stm/common-hal/canio/Listener.c ports/stm/common-hal/rtc/RTC.c
#: shared-bindings/audiobusio/I2SOut.c shared-bindings/audiobusio/PDMIn.c
@ -458,9 +462,14 @@ msgstr ""
#: ports/espressif/common-hal/memorymap/AddressRange.c
#: ports/nrf/common-hal/memorymap/AddressRange.c
#: ports/raspberrypi/common-hal/memorymap/AddressRange.c
msgid "Address range not allowed"
msgstr ""
#: shared-bindings/memorymap/AddressRange.c
msgid "Address range wraps around"
msgstr ""
#: ports/espressif/common-hal/canio/CAN.c
msgid "All CAN peripherals are in use"
msgstr ""
@ -2127,6 +2136,10 @@ msgstr ""
msgid "UUID value is not str, int or byte buffer"
msgstr ""
#: ports/raspberrypi/common-hal/memorymap/AddressRange.c
msgid "Unable to access unaliged IO register"
msgstr ""
#: ports/atmel-samd/common-hal/audiobusio/I2SOut.c
#: ports/atmel-samd/common-hal/audioio/AudioOut.c
#: ports/raspberrypi/common-hal/audiobusio/I2SOut.c
@ -2180,14 +2193,14 @@ msgstr ""
msgid "Unable to start mDNS query"
msgstr ""
#: shared-bindings/memorymap/AddressRange.c
msgid "Unable to write to address."
msgstr ""
#: shared-bindings/nvm/ByteArray.c
msgid "Unable to write to nvm."
msgstr ""
#: ports/raspberrypi/common-hal/memorymap/AddressRange.c
msgid "Unable to write to read-only memory"
msgstr ""
#: shared-bindings/alarm/SleepMemory.c
msgid "Unable to write to sleep_memory."
msgstr ""
@ -2948,7 +2961,7 @@ msgstr ""
msgid "empty file"
msgstr ""
#: extmod/moduasyncio.c extmod/moduheapq.c extmod/modutimeq.c
#: extmod/moduasyncio.c extmod/moduheapq.c
msgid "empty heap"
msgstr ""
@ -3899,10 +3912,6 @@ msgstr ""
msgid "pull masks conflict with direction masks"
msgstr ""
#: extmod/modutimeq.c
msgid "queue overflow"
msgstr ""
#: py/parse.c
msgid "raw f-strings are not supported"
msgstr ""

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@ -66,7 +66,7 @@ size_t common_hal_memorymap_addressrange_get_length(const memorymap_addressrange
return self->len;
}
bool common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self,
void common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self,
size_t start_index, uint8_t *values, size_t len) {
uint8_t *address = self->start_address + start_index;
#pragma GCC diagnostic push
@ -83,8 +83,6 @@ bool common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_ob
memcpy(address, values, len);
}
#pragma GCC diagnostic pop
return true;
}
void common_hal_memorymap_addressrange_get_bytes(const memorymap_addressrange_obj_t *self,

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@ -95,7 +95,7 @@ uint32_t common_hal_memorymap_addressrange_get_length(const memorymap_addressran
}
bool common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self,
void common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self,
uint32_t start_index, uint8_t *values, uint32_t len) {
uint8_t *address = self->start_address + start_index;
#pragma GCC diagnostic push
@ -112,8 +112,6 @@ bool common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_ob
memcpy(address, values, len);
}
#pragma GCC diagnostic pop
return true;
}
void common_hal_memorymap_addressrange_get_bytes(const memorymap_addressrange_obj_t *self,

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@ -0,0 +1,136 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 microDev
* Copyright (c) 2023 Bob Abeles
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <string.h>
#include "shared-bindings/memorymap/AddressRange.h"
#include "py/runtime.h"
#include "hardware/regs/addressmap.h"
// RP2 address map ranges, must be arranged in order by ascending start address
addressmap_rp2_range_t rp2_ranges[] = {
{(uint8_t *)ROM_BASE, 0x00004000, ROM}, // boot ROM
{(uint8_t *)XIP_BASE, 0x00100000, XIP}, // XIP normal cache operation
{(uint8_t *)XIP_NOALLOC_BASE, 0x00100000, XIP}, // XIP check for hit, no update on miss
{(uint8_t *)XIP_NOCACHE_BASE, 0x00100000, XIP}, // XIP don't check for hit, no update on miss
{(uint8_t *)XIP_NOCACHE_NOALLOC_BASE, 0x00100000, XIP}, // XIP bypass cache completely
{(uint8_t *)XIP_CTRL_BASE, 0x00004000, IO}, // XIP control registers
{(uint8_t *)XIP_SRAM_BASE, 0x00004000, SRAM}, // XIP SRAM 16KB XIP cache
{(uint8_t *)XIP_SSI_BASE, 0x00004000, IO}, // XIP SSI registers
{(uint8_t *)SRAM_BASE, 0x00042000, SRAM}, // SRAM 256KB striped plus 16KB contiguous
{(uint8_t *)SRAM0_BASE, 0x00040000, SRAM}, // SRAM0 to SRAM3 256KB non-striped
{(uint8_t *)SYSINFO_BASE, 0x00070000, IO}, // APB peripherals
{(uint8_t *)DMA_BASE, 0x00004000, IO}, // DMA registers
{(uint8_t *)USBCTRL_DPRAM_BASE, 0x00001000, SRAM}, // USB DPSRAM 4KB
{(uint8_t *)USBCTRL_REGS_BASE, 0x00004000, IO}, // USB registers
{(uint8_t *)PIO0_BASE, 0x00004000, IO}, // PIO0 registers
{(uint8_t *)PIO1_BASE, 0x00004000, IO}, // PIO1 registers
{(uint8_t *)SIO_BASE, 0x00001000, IO}, // SIO registers, no aliases
{(uint8_t *)PPB_BASE, 0x00004000, IO} // PPB registers
};
void common_hal_memorymap_addressrange_construct(memorymap_addressrange_obj_t *self,
uint8_t *start_address, size_t length) {
for (size_t i = 0; i < MP_ARRAY_SIZE(rp2_ranges); i++) {
if (start_address <= rp2_ranges[i].start_address) {
uint8_t *range_end_address = rp2_ranges[i].start_address + rp2_ranges[i].len - 1;
uint8_t *end_address = start_address + length - 1;
if (start_address > range_end_address || end_address > range_end_address) {
break;
}
self->start_address = start_address;
self->len = length;
self->type = rp2_ranges[i].type;
return;
}
}
mp_raise_ValueError(translate("Address range not allowed"));
}
size_t common_hal_memorymap_addressrange_get_length(const memorymap_addressrange_obj_t *self) {
return self->len;
}
void common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self,
size_t start_index, uint8_t *values, size_t len) {
uint8_t *dest_addr = self->start_address + start_index;
switch (self->type) {
case SRAM:
// Writes to SRAM may be arbitrary length and alignment. We use memcpy() which
// may optimize aligned writes depending on CIRCUITPY_FULL_BUILD of the CP build.
memcpy(dest_addr, values, len);
break;
case IO:
if ((size_t)dest_addr & 0x03 || len & 0x03) {
// Unaligned access or unaligned length not supported by RP2 for IO registers
mp_raise_RuntimeError(translate("Unable to access unaliged IO register"));
} else {
// Aligned access and length, use 32-bit writes
uint32_t *dest_addr32 = (uint32_t *)dest_addr;
size_t len32 = len >> 2;
for (size_t i = 0; i < len32; i++) {
*dest_addr32++ = ((uint32_t *)values)[i << 2];
}
}
break;
case XIP:
case ROM:
// XIP and ROM are read-only
mp_raise_RuntimeError(translate("Unable to write to read-only memory"));
break;
}
}
void common_hal_memorymap_addressrange_get_bytes(const memorymap_addressrange_obj_t *self,
size_t start_index, size_t len, uint8_t *values) {
uint8_t *src_addr = self->start_address + start_index;
switch (self->type) {
case SRAM:
case XIP:
case ROM:
// Reads from these sources may be arbitrary length and alignment. We use memcpy()
// which may optimize aligned writes depending on CIRCUITPY_FULL_BUILD of the CP build.
memcpy(values, src_addr, len);
break;
case IO:
if ((size_t)src_addr & 0x03 || len & 0x03) {
// Unaligned access or unaligned length not supported by RP2 for IO registers
mp_raise_RuntimeError(translate("Unable to access unaliged IO register"));
} else {
// Aligned access and length, use 32-bit writes
uint32_t *src_addr32 = (uint32_t *)src_addr;
size_t len32 = len >> 2;
for (size_t i = 0; i < len32; i++) {
((uint32_t *)values)[i] = *src_addr32++;
}
}
break;
}
}

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@ -0,0 +1,49 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 microDev
* Copyright (c) 2023 Bob Abeles
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_RASPBERRYPI_COMMON_HAL_MEMORYMAP_ADDRESSRANGE_H
#define MICROPY_INCLUDED_RASPBERRYPI_COMMON_HAL_MEMORYMAP_ADDRESSRANGE_H
#include "py/obj.h"
// depending on the section memory type, different access methods and rules apply
typedef enum { SRAM, ROM, XIP, IO } memorymap_rp2_section_t;
typedef struct {
mp_obj_base_t base;
uint8_t *start_address;
size_t len;
memorymap_rp2_section_t type;
} memorymap_addressrange_obj_t;
typedef struct {
uint8_t *start_address;
size_t len;
memorymap_rp2_section_t type;
} addressmap_rp2_range_t;
#endif // MICROPY_INCLUDED_RASPBERRYPI_COMMON_HAL_MEMORYMAP_ADDRESSRANGE_H

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@ -0,0 +1 @@
// No memorymap module functions.

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@ -15,6 +15,7 @@ CIRCUITPY_FULL_BUILD ?= 1
CIRCUITPY_AUDIOMP3 ?= 1
CIRCUITPY_BITOPS ?= 1
CIRCUITPY_IMAGECAPTURE ?= 1
CIRCUITPY_MEMORYMAP ?= 1
CIRCUITPY_PWMIO ?= 1
CIRCUITPY_RGBMATRIX ?= $(CIRCUITPY_DISPLAYIO)
CIRCUITPY_ROTARYIO ?= 1

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@ -115,6 +115,8 @@ void mp_arg_parse_all(size_t n_pos, const mp_obj_t *pos, mp_map_t *kws, size_t n
out_vals[i].u_bool = mp_obj_is_true(given_arg);
} else if ((allowed[i].flags & MP_ARG_KIND_MASK) == MP_ARG_INT) {
out_vals[i].u_int = mp_obj_get_int(given_arg);
} else if ((allowed[i].flags & MP_ARG_KIND_MASK) == MP_ARG_UINT) {
out_vals[i].u_uint = mp_obj_get_uint(given_arg);
} else {
assert((allowed[i].flags & MP_ARG_KIND_MASK) == MP_ARG_OBJ);
out_vals[i].u_obj = given_arg;

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@ -420,6 +420,21 @@ bool mp_obj_get_int_maybe(mp_const_obj_t arg, mp_int_t *value) {
return true;
}
mp_uint_t mp_obj_get_uint(mp_const_obj_t arg) {
if (arg == mp_const_false) {
return 0;
} else if (arg == mp_const_true) {
return 1;
} else if (mp_obj_is_small_int(arg)) {
return MP_OBJ_SMALL_INT_VALUE(arg);
} else if (mp_obj_is_type(arg, &mp_type_int)) {
return mp_obj_int_get_uint_checked(arg);
} else {
mp_obj_t res = mp_unary_op(MP_UNARY_OP_INT, (mp_obj_t)arg);
return mp_obj_int_get_uint_checked(res);
}
}
#if MICROPY_PY_BUILTINS_FLOAT
bool mp_obj_get_float_maybe(mp_obj_t arg, mp_float_t *value) {
mp_float_t val;

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@ -939,6 +939,7 @@ static MP_INLINE bool mp_obj_is_integer(mp_const_obj_t o) {
mp_int_t mp_obj_get_int(mp_const_obj_t arg);
mp_int_t mp_obj_get_int_truncated(mp_const_obj_t arg);
bool mp_obj_get_int_maybe(mp_const_obj_t arg, mp_int_t *value);
mp_uint_t mp_obj_get_uint(mp_const_obj_t arg);
#if MICROPY_PY_BUILTINS_FLOAT
mp_float_t mp_obj_get_float(mp_obj_t self_in);
bool mp_obj_get_float_maybe(mp_obj_t arg, mp_float_t *value);

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@ -45,6 +45,7 @@ typedef enum {
MP_ARG_BOOL = 0x001,
MP_ARG_INT = 0x002,
MP_ARG_OBJ = 0x003,
MP_ARG_UINT = 0x004,
MP_ARG_KIND_MASK = 0x0ff,
MP_ARG_REQUIRED = 0x100,
MP_ARG_KW_ONLY = 0x200,
@ -53,6 +54,7 @@ typedef enum {
typedef union _mp_arg_val_t {
bool u_bool;
mp_int_t u_int;
mp_uint_t u_uint;
mp_obj_t u_obj;
mp_rom_obj_t u_rom_obj;
} mp_arg_val_t;

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@ -51,23 +51,25 @@
//| def __init__(self, *, start, length) -> None:
//| """Constructs an address range starting at ``start`` and ending at
//| ``start + length``. An exception will be raised if any of the
//| ``start + length - 1``. An exception will be raised if any of the
//| addresses are invalid or protected."""
//| ...
STATIC mp_obj_t memorymap_addressrange_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
enum { ARG_start, ARG_length };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_start, MP_ARG_KW_ONLY | MP_ARG_REQUIRED | MP_ARG_INT },
{ MP_QSTR_start, MP_ARG_KW_ONLY | MP_ARG_REQUIRED | MP_ARG_UINT },
{ MP_QSTR_length, MP_ARG_KW_ONLY | MP_ARG_REQUIRED | MP_ARG_INT },
};
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
size_t start =
mp_arg_validate_int_min(args[ARG_start].u_int, 0, MP_QSTR_start);
size_t start = args[ARG_start].u_uint;
size_t length =
mp_arg_validate_int_min(args[ARG_length].u_int, 1, MP_QSTR_length);
// Check for address range wrap here as this can break port-specific code due to size_t overflow.
if (start + length - 1 < start) {
mp_raise_ValueError(translate("Address range wraps around"));
}
memorymap_addressrange_obj_t *self = mp_obj_malloc(memorymap_addressrange_obj_t, &memorymap_addressrange_type);
@ -104,7 +106,8 @@ STATIC MP_DEFINE_CONST_DICT(memorymap_addressrange_locals_dict, memorymap_addres
//| def __getitem__(self, index: int) -> int:
//| """Returns the value(s) at the given index.
//|
//| 1, 2, 4 and 8 byte aligned reads will be done in one transaction.
//| 1, 2, 4 and 8 byte aligned reads will be done in one transaction
//| when possible.
//| All others may use multiple transactions."""
//| ...
//| @overload
@ -113,7 +116,8 @@ STATIC MP_DEFINE_CONST_DICT(memorymap_addressrange_locals_dict, memorymap_addres
//| def __setitem__(self, index: int, value: int) -> None:
//| """Set the value(s) at the given index.
//|
//| 1, 2, 4 and 8 byte aligned writes will be done in one transaction.
//| 1, 2, 4 and 8 byte aligned writes will be done in one transaction
//| when possible.
//| All others may use multiple transactions."""
//| ...
//|
@ -154,9 +158,7 @@ STATIC mp_obj_t memorymap_addressrange_subscr(mp_obj_t self_in, mp_obj_t index_i
mp_raise_NotImplementedError(translate("array/bytes required on right side"));
}
if (!common_hal_memorymap_addressrange_set_bytes(self, slice.start, src_items, src_len)) {
mp_raise_RuntimeError(translate("Unable to write to address."));
}
common_hal_memorymap_addressrange_set_bytes(self, slice.start, src_items, src_len);
return mp_const_none;
#else
return MP_OBJ_NULL; // op not supported
@ -184,9 +186,7 @@ STATIC mp_obj_t memorymap_addressrange_subscr(mp_obj_t self_in, mp_obj_t index_i
mp_arg_validate_int_range(byte_value, 0, 255, MP_QSTR_bytes);
uint8_t short_value = byte_value;
if (!common_hal_memorymap_addressrange_set_bytes(self, index, &short_value, 1)) {
mp_raise_RuntimeError(translate("Unable to write to address."));
}
common_hal_memorymap_addressrange_set_bytes(self, index, &short_value, 1);
return mp_const_none;
}
}

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@ -33,14 +33,14 @@ extern const mp_obj_type_t memorymap_addressrange_type;
void common_hal_memorymap_addressrange_construct(memorymap_addressrange_obj_t *self, uint8_t *start_address, size_t length);
uint32_t common_hal_memorymap_addressrange_get_length(const memorymap_addressrange_obj_t *self);
size_t common_hal_memorymap_addressrange_get_length(const memorymap_addressrange_obj_t *self);
bool common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self,
uint32_t start_index, uint8_t *values, uint32_t len);
void common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self,
size_t start_index, uint8_t *values, size_t len);
// len and values are intentionally swapped to signify values is an output and
// also leverage the compiler to validate uses are expected.
void common_hal_memorymap_addressrange_get_bytes(const memorymap_addressrange_obj_t *self,
uint32_t start_index, uint32_t len, uint8_t *values);
size_t start_index, size_t len, uint8_t *values);
#endif // MICROPY_INCLUDED_SHARED_BINDINGS_MEMORYMAP_ADDRESSRANGE_H