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Merge pull request #6961 from flom84/stm32f4-dfu-mode-fixes 

Update STM DFU mode software implementation.
This commit is contained in:
Jeff Epler 2022-09-29 16:02:13 -05:00 committed by GitHub
parent 03f02c7e8a 7af8a23ddf
commit 66372605c4
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 13 additions and 4 deletions
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17
ports/stm/supervisor/port.c
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@ -290,13 +290,22 @@ condition and generating hardware reset or using Go command to execute user code
HAL_RCC_DeInit();
HAL_DeInit();
// disable all interupts
__disable_irq();
// Disable all pending interrupts using NVIC
for (uint8_t i = 0; i < MP_ARRAY_SIZE(NVIC->ICER); ++i) {
NVIC->ICER[i] = 0xFFFFFFFF;
}
// Clear all pending interrupts
for (uint8_t i = 0; i < (sizeof(NVIC->ICPR) / NVIC->ICPR[0]); ++i) {
// if it is necessary to ensure an interrupt will not be triggered after disabling it in the NVIC,
// add a DSB instruction and then an ISB instruction. (ARM Cortex™-M Programming Guide to
// Memory Barrier Instructions, 4.6 Disabling Interrupts using NVIC)
__DSB();
__ISB();
// Clear all pending interrupts using NVIC
for (uint8_t i = 0; i < MP_ARRAY_SIZE(NVIC->ICPR); ++i) {
NVIC->ICPR[i] = 0xFFFFFFFF;
}
// information about jump addresses has been taken from STM AN2606.
#if defined(STM32F4)
__set_MSP(*((uint32_t *)0x1FFF0000));