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clock fixes

This commit is contained in:
Hierophect 2019-09-24 13:17:46 -04:00
parent 31a22858d5
commit 61a45cdaed
2 changed files with 9 additions and 6 deletions
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5
ports/stm32f4/boards/pybv1_1/mpconfigboard.mk
View File

@ -2,9 +2,10 @@ USB_VID = 0x239A
USB_PID = 0x8056
USB_PRODUCT = "Pyboard Version 1.1"
USB_MANUFACTURER = "STMicroelectronics"
USB_DEVICES = "CDC"
USB_DEVICES = "CDC,MSC"
DISABLE_FILESYSTEM = 1
INTERNAL_FLASH_FILESYSTEM = 1
#DISABLE_FILESYSTEM = 1
LONGINT_IMPL = NONE
MCU_SERIES = m4

10
ports/stm32f4/peripherals/stm32f4/stm32f405xx/clocks.c
View File

@ -27,6 +27,8 @@
#include "stm32f4xx_hal.h"
void stm32f4_peripherals_clocks_init(void) {
//TODO: All parameters must be moved to board level, due to relationship with HSE Osc.
//System clock init
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
@ -44,9 +46,9 @@ void stm32f4_peripherals_clocks_init(void) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
@ -55,7 +57,7 @@ void stm32f4_peripherals_clocks_init(void) {
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
}