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update watchdog implementation for atmel-samd

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MicroDev 2023-03-15 13:14:21 +05:30
parent 668f96e6e9
commit 5e0dce286e
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GPG Key ID: 2C0867BE60967730
3 changed files with 76 additions and 44 deletions
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107
ports/atmel-samd/common-hal/watchdog/WatchDogTimer.c
View File

@ -34,58 +34,69 @@
#include "component/wdt.h"
#define SYNC_CTRL_WRITE while (WDT->SYNCBUSY.reg) {}
static void watchdog_disable(void) {
// disable watchdog
WDT->CTRLA.reg = 0;
SYNC_CTRL_WRITE
}
static void watchdog_enable(watchdog_watchdogtimer_obj_t *self) {
// disable watchdog for config
watchdog_disable();
int wdt_cycles = (int)(self->timeout * 1024);
if (wdt_cycles < 8) {
wdt_cycles = 8;
}
// ceil(log2(n)) = 32 - __builtin_clz(n - 1) when n > 1 (if int is 32 bits)
int log2_wdt_cycles = (sizeof(int) * CHAR_BIT) - __builtin_clz(wdt_cycles - 1);
int setting = log2_wdt_cycles - 3; // CYC8_Val is 0
OSC32KCTRL->OSCULP32K.bit.EN1K = 1; // Enable out 1K (for WDT)
WDT->INTENCLR.reg = WDT_INTENCLR_EW; // Disable early warning interrupt
WDT->CONFIG.bit.PER = setting; // Set period for chip reset
WDT->CTRLA.bit.WEN = 0; // Disable window mode
SYNC_CTRL_WRITE
common_hal_watchdog_feed(self); // Clear watchdog interval
WDT->CTRLA.bit.ENABLE = 1; // Start watchdog now!
SYNC_CTRL_WRITE
}
void common_hal_watchdog_feed(watchdog_watchdogtimer_obj_t *self) {
WDT->CLEAR.reg = WDT_CLEAR_CLEAR_KEY;
}
void common_hal_watchdog_deinit(watchdog_watchdogtimer_obj_t *self) {
if (self->mode == WATCHDOGMODE_RESET) {
mp_raise_RuntimeError(translate("WatchDogTimer cannot be deinitialized once mode is set to RESET"));
} else {
self->mode = WATCHDOGMODE_NONE;
if (self->mode == WATCHDOGMODE_NONE) {
return;
}
watchdog_disable();
self->mode = WATCHDOGMODE_NONE;
}
void watchdog_reset(void) {
common_hal_watchdog_deinit(&common_hal_mcu_watchdogtimer_obj);
}
mp_float_t common_hal_watchdog_get_timeout(watchdog_watchdogtimer_obj_t *self) {
return self->timeout;
}
STATIC void setup_wdt(watchdog_watchdogtimer_obj_t *self, int setting) {
OSC32KCTRL->OSCULP32K.bit.EN1K = 1; // Enable out 1K (for WDT)
// disable watchdog for config
WDT->CTRLA.reg = 0;
while (WDT->SYNCBUSY.reg) { // Sync CTRL write
}
WDT->INTENCLR.reg = WDT_INTENCLR_EW; // Disable early warning interrupt
WDT->CONFIG.bit.PER = setting; // Set period for chip reset
WDT->CTRLA.bit.WEN = 0; // Disable window mode
while (WDT->SYNCBUSY.reg) { // Sync CTRL write
}
common_hal_watchdog_feed(self); // Clear watchdog interval
WDT->CTRLA.bit.ENABLE = 1; // Start watchdog now!
while (WDT->SYNCBUSY.reg) {
}
}
void common_hal_watchdog_set_timeout(watchdog_watchdogtimer_obj_t *self, mp_float_t new_timeout) {
int wdt_cycles = (int)(new_timeout * 1024);
if (wdt_cycles < 8) {
wdt_cycles = 8;
if (!(self->timeout < new_timeout || self->timeout > new_timeout)) {
return;
}
if (wdt_cycles > 16384) {
mp_raise_ValueError(translate("timeout duration exceeded the maximum supported value"));
}
// ceil(log2(n)) = 32 - __builtin_clz(n - 1) when n > 1 (if int is 32 bits)
int log2_wdt_cycles = (sizeof(int) * CHAR_BIT) - __builtin_clz(wdt_cycles - 1);
int setting = log2_wdt_cycles - 3; // CYC8_Val is 0
float timeout = (8 << setting) / 1024.f;
mp_arg_validate_int_max(new_timeout, 16, MP_QSTR_timeout);
self->timeout = new_timeout;
if (self->mode == WATCHDOGMODE_RESET) {
setup_wdt(self, setting);
watchdog_enable(self);
}
self->timeout = timeout;
}
watchdog_watchdogmode_t common_hal_watchdog_get_mode(watchdog_watchdogtimer_obj_t *self) {
@ -93,13 +104,23 @@ watchdog_watchdogmode_t common_hal_watchdog_get_mode(watchdog_watchdogtimer_obj_
}
void common_hal_watchdog_set_mode(watchdog_watchdogtimer_obj_t *self, watchdog_watchdogmode_t new_mode) {
if (self->mode != new_mode) {
if (new_mode == WATCHDOGMODE_RAISE) {
mp_raise_NotImplementedError(translate("RAISE mode is not implemented"));
} else if (new_mode == WATCHDOGMODE_NONE) {
common_hal_watchdog_deinit(self);
}
self->mode = new_mode;
common_hal_watchdog_set_timeout(self, self->timeout);
if (self->mode == new_mode) {
return;
}
switch (new_mode) {
case WATCHDOGMODE_NONE:
common_hal_watchdog_deinit(self);
break;
case WATCHDOGMODE_RAISE:
mp_raise_NotImplementedError(NULL);
break;
case WATCHDOGMODE_RESET:
watchdog_enable(self);
break;
default:
return;
}
self->mode = new_mode;
}

2
ports/atmel-samd/common-hal/watchdog/WatchDogTimer.h
View File

@ -38,6 +38,6 @@ struct _watchdog_watchdogtimer_obj_t {
};
// This needs to be called in order to disable the watchdog
// void watchdog_reset(void);
void watchdog_reset(void);
#endif // MICROPY_INCLUDED_RASPBERRYPI_COMMON_HAL_WATCHDOG_WATCHDOGTIMER_H

11
ports/atmel-samd/supervisor/port.c
View File

@ -388,13 +388,16 @@ void reset_port(void) {
#if CIRCUITPY_BUSIO
reset_sercoms();
#endif
#if CIRCUITPY_AUDIOIO
audio_dma_reset();
audioout_reset();
#endif
#if CIRCUITPY_AUDIOBUSIO
pdmin_reset();
#endif
#if CIRCUITPY_AUDIOBUSIO_I2SOUT
i2sout_reset();
#endif
@ -406,14 +409,18 @@ void reset_port(void) {
#if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE
touchin_reset();
#endif
eic_reset();
#if CIRCUITPY_PULSEIO
pulsein_reset();
pulseout_reset();
#endif
#if CIRCUITPY_PWMIO
pwmout_reset();
#endif
#if CIRCUITPY_PWMIO || CIRCUITPY_AUDIOIO || CIRCUITPY_FREQUENCYIO
reset_timers();
#endif
@ -423,6 +430,10 @@ void reset_port(void) {
analogout_reset();
#endif
#if CIRCUITPY_WATCHDOG
watchdog_reset();
#endif
reset_gclks();
#if CIRCUITPY_PEW