Redo RP2040 flash settings
This switches stage2 to C and uses Jinja to change the C code based on flash settings from https://github.com/adafruit/nvm.toml. It produces the fastest settings for the given set of external flashes. Flash size is no longer hard coded so switching flashes with similar capabilities but different sizes should *just work*. This PR also places "ITCM" code in RAM to save the XIP cache for code execution. Further optimization is possible. A blink code.py still requires a number of flash fetches every blink. Fixes #4041
This commit is contained in:
Scott Shawcroft
parent
2589515342
commit
5d2b60cbf6
6
.gitmodules
vendored
6
.gitmodules
vendored
@ -173,4 +173,8 @@
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url = https://github.com/adafruit/Adafruit_CircuitPython_LC709203F
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[submodule "ports/raspberrypi/sdk"]
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path = ports/raspberrypi/sdk
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url = https://github.com/raspberrypi/pico-sdk.git
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url = https://github.com/adafruit/pico-sdk.git
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[submodule "data/nvm.toml"]
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path = data/nvm.toml
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url = https://github.com/adafruit/nvm.toml.git
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branch = main
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1
data/nvm.toml
Submodule
1
data/nvm.toml
Submodule
@ -0,0 +1 @@
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Subproject commit da5054787d5a428823b5bd032e810edf8105fc02
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@ -106,7 +106,7 @@ INC += -I. \
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-I$(BUILD)
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# Pico specific configuration
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CFLAGS += -DPICO_ON_DEVICE=1 -DPICO_NO_BINARY_INFO=0 -DPICO_TIME_DEFAULT_ALARM_POOL_DISABLED=1 -DPICO_DIVIDER_CALL_IDIV0=0 -DPICO_DIVIDER_CALL_LDIV0=0 -DPICO_DIVIDER_HARDWARE=1 -DPICO_DOUBLE_ROM=1 -DPICO_FLOAT_ROM=1 -DPICO_MULTICORE=1 -DPICO_BITS_IN_RAM=0 -DPICO_DIVIDER_IN_RAM=0 -DPICO_DOUBLE_PROPAGATE_NANS=0 -DPICO_DOUBLE_IN_RAM=0 -DPICO_MEM_IN_RAM=0 -DPICO_FLOAT_IN_RAM=0 -DPICO_FLOAT_PROPAGATE_NANS=1 -DPICO_NO_FLASH=0 -DPICO_COPY_TO_RAM=0 -DPICO_DISABLE_SHARED_IRQ_HANDLERS=0 -DPICO_NO_BI_BOOTSEL_VIA_DOUBLE_RESET=0
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CFLAGS += -DRASPBERRYPI -DPICO_ON_DEVICE=1 -DPICO_NO_BINARY_INFO=0 -DPICO_TIME_DEFAULT_ALARM_POOL_DISABLED=1 -DPICO_DIVIDER_CALL_IDIV0=0 -DPICO_DIVIDER_CALL_LDIV0=0 -DPICO_DIVIDER_HARDWARE=1 -DPICO_DOUBLE_ROM=1 -DPICO_FLOAT_ROM=1 -DPICO_MULTICORE=1 -DPICO_BITS_IN_RAM=0 -DPICO_DIVIDER_IN_RAM=0 -DPICO_DOUBLE_PROPAGATE_NANS=0 -DPICO_DOUBLE_IN_RAM=0 -DPICO_MEM_IN_RAM=0 -DPICO_FLOAT_IN_RAM=0 -DPICO_FLOAT_PROPAGATE_NANS=1 -DPICO_NO_FLASH=0 -DPICO_COPY_TO_RAM=0 -DPICO_DISABLE_SHARED_IRQ_HANDLERS=0 -DPICO_NO_BI_BOOTSEL_VIA_DOUBLE_RESET=0
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OPTIMIZATION_FLAGS ?= -O3
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# TinyUSB defines
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CFLAGS += -DTUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX=1 -DCFG_TUSB_MCU=OPT_MCU_RP2040 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024
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@ -169,7 +169,7 @@ SRC_SDK := \
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src/rp2_common/hardware_irq/irq.c \
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src/rp2_common/hardware_pio/pio.c \
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src/rp2_common/hardware_pll/pll.c \
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src/rp2_common/hardware_rtc/rtc.c \
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src/rp2_common/hardware_rtc/rtc.c \
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src/rp2_common/hardware_spi/spi.c \
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src/rp2_common/hardware_sync/sync.c \
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src/rp2_common/hardware_timer/timer.c \
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@ -270,9 +270,15 @@ $(BUILD)/boot2.bin: $(BUILD)/boot2.elf
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$(STEPECHO) "OBJCOPY $<"
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$(Q)$(OBJCOPY) -O binary $< $@
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$(BUILD)/boot2.elf: $(BOOT2_S_UPPER) | $(BUILD)/
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$(BUILD)/stage2.c: stage2.c.jinja gen_stage2.py | $(BUILD)/
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$(STEPECHO) "GEN $<"
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$(Q)$(PYTHON3) gen_stage2.py $< $@ $(EXTERNAL_FLASH_DEVICES)
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$(BUILD)/boot2.elf: $(BUILD)/stage2.c
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$(STEPECHO) "BOOT $<"
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$(Q)$(CC) $(CFLAGS) $(BOOT2_S_CFLAGS) -Isdk/src/rp2_common/boot_stage2/asminclude --specs=nosys.specs -nostartfiles -Wl,-T,sdk/src/rp2_common/boot_stage2/boot_stage2.ld -o $@ $<
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$(Q)$(CC) $(CFLAGS) $(BOOT2_S_CFLAGS) -Os -ggdb3 -I. -fPIC --specs=nosys.specs -nostartfiles -Wl,-T,boot_stage2.ld -Wl,-Map=$@.map -o $@ $<
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$(Q)$(SIZE) $@
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SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
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@ -285,7 +291,7 @@ $(BUILD)/firmware.elf: $(OBJ) link.ld
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$(BUILD)/firmware.bin: $(BUILD)/firmware.elf
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$(STEPECHO) "Create $@"
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$(Q)$(OBJCOPY) -O binary $^ $@
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$(Q)$(OBJCOPY) -O binary -R .dtcm_bss $^ $@
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$(BUILD)/firmware.uf2: $(BUILD)/firmware.bin
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$(STEPECHO) "Create $@"
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@ -12,6 +12,3 @@
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#define DEFAULT_UART_BUS_RX (&pin_GPIO1)
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#define DEFAULT_UART_BUS_TX (&pin_GPIO0)
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// Flash chip is GD25Q64 connected over QSPI
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#define TOTAL_FLASH_SIZE (8 * 1024 * 1024)
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@ -6,4 +6,4 @@ USB_MANUFACTURER = "Adafruit"
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CHIP_VARIANT = RP2040
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CHIP_FAMILY = rp2
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INTERNAL_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "GD25Q64C"
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@ -28,8 +28,6 @@
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#define DEFAULT_UART_BUS_RX (&pin_GPIO1)
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#define DEFAULT_UART_BUS_TX (&pin_GPIO0)
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#define TOTAL_FLASH_SIZE (2 * 1024 * 1024)
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// These pins are unconnected
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#define IGNORE_PIN_GPIO2 1
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#define IGNORE_PIN_GPIO22 1
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@ -6,6 +6,6 @@ USB_MANUFACTURER = "Pimoroni"
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CHIP_VARIANT = RP2040
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CHIP_FAMILY = rp2
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INTERNAL_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "W25Q16JV_IQ"
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CIRCUITPY__EVE = 1
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@ -38,8 +38,6 @@
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#define DEFAULT_UART_BUS_RX (&pin_GPIO1)
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#define DEFAULT_UART_BUS_TX (&pin_GPIO0)
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#define TOTAL_FLASH_SIZE (16 * 1024 * 1024)
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// These pins are unconnected
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#define IGNORE_PIN_GPIO3 1
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#define IGNORE_PIN_GPIO10 1
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@ -6,6 +6,6 @@ USB_MANUFACTURER = "Pimoroni"
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CHIP_VARIANT = RP2040
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CHIP_FAMILY = rp2
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INTERNAL_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "W25Q128JV_IQ"
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CIRCUITPY__EVE = 1
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@ -7,8 +7,6 @@
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#define MICROPY_HW_USER_SW (&pin_GPIO23)
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#define TOTAL_FLASH_SIZE (8 * 1024 * 1024)
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// These pins are unconnected
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#define IGNORE_PIN_GPIO8 1
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#define IGNORE_PIN_GPIO9 1
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@ -6,6 +6,6 @@ USB_MANUFACTURER = "Pimoroni"
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CHIP_VARIANT = RP2040
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CHIP_FAMILY = rp2
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INTERNAL_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "W25Q64JV_IQ"
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CIRCUITPY__EVE = 1
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@ -12,6 +12,3 @@
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// #define DEFAULT_UART_BUS_RX (&pin_PA11)
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// #define DEFAULT_UART_BUS_TX (&pin_PA10)
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// Flash chip is GD25Q64 connected over QSPI
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#define TOTAL_FLASH_SIZE (8 * 1024 * 1024)
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@ -6,4 +6,4 @@ USB_MANUFACTURER = "Adafruit"
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CHIP_VARIANT = RP2040
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CHIP_FAMILY = rp2
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INTERNAL_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "W25Q32JV_IQ"
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@ -1,18 +1,2 @@
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// LEDs
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// #define MICROPY_HW_LED_STATUS (&pin_PA17)
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#define MICROPY_HW_BOARD_NAME "Raspberry Pi Pico"
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#define MICROPY_HW_MCU_NAME "rp2040"
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// #define DEFAULT_I2C_BUS_SCL (&pin_PA23)
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// #define DEFAULT_I2C_BUS_SDA (&pin_PA22)
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// #define DEFAULT_SPI_BUS_SCK (&pin_PB11)
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// #define DEFAULT_SPI_BUS_MOSI (&pin_PB10)
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// #define DEFAULT_SPI_BUS_MISO (&pin_PA12)
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// #define DEFAULT_UART_BUS_RX (&pin_PA11)
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// #define DEFAULT_UART_BUS_TX (&pin_PA10)
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// Flash chip is W25Q16JVUXIQ connected over QSPI
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#define TOTAL_FLASH_SIZE (2 * 1024 * 1024)
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@ -6,8 +6,6 @@ USB_MANUFACTURER = "Raspberry Pi"
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CHIP_VARIANT = RP2040
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CHIP_FAMILY = rp2
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INTERNAL_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "W25Q16JV_IQ"
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CIRCUITPY__EVE = 1
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BOOT2_S_UPPER = sdk/src/rp2_common/boot_stage2/boot2_w25q080.S
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@ -12,6 +12,3 @@
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#define DEFAULT_UART_BUS_RX (&pin_GPIO1)
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#define DEFAULT_UART_BUS_TX (&pin_GPIO0)
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// Flash chip is GD25Q128 connected over QSPI
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#define TOTAL_FLASH_SIZE (16 * 1024 * 1024)
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@ -6,4 +6,4 @@ USB_MANUFACTURER = "SparkFun"
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CHIP_VARIANT = RP2040
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CHIP_FAMILY = rp2
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INTERNAL_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "W25Q128JV_IM"
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@ -12,6 +12,3 @@
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#define DEFAULT_UART_BUS_RX (&pin_GPIO1)
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#define DEFAULT_UART_BUS_TX (&pin_GPIO0)
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// Flash chip is GD25Q128 connected over QSPI
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#define TOTAL_FLASH_SIZE (16 * 1024 * 1024)
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@ -6,4 +6,4 @@ USB_MANUFACTURER = "SparkFun"
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CHIP_VARIANT = RP2040
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CHIP_FAMILY = rp2
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INTERNAL_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "W25Q128JV_IM"
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13
ports/raspberrypi/boot_stage2.ld
Normal file
13
ports/raspberrypi/boot_stage2.ld
Normal file
@ -0,0 +1,13 @@
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MEMORY {
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/* We are loaded to the top 256 bytes of SRAM, which is above the bootrom
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stack. Note 4 bytes occupied by checksum. */
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SRAM(rx) : ORIGIN = 0x20041f00, LENGTH = 252
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}
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SECTIONS {
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. = ORIGIN(SRAM);
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.text : {
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*(.entry.*)
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*(.text.*)
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} >SRAM
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}
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82
ports/raspberrypi/gen_stage2.py
Normal file
82
ports/raspberrypi/gen_stage2.py
Normal file
@ -0,0 +1,82 @@
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import sys
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import cascadetoml
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import pathlib
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import typer
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from jinja2 import Template
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def main(input_template: pathlib.Path, output_path: pathlib.Path, skus: str = typer.Argument("")):
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if ", " in skus:
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skus = skus.split(", ")
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else:
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skus = [skus]
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skus = ['sku="{}"'.format(f) for f in skus]
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flashes = cascadetoml.filter_toml(pathlib.Path("../../data/nvm.toml"), skus)
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if len(skus) == 0:
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print("Set EXTERNAL_FLASH_DEVICES in mpconfigboard.mk with all possible flash skus")
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raise typer.Exit(code=1)
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def all_have(nvms, key):
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for nvm in nvms:
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if not nvm.get(key, False):
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return False
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return True
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def all_match(nvms, key, default=None):
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shared_value = nvms[0].get(key, default)
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for nvm in nvms:
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this_value = nvm.get(key, default)
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if this_value != shared_value:
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print(
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"{}.{} = {} does not match {}".format(
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nvm["sku"], key, this_value, shared_value
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)
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)
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return None
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return shared_value
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quad_enable_status_byte = all_match(flashes["nvm"], "quad_enable_status_byte", 0)
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quad_enable_bit_mask = all_match(flashes["nvm"], "quad_enable_bit_mask")
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continuous_status_write = all_have(flashes["nvm"], "01_continuous_status_write")
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split_status_write = all_have(flashes["nvm"], "write_status_register_split")
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e7_quad_word_read = all_have(flashes["nvm"], "e7_quad_word_read")
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quad_ok = quad_enable_status_byte is not None and quad_enable_bit_mask is not None
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max_clock_speed_mhz = min((x.get("max_clock_speed_mhz", 1000) for x in flashes["nvm"]))
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# Check that we have a consistent way to set quad enable.
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if continuous_status_write is None and split_status_write is None:
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print("quad not ok", continuous_status_write, split_status_write)
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quad_ok = False
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clock_divider = 4
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read_command = 0x03
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wait_cycles = 0
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if quad_ok:
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if e7_quad_word_read:
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read_command = 0xE7
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wait_cycles = 2
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else:
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read_command = 0xEB
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wait_cycles = 4
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flash_settings = {
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"quad_ok": quad_ok,
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"quad_enable_status_byte": quad_enable_status_byte,
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"quad_enable_bit_mask": quad_enable_bit_mask,
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"split_status_write": split_status_write,
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"clock_divider": clock_divider,
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"read_command": read_command,
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"wait_cycles": wait_cycles,
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}
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template = Template(input_template.read_text())
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output_path.write_text(template.render(flash_settings))
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if __name__ == "__main__":
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typer.run(main)
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@ -174,6 +174,40 @@ SECTIONS
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__data_end__ = .;
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} > RAM AT> FLASH_FIRMWARE
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.itcm :
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{
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. = ALIGN(4);
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*(.itcm.*)
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. = ALIGN(4);
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} > RAM AT> FLASH_FIRMWARE
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_ld_itcm_destination = ADDR(.itcm);
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_ld_itcm_flash_copy = LOADADDR(.itcm);
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_ld_itcm_size = SIZEOF(.itcm);
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.dtcm_data :
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{
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. = ALIGN(4);
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*(.dtcm_data.*)
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. = ALIGN(4);
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} > RAM AT> FLASH_FIRMWARE
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_ld_dtcm_data_destination = ADDR(.dtcm_data);
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_ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data);
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_ld_dtcm_data_size = SIZEOF(.dtcm_data);
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.dtcm_bss :
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{
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. = ALIGN(4);
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*(.dtcm_bss.*)
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. = ALIGN(4);
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} > RAM AT> RAM
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_ld_dtcm_bss_start = ADDR(.dtcm_bss);
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_ld_dtcm_bss_size = SIZEOF(.dtcm_bss);
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.uninitialized_data (COPY): {
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. = ALIGN(4);
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*(.uninitialized_data*)
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@ -55,3 +55,5 @@ USB_SERIAL_NUMBER_LENGTH = 16
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# Number of USB endpoint pairs.
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USB_NUM_EP = 8
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INTERNAL_FLASH_FILESYSTEM = 1
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@ -1 +1 @@
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Subproject commit fc10a97c386f65c1a44c68684fe52a56aaf50df0
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Subproject commit 12538a7c456607b7abe3b88c606c62b6f7342b46
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197
ports/raspberrypi/stage2.c.jinja
Normal file
197
ports/raspberrypi/stage2.c.jinja
Normal file
@ -0,0 +1,197 @@
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#include "sdk/src/rp2040/hardware_structs/include/hardware/structs/ssi.h"
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#include "sdk/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h"
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#include "sdk/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h"
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#include "sdk/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h"
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#include "sdk/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h"
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// "Mode bits" are 8 special bits sent immediately after
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// the address bits in a "Read Data Fast Quad I/O" command sequence.
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// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
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// next read does not require the 0xeb instruction prefix.
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#define MODE_CONTINUOUS_READ 0xa0
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// Define interface width: single/dual/quad IO
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{% if quad_ok %}
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#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
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#define TRANSACTION_TYPE SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A
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// Note that the INST_L field is used to select what XIP data gets pushed into
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// the TX FIFO:
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// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
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// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
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#define INSTRUCTION_LENGTH SSI_SPI_CTRLR0_INST_L_VALUE_NONE
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#define READ_INSTRUCTION MODE_CONTINUOUS_READ
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#define ADDR_L 8 // 6 for address, 2 for mode
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{% else %}
|
||||
#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_STD
|
||||
#define TRANSACTION_TYPE SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A
|
||||
#define INSTRUCTION_LENGTH SSI_SPI_CTRLR0_INST_L_VALUE_8B
|
||||
#define READ_INSTRUCTION (0x{{ '%02x' % read_command }})
|
||||
#define ADDR_L 6 // * 4 = 24
|
||||
{% endif %}
|
||||
|
||||
#define CMD_READ_STATUS1 0x05
|
||||
#define CMD_READ_STATUS2 0x35
|
||||
#define CMD_WRITE_ENABLE 0x06
|
||||
#define CMD_WRITE_STATUS1 0x01
|
||||
#define CMD_WRITE_STATUS2 0x31
|
||||
|
||||
#define SREG_DATA 0x02
|
||||
|
||||
static uint32_t wait_and_read(uint8_t);
|
||||
static uint8_t read_flash_sreg(uint8_t status_command);
|
||||
|
||||
// This function is use by the bootloader to enable the XIP flash. It is also
|
||||
// used by the SDK to reinit XIP after doing non-read flash interactions such as
|
||||
// writing or erasing. This code must compile down to position independent
|
||||
// assembly because we don't know where in RAM it'll be when run.
|
||||
|
||||
// This must be the first defined function so that it is placed at the start of
|
||||
// memory where the bootloader jumps to!
|
||||
void __attribute__((section(".entry._stage2_boot"), used)) _stage2_boot(void) {
|
||||
uint32_t lr;
|
||||
asm ("MOV %0, LR\n" : "=r" (lr) );
|
||||
|
||||
// Set aggressive pad configuration for QSPI
|
||||
// - SCLK 8mA drive, no slew limiting
|
||||
// - SDx disable input Schmitt to reduce delay
|
||||
|
||||
// SCLK
|
||||
pads_qspi_hw->io[0] = PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB |
|
||||
PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS;
|
||||
|
||||
// Data lines
|
||||
uint32_t data_settings = pads_qspi_hw->io[1];
|
||||
data_settings &= ~PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS;
|
||||
pads_qspi_hw->io[2] = data_settings;
|
||||
{% if quad_ok %}
|
||||
pads_qspi_hw->io[1] = data_settings;
|
||||
pads_qspi_hw->io[3] = data_settings;
|
||||
pads_qspi_hw->io[4] = data_settings;
|
||||
{% endif %}
|
||||
|
||||
// Disable the SSI so we can change the settings.
|
||||
ssi_hw->ssienr = 0;
|
||||
|
||||
// QSPI config
|
||||
ssi_hw->baudr = {{ clock_divider }}; // 125 mhz / clock divider
|
||||
|
||||
// Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
|
||||
// if the flash launches data on SCLK posedge, we capture it at the time that
|
||||
// the next SCLK posedge is launched. This is shortly before that posedge
|
||||
// arrives at the flash, so data hold time should be ok. For
|
||||
// PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
|
||||
ssi_hw->rx_sample_dly = 1;
|
||||
|
||||
// Set a temporary mode for doing simple commands.
|
||||
ssi_hw->ctrlr0 = (7 << SSI_CTRLR0_DFS_32_LSB) | // 8 bits per data frame
|
||||
(SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB);
|
||||
|
||||
ssi_hw->ssienr = 0x1;
|
||||
|
||||
{% if quad_ok %}
|
||||
// Program status register.
|
||||
// Enable SSI and select slave 0
|
||||
{% if quad_enable_status_byte == 1 %}
|
||||
uint8_t result = read_flash_sreg(CMD_READ_STATUS1);
|
||||
{% elif quad_enable_status_byte == 2 %}
|
||||
uint8_t result = read_flash_sreg(CMD_READ_STATUS2);
|
||||
{% endif %}
|
||||
if (result != {{ quad_enable_bit_mask }}) {
|
||||
ssi_hw->dr0 = (uint8_t) CMD_WRITE_ENABLE;
|
||||
wait_and_read(1);
|
||||
|
||||
{% if split_status_write %}
|
||||
{% if quad_enable_status_byte == 1 %}
|
||||
ssi_hw->dr0 = (uint8_t) CMD_WRITE_STATUS1;
|
||||
{% elif quad_enable_status_byte == 2 %}
|
||||
ssi_hw->dr0 = (uint8_t) CMD_WRITE_STATUS2;
|
||||
{% endif %}
|
||||
ssi_hw->dr0 = {{ quad_enable_bit_mask }};
|
||||
wait_and_read(2);
|
||||
{% else %}
|
||||
ssi_hw->dr0 = (uint8_t) CMD_WRITE_STATUS1;
|
||||
{% if quad_enable_status_byte == 2 %}
|
||||
ssi_hw->dr0 = 0x0;
|
||||
{% endif %}
|
||||
ssi_hw->dr0 = {{ quad_enable_bit_mask }};
|
||||
wait_and_read({{ quad_enable_status_byte + 1 }});
|
||||
{% endif %}
|
||||
// Wait for the write to complete.
|
||||
while ((read_flash_sreg(CMD_READ_STATUS1) & 0x1) != 0) {}
|
||||
}
|
||||
{% endif %}
|
||||
|
||||
// Disable SSI again so that it can be reconfigured
|
||||
ssi_hw->ssienr = 0;
|
||||
|
||||
// Do a single read to get us in continuous mode.
|
||||
|
||||
// Final SSI ctrlr0 settings. We only change the SPI specific settings later.
|
||||
ssi_hw->ctrlr0 = (FRAME_FORMAT << SSI_CTRLR0_SPI_FRF_LSB) | // Quad I/O mode
|
||||
(31 << SSI_CTRLR0_DFS_32_LSB) | // 32 data bits
|
||||
(SSI_CTRLR0_TMOD_VALUE_EEPROM_READ << SSI_CTRLR0_TMOD_LSB); // Send INST/ADDR, Receive Data
|
||||
|
||||
ssi_hw->ctrlr1 = 0; // Single 32b read
|
||||
|
||||
{% if quad_ok %}
|
||||
ssi_hw->spi_ctrlr0 = (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | // Address + mode bits
|
||||
// Hi-Z dummy clocks following address + mode
|
||||
({{ wait_cycles }} << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |
|
||||
// 8-bit instruction
|
||||
(SSI_SPI_CTRLR0_INST_L_VALUE_8B << SSI_SPI_CTRLR0_INST_L_LSB) |
|
||||
// Send Command in serial mode then address in Quad I/O mode
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A << SSI_SPI_CTRLR0_TRANS_TYPE_LSB);
|
||||
|
||||
// Re-enable the SSI
|
||||
ssi_hw->ssienr = 1;
|
||||
|
||||
// Do a single read to get us in continuous mode.
|
||||
ssi_hw->dr0 = 0x{{ '%02x' % read_command }};
|
||||
ssi_hw->dr0 = MODE_CONTINUOUS_READ;
|
||||
wait_and_read(2);
|
||||
|
||||
// Disable the SSI to switch to no-command mode (because we're setup for continuous.)
|
||||
ssi_hw->ssienr = 0;
|
||||
{% endif %}
|
||||
|
||||
// Final SPI ctrlr0 settings.
|
||||
ssi_hw->spi_ctrlr0 = (READ_INSTRUCTION << SSI_SPI_CTRLR0_XIP_CMD_LSB) | // Mode bits to keep flash in continuous read mode
|
||||
(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | // Total number of address + mode bits
|
||||
({{ wait_cycles }} << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | // Hi-Z dummy clocks following address + mode
|
||||
(INSTRUCTION_LENGTH << SSI_SPI_CTRLR0_INST_L_LSB) | // Do not send a command, instead send XIP_CMD as mode bits after address
|
||||
(TRANSACTION_TYPE << SSI_SPI_CTRLR0_TRANS_TYPE_LSB); // Send Address in Quad I/O mode (and Command but that is zero bits long)
|
||||
|
||||
// Re-enable the SSI
|
||||
ssi_hw->ssienr = 1;
|
||||
|
||||
// If lr is 0, then we came from the bootloader.
|
||||
if (lr == 0) {
|
||||
uint32_t* vector_table = (uint32_t*) (XIP_BASE + 0x100);
|
||||
// Switch the vector table to immediately after the stage 2 area.
|
||||
*((uint32_t *) (PPB_BASE + M0PLUS_VTOR_OFFSET)) = (uint32_t) vector_table;
|
||||
// Set the top of the stack according to the vector table.
|
||||
asm volatile ("MSR msp, %0" : : "r" (vector_table[0]) : );
|
||||
// The reset handler is the second entry in the vector table
|
||||
asm volatile ("bx %0" : : "r" (vector_table[1]) : );
|
||||
// Doesn't return. It jumps to the reset handler instead.
|
||||
}
|
||||
// Otherwise we return.
|
||||
}
|
||||
|
||||
static uint32_t wait_and_read(uint8_t count) {
|
||||
while ((ssi_hw->sr & SSI_SR_TFE_BITS) == 0) {}
|
||||
while ((ssi_hw->sr & SSI_SR_BUSY_BITS) != 0) {}
|
||||
uint32_t result = 0;
|
||||
while (count > 0) {
|
||||
result = ssi_hw->dr0;
|
||||
count--;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static uint8_t read_flash_sreg(uint8_t status_command) {
|
||||
ssi_hw->dr0 = status_command;
|
||||
ssi_hw->dr0 = status_command;
|
||||
|
||||
return wait_and_read(2);
|
||||
}
|
||||
@ -51,17 +51,28 @@
|
||||
#define NO_CACHE 0xffffffff
|
||||
STATIC uint8_t _cache[SECTOR_SIZE];
|
||||
STATIC uint32_t _cache_lba = NO_CACHE;
|
||||
STATIC uint32_t _flash_size = 0;
|
||||
|
||||
void supervisor_flash_init(void) {
|
||||
bi_decl_if_func_used(bi_block_device(
|
||||
BINARY_INFO_MAKE_TAG('C', 'P'),
|
||||
"CircuitPython",
|
||||
RESERVED_FLASH,
|
||||
TOTAL_FLASH_SIZE - RESERVED_FLASH,
|
||||
(1 * 1024 * 1024), // This is a minimum. We can't set it dynamically.
|
||||
NULL,
|
||||
BINARY_INFO_BLOCK_DEV_FLAG_READ |
|
||||
BINARY_INFO_BLOCK_DEV_FLAG_WRITE |
|
||||
BINARY_INFO_BLOCK_DEV_FLAG_PT_UNKNOWN));
|
||||
|
||||
// Read the RDID register to get the flash capacity.
|
||||
uint8_t cmd[] = {0x9f, 0, 0, 0};
|
||||
uint8_t data[4];
|
||||
flash_do_cmd(cmd, data, 4);
|
||||
uint8_t power_of_two = 21;
|
||||
if (data[3] >= 20 && data[3] < 30) {
|
||||
power_of_two = data[3];
|
||||
}
|
||||
_flash_size = 1 << power_of_two;
|
||||
}
|
||||
|
||||
uint32_t supervisor_flash_get_block_size(void) {
|
||||
@ -69,7 +80,7 @@ uint32_t supervisor_flash_get_block_size(void) {
|
||||
}
|
||||
|
||||
uint32_t supervisor_flash_get_block_count(void) {
|
||||
return (TOTAL_FLASH_SIZE - RESERVED_FLASH) / FILESYSTEM_BLOCK_SIZE;
|
||||
return (_flash_size - RESERVED_FLASH) / FILESYSTEM_BLOCK_SIZE;
|
||||
}
|
||||
|
||||
void port_internal_flash_flush(void) {
|
||||
|
||||
@ -74,10 +74,42 @@ STATIC void _binary_info(void) {
|
||||
// TODO: Add build attribute for debug builds. Needs newer CircuitPython with CIRCUITPY_DEBUG.
|
||||
}
|
||||
|
||||
extern uint32_t _ld_dtcm_bss_start;
|
||||
extern uint32_t _ld_dtcm_bss_size;
|
||||
extern uint32_t _ld_dtcm_data_destination;
|
||||
extern uint32_t _ld_dtcm_data_size;
|
||||
extern uint32_t _ld_dtcm_data_flash_copy;
|
||||
extern uint32_t _ld_itcm_destination;
|
||||
extern uint32_t _ld_itcm_size;
|
||||
extern uint32_t _ld_itcm_flash_copy;
|
||||
|
||||
safe_mode_t port_init(void) {
|
||||
_binary_info();
|
||||
// Set brown out.
|
||||
|
||||
// Copy all of the "tightly coupled memory" code and data to run from RAM.
|
||||
// This let's us use the 16k cache for dynamically used data and code.
|
||||
// We must do this before we try and call any of its code or load the data.
|
||||
for (uint32_t i = 0; i < ((size_t)&_ld_itcm_size) / 4; i++) {
|
||||
(&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i];
|
||||
// Now zero it out to evict the line from the XIP cache. Without this,
|
||||
// it'll stay in the XIP cache anyway.
|
||||
(&_ld_itcm_flash_copy)[i] = 0x0;
|
||||
}
|
||||
|
||||
// Copy all of the data to run from DTCM.
|
||||
for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_data_size) / 4; i++) {
|
||||
(&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i];
|
||||
// Now zero it out to evict the line from the XIP cache. Without this,
|
||||
// it'll stay in the XIP cache anyway.
|
||||
(&_ld_dtcm_data_flash_copy)[i] = 0x0;
|
||||
}
|
||||
|
||||
// Clear DTCM bss.
|
||||
for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_bss_size) / 4; i++) {
|
||||
(&_ld_dtcm_bss_start)[i] = 0;
|
||||
}
|
||||
|
||||
// Reset everything into a known state before board_init.
|
||||
reset_port();
|
||||
|
||||
|
||||
@ -31,10 +31,10 @@
|
||||
|
||||
#include "py/mpconfig.h"
|
||||
|
||||
#ifdef EXTERNAL_FLASH_DEVICES
|
||||
#include "supervisor/shared/external_flash/external_flash.h"
|
||||
#else
|
||||
#if INTERNAL_FLASH_FILESYSTEM
|
||||
#include "supervisor/shared/internal_flash.h"
|
||||
#else
|
||||
#include "supervisor/shared/external_flash/external_flash.h"
|
||||
#endif
|
||||
|
||||
void supervisor_flash_init(void);
|
||||
|
||||
@ -29,7 +29,7 @@
|
||||
#ifndef MICROPY_INCLUDED_SUPERVISOR_LINKER_H
|
||||
#define MICROPY_INCLUDED_SUPERVISOR_LINKER_H
|
||||
|
||||
#if defined(IMXRT10XX) || defined(FOMU) || defined(STM32H7)
|
||||
#if defined(IMXRT10XX) || defined(FOMU) || defined(STM32H7) || defined(RASPBERRYPI)
|
||||
#define PLACE_IN_DTCM_DATA(name) name __attribute__((section(".dtcm_data." #name)))
|
||||
#define PLACE_IN_DTCM_BSS(name) name __attribute__((section(".dtcm_bss." #name)))
|
||||
#define PLACE_IN_ITCM(name) __attribute__((section(".itcm." #name))) name
|
||||
|
||||
@ -36,7 +36,7 @@ enum {
|
||||
CIRCUITPY_SUPERVISOR_IMMOVABLE_ALLOC_COUNT =
|
||||
// stack + heap
|
||||
2
|
||||
#ifdef EXTERNAL_FLASH_DEVICES
|
||||
#if INTERNAL_FLASH_FILESYSTEM == 0
|
||||
+ 1
|
||||
#endif
|
||||
#if CIRCUITPY_USB_MIDI
|
||||
|
||||
@ -32,7 +32,13 @@ endif
|
||||
# Choose which flash filesystem impl to use.
|
||||
# (Right now INTERNAL_FLASH_FILESYSTEM and (Q)SPI_FLASH_FILESYSTEM are mutually exclusive.
|
||||
# But that might not be true in the future.)
|
||||
ifdef EXTERNAL_FLASH_DEVICES
|
||||
ifeq ($(INTERNAL_FLASH_FILESYSTEM),1)
|
||||
ifeq ($(DISABLE_FILESYSTEM),1)
|
||||
SRC_SUPERVISOR += supervisor/stub/internal_flash.c
|
||||
else
|
||||
SRC_SUPERVISOR += supervisor/internal_flash.c
|
||||
endif
|
||||
else
|
||||
CFLAGS += -DEXTERNAL_FLASH_DEVICES=$(EXTERNAL_FLASH_DEVICES) \
|
||||
|
||||
SRC_SUPERVISOR += supervisor/shared/external_flash/external_flash.c
|
||||
@ -42,12 +48,6 @@ ifdef EXTERNAL_FLASH_DEVICES
|
||||
ifeq ($(QSPI_FLASH_FILESYSTEM),1)
|
||||
SRC_SUPERVISOR += supervisor/qspi_flash.c supervisor/shared/external_flash/qspi_flash.c
|
||||
endif
|
||||
else
|
||||
ifeq ($(DISABLE_FILESYSTEM),1)
|
||||
SRC_SUPERVISOR += supervisor/stub/internal_flash.c
|
||||
else
|
||||
SRC_SUPERVISOR += supervisor/internal_flash.c
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(USB),FALSE)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user