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ports: Reformat more C and Python source code.

Browse Source 
These files that are reformatted only now fall under the list of files to
apply uncrustify/black formatting to.

Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George 2022-04-19 11:41:41 +10:00
parent fb10d15d47
commit 5c32111fa0
47 changed files with 322 additions and 328 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ports/rp2/boards/ARDUINO_NANO_RP2040_CONNECT/mpconfigboard.h
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@ -1,4 +1,4 @@
//Board config for Arduino Nano RP2040 Connect. // Board config for Arduino Nano RP2040 Connect.
// Board and hardware specific configuration // Board and hardware specific configuration
#define MICROPY_HW_BOARD_NAME "Arduino Nano RP2040 Connect" #define MICROPY_HW_BOARD_NAME "Arduino Nano RP2040 Connect"

4
ports/rp2/boards/PICO/mpconfigboard.h
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@ -1,6 +1,6 @@
// Board and hardware specific configuration // Board and hardware specific configuration
#define MICROPY_HW_BOARD_NAME "Raspberry Pi Pico" #define MICROPY_HW_BOARD_NAME "Raspberry Pi Pico"
#define MICROPY_HW_FLASH_STORAGE_BYTES (1408 * 1024) #define MICROPY_HW_FLASH_STORAGE_BYTES (1408 * 1024)
// Enable USB Mass Storage with FatFS filesystem. // Enable USB Mass Storage with FatFS filesystem.
//#define MICROPY_HW_USB_MSC (1) // #define MICROPY_HW_USB_MSC (1)

2
ports/samd/boards/ADAFRUIT_FEATHER_M0_EXPRESS/mpconfigboard.h
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@ -17,7 +17,7 @@
// USART pin assignments: Tx=PA10=SERCOM0/PAD[2], Rx=PA11==SERCOM0/PAD[3] // USART pin assignments: Tx=PA10=SERCOM0/PAD[2], Rx=PA11==SERCOM0/PAD[3]
#define CPU_FREQ (48000000) // For selecting Baud from clock. #define CPU_FREQ (48000000) // For selecting Baud from clock.
#define MP_PIN_GRP 0 // A=0, B=1 #define MP_PIN_GRP 0 // A=0, B=1
#define MP_TX_PIN 10 //'n' #define MP_TX_PIN 10 // 'n'
#define MP_RX_PIN 11 #define MP_RX_PIN 11
#define MP_PERIPHERAL_MUX 5 // 'n'th group of 2 pins #define MP_PERIPHERAL_MUX 5 // 'n'th group of 2 pins
#define USARTx SERCOM0 // SERCOM0: tx/rx #define USARTx SERCOM0 // SERCOM0: tx/rx

2
ports/stm32/boards/ADAFRUIT_F405_EXPRESS/mpconfigboard.h
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@ -42,7 +42,7 @@ extern struct _spi_bdev_t spi_bdev;
(op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
(op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
) )
#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) #define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) #define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol #define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol

4
ports/stm32/boards/CERB40/mpconfigboard.h
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@ -61,5 +61,5 @@
// USB config // USB config
#define MICROPY_HW_USB_FS (1) #define MICROPY_HW_USB_FS (1)
//#define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9) // #define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9)
//#define MICROPY_HW_USB_OTG_ID_PIN (pin_A10) // #define MICROPY_HW_USB_OTG_ID_PIN (pin_A10)

6
ports/stm32/boards/GARATRONIC_PYBSTICK26_F411/mpconfigboard.h
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@ -30,8 +30,8 @@
#define MICROPY_HW_UART2_NAME "XA" #define MICROPY_HW_UART2_NAME "XA"
#define MICROPY_HW_UART2_TX (pin_A2) #define MICROPY_HW_UART2_TX (pin_A2)
#define MICROPY_HW_UART2_RX (pin_A3) #define MICROPY_HW_UART2_RX (pin_A3)
//#define MICROPY_HW_UART2_RTS (pin_A1) // #define MICROPY_HW_UART2_RTS (pin_A1)
//#define MICROPY_HW_UART2_CTS (pin_A0) // #define MICROPY_HW_UART2_CTS (pin_A0)
#define MICROPY_HW_UART6_NAME "YA" #define MICROPY_HW_UART6_NAME "YA"
#define MICROPY_HW_UART6_TX (pin_C6) #define MICROPY_HW_UART6_TX (pin_C6)
#define MICROPY_HW_UART6_RX (pin_C7) #define MICROPY_HW_UART6_RX (pin_C7)
@ -41,7 +41,7 @@
#define MICROPY_HW_I2C1_SCL (pin_B8) // S5 #define MICROPY_HW_I2C1_SCL (pin_B8) // S5
#define MICROPY_HW_I2C1_SDA (pin_B9) // S3 #define MICROPY_HW_I2C1_SDA (pin_B9) // S3
#define MICROPY_HW_I2C2_NAME "Y" #define MICROPY_HW_I2C2_NAME "Y"
#define MICROPY_HW_I2C2_SCL (pin_B10) //S13 #define MICROPY_HW_I2C2_SCL (pin_B10) // S13
#define MICROPY_HW_I2C2_SDA (pin_B3) // S11 #define MICROPY_HW_I2C2_SDA (pin_B3) // S11
// SPI buses // SPI buses

2
ports/stm32/boards/LEGO_HUB_NO6/bluetooth_init_cc2564C_1.5.c
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@ -530,7 +530,7 @@ const uint8_t cc256x_init_script[] = {
0x00, 0x6d, 0x22, 0x08, 0x00, 0x69, 0x53, 0x08, 0x00, 0x50, 0x66, 0x08, 0x00, 0x54, 0x66, 0x00, 0x6d, 0x22, 0x08, 0x00, 0x69, 0x53, 0x08, 0x00, 0x50, 0x66, 0x08, 0x00, 0x54, 0x66,
0x08, 0x00, 0xd1, 0xa1, 0x04, 0x00, 0x5c, 0x66, 0x08, 0x00, 0xb3, 0x11, 0x08, 0x00, 0xe4, 0x08, 0x00, 0xd1, 0xa1, 0x04, 0x00, 0x5c, 0x66, 0x08, 0x00, 0xb3, 0x11, 0x08, 0x00, 0xe4,
0x15, 0x08, 0x00, 0x63, 0x66, 0x08, 0x00, 0x60, 0x66, 0x08, 0x00, 0x61, 0x66, 0x08, 0x00, 0x15, 0x08, 0x00, 0x63, 0x66, 0x08, 0x00, 0x60, 0x66, 0x08, 0x00, 0x61, 0x66, 0x08, 0x00,
0x01, 0x83, 0xff, 0x14, 0x79, 0x7b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x83, 0xff, 0x14, 0x79, 0x7b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

4
ports/stm32/boards/LEGO_HUB_NO6/hub_display.c
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@ -30,7 +30,7 @@
// Map pixel number 0-24, and 25-36 to TLC bit number. // Map pixel number 0-24, and 25-36 to TLC bit number.
static const uint8_t hub_display_pixel_map[] = { static const uint8_t hub_display_pixel_map[] = {
// 5x5 display // 5x5 display
9, 11, 6, 1, 14, 9, 11, 6, 1, 14,
10, 19, 8, 0, 26, 10, 19, 8, 0, 26,
23, 18, 3, 2, 24, 23, 18, 3, 2, 24,
21, 20, 15, 13, 25, 21, 20, 15, 13, 25,
@ -61,7 +61,7 @@ static void hub_display_tim_init(void) {
uint32_t reg = 6 << TIM_CCMR1_OC1M_Pos // PWM1 mode uint32_t reg = 6 << TIM_CCMR1_OC1M_Pos // PWM1 mode
| 1 << TIM_CCMR1_OC1PE_Pos // preload enabled | 1 << TIM_CCMR1_OC1PE_Pos // preload enabled
| 0 << TIM_CCMR1_CC1S_Pos // output mode | 0 << TIM_CCMR1_CC1S_Pos // output mode
; ;
uint32_t shift = 8 * (ch & 1); uint32_t shift = 8 * (ch & 1);
tim->CCMR1 = (tim->CCMR1 & ~(0xff << shift)) | reg << shift; tim->CCMR1 = (tim->CCMR1 & ~(0xff << shift)) | reg << shift;

62
ports/stm32/boards/LIMIFROG/board_init.c
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@ -40,23 +40,18 @@ void LIMIFROG_board_early_init(void) {
#define CONN_POS10_PORT GPIOB #define CONN_POS10_PORT GPIOB
#endif #endif
static inline void GPIO_HIGH(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) static inline void GPIO_HIGH(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
{ GPIOx->BSRR = (uint32_t)GPIO_Pin;
GPIOx->BSRR = (uint32_t)GPIO_Pin;
} }
static inline int IS_GPIO_RESET(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) static inline int IS_GPIO_RESET(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
{
GPIO_PinState bitstatus; GPIO_PinState bitstatus;
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) {
{ bitstatus = GPIO_PIN_SET;
bitstatus = GPIO_PIN_SET; } else {
} bitstatus = GPIO_PIN_RESET;
else }
{ return bitstatus == GPIO_PIN_RESET;
bitstatus = GPIO_PIN_RESET;
}
return (bitstatus==GPIO_PIN_RESET);
} }
/************************************************************** /**************************************************************
@ -94,15 +89,14 @@ static inline int IS_GPIO_RESET(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
********************************************************************/ ********************************************************************/
static void LBF_DFU_If_Needed(void) static void LBF_DFU_If_Needed(void) {
{
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
// Initialize and assert pin BTLE_RST // Initialize and assert pin BTLE_RST
// (hw reset to BLE module, so it won't drive UART3) // (hw reset to BLE module, so it won't drive UART3)
__HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE();
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@ -114,11 +108,11 @@ static void LBF_DFU_If_Needed(void)
GPIO_HIGH(BT_RST_PORT, BT_RST_PIN); // assert BTLE reset GPIO_HIGH(BT_RST_PORT, BT_RST_PIN); // assert BTLE reset
/* -- Bootloader will be called if position 10 on the extension port /* -- Bootloader will be called if position 10 on the extension port
is actively pulled low -- */ is actively pulled low -- */
// Note - this is an arbitrary choice, code could be modified to // Note - this is an arbitrary choice, code could be modified to
// monitor another GPIO of the STM32 and/or decide that active level // monitor another GPIO of the STM32 and/or decide that active level
// is high rather than low // is high rather than low
// Initialize Extension Port Position 10 = PB8 (bears I2C1_SCL) // Initialize Extension Port Position 10 = PB8 (bears I2C1_SCL)
@ -131,24 +125,22 @@ static void LBF_DFU_If_Needed(void)
HAL_GPIO_Init(CONN_POS10_PORT, &GPIO_InitStruct); HAL_GPIO_Init(CONN_POS10_PORT, &GPIO_InitStruct);
// If selection pin pulled low... // If selection pin pulled low...
if ( IS_GPIO_RESET(CONN_POS10_PORT, CONN_POS10_PIN )) if (IS_GPIO_RESET(CONN_POS10_PORT, CONN_POS10_PIN)) {
{
// Remap bootloader ROM (ie System Flash) to address 0x0 // Remap bootloader ROM (ie System Flash) to address 0x0
SYSCFG->MEMRMP = 0x00000001; SYSCFG->MEMRMP = 0x00000001;
// Init stack pointer with value residing at ROM base // Init stack pointer with value residing at ROM base
asm ( asm (
"LDR R0, =0x00000000\n\t" // load ROM base address" "LDR R0, =0x00000000\n\t" // load ROM base address"
"LDR SP,[R0, #0]\n\t" // assign main stack pointer" "LDR SP,[R0, #0]\n\t" // assign main stack pointer"
); );
// Jump to address pointed by 0x00000004 -- */ // Jump to address pointed by 0x00000004 -- */
asm ( asm (
"LDR R0,[R0, #4]\n\t" // load bootloader address "LDR R0,[R0, #4]\n\t" // load bootloader address
"BX R0\n\t" "BX R0\n\t"
); );
} }
} }

4
ports/stm32/boards/MIKROE_QUAIL/mpconfigboard.h
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@ -85,7 +85,7 @@ extern struct _spi_bdev_t spi_bdev;
(op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
(op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
) )
#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) #define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) #define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol #define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol
@ -104,6 +104,6 @@ extern struct _spi_bdev_t spi_bdev;
#define MBOOT_SPIFLASH_BYTE_SIZE (8 * 1024 * 1024) #define MBOOT_SPIFLASH_BYTE_SIZE (8 * 1024 * 1024)
#define MBOOT_SPIFLASH_LAYOUT "/0x80000000/512*8Kg" #define MBOOT_SPIFLASH_LAYOUT "/0x80000000/512*8Kg"
#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE \ #define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE \
(8 / 4) // 8k page, 4k erase block (8 / 4) // 8k page, 4k erase block
#define MBOOT_SPIFLASH_CONFIG (&spiflash_config) #define MBOOT_SPIFLASH_CONFIG (&spiflash_config)
#define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash) #define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash)

4
ports/stm32/boards/NETDUINO_PLUS_2/board_init.c
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@ -10,12 +10,12 @@ void NETDUINO_PLUS_2_board_early_init(void) {
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStructure.Pull = GPIO_PULLUP; GPIO_InitStructure.Pull = GPIO_PULLUP;
#if MICROPY_HW_ENABLE_SDCARD #if MICROPY_HW_ENABLE_SDCARD
// Turn on the power enable for the sdcard (PB1) // Turn on the power enable for the sdcard (PB1)
GPIO_InitStructure.Pin = GPIO_PIN_1; GPIO_InitStructure.Pin = GPIO_PIN_1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_SET);
#endif #endif
// Turn on the power for the 5V on the expansion header (PB2) // Turn on the power for the 5V on the expansion header (PB2)
GPIO_InitStructure.Pin = GPIO_PIN_2; GPIO_InitStructure.Pin = GPIO_PIN_2;

4
ports/stm32/boards/NUCLEO_F091RC/mpconfigboard.h
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@ -17,9 +17,9 @@
#define MICROPY_HW_HAS_SWITCH (1) #define MICROPY_HW_HAS_SWITCH (1)
// For system clock, enable one source: // For system clock, enable one source:
//#define MICROPY_HW_CLK_USE_HSI (1) // internal 8MHz -> PLL = 48MHz. // #define MICROPY_HW_CLK_USE_HSI (1) // internal 8MHz -> PLL = 48MHz.
#define MICROPY_HW_CLK_USE_HSI48 (1) // internal 48MHz. #define MICROPY_HW_CLK_USE_HSI48 (1) // internal 48MHz.
//#define MICROPY_HW_CLK_USE_HSE (1) // external crystal -> PLL = 48MHz. // #define MICROPY_HW_CLK_USE_HSE (1) // external crystal -> PLL = 48MHz.
// For HSE set the crystal / clock input frequency HSE_VALUE in stm32f0xx_hal_conf.h // For HSE set the crystal / clock input frequency HSE_VALUE in stm32f0xx_hal_conf.h
#if MICROPY_HW_CLK_USE_HSE #if MICROPY_HW_CLK_USE_HSE
#define MICROPY_HW_CLK_USE_BYPASS (1) // HSE comes from STLINK 8MHz, not crystal. #define MICROPY_HW_CLK_USE_BYPASS (1) // HSE comes from STLINK 8MHz, not crystal.

46
ports/stm32/boards/NUCLEO_G474RE/mpconfigboard.h
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@ -36,16 +36,16 @@
#define MICROPY_HW_LPUART1_RX (pin_A3) // A3 (to STLINK), B10, C0 #define MICROPY_HW_LPUART1_RX (pin_A3) // A3 (to STLINK), B10, C0
#define MICROPY_HW_UART1_TX (pin_C4) // A9, B6, C4, E0 #define MICROPY_HW_UART1_TX (pin_C4) // A9, B6, C4, E0
#define MICROPY_HW_UART1_RX (pin_C5) // A10, B7, C5, E1 #define MICROPY_HW_UART1_RX (pin_C5) // A10, B7, C5, E1
//#define MICROPY_HW_UART2_TX (pin_A2) // A14, B3, D5 // #define MICROPY_HW_UART2_TX (pin_A2) // A14, B3, D5
//#define MICROPY_HW_UART2_RX (pin_A3) // A15, B4, D6 // #define MICROPY_HW_UART2_RX (pin_A3) // A15, B4, D6
//#define MICROPY_HW_UART2_RTS (pin_A1) // D4 // #define MICROPY_HW_UART2_RTS (pin_A1) // D4
//#define MICROPY_HW_UART2_CTS (pin_A0) // D3 // #define MICROPY_HW_UART2_CTS (pin_A0) // D3
#define MICROPY_HW_UART3_TX (pin_B10) // B9, B10, C10, D8 #define MICROPY_HW_UART3_TX (pin_B10) // B9, B10, C10, D8
#define MICROPY_HW_UART3_RX (pin_B11) // B8 = boot0, B11, C11, D9, E15 #define MICROPY_HW_UART3_RX (pin_B11) // B8 = boot0, B11, C11, D9, E15
//#define MICROPY_HW_UART3_RTS (pin_B14) // D12, F6 // #define MICROPY_HW_UART3_RTS (pin_B14) // D12, F6
//#define MICROPY_HW_UART3_CTS (pin_B13) // A13, D11 // #define MICROPY_HW_UART3_CTS (pin_B13) // A13, D11
//#define MICROPY_HW_UART4_TX (pin_) // C10 // #define MICROPY_HW_UART4_TX (pin_) // C10
//#define MICROPY_HW_UART4_RX (pin_) // C11 // #define MICROPY_HW_UART4_RX (pin_) // C11
#define MICROPY_HW_UART_REPL (PYB_LPUART_1) // default on Nucleo G474 #define MICROPY_HW_UART_REPL (PYB_LPUART_1) // default on Nucleo G474
#define MICROPY_HW_UART_REPL_BAUD (115200) #define MICROPY_HW_UART_REPL_BAUD (115200)
@ -53,24 +53,24 @@
// I2C buses // I2C buses
#define MICROPY_HW_I2C1_SCL (pin_B8) // A13, A15, B8 (=boot0) #define MICROPY_HW_I2C1_SCL (pin_B8) // A13, A15, B8 (=boot0)
#define MICROPY_HW_I2C1_SDA (pin_B9) // A14, B7, B9 #define MICROPY_HW_I2C1_SDA (pin_B9) // A14, B7, B9
//#define MICROPY_HW_I2C2_SCL (pin_) // A9, C4 // #define MICROPY_HW_I2C2_SCL (pin_) // A9, C4
//#define MICROPY_HW_I2C2_SDA (pin_) // A8, F0 // #define MICROPY_HW_I2C2_SDA (pin_) // A8, F0
//#define MICROPY_HW_I2C3_SCL (pin_) // A8, C8 // #define MICROPY_HW_I2C3_SCL (pin_) // A8, C8
//#define MICROPY_HW_I2C3_SDA (pin_) // B5, C9, C11 // #define MICROPY_HW_I2C3_SDA (pin_) // B5, C9, C11
// SPI // SPI
#define MICROPY_HW_SPI1_NSS (pin_A4) // A4, A15 (Nucleo64 specifies B6 as pin CS, must be done as GPIO, not as AF) #define MICROPY_HW_SPI1_NSS (pin_A4) // A4, A15 (Nucleo64 specifies B6 as pin CS, must be done as GPIO, not as AF)
#define MICROPY_HW_SPI1_SCK (pin_A5) // A5 (LED), B3 (SWO) #define MICROPY_HW_SPI1_SCK (pin_A5) // A5 (LED), B3 (SWO)
#define MICROPY_HW_SPI1_MISO (pin_A6) // A6, B4 #define MICROPY_HW_SPI1_MISO (pin_A6) // A6, B4
#define MICROPY_HW_SPI1_MOSI (pin_A7) // A7, B5 #define MICROPY_HW_SPI1_MOSI (pin_A7) // A7, B5
//#define MICROPY_HW_SPI2_NSS (pin_) // B12, D15, F0 // #define MICROPY_HW_SPI2_NSS (pin_) // B12, D15, F0
//#define MICROPY_HW_SPI2_SCK (pin_) // B13, F1, F9, F10 // #define MICROPY_HW_SPI2_SCK (pin_) // B13, F1, F9, F10
//#define MICROPY_HW_SPI2_MISO (pin_) // A10, B14 // #define MICROPY_HW_SPI2_MISO (pin_) // A10, B14
//#define MICROPY_HW_SPI2_MOSI (pin_) // A11, B15 // #define MICROPY_HW_SPI2_MOSI (pin_) // A11, B15
//#define MICROPY_HW_SPI3_NSS (pin_) // A4, A15 // #define MICROPY_HW_SPI3_NSS (pin_) // A4, A15
//#define MICROPY_HW_SPI3_SCK (pin_) // B3, C10 // #define MICROPY_HW_SPI3_SCK (pin_) // B3, C10
//#define MICROPY_HW_SPI3_MISO (pin_) // B4, C11 // #define MICROPY_HW_SPI3_MISO (pin_) // B4, C11
//#define MICROPY_HW_SPI3_MOSI (pin_) // B5, C12 // #define MICROPY_HW_SPI3_MOSI (pin_) // B5, C12
// USRSW is pulled low. Pressing the button makes the input go high. // USRSW is pulled low. Pressing the button makes the input go high.
#define MICROPY_HW_USRSW_PIN (pin_C13) #define MICROPY_HW_USRSW_PIN (pin_C13)
@ -84,9 +84,9 @@
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin)) #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
// USB config pin A12 (dp), A11 (dm) not mounted on Nucleo // USB config pin A12 (dp), A11 (dm) not mounted on Nucleo
//#define MICROPY_HW_USB_FS (1) // #define MICROPY_HW_USB_FS (1)
//#define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9) // #define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9)
//#define MICROPY_HW_USB_OTG_ID_PIN (pin_A10) // #define MICROPY_HW_USB_OTG_ID_PIN (pin_A10)
// FDCAN bus // FDCAN bus
// User TODO: fit transceiver chip // User TODO: fit transceiver chip

2
ports/stm32/boards/NUCLEO_WB55/mboot_keys.h
View File

@ -1,4 +1,4 @@
//const uint8_t mboot_pack_sign_secret_key[] = {0xf1,0xd8,0x66,0x08,0xbc,0x78,0x39,0x65,0x6a,0xf4,0x88,0xf4,0x43,0x4d,0x10,0xfe,0x4f,0x79,0xb9,0xc3,0x77,0x36,0x23,0xc8,0xcf,0x62,0xa1,0x90,0xf1,0xdc,0xd9,0xbc,0xb2,0x2e,0x59,0x1e,0x53,0x04,0x54,0xd5,0xd1,0x3a,0x6d,0x2e,0x79,0x3e,0xb5,0x70,0xb4,0x9f,0x33,0xff,0x90,0x1d,0xc3,0x54,0x90,0x12,0x96,0x79,0xf4,0xed,0x56,0x75}; // const uint8_t mboot_pack_sign_secret_key[] = {0xf1,0xd8,0x66,0x08,0xbc,0x78,0x39,0x65,0x6a,0xf4,0x88,0xf4,0x43,0x4d,0x10,0xfe,0x4f,0x79,0xb9,0xc3,0x77,0x36,0x23,0xc8,0xcf,0x62,0xa1,0x90,0xf1,0xdc,0xd9,0xbc,0xb2,0x2e,0x59,0x1e,0x53,0x04,0x54,0xd5,0xd1,0x3a,0x6d,0x2e,0x79,0x3e,0xb5,0x70,0xb4,0x9f,0x33,0xff,0x90,0x1d,0xc3,0x54,0x90,0x12,0x96,0x79,0xf4,0xed,0x56,0x75};
const uint8_t mboot_pack_sign_public_key[] = {0xb2,0x2e,0x59,0x1e,0x53,0x04,0x54,0xd5,0xd1,0x3a,0x6d,0x2e,0x79,0x3e,0xb5,0x70,0xb4,0x9f,0x33,0xff,0x90,0x1d,0xc3,0x54,0x90,0x12,0x96,0x79,0xf4,0xed,0x56,0x75}; const uint8_t mboot_pack_sign_public_key[] = {0xb2,0x2e,0x59,0x1e,0x53,0x04,0x54,0xd5,0xd1,0x3a,0x6d,0x2e,0x79,0x3e,0xb5,0x70,0xb4,0x9f,0x33,0xff,0x90,0x1d,0xc3,0x54,0x90,0x12,0x96,0x79,0xf4,0xed,0x56,0x75};
const uint8_t mboot_pack_secretbox_key[] = {0x4a,0xbe,0x9b,0xed,0x55,0x9f,0x74,0xeb,0x1e,0x70,0xde,0xf5,0x19,0x0a,0xeb,0xa5,0x68,0xea,0xb0,0x88,0xe6,0xfe,0x4d,0x10,0x69,0x23,0x06,0x7f,0xdd,0x83,0xf0,0xbf}; const uint8_t mboot_pack_secretbox_key[] = {0x4a,0xbe,0x9b,0xed,0x55,0x9f,0x74,0xeb,0x1e,0x70,0xde,0xf5,0x19,0x0a,0xeb,0xa5,0x68,0xea,0xb0,0x88,0xe6,0xfe,0x4d,0x10,0x69,0x23,0x06,0x7f,0xdd,0x83,0xf0,0xbf};

2
ports/stm32/boards/PYBD_SF2/bdev.c
View File

@ -45,7 +45,7 @@ STATIC const mp_soft_qspi_obj_t soft_qspi_bus = {
const mp_spiflash_config_t spiflash_config = { const mp_spiflash_config_t spiflash_config = {
.bus_kind = MP_SPIFLASH_BUS_QSPI, .bus_kind = MP_SPIFLASH_BUS_QSPI,
.bus.u_qspi.data = (void*)&soft_qspi_bus, .bus.u_qspi.data = (void *)&soft_qspi_bus,
.bus.u_qspi.proto = &mp_soft_qspi_proto, .bus.u_qspi.proto = &mp_soft_qspi_proto,
#if MICROPY_HW_SPIFLASH_ENABLE_CACHE #if MICROPY_HW_SPIFLASH_ENABLE_CACHE
.cache = &spi_bdev_cache, .cache = &spi_bdev_cache,

2
ports/stm32/boards/PYBD_SF2/board_init.c
View File

@ -33,7 +33,7 @@
#else #else
#define OTP_ADDR (0x1ff0f3c0) #define OTP_ADDR (0x1ff0f3c0)
#endif #endif
#define OTP ((pyb_otp_t*)OTP_ADDR) #define OTP ((pyb_otp_t *)OTP_ADDR)
typedef struct _pyb_otp_t { typedef struct _pyb_otp_t {
uint16_t series; uint16_t series;

2
ports/stm32/boards/PYBD_SF2/mpconfigboard.h
View File

@ -84,7 +84,7 @@ extern struct _spi_bdev_t spi_bdev;
(op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
(op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
) )
#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) #define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) #define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol #define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol

2
ports/stm32/boards/SPARKFUN_MICROMOD_STM32/bdev.c
View File

@ -18,7 +18,7 @@ STATIC mp_spiflash_cache_t spi_bdev_cache;
const mp_spiflash_config_t spiflash_config = { const mp_spiflash_config_t spiflash_config = {
.bus_kind = MP_SPIFLASH_BUS_SPI, .bus_kind = MP_SPIFLASH_BUS_SPI,
.bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS, .bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS,
.bus.u_spi.data = (void*)&soft_spi_bus, .bus.u_spi.data = (void *)&soft_spi_bus,
.bus.u_spi.proto = &mp_soft_spi_proto, .bus.u_spi.proto = &mp_soft_spi_proto,
.cache = &spi_bdev_cache, .cache = &spi_bdev_cache,
}; };

4
ports/stm32/boards/SPARKFUN_MICROMOD_STM32/board_init.c
View File

@ -2,10 +2,10 @@
void board_early_init(void) { void board_early_init(void) {
#if !MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE #if !MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE
// set external SPI flash CS pin high // set external SPI flash CS pin high
mp_hal_pin_output(MICROPY_HW_SPIFLASH_CS); mp_hal_pin_output(MICROPY_HW_SPIFLASH_CS);
mp_hal_pin_write(MICROPY_HW_SPIFLASH_CS, 1); mp_hal_pin_write(MICROPY_HW_SPIFLASH_CS, 1);
#endif #endif
} }

2
ports/stm32/boards/SPARKFUN_MICROMOD_STM32/mpconfigboard.h
View File

@ -42,7 +42,7 @@ extern struct _spi_bdev_t spi_bdev;
(op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
(op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
) )
#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) #define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) #define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol #define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol

4
ports/stm32/boards/STM32F411DISC/mpconfigboard.h
View File

@ -29,8 +29,8 @@
// I2C buses // I2C buses
#define MICROPY_HW_I2C1_SCL (pin_B6) #define MICROPY_HW_I2C1_SCL (pin_B6)
#define MICROPY_HW_I2C1_SDA (pin_B9) #define MICROPY_HW_I2C1_SDA (pin_B9)
//#define MICROPY_HW_I2C2_SCL (pin_B10) // #define MICROPY_HW_I2C2_SCL (pin_B10)
//#define MICROPY_HW_I2C2_SDA (pin_B11) // #define MICROPY_HW_I2C2_SDA (pin_B11)
#define MICROPY_HW_I2C3_SCL (pin_A8) #define MICROPY_HW_I2C3_SCL (pin_A8)
#define MICROPY_HW_I2C3_SDA (pin_A9) #define MICROPY_HW_I2C3_SDA (pin_A9)

24
ports/stm32/boards/STM32F429DISC/mpconfigboard.h
View File

@ -32,10 +32,10 @@
#define MICROPY_HW_I2C3_SDA (pin_C9) #define MICROPY_HW_I2C3_SDA (pin_C9)
// SPI buses // SPI buses
//#define MICROPY_HW_SPI1_NSS (pin_A4) // #define MICROPY_HW_SPI1_NSS (pin_A4)
//#define MICROPY_HW_SPI1_SCK (pin_A5) // #define MICROPY_HW_SPI1_SCK (pin_A5)
//#define MICROPY_HW_SPI1_MISO (pin_A6) // #define MICROPY_HW_SPI1_MISO (pin_A6)
//#define MICROPY_HW_SPI1_MOSI (pin_A7) // #define MICROPY_HW_SPI1_MOSI (pin_A7)
#if defined(USE_USB_HS_IN_FS) #if defined(USE_USB_HS_IN_FS)
// The HS USB uses B14 & B15 for D- and D+ // The HS USB uses B14 & B15 for D- and D+
#else #else
@ -44,18 +44,18 @@
#define MICROPY_HW_SPI2_MISO (pin_B14) #define MICROPY_HW_SPI2_MISO (pin_B14)
#define MICROPY_HW_SPI2_MOSI (pin_B15) #define MICROPY_HW_SPI2_MOSI (pin_B15)
#endif #endif
//#define MICROPY_HW_SPI4_NSS (pin_E11) // #define MICROPY_HW_SPI4_NSS (pin_E11)
//#define MICROPY_HW_SPI4_SCK (pin_E12) // #define MICROPY_HW_SPI4_SCK (pin_E12)
//#define MICROPY_HW_SPI4_MISO (pin_E13) // #define MICROPY_HW_SPI4_MISO (pin_E13)
//#define MICROPY_HW_SPI4_MOSI (pin_E14) // #define MICROPY_HW_SPI4_MOSI (pin_E14)
#define MICROPY_HW_SPI5_NSS (pin_F6) #define MICROPY_HW_SPI5_NSS (pin_F6)
#define MICROPY_HW_SPI5_SCK (pin_F7) #define MICROPY_HW_SPI5_SCK (pin_F7)
#define MICROPY_HW_SPI5_MISO (pin_F8) #define MICROPY_HW_SPI5_MISO (pin_F8)
#define MICROPY_HW_SPI5_MOSI (pin_F9) #define MICROPY_HW_SPI5_MOSI (pin_F9)
//#define MICROPY_HW_SPI6_NSS (pin_G8) // #define MICROPY_HW_SPI6_NSS (pin_G8)
//#define MICROPY_HW_SPI6_SCK (pin_G13) // #define MICROPY_HW_SPI6_SCK (pin_G13)
//#define MICROPY_HW_SPI6_MISO (pin_G12) // #define MICROPY_HW_SPI6_MISO (pin_G12)
//#define MICROPY_HW_SPI6_MOSI (pin_G14) // #define MICROPY_HW_SPI6_MOSI (pin_G14)
// CAN buses // CAN buses
#define MICROPY_HW_CAN1_TX (pin_B9) #define MICROPY_HW_CAN1_TX (pin_B9)

33
ports/stm32/boards/STM32F439/mpconfigboard.h
View File

@ -17,10 +17,10 @@
#endif #endif
// HSE is 8MHz // HSE is 8MHz
#define MICROPY_HW_CLK_PLLM (8) //divide external clock by this to get 1MHz #define MICROPY_HW_CLK_PLLM (8) // divide external clock by this to get 1MHz
#define MICROPY_HW_CLK_PLLN (384) //this number is the PLL clock in MHz #define MICROPY_HW_CLK_PLLN (384) // this number is the PLL clock in MHz
#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2) //divide PLL clock by this to get core clock #define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2) // divide PLL clock by this to get core clock
#define MICROPY_HW_CLK_PLLQ (8) //divide core clock by this to get 48MHz #define MICROPY_HW_CLK_PLLQ (8) // divide core clock by this to get 48MHz
// USB config // USB config
#define MICROPY_HW_USB_FS (1) #define MICROPY_HW_USB_FS (1)
@ -62,18 +62,18 @@
#define MICROPY_HW_SPI3_SCK (pin_E12) #define MICROPY_HW_SPI3_SCK (pin_E12)
#define MICROPY_HW_SPI3_MISO (pin_E13) #define MICROPY_HW_SPI3_MISO (pin_E13)
#define MICROPY_HW_SPI3_MOSI (pin_E14) #define MICROPY_HW_SPI3_MOSI (pin_E14)
//#define MICROPY_HW_SPI4_NSS (pin_E11) // #define MICROPY_HW_SPI4_NSS (pin_E11)
//#define MICROPY_HW_SPI4_SCK (pin_E12) // #define MICROPY_HW_SPI4_SCK (pin_E12)
//#define MICROPY_HW_SPI4_MISO (pin_E13) // #define MICROPY_HW_SPI4_MISO (pin_E13)
//#define MICROPY_HW_SPI4_MOSI (pin_E14) // #define MICROPY_HW_SPI4_MOSI (pin_E14)
//#define MICROPY_HW_SPI5_NSS (pin_F6) // #define MICROPY_HW_SPI5_NSS (pin_F6)
//#define MICROPY_HW_SPI5_SCK (pin_F7) // #define MICROPY_HW_SPI5_SCK (pin_F7)
//#define MICROPY_HW_SPI5_MISO (pin_F8) // #define MICROPY_HW_SPI5_MISO (pin_F8)
//#define MICROPY_HW_SPI5_MOSI (pin_F9) // #define MICROPY_HW_SPI5_MOSI (pin_F9)
//#define MICROPY_HW_SPI6_NSS (pin_G8) // #define MICROPY_HW_SPI6_NSS (pin_G8)
//#define MICROPY_HW_SPI6_SCK (pin_G13) // #define MICROPY_HW_SPI6_SCK (pin_G13)
//#define MICROPY_HW_SPI6_MISO (pin_G12) // #define MICROPY_HW_SPI6_MISO (pin_G12)
//#define MICROPY_HW_SPI6_MOSI (pin_G14) // #define MICROPY_HW_SPI6_MOSI (pin_G14)
// CAN buses // CAN buses
#define MICROPY_HW_CAN1_TX (pin_B9) #define MICROPY_HW_CAN1_TX (pin_B9)
@ -86,4 +86,3 @@
#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) #define MICROPY_HW_USRSW_PULL (GPIO_NOPULL)
#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING) #define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING)
#define MICROPY_HW_USRSW_PRESSED (1) #define MICROPY_HW_USRSW_PRESSED (1)

2
ports/stm32/boards/STM32F769DISC/mpconfigboard.h
View File

@ -46,7 +46,7 @@ extern struct _spi_bdev_t spi_bdev;
(op) == BDEV_IOCTL_NUM_BLOCKS ? ((1 << MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2) / 8 / FLASH_BLOCK_SIZE) : \ (op) == BDEV_IOCTL_NUM_BLOCKS ? ((1 << MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2) / 8 / FLASH_BLOCK_SIZE) : \
(op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
) )
#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) #define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) #define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol #define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol

2
ports/stm32/boards/STM32L476DISC/bdev.c
View File

@ -16,7 +16,7 @@ STATIC mp_spiflash_cache_t spi_bdev_cache;
const mp_spiflash_config_t spiflash_config = { const mp_spiflash_config_t spiflash_config = {
.bus_kind = MP_SPIFLASH_BUS_SPI, .bus_kind = MP_SPIFLASH_BUS_SPI,
.bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS, .bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS,
.bus.u_spi.data = (void*)&soft_spi_bus, .bus.u_spi.data = (void *)&soft_spi_bus,
.bus.u_spi.proto = &mp_soft_spi_proto, .bus.u_spi.proto = &mp_soft_spi_proto,
.cache = &spi_bdev_cache, .cache = &spi_bdev_cache,
}; };

2
ports/stm32/boards/STM32L476DISC/mpconfigboard.h
View File

@ -27,7 +27,7 @@ extern struct _spi_bdev_t spi_bdev;
(op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
(op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
) )
#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) #define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) #define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))

2
ports/stm32/boards/VCC_GND_F407VE/bdev.c
View File

@ -18,7 +18,7 @@ STATIC mp_spiflash_cache_t spi_bdev_cache;
const mp_spiflash_config_t spiflash_config = { const mp_spiflash_config_t spiflash_config = {
.bus_kind = MP_SPIFLASH_BUS_SPI, .bus_kind = MP_SPIFLASH_BUS_SPI,
.bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS, .bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS,
.bus.u_spi.data = (void*)&soft_spi_bus, .bus.u_spi.data = (void *)&soft_spi_bus,
.bus.u_spi.proto = &mp_soft_spi_proto, .bus.u_spi.proto = &mp_soft_spi_proto,
.cache = &spi_bdev_cache, .cache = &spi_bdev_cache,
}; };

2
ports/stm32/boards/VCC_GND_F407VE/mpconfigboard.h
View File

@ -137,7 +137,7 @@ extern struct _spi_bdev_t spi_bdev;
(op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
(op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
) )
#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) #define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) #define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))

2
ports/stm32/boards/VCC_GND_F407ZG/bdev.c
View File

@ -18,7 +18,7 @@ STATIC mp_spiflash_cache_t spi_bdev_cache;
const mp_spiflash_config_t spiflash_config = { const mp_spiflash_config_t spiflash_config = {
.bus_kind = MP_SPIFLASH_BUS_SPI, .bus_kind = MP_SPIFLASH_BUS_SPI,
.bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS, .bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS,
.bus.u_spi.data = (void*)&soft_spi_bus, .bus.u_spi.data = (void *)&soft_spi_bus,
.bus.u_spi.proto = &mp_soft_spi_proto, .bus.u_spi.proto = &mp_soft_spi_proto,
.cache = &spi_bdev_cache, .cache = &spi_bdev_cache,
}; };

2
ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.h
View File

@ -145,7 +145,7 @@ extern struct _spi_bdev_t spi_bdev;
(op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
(op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
) )
#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) #define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) #define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))

42
ports/stm32/boards/stm32f4xx_prefix.c
View File

@ -7,26 +7,26 @@
#include "pin.h" #include "pin.h"
#define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \ #define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \
{ \ { \
{ &pin_af_type }, \ { &pin_af_type }, \
.name = MP_QSTR_AF ## af_idx ## _ ## af_fn ## af_unit, \ .name = MP_QSTR_AF##af_idx##_##af_fn##af_unit, \
.idx = (af_idx), \ .idx = (af_idx), \
.fn = AF_FN_ ## af_fn, \ .fn = AF_FN_##af_fn, \
.unit = (af_unit), \ .unit = (af_unit), \
.type = AF_PIN_TYPE_ ## af_fn ## _ ## af_type, \ .type = AF_PIN_TYPE_##af_fn##_##af_type, \
.reg = (af_ptr) \ .reg = (af_ptr) \
} }
#define PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel) \ #define PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel) \
{ \ { \
{ &pin_type }, \ { &pin_type }, \
.name = MP_QSTR_ ## p_port ## p_pin, \ .name = MP_QSTR_##p_port##p_pin, \
.port = PORT_ ## p_port, \ .port = PORT_##p_port, \
.pin = (p_pin), \ .pin = (p_pin), \
.num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \ .num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \
.pin_mask = (1 << ((p_pin) & 0x0f)), \ .pin_mask = (1 << ((p_pin) & 0x0f)), \
.gpio = GPIO ## p_port, \ .gpio = GPIO##p_port, \
.af = p_af, \ .af = p_af, \
.adc_num = p_adc_num, \ .adc_num = p_adc_num, \
.adc_channel = p_adc_channel, \ .adc_channel = p_adc_channel, \
} }

2
ports/stm32/mbedtls/mbedtls_config.h
View File

@ -65,7 +65,7 @@
#define MBEDTLS_BIGNUM_C #define MBEDTLS_BIGNUM_C
#define MBEDTLS_CIPHER_C #define MBEDTLS_CIPHER_C
#define MBEDTLS_CTR_DRBG_C #define MBEDTLS_CTR_DRBG_C
//#define MBEDTLS_ECP_C // #define MBEDTLS_ECP_C
#define MBEDTLS_ENTROPY_C #define MBEDTLS_ENTROPY_C
#define MBEDTLS_ERROR_C #define MBEDTLS_ERROR_C
#define MBEDTLS_MD_C #define MBEDTLS_MD_C

8
ports/stm32/mbedtls/mbedtls_port.c
View File

@ -39,7 +39,7 @@ static size_t count_links(uint32_t *nb) {
while (p != NULL) { while (p != NULL) {
++n; ++n;
*nb += gc_nbytes(p); *nb += gc_nbytes(p);
p = (void**)p[1]; p = (void **)p[1];
} }
return n; return n;
} }
@ -65,17 +65,17 @@ void m_free_mbedtls(void *ptr_in) {
if (ptr_in == NULL) { if (ptr_in == NULL) {
return; return;
} }
void **ptr = &((void**)ptr_in)[-2]; void **ptr = &((void **)ptr_in)[-2];
#if DEBUG #if DEBUG
uint32_t nb; uint32_t nb;
size_t n = count_links(&nb); size_t n = count_links(&nb);
printf("mbed_free(%p, [%p, %p], nbytes=%u, links=%u;%u)\n", ptr, ptr[0], ptr[1], gc_nbytes(ptr), n, (uint)nb); printf("mbed_free(%p, [%p, %p], nbytes=%u, links=%u;%u)\n", ptr, ptr[0], ptr[1], gc_nbytes(ptr), n, (uint)nb);
#endif #endif
if (ptr[1] != NULL) { if (ptr[1] != NULL) {
((void**)ptr[1])[0] = ptr[0]; ((void **)ptr[1])[0] = ptr[0];
} }
if (ptr[0] != NULL) { if (ptr[0] != NULL) {
((void**)ptr[0])[1] = ptr[1]; ((void **)ptr[0])[1] = ptr[1];
} else { } else {
MP_STATE_PORT(mbedtls_memory) = ptr[1]; MP_STATE_PORT(mbedtls_memory) = ptr[1];
} }

102
ports/stm32/mboot/main.c
View File

@ -62,13 +62,13 @@
#define IRQ_PRI_I2C (NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 1, 0)) #define IRQ_PRI_I2C (NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 1, 0))
#if defined(MBOOT_CLK_PLLM) #if defined(MBOOT_CLK_PLLM)
// The board specified the PLL values, flash latency and bus dividers // The board specified the PLL values, flash latency and bus dividers
#define CORE_PLL_FREQ (1000000 * MBOOT_CLK_PLLN / MBOOT_CLK_PLLP) #define CORE_PLL_FREQ (1000000 * MBOOT_CLK_PLLN / MBOOT_CLK_PLLP)
#else #else
// The board did not specify the clock values, so configure defaults // The board did not specify the clock values, so configure defaults
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F4) || defined(STM32F7)
#if MBOOT_ENABLE_PACKING #if MBOOT_ENABLE_PACKING
// With encryption/signing/compression, a faster CPU makes processing much faster. // With encryption/signing/compression, a faster CPU makes processing much faster.
#define CORE_PLL_FREQ (96000000) #define CORE_PLL_FREQ (96000000)
#define MBOOT_FLASH_LATENCY FLASH_LATENCY_3 #define MBOOT_FLASH_LATENCY FLASH_LATENCY_3
#else #else
@ -120,7 +120,7 @@ uint32_t get_le32(const uint8_t *b) {
uint64_t get_le64(const uint8_t *b) { uint64_t get_le64(const uint8_t *b) {
return (uint64_t)b[0] | (uint64_t)b[1] << 8 | (uint64_t)b[2] << 16 | (uint64_t)b[3] << 24 return (uint64_t)b[0] | (uint64_t)b[1] << 8 | (uint64_t)b[2] << 16 | (uint64_t)b[3] << 24
| (uint64_t)b[4] << 32 | (uint64_t)b[5] << 40 | (uint64_t)b[6] << 48 | (uint64_t)b[7] << 56; | (uint64_t)b[4] << 32 | (uint64_t)b[5] << 40 | (uint64_t)b[6] << 48 | (uint64_t)b[7] << 56;
} }
mp_uint_t mp_hal_ticks_ms(void) { mp_uint_t mp_hal_ticks_ms(void) {
@ -217,17 +217,17 @@ void SystemClock_Config(void) {
1 << RCC_PLLCFGR_PLLSRC_Pos // HSE selected as PLL source 1 << RCC_PLLCFGR_PLLSRC_Pos // HSE selected as PLL source
#endif #endif
| MBOOT_CLK_PLLM << RCC_PLLCFGR_PLLM_Pos | MBOOT_CLK_PLLM << RCC_PLLCFGR_PLLM_Pos
| MBOOT_CLK_PLLN << RCC_PLLCFGR_PLLN_Pos | MBOOT_CLK_PLLN << RCC_PLLCFGR_PLLN_Pos
| ((MBOOT_CLK_PLLP >> 1) - 1) << RCC_PLLCFGR_PLLP_Pos | ((MBOOT_CLK_PLLP >> 1) - 1) << RCC_PLLCFGR_PLLP_Pos
| MBOOT_CLK_PLLQ << RCC_PLLCFGR_PLLQ_Pos | MBOOT_CLK_PLLQ << RCC_PLLCFGR_PLLQ_Pos
#ifdef RCC_PLLCFGR_PLLR #ifdef RCC_PLLCFGR_PLLR
| 2 << RCC_PLLCFGR_PLLR_Pos // default PLLR value of 2 | 2 << RCC_PLLCFGR_PLLR_Pos // default PLLR value of 2
#endif #endif
; ;
// Enable PLL // Enable PLL
__HAL_RCC_PLL_ENABLE(); __HAL_RCC_PLL_ENABLE();
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) {
} }
// Increase latency before changing clock // Increase latency before changing clock
@ -299,9 +299,9 @@ void SystemClock_Config(void) {
RCC->PLL1FRACR = 0; RCC->PLL1FRACR = 0;
RCC->PLL1DIVR = RCC->PLL1DIVR =
(MBOOT_CLK_PLLN - 1) << RCC_PLL1DIVR_N1_Pos (MBOOT_CLK_PLLN - 1) << RCC_PLL1DIVR_N1_Pos
| (MBOOT_CLK_PLLP - 1) << RCC_PLL1DIVR_P1_Pos // only even P allowed | (MBOOT_CLK_PLLP - 1) << RCC_PLL1DIVR_P1_Pos // only even P allowed
| (MBOOT_CLK_PLLQ - 1) << RCC_PLL1DIVR_Q1_Pos | (MBOOT_CLK_PLLQ - 1) << RCC_PLL1DIVR_Q1_Pos
| (MBOOT_CLK_PLLR - 1) << RCC_PLL1DIVR_R1_Pos; | (MBOOT_CLK_PLLR - 1) << RCC_PLL1DIVR_R1_Pos;
// Configure PLL3 for use by USB at Q=48MHz // Configure PLL3 for use by USB at Q=48MHz
RCC->PLLCKSELR |= MICROPY_HW_CLK_PLL3M << RCC_PLLCKSELR_DIVM3_Pos; RCC->PLLCKSELR |= MICROPY_HW_CLK_PLL3M << RCC_PLLCKSELR_DIVM3_Pos;
@ -309,21 +309,21 @@ void SystemClock_Config(void) {
RCC->PLL3FRACR = 0; RCC->PLL3FRACR = 0;
RCC->PLL3DIVR = RCC->PLL3DIVR =
(MICROPY_HW_CLK_PLL3N - 1) << RCC_PLL3DIVR_N3_Pos (MICROPY_HW_CLK_PLL3N - 1) << RCC_PLL3DIVR_N3_Pos
| (MICROPY_HW_CLK_PLL3P - 1) << RCC_PLL3DIVR_P3_Pos // only even P allowed | (MICROPY_HW_CLK_PLL3P - 1) << RCC_PLL3DIVR_P3_Pos // only even P allowed
| (MICROPY_HW_CLK_PLL3Q - 1) << RCC_PLL3DIVR_Q3_Pos | (MICROPY_HW_CLK_PLL3Q - 1) << RCC_PLL3DIVR_Q3_Pos
| (MICROPY_HW_CLK_PLL3R - 1) << RCC_PLL3DIVR_R3_Pos; | (MICROPY_HW_CLK_PLL3R - 1) << RCC_PLL3DIVR_R3_Pos;
// Select PLL3-Q for USB clock source // Select PLL3-Q for USB clock source
MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, RCC_D2CCIP2R_USBSEL_1); MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, RCC_D2CCIP2R_USBSEL_1);
// Enable PLL1 // Enable PLL1
__HAL_RCC_PLL_ENABLE(); __HAL_RCC_PLL_ENABLE();
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) {
} }
// Enable PLL3 // Enable PLL3
__HAL_RCC_PLL3_ENABLE(); __HAL_RCC_PLL3_ENABLE();
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET) { while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET) {
} }
// Increase latency before changing SYSCLK // Increase latency before changing SYSCLK
@ -334,8 +334,8 @@ void SystemClock_Config(void) {
// Configure AHB divider // Configure AHB divider
RCC->D1CFGR = RCC->D1CFGR =
0 << RCC_D1CFGR_D1CPRE_Pos // SYSCLK prescaler of 1 0 << RCC_D1CFGR_D1CPRE_Pos // SYSCLK prescaler of 1
| MBOOT_CLK_AHB_DIV | MBOOT_CLK_AHB_DIV
; ;
// Configure SYSCLK source from PLL // Configure SYSCLK source from PLL
__HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_PLLCLK); __HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_PLLCLK);
@ -374,7 +374,7 @@ void SystemClock_Config(void) {
#endif #endif
void mp_hal_pin_config(mp_hal_pin_obj_t port_pin, uint32_t mode, uint32_t pull, uint32_t alt) { void mp_hal_pin_config(mp_hal_pin_obj_t port_pin, uint32_t mode, uint32_t pull, uint32_t alt) {
GPIO_TypeDef *gpio = (GPIO_TypeDef*)(port_pin & ~0xf); GPIO_TypeDef *gpio = (GPIO_TypeDef *)(port_pin & ~0xf);
// Enable the GPIO peripheral clock // Enable the GPIO peripheral clock
uint32_t gpio_idx = ((uintptr_t)gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE); uint32_t gpio_idx = ((uintptr_t)gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE);
@ -392,7 +392,7 @@ void mp_hal_pin_config(mp_hal_pin_obj_t port_pin, uint32_t mode, uint32_t pull,
} }
void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed) { void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed) {
GPIO_TypeDef *gpio = (GPIO_TypeDef*)(port_pin & ~0xf); GPIO_TypeDef *gpio = (GPIO_TypeDef *)(port_pin & ~0xf);
uint32_t pin = port_pin & 0xf; uint32_t pin = port_pin & 0xf;
gpio->OSPEEDR = (gpio->OSPEEDR & ~(3 << (2 * pin))) | (speed << (2 * pin)); gpio->OSPEEDR = (gpio->OSPEEDR & ~(3 << (2 * pin))) | (speed << (2 * pin));
} }
@ -457,7 +457,7 @@ static int mboot_flash_page_erase(uint32_t addr, uint32_t *next_addr) {
// Check the erase set bits to 1, at least for the first 256 bytes // Check the erase set bits to 1, at least for the first 256 bytes
for (int i = 0; i < 64; ++i) { for (int i = 0; i < 64; ++i) {
if (((volatile uint32_t*)sector_start)[i] != 0xffffffff) { if (((volatile uint32_t *)sector_start)[i] != 0xffffffff) {
return -MBOOT_ERRNO_FLASH_ERASE_FAILED; return -MBOOT_ERRNO_FLASH_ERASE_FAILED;
} }
} }
@ -475,7 +475,7 @@ static int mboot_flash_write(uint32_t addr, const uint8_t *src8, size_t len) {
return -MBOOT_ERRNO_FLASH_WRITE_DISALLOWED; return -MBOOT_ERRNO_FLASH_WRITE_DISALLOWED;
} }
const uint32_t *src = (const uint32_t*)src8; const uint32_t *src = (const uint32_t *)src8;
size_t num_word32 = (len + 3) / 4; size_t num_word32 = (len + 3) / 4;
// Write the data to flash. // Write the data to flash.
@ -633,8 +633,8 @@ int do_write(uint32_t addr, const uint8_t *src8, size_t len, bool dry_run) {
#if defined(MBOOT_I2C_SCL) #if defined(MBOOT_I2C_SCL)
#define PASTE2(a, b) a ## b #define PASTE2(a, b) a##b
#define PASTE3(a, b, c) a ## b ## c #define PASTE3(a, b, c) a##b##c
#define EVAL_PASTE2(a, b) PASTE2(a, b) #define EVAL_PASTE2(a, b) PASTE2(a, b)
#define EVAL_PASTE3(a, b, c) PASTE3(a, b, c) #define EVAL_PASTE3(a, b, c) PASTE3(a, b, c)
@ -714,7 +714,7 @@ void i2c_slave_process_rx_end(i2c_slave_t *i2c) {
#pragma GCC diagnostic ignored "-Warray-bounds" #pragma GCC diagnostic ignored "-Warray-bounds"
#pragma GCC diagnostic ignored "-Wstringop-overread" #pragma GCC diagnostic ignored "-Wstringop-overread"
#endif #endif
memcpy(buf, (uint8_t*)MP_HAL_UNIQUE_ID_ADDRESS, 12); memcpy(buf, (uint8_t *)MP_HAL_UNIQUE_ID_ADDRESS, 12);
#if __GNUC__ >= 11 #if __GNUC__ >= 11
#pragma GCC diagnostic pop #pragma GCC diagnostic pop
#endif #endif
@ -760,22 +760,22 @@ void i2c_slave_process_rx_end(i2c_slave_t *i2c) {
uint32_t hashlen = get_le32(buf + 1); uint32_t hashlen = get_le32(buf + 1);
static CRYAL_SHA256_CTX ctx; static CRYAL_SHA256_CTX ctx;
sha256_init(&ctx); sha256_init(&ctx);
sha256_update(&ctx, (const void*)i2c_obj.cmd_rdaddr, hashlen); sha256_update(&ctx, (const void *)i2c_obj.cmd_rdaddr, hashlen);
i2c_obj.cmd_rdaddr += hashlen; i2c_obj.cmd_rdaddr += hashlen;
sha256_final(&ctx, buf); sha256_final(&ctx, buf);
len = 32; len = 32;
} else if (buf[0] == I2C_CMD_MARKVALID && len == 0) { } else if (buf[0] == I2C_CMD_MARKVALID && len == 0) {
uint32_t buf; uint32_t buf;
buf = *(volatile uint32_t*)APPLICATION_ADDR; buf = *(volatile uint32_t *)APPLICATION_ADDR;
if ((buf & APP_VALIDITY_BITS) != APP_VALIDITY_BITS) { if ((buf & APP_VALIDITY_BITS) != APP_VALIDITY_BITS) {
len = -1; len = -1;
} else { } else {
buf &= ~APP_VALIDITY_BITS; buf &= ~APP_VALIDITY_BITS;
int ret = do_write(APPLICATION_ADDR, (void*)&buf, 4, false); int ret = do_write(APPLICATION_ADDR, (void *)&buf, 4, false);
if (ret < 0) { if (ret < 0) {
len = ret; len = ret;
} else { } else {
buf = *(volatile uint32_t*)APPLICATION_ADDR; buf = *(volatile uint32_t *)APPLICATION_ADDR;
if ((buf & APP_VALIDITY_BITS) != 0) { if ((buf & APP_VALIDITY_BITS) != 0) {
len = -2; len = -2;
} else { } else {
@ -1018,7 +1018,7 @@ static uint8_t cfg_descr[9 + 9 + 9] =
static uint8_t *pyb_usbdd_DeviceDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) { static uint8_t *pyb_usbdd_DeviceDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
*length = USB_LEN_DEV_DESC; *length = USB_LEN_DEV_DESC;
return (uint8_t*)dev_descr; return (uint8_t *)dev_descr;
} }
static char get_hex_char(int val) { static char get_hex_char(int val) {
@ -1036,19 +1036,19 @@ static void format_hex(char *buf, int val) {
} }
static uint8_t *pyb_usbdd_StrDescriptor(USBD_HandleTypeDef *pdev, uint8_t idx, uint16_t *length) { static uint8_t *pyb_usbdd_StrDescriptor(USBD_HandleTypeDef *pdev, uint8_t idx, uint16_t *length) {
pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t*)pdev->pClassData; pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t *)pdev->pClassData;
uint8_t *str_desc = self->usbd_str_desc; uint8_t *str_desc = self->usbd_str_desc;
switch (idx) { switch (idx) {
case USBD_IDX_LANGID_STR: case USBD_IDX_LANGID_STR:
*length = sizeof(USBD_LangIDDesc); *length = sizeof(USBD_LangIDDesc);
return (uint8_t*)USBD_LangIDDesc; // the data should only be read from this buf return (uint8_t *)USBD_LangIDDesc; // the data should only be read from this buf
case USBD_IDX_MFC_STR: case USBD_IDX_MFC_STR:
USBD_GetString((uint8_t*)MBOOT_USBD_MANUFACTURER_STRING, str_desc, length); USBD_GetString((uint8_t *)MBOOT_USBD_MANUFACTURER_STRING, str_desc, length);
return str_desc; return str_desc;
case USBD_IDX_PRODUCT_STR: case USBD_IDX_PRODUCT_STR:
USBD_GetString((uint8_t*)MBOOT_USBD_PRODUCT_STRING, str_desc, length); USBD_GetString((uint8_t *)MBOOT_USBD_PRODUCT_STRING, str_desc, length);
return str_desc; return str_desc;
case USBD_IDX_SERIAL_STR: { case USBD_IDX_SERIAL_STR: {
@ -1064,7 +1064,7 @@ static uint8_t *pyb_usbdd_StrDescriptor(USBD_HandleTypeDef *pdev, uint8_t idx, u
// dfu-util -l // dfu-util -l
// //
// See: https://my.st.com/52d187b7 for the algorithim used. // See: https://my.st.com/52d187b7 for the algorithim used.
uint8_t *id = (uint8_t*)MP_HAL_UNIQUE_ID_ADDRESS; uint8_t *id = (uint8_t *)MP_HAL_UNIQUE_ID_ADDRESS;
char serial_buf[16]; char serial_buf[16];
format_hex(&serial_buf[0], id[11]); format_hex(&serial_buf[0], id[11]);
format_hex(&serial_buf[2], id[10] + id[2]); format_hex(&serial_buf[2], id[10] + id[2]);
@ -1074,29 +1074,29 @@ static uint8_t *pyb_usbdd_StrDescriptor(USBD_HandleTypeDef *pdev, uint8_t idx, u
format_hex(&serial_buf[10], id[6]); format_hex(&serial_buf[10], id[6]);
serial_buf[12] = '\0'; serial_buf[12] = '\0';
USBD_GetString((uint8_t*)serial_buf, str_desc, length); USBD_GetString((uint8_t *)serial_buf, str_desc, length);
return str_desc; return str_desc;
} }
case USBD_IDX_CONFIG_STR: case USBD_IDX_CONFIG_STR:
USBD_GetString((uint8_t*)FLASH_LAYOUT_STR, str_desc, length); USBD_GetString((uint8_t *)FLASH_LAYOUT_STR, str_desc, length);
return str_desc; return str_desc;
case MBOOT_ERROR_STR_OVERWRITE_BOOTLOADER_IDX: case MBOOT_ERROR_STR_OVERWRITE_BOOTLOADER_IDX:
USBD_GetString((uint8_t*)MBOOT_ERROR_STR_OVERWRITE_BOOTLOADER, str_desc, length); USBD_GetString((uint8_t *)MBOOT_ERROR_STR_OVERWRITE_BOOTLOADER, str_desc, length);
return str_desc; return str_desc;
case MBOOT_ERROR_STR_INVALID_ADDRESS_IDX: case MBOOT_ERROR_STR_INVALID_ADDRESS_IDX:
USBD_GetString((uint8_t*)MBOOT_ERROR_STR_INVALID_ADDRESS, str_desc, length); USBD_GetString((uint8_t *)MBOOT_ERROR_STR_INVALID_ADDRESS, str_desc, length);
return str_desc; return str_desc;
#if MBOOT_ENABLE_PACKING #if MBOOT_ENABLE_PACKING
case MBOOT_ERROR_STR_INVALID_SIG_IDX: case MBOOT_ERROR_STR_INVALID_SIG_IDX:
USBD_GetString((uint8_t*)MBOOT_ERROR_STR_INVALID_SIG, str_desc, length); USBD_GetString((uint8_t *)MBOOT_ERROR_STR_INVALID_SIG, str_desc, length);
return str_desc; return str_desc;
case MBOOT_ERROR_STR_INVALID_READ_IDX: case MBOOT_ERROR_STR_INVALID_READ_IDX:
USBD_GetString((uint8_t*)MBOOT_ERROR_STR_INVALID_READ, str_desc, length); USBD_GetString((uint8_t *)MBOOT_ERROR_STR_INVALID_READ, str_desc, length);
return str_desc; return str_desc;
#endif #endif
@ -1111,19 +1111,19 @@ static const USBD_DescriptorsTypeDef pyb_usbdd_descriptors = {
}; };
static uint8_t pyb_usbdd_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { static uint8_t pyb_usbdd_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) {
pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t*)pdev->pClassData; pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t *)pdev->pClassData;
(void)self; (void)self;
return USBD_OK; return USBD_OK;
} }
static uint8_t pyb_usbdd_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { static uint8_t pyb_usbdd_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) {
pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t*)pdev->pClassData; pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t *)pdev->pClassData;
(void)self; (void)self;
return USBD_OK; return USBD_OK;
} }
static uint8_t pyb_usbdd_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { static uint8_t pyb_usbdd_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) {
pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t*)pdev->pClassData; pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t *)pdev->pClassData;
(void)self; (void)self;
self->bRequest = req->bRequest; self->bRequest = req->bRequest;
self->wValue = req->wValue; self->wValue = req->wValue;
@ -1149,7 +1149,7 @@ static uint8_t pyb_usbdd_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *r
} }
static uint8_t pyb_usbdd_EP0_TxSent(USBD_HandleTypeDef *pdev) { static uint8_t pyb_usbdd_EP0_TxSent(USBD_HandleTypeDef *pdev) {
pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t*)pdev->pClassData; pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t *)pdev->pClassData;
self->tx_pending = false; self->tx_pending = false;
#if !USE_USB_POLLING #if !USE_USB_POLLING
// Process now that we have sent a response // Process now that we have sent a response
@ -1159,19 +1159,19 @@ static uint8_t pyb_usbdd_EP0_TxSent(USBD_HandleTypeDef *pdev) {
} }
static uint8_t pyb_usbdd_EP0_RxReady(USBD_HandleTypeDef *pdev) { static uint8_t pyb_usbdd_EP0_RxReady(USBD_HandleTypeDef *pdev) {
pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t*)pdev->pClassData; pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t *)pdev->pClassData;
dfu_handle_rx(self->bRequest, self->wValue, self->wLength, self->rx_buf); dfu_handle_rx(self->bRequest, self->wValue, self->wLength, self->rx_buf);
return USBD_OK; return USBD_OK;
} }
static uint8_t *pyb_usbdd_GetCfgDesc(USBD_HandleTypeDef *pdev, uint16_t *length) { static uint8_t *pyb_usbdd_GetCfgDesc(USBD_HandleTypeDef *pdev, uint16_t *length) {
*length = sizeof(cfg_descr); *length = sizeof(cfg_descr);
return (uint8_t*)cfg_descr; return (uint8_t *)cfg_descr;
} }
// this is used only in high-speed mode, which we don't support // this is used only in high-speed mode, which we don't support
static uint8_t *pyb_usbdd_GetDeviceQualifierDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) { static uint8_t *pyb_usbdd_GetDeviceQualifierDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t*)pdev->pClassData; pyb_usbdd_obj_t *self = (pyb_usbdd_obj_t *)pdev->pClassData;
(void)self; (void)self;
/* /*
*length = sizeof(USBD_CDC_MSC_HID_DeviceQualifierDesc); *length = sizeof(USBD_CDC_MSC_HID_DeviceQualifierDesc);
@ -1228,7 +1228,7 @@ static void pyb_usbdd_init(pyb_usbdd_obj_t *self, int phy_id) {
USBD_HandleTypeDef *usbd = &self->hUSBDDevice; USBD_HandleTypeDef *usbd = &self->hUSBDDevice;
usbd->id = phy_id; usbd->id = phy_id;
usbd->dev_state = USBD_STATE_DEFAULT; usbd->dev_state = USBD_STATE_DEFAULT;
usbd->pDesc = (USBD_DescriptorsTypeDef*)&pyb_usbdd_descriptors; usbd->pDesc = (USBD_DescriptorsTypeDef *)&pyb_usbdd_descriptors;
usbd->pClass = &pyb_usbdd_class; usbd->pClass = &pyb_usbdd_class;
usbd->pClassData = self; usbd->pClassData = self;
} }
@ -1272,7 +1272,7 @@ NORETURN static __attribute__((naked)) void branch_to_application(uint32_t r0, u
} }
static void try_enter_application(int reset_mode) { static void try_enter_application(int reset_mode) {
uint32_t msp = *(volatile uint32_t*)APPLICATION_ADDR; uint32_t msp = *(volatile uint32_t *)APPLICATION_ADDR;
if ((msp & APP_VALIDITY_BITS) != 0) { if ((msp & APP_VALIDITY_BITS) != 0) {
// Application is invalid. // Application is invalid.
return; return;

206
ports/stm32/mboot/mphalport.h
View File

@ -58,26 +58,26 @@ static inline int mp_hal_status_to_neg_errno(HAL_StatusTypeDef status) {
#define mp_hal_pin_input(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_INPUT, MP_HAL_PIN_PULL_NONE, 0) #define mp_hal_pin_input(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_INPUT, MP_HAL_PIN_PULL_NONE, 0)
#define mp_hal_pin_output(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_OUTPUT, MP_HAL_PIN_PULL_NONE, 0) #define mp_hal_pin_output(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_OUTPUT, MP_HAL_PIN_PULL_NONE, 0)
#define mp_hal_pin_open_drain(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_OPEN_DRAIN, MP_HAL_PIN_PULL_NONE, 0) #define mp_hal_pin_open_drain(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_OPEN_DRAIN, MP_HAL_PIN_PULL_NONE, 0)
#define mp_hal_pin_low(p) (((GPIO_TypeDef*)((p) & ~0xf))->BSRR = 0x10000 << ((p) & 0xf)) #define mp_hal_pin_low(p) (((GPIO_TypeDef *)((p) & ~0xf))->BSRR = 0x10000 << ((p) & 0xf))
#define mp_hal_pin_high(p) (((GPIO_TypeDef*)((p) & ~0xf))->BSRR = 1 << ((p) & 0xf)) #define mp_hal_pin_high(p) (((GPIO_TypeDef *)((p) & ~0xf))->BSRR = 1 << ((p) & 0xf))
#define mp_hal_pin_od_low(p) mp_hal_pin_low(p) #define mp_hal_pin_od_low(p) mp_hal_pin_low(p)
#define mp_hal_pin_od_high(p) mp_hal_pin_high(p) #define mp_hal_pin_od_high(p) mp_hal_pin_high(p)
#define mp_hal_pin_read(p) ((((GPIO_TypeDef*)((p) & ~0xf))->IDR >> ((p) & 0xf)) & 1) #define mp_hal_pin_read(p) ((((GPIO_TypeDef *)((p) & ~0xf))->IDR >> ((p) & 0xf)) & 1)
#define mp_hal_pin_write(p, v) ((v) ? mp_hal_pin_high(p) : mp_hal_pin_low(p)) #define mp_hal_pin_write(p, v) ((v) ? mp_hal_pin_high(p) : mp_hal_pin_low(p))
void mp_hal_pin_config(uint32_t port_pin, uint32_t mode, uint32_t pull, uint32_t alt); void mp_hal_pin_config(uint32_t port_pin, uint32_t mode, uint32_t pull, uint32_t alt);
void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed); void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_A0 (GPIOA_BASE | 0) #define pin_A0 (GPIOA_BASE | 0)
#define pin_A1 (GPIOA_BASE | 1) #define pin_A1 (GPIOA_BASE | 1)
#define pin_A2 (GPIOA_BASE | 2) #define pin_A2 (GPIOA_BASE | 2)
#define pin_A3 (GPIOA_BASE | 3) #define pin_A3 (GPIOA_BASE | 3)
#define pin_A4 (GPIOA_BASE | 4) #define pin_A4 (GPIOA_BASE | 4)
#define pin_A5 (GPIOA_BASE | 5) #define pin_A5 (GPIOA_BASE | 5)
#define pin_A6 (GPIOA_BASE | 6) #define pin_A6 (GPIOA_BASE | 6)
#define pin_A7 (GPIOA_BASE | 7) #define pin_A7 (GPIOA_BASE | 7)
#define pin_A8 (GPIOA_BASE | 8) #define pin_A8 (GPIOA_BASE | 8)
#define pin_A9 (GPIOA_BASE | 9) #define pin_A9 (GPIOA_BASE | 9)
#define pin_A10 (GPIOA_BASE | 10) #define pin_A10 (GPIOA_BASE | 10)
#define pin_A11 (GPIOA_BASE | 11) #define pin_A11 (GPIOA_BASE | 11)
#define pin_A12 (GPIOA_BASE | 12) #define pin_A12 (GPIOA_BASE | 12)
@ -85,16 +85,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_A14 (GPIOA_BASE | 14) #define pin_A14 (GPIOA_BASE | 14)
#define pin_A15 (GPIOA_BASE | 15) #define pin_A15 (GPIOA_BASE | 15)
#define pin_B0 (GPIOB_BASE | 0) #define pin_B0 (GPIOB_BASE | 0)
#define pin_B1 (GPIOB_BASE | 1) #define pin_B1 (GPIOB_BASE | 1)
#define pin_B2 (GPIOB_BASE | 2) #define pin_B2 (GPIOB_BASE | 2)
#define pin_B3 (GPIOB_BASE | 3) #define pin_B3 (GPIOB_BASE | 3)
#define pin_B4 (GPIOB_BASE | 4) #define pin_B4 (GPIOB_BASE | 4)
#define pin_B5 (GPIOB_BASE | 5) #define pin_B5 (GPIOB_BASE | 5)
#define pin_B6 (GPIOB_BASE | 6) #define pin_B6 (GPIOB_BASE | 6)
#define pin_B7 (GPIOB_BASE | 7) #define pin_B7 (GPIOB_BASE | 7)
#define pin_B8 (GPIOB_BASE | 8) #define pin_B8 (GPIOB_BASE | 8)
#define pin_B9 (GPIOB_BASE | 9) #define pin_B9 (GPIOB_BASE | 9)
#define pin_B10 (GPIOB_BASE | 10) #define pin_B10 (GPIOB_BASE | 10)
#define pin_B11 (GPIOB_BASE | 11) #define pin_B11 (GPIOB_BASE | 11)
#define pin_B12 (GPIOB_BASE | 12) #define pin_B12 (GPIOB_BASE | 12)
@ -102,16 +102,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_B14 (GPIOB_BASE | 14) #define pin_B14 (GPIOB_BASE | 14)
#define pin_B15 (GPIOB_BASE | 15) #define pin_B15 (GPIOB_BASE | 15)
#define pin_C0 (GPIOC_BASE | 0) #define pin_C0 (GPIOC_BASE | 0)
#define pin_C1 (GPIOC_BASE | 1) #define pin_C1 (GPIOC_BASE | 1)
#define pin_C2 (GPIOC_BASE | 2) #define pin_C2 (GPIOC_BASE | 2)
#define pin_C3 (GPIOC_BASE | 3) #define pin_C3 (GPIOC_BASE | 3)
#define pin_C4 (GPIOC_BASE | 4) #define pin_C4 (GPIOC_BASE | 4)
#define pin_C5 (GPIOC_BASE | 5) #define pin_C5 (GPIOC_BASE | 5)
#define pin_C6 (GPIOC_BASE | 6) #define pin_C6 (GPIOC_BASE | 6)
#define pin_C7 (GPIOC_BASE | 7) #define pin_C7 (GPIOC_BASE | 7)
#define pin_C8 (GPIOC_BASE | 8) #define pin_C8 (GPIOC_BASE | 8)
#define pin_C9 (GPIOC_BASE | 9) #define pin_C9 (GPIOC_BASE | 9)
#define pin_C10 (GPIOC_BASE | 10) #define pin_C10 (GPIOC_BASE | 10)
#define pin_C11 (GPIOC_BASE | 11) #define pin_C11 (GPIOC_BASE | 11)
#define pin_C12 (GPIOC_BASE | 12) #define pin_C12 (GPIOC_BASE | 12)
@ -119,16 +119,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_C14 (GPIOC_BASE | 14) #define pin_C14 (GPIOC_BASE | 14)
#define pin_C15 (GPIOC_BASE | 15) #define pin_C15 (GPIOC_BASE | 15)
#define pin_D0 (GPIOD_BASE | 0) #define pin_D0 (GPIOD_BASE | 0)
#define pin_D1 (GPIOD_BASE | 1) #define pin_D1 (GPIOD_BASE | 1)
#define pin_D2 (GPIOD_BASE | 2) #define pin_D2 (GPIOD_BASE | 2)
#define pin_D3 (GPIOD_BASE | 3) #define pin_D3 (GPIOD_BASE | 3)
#define pin_D4 (GPIOD_BASE | 4) #define pin_D4 (GPIOD_BASE | 4)
#define pin_D5 (GPIOD_BASE | 5) #define pin_D5 (GPIOD_BASE | 5)
#define pin_D6 (GPIOD_BASE | 6) #define pin_D6 (GPIOD_BASE | 6)
#define pin_D7 (GPIOD_BASE | 7) #define pin_D7 (GPIOD_BASE | 7)
#define pin_D8 (GPIOD_BASE | 8) #define pin_D8 (GPIOD_BASE | 8)
#define pin_D9 (GPIOD_BASE | 9) #define pin_D9 (GPIOD_BASE | 9)
#define pin_D10 (GPIOD_BASE | 10) #define pin_D10 (GPIOD_BASE | 10)
#define pin_D11 (GPIOD_BASE | 11) #define pin_D11 (GPIOD_BASE | 11)
#define pin_D12 (GPIOD_BASE | 12) #define pin_D12 (GPIOD_BASE | 12)
@ -136,16 +136,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_D14 (GPIOD_BASE | 14) #define pin_D14 (GPIOD_BASE | 14)
#define pin_D15 (GPIOD_BASE | 15) #define pin_D15 (GPIOD_BASE | 15)
#define pin_E0 (GPIOE_BASE | 0) #define pin_E0 (GPIOE_BASE | 0)
#define pin_E1 (GPIOE_BASE | 1) #define pin_E1 (GPIOE_BASE | 1)
#define pin_E2 (GPIOE_BASE | 2) #define pin_E2 (GPIOE_BASE | 2)
#define pin_E3 (GPIOE_BASE | 3) #define pin_E3 (GPIOE_BASE | 3)
#define pin_E4 (GPIOE_BASE | 4) #define pin_E4 (GPIOE_BASE | 4)
#define pin_E5 (GPIOE_BASE | 5) #define pin_E5 (GPIOE_BASE | 5)
#define pin_E6 (GPIOE_BASE | 6) #define pin_E6 (GPIOE_BASE | 6)
#define pin_E7 (GPIOE_BASE | 7) #define pin_E7 (GPIOE_BASE | 7)
#define pin_E8 (GPIOE_BASE | 8) #define pin_E8 (GPIOE_BASE | 8)
#define pin_E9 (GPIOE_BASE | 9) #define pin_E9 (GPIOE_BASE | 9)
#define pin_E10 (GPIOE_BASE | 10) #define pin_E10 (GPIOE_BASE | 10)
#define pin_E11 (GPIOE_BASE | 11) #define pin_E11 (GPIOE_BASE | 11)
#define pin_E12 (GPIOE_BASE | 12) #define pin_E12 (GPIOE_BASE | 12)
@ -153,16 +153,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_E14 (GPIOE_BASE | 14) #define pin_E14 (GPIOE_BASE | 14)
#define pin_E15 (GPIOE_BASE | 15) #define pin_E15 (GPIOE_BASE | 15)
#define pin_F0 (GPIOF_BASE | 0) #define pin_F0 (GPIOF_BASE | 0)
#define pin_F1 (GPIOF_BASE | 1) #define pin_F1 (GPIOF_BASE | 1)
#define pin_F2 (GPIOF_BASE | 2) #define pin_F2 (GPIOF_BASE | 2)
#define pin_F3 (GPIOF_BASE | 3) #define pin_F3 (GPIOF_BASE | 3)
#define pin_F4 (GPIOF_BASE | 4) #define pin_F4 (GPIOF_BASE | 4)
#define pin_F5 (GPIOF_BASE | 5) #define pin_F5 (GPIOF_BASE | 5)
#define pin_F6 (GPIOF_BASE | 6) #define pin_F6 (GPIOF_BASE | 6)
#define pin_F7 (GPIOF_BASE | 7) #define pin_F7 (GPIOF_BASE | 7)
#define pin_F8 (GPIOF_BASE | 8) #define pin_F8 (GPIOF_BASE | 8)
#define pin_F9 (GPIOF_BASE | 9) #define pin_F9 (GPIOF_BASE | 9)
#define pin_F10 (GPIOF_BASE | 10) #define pin_F10 (GPIOF_BASE | 10)
#define pin_F11 (GPIOF_BASE | 11) #define pin_F11 (GPIOF_BASE | 11)
#define pin_F12 (GPIOF_BASE | 12) #define pin_F12 (GPIOF_BASE | 12)
@ -170,16 +170,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_F14 (GPIOF_BASE | 14) #define pin_F14 (GPIOF_BASE | 14)
#define pin_F15 (GPIOF_BASE | 15) #define pin_F15 (GPIOF_BASE | 15)
#define pin_G0 (GPIOG_BASE | 0) #define pin_G0 (GPIOG_BASE | 0)
#define pin_G1 (GPIOG_BASE | 1) #define pin_G1 (GPIOG_BASE | 1)
#define pin_G2 (GPIOG_BASE | 2) #define pin_G2 (GPIOG_BASE | 2)
#define pin_G3 (GPIOG_BASE | 3) #define pin_G3 (GPIOG_BASE | 3)
#define pin_G4 (GPIOG_BASE | 4) #define pin_G4 (GPIOG_BASE | 4)
#define pin_G5 (GPIOG_BASE | 5) #define pin_G5 (GPIOG_BASE | 5)
#define pin_G6 (GPIOG_BASE | 6) #define pin_G6 (GPIOG_BASE | 6)
#define pin_G7 (GPIOG_BASE | 7) #define pin_G7 (GPIOG_BASE | 7)
#define pin_G8 (GPIOG_BASE | 8) #define pin_G8 (GPIOG_BASE | 8)
#define pin_G9 (GPIOG_BASE | 9) #define pin_G9 (GPIOG_BASE | 9)
#define pin_G10 (GPIOG_BASE | 10) #define pin_G10 (GPIOG_BASE | 10)
#define pin_G11 (GPIOG_BASE | 11) #define pin_G11 (GPIOG_BASE | 11)
#define pin_G12 (GPIOG_BASE | 12) #define pin_G12 (GPIOG_BASE | 12)
@ -187,16 +187,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_G14 (GPIOG_BASE | 14) #define pin_G14 (GPIOG_BASE | 14)
#define pin_G15 (GPIOG_BASE | 15) #define pin_G15 (GPIOG_BASE | 15)
#define pin_H0 (GPIOH_BASE | 0) #define pin_H0 (GPIOH_BASE | 0)
#define pin_H1 (GPIOH_BASE | 1) #define pin_H1 (GPIOH_BASE | 1)
#define pin_H2 (GPIOH_BASE | 2) #define pin_H2 (GPIOH_BASE | 2)
#define pin_H3 (GPIOH_BASE | 3) #define pin_H3 (GPIOH_BASE | 3)
#define pin_H4 (GPIOH_BASE | 4) #define pin_H4 (GPIOH_BASE | 4)
#define pin_H5 (GPIOH_BASE | 5) #define pin_H5 (GPIOH_BASE | 5)
#define pin_H6 (GPIOH_BASE | 6) #define pin_H6 (GPIOH_BASE | 6)
#define pin_H7 (GPIOH_BASE | 7) #define pin_H7 (GPIOH_BASE | 7)
#define pin_H8 (GPIOH_BASE | 8) #define pin_H8 (GPIOH_BASE | 8)
#define pin_H9 (GPIOH_BASE | 9) #define pin_H9 (GPIOH_BASE | 9)
#define pin_H10 (GPIOH_BASE | 10) #define pin_H10 (GPIOH_BASE | 10)
#define pin_H11 (GPIOH_BASE | 11) #define pin_H11 (GPIOH_BASE | 11)
#define pin_H12 (GPIOH_BASE | 12) #define pin_H12 (GPIOH_BASE | 12)
@ -204,16 +204,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_H14 (GPIOH_BASE | 14) #define pin_H14 (GPIOH_BASE | 14)
#define pin_H15 (GPIOH_BASE | 15) #define pin_H15 (GPIOH_BASE | 15)
#define pin_I0 (GPIOI_BASE | 0) #define pin_I0 (GPIOI_BASE | 0)
#define pin_I1 (GPIOI_BASE | 1) #define pin_I1 (GPIOI_BASE | 1)
#define pin_I2 (GPIOI_BASE | 2) #define pin_I2 (GPIOI_BASE | 2)
#define pin_I3 (GPIOI_BASE | 3) #define pin_I3 (GPIOI_BASE | 3)
#define pin_I4 (GPIOI_BASE | 4) #define pin_I4 (GPIOI_BASE | 4)
#define pin_I5 (GPIOI_BASE | 5) #define pin_I5 (GPIOI_BASE | 5)
#define pin_I6 (GPIOI_BASE | 6) #define pin_I6 (GPIOI_BASE | 6)
#define pin_I7 (GPIOI_BASE | 7) #define pin_I7 (GPIOI_BASE | 7)
#define pin_I8 (GPIOI_BASE | 8) #define pin_I8 (GPIOI_BASE | 8)
#define pin_I9 (GPIOI_BASE | 9) #define pin_I9 (GPIOI_BASE | 9)
#define pin_I10 (GPIOI_BASE | 10) #define pin_I10 (GPIOI_BASE | 10)
#define pin_I11 (GPIOI_BASE | 11) #define pin_I11 (GPIOI_BASE | 11)
#define pin_I12 (GPIOI_BASE | 12) #define pin_I12 (GPIOI_BASE | 12)
@ -221,16 +221,16 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed);
#define pin_I14 (GPIOI_BASE | 14) #define pin_I14 (GPIOI_BASE | 14)
#define pin_I15 (GPIOI_BASE | 15) #define pin_I15 (GPIOI_BASE | 15)
#define pin_J0 (GPIOJ_BASE | 0) #define pin_J0 (GPIOJ_BASE | 0)
#define pin_J1 (GPIOJ_BASE | 1) #define pin_J1 (GPIOJ_BASE | 1)
#define pin_J2 (GPIOJ_BASE | 2) #define pin_J2 (GPIOJ_BASE | 2)
#define pin_J3 (GPIOJ_BASE | 3) #define pin_J3 (GPIOJ_BASE | 3)
#define pin_J4 (GPIOJ_BASE | 4) #define pin_J4 (GPIOJ_BASE | 4)
#define pin_J5 (GPIOJ_BASE | 5) #define pin_J5 (GPIOJ_BASE | 5)
#define pin_J6 (GPIOJ_BASE | 6) #define pin_J6 (GPIOJ_BASE | 6)
#define pin_J7 (GPIOJ_BASE | 7) #define pin_J7 (GPIOJ_BASE | 7)
#define pin_J8 (GPIOJ_BASE | 8) #define pin_J8 (GPIOJ_BASE | 8)
#define pin_J9 (GPIOJ_BASE | 9) #define pin_J9 (GPIOJ_BASE | 9)
#define pin_J10 (GPIOJ_BASE | 10) #define pin_J10 (GPIOJ_BASE | 10)
#define pin_J11 (GPIOJ_BASE | 11) #define pin_J11 (GPIOJ_BASE | 11)
#define pin_J12 (GPIOJ_BASE | 12) #define pin_J12 (GPIOJ_BASE | 12)

2
ports/stm32/mboot/pack.c
View File

@ -284,7 +284,7 @@ int mboot_pack_write(uint32_t addr, const uint8_t *src8, size_t len, bool dry_ru
} else if (firmware_chunk_buf.header.format == MBOOT_PACK_CHUNK_FULL_SIG) { } else if (firmware_chunk_buf.header.format == MBOOT_PACK_CHUNK_FULL_SIG) {
return mboot_pack_handle_full_sig(); return mboot_pack_handle_full_sig();
} else if (firmware_chunk_buf.header.format == MBOOT_PACK_CHUNK_FW_RAW } else if (firmware_chunk_buf.header.format == MBOOT_PACK_CHUNK_FW_RAW
|| firmware_chunk_buf.header.format == MBOOT_PACK_CHUNK_FW_GZIP) { || firmware_chunk_buf.header.format == MBOOT_PACK_CHUNK_FW_GZIP) {
return mboot_pack_handle_firmware(); return mboot_pack_handle_firmware();
} else { } else {
// Unsupported contents. // Unsupported contents.

8
ports/stm32/mboot/vfs_fat.c
View File

@ -58,20 +58,20 @@ DRESULT disk_ioctl(void *pdrv, BYTE cmd, void *buf) {
return RES_OK; return RES_OK;
case GET_SECTOR_COUNT: case GET_SECTOR_COUNT:
*((DWORD*)buf) = ctx->bdev_num_blocks; *((DWORD *)buf) = ctx->bdev_num_blocks;
return RES_OK; return RES_OK;
case GET_SECTOR_SIZE: case GET_SECTOR_SIZE:
*((WORD*)buf) = SECSIZE; *((WORD *)buf) = SECSIZE;
return RES_OK; return RES_OK;
case GET_BLOCK_SIZE: case GET_BLOCK_SIZE:
*((DWORD*)buf) = 1; // erase block size in units of sector size *((DWORD *)buf) = 1; // erase block size in units of sector size
return RES_OK; return RES_OK;
case IOCTL_INIT: case IOCTL_INIT:
case IOCTL_STATUS: case IOCTL_STATUS:
*((DSTATUS*)buf) = STA_PROTECT; *((DSTATUS *)buf) = STA_PROTECT;
return RES_OK; return RES_OK;
default: default:

12
ports/stm32/mboot/vfs_lfs.c
View File

@ -41,7 +41,7 @@
#define MBOOT_ERRNO_VFS_LFS_OPEN_FAILED MBOOT_ERRNO_VFS_LFS1_OPEN_FAILED #define MBOOT_ERRNO_VFS_LFS_OPEN_FAILED MBOOT_ERRNO_VFS_LFS1_OPEN_FAILED
#define LFSx_MACRO(s) LFS1##s #define LFSx_MACRO(s) LFS1##s
#define LFSx_API(x) lfs1_ ## x #define LFSx_API(x) lfs1_##x
#define VFS_LFSx_CONTEXT_T vfs_lfs1_context_t #define VFS_LFSx_CONTEXT_T vfs_lfs1_context_t
#define VFS_LFSx_MOUNT vfs_lfs1_mount #define VFS_LFSx_MOUNT vfs_lfs1_mount
#define VFS_LFSx_STREAM_METHODS vfs_lfs1_stream_methods #define VFS_LFSx_STREAM_METHODS vfs_lfs1_stream_methods
@ -56,7 +56,7 @@ static uint8_t lfs_lookahead_buffer[LFS_LOOKAHEAD_SIZE / 8];
#define MBOOT_ERRNO_VFS_LFS_OPEN_FAILED MBOOT_ERRNO_VFS_LFS2_OPEN_FAILED #define MBOOT_ERRNO_VFS_LFS_OPEN_FAILED MBOOT_ERRNO_VFS_LFS2_OPEN_FAILED
#define LFSx_MACRO(s) LFS2##s #define LFSx_MACRO(s) LFS2##s
#define LFSx_API(x) lfs2_ ## x #define LFSx_API(x) lfs2_##x
#define VFS_LFSx_CONTEXT_T vfs_lfs2_context_t #define VFS_LFSx_CONTEXT_T vfs_lfs2_context_t
#define VFS_LFSx_MOUNT vfs_lfs2_mount #define VFS_LFSx_MOUNT vfs_lfs2_mount
#define VFS_LFSx_STREAM_METHODS vfs_lfs2_stream_methods #define VFS_LFSx_STREAM_METHODS vfs_lfs2_stream_methods
@ -67,7 +67,7 @@ static uint8_t lfs_lookahead_buffer[LFS_LOOKAHEAD_SIZE];
#endif #endif
static int dev_read(const struct LFSx_API (config) * c, LFSx_API(block_t) block, LFSx_API(off_t) off, void *buffer, LFSx_API(size_t) size) { static int dev_read(const struct LFSx_API (config) * c, LFSx_API(block_t)block, LFSx_API(off_t)off, void *buffer, LFSx_API(size_t)size) {
VFS_LFSx_CONTEXT_T *ctx = c->context; VFS_LFSx_CONTEXT_T *ctx = c->context;
if (0 <= block && block < ctx->config.block_count) { if (0 <= block && block < ctx->config.block_count) {
mboot_addr_t addr = ctx->bdev_base_addr + (mboot_addr_t)block * (mboot_addr_t)ctx->config.block_size + (mboot_addr_t)off; mboot_addr_t addr = ctx->bdev_base_addr + (mboot_addr_t)block * (mboot_addr_t)ctx->config.block_size + (mboot_addr_t)off;
@ -77,11 +77,11 @@ static int dev_read(const struct LFSx_API (config) * c, LFSx_API(block_t) block,
return LFSx_MACRO(_ERR_IO); return LFSx_MACRO(_ERR_IO);
} }
static int dev_prog(const struct LFSx_API (config) * c, LFSx_API(block_t) block, LFSx_API(off_t) off, const void *buffer, LFSx_API(size_t) size) { static int dev_prog(const struct LFSx_API (config) * c, LFSx_API(block_t)block, LFSx_API(off_t)off, const void *buffer, LFSx_API(size_t)size) {
return LFSx_MACRO(_ERR_IO); return LFSx_MACRO(_ERR_IO);
} }
static int dev_erase(const struct LFSx_API (config) * c, LFSx_API(block_t) block) { static int dev_erase(const struct LFSx_API (config) * c, LFSx_API(block_t)block) {
return LFSx_MACRO(_ERR_IO); return LFSx_MACRO(_ERR_IO);
} }
@ -92,7 +92,7 @@ static int dev_sync(const struct LFSx_API (config) * c) {
int VFS_LFSx_MOUNT(VFS_LFSx_CONTEXT_T *ctx, mboot_addr_t base_addr, mboot_addr_t byte_len, uint32_t block_size) { int VFS_LFSx_MOUNT(VFS_LFSx_CONTEXT_T *ctx, mboot_addr_t base_addr, mboot_addr_t byte_len, uint32_t block_size) {
ctx->bdev_base_addr = base_addr; ctx->bdev_base_addr = base_addr;
struct LFSx_API (config) *config = &ctx->config; struct LFSx_API (config) * config = &ctx->config;
memset(config, 0, sizeof(*config)); memset(config, 0, sizeof(*config));
config->context = ctx; config->context = ctx;

2
ports/unix/variants/coverage/frzmpy/frzmpy1.py
View File

@ -1 +1 @@
print('frzmpy1') print("frzmpy1")

2
ports/unix/variants/coverage/frzmpy/frzmpy_pkg1/__init__.py
View File

@ -1,3 +1,3 @@
# test frozen package with __init__.py # test frozen package with __init__.py
print('frzmpy_pkg1.__init__') print("frzmpy_pkg1.__init__")
x = 1 x = 1

4
ports/unix/variants/coverage/frzmpy/frzmpy_pkg2/mod.py
View File

@ -1,4 +1,6 @@
# test frozen package without __init__.py # test frozen package without __init__.py
print('frzmpy_pkg2.mod') print("frzmpy_pkg2.mod")
class Foo: class Foo:
x = 1 x = 1

2
ports/unix/variants/coverage/frzstr/frzstr1.py
View File

@ -1 +1 @@
print('frzstr1') print("frzstr1")

2
ports/unix/variants/coverage/frzstr/frzstr_pkg1/__init__.py
View File

@ -1,3 +1,3 @@
# test frozen package with __init__.py # test frozen package with __init__.py
print('frzstr_pkg1.__init__') print("frzstr_pkg1.__init__")
x = 1 x = 1

4
ports/unix/variants/coverage/frzstr/frzstr_pkg2/mod.py
View File

@ -1,4 +1,6 @@
# test frozen package without __init__.py # test frozen package without __init__.py
print('frzstr_pkg2.mod') print("frzstr_pkg2.mod")
class Foo: class Foo:
x = 1 x = 1

4
ports/unix/variants/manifest.py
View File

@ -1,2 +1,2 @@
freeze_as_mpy('$(MPY_DIR)/tools', 'upip.py') freeze_as_mpy("$(MPY_DIR)/tools", "upip.py")
freeze_as_mpy('$(MPY_DIR)/tools', 'upip_utarfile.py', opt=3) freeze_as_mpy("$(MPY_DIR)/tools", "upip_utarfile.py", opt=3)

5
ports/zephyr/src/zephyr_getchar.c
View File

@ -30,8 +30,7 @@ static struct k_sem uart_sem;
static uint8_t uart_ringbuf[UART_BUFSIZE]; static uint8_t uart_ringbuf[UART_BUFSIZE];
static uint8_t i_get, i_put; static uint8_t i_get, i_put;
static int console_irq_input_hook(uint8_t ch) static int console_irq_input_hook(uint8_t ch) {
{
int i_next = (i_put + 1) & (UART_BUFSIZE - 1); int i_next = (i_put + 1) & (UART_BUFSIZE - 1);
if (i_next == i_get) { if (i_next == i_get) {
printk("UART buffer overflow - char dropped\n"); printk("UART buffer overflow - char dropped\n");
@ -45,7 +44,7 @@ static int console_irq_input_hook(uint8_t ch)
uart_ringbuf[i_put] = ch; uart_ringbuf[i_put] = ch;
i_put = i_next; i_put = i_next;
} }
//printk("%x\n", ch); // printk("%x\n", ch);
k_sem_give(&uart_sem); k_sem_give(&uart_sem);
k_yield(); k_yield();
return 1; return 1;

6
ports/zephyr/src/zephyr_start.c
View File

@ -30,11 +30,11 @@
int real_main(void); int real_main(void);
void main(void) { void main(void) {
#ifdef CONFIG_CONSOLE_SUBSYS #ifdef CONFIG_CONSOLE_SUBSYS
console_init(); console_init();
#else #else
zephyr_getchar_init(); zephyr_getchar_init();
#endif #endif
real_main(); real_main();
// This is needed so the linker includes k_timer_init, z_impl_k_timer_start // This is needed so the linker includes k_timer_init, z_impl_k_timer_start