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feat(swan_r5): the upper 1MB of flash (bank 2) is made available for the filesystem

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This commit is contained in:
Matthew McGowan 2022-05-25 14:19:35 -07:00
parent b607631ae1
commit 5bbaa3b732
4 changed files with 10 additions and 11 deletions
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2
ports/stm/boards/STM32L4R5_boot.ld
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@ -8,7 +8,7 @@ MEMORY
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
FLASH_ISR (rx) : ORIGIN = 0x08010000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 1024K-128K-64K-4K /* For now, limit to 1MB so that bank switching is still possible. */
FLASH_FS (rw) : ORIGIN = 0x080e0000, LENGTH = 128K
FLASH_FS (rw) : ORIGIN = 0x08100000, LENGTH = 1024K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K
}

2
ports/stm/boards/STM32L4R5_default.ld
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@ -8,7 +8,7 @@ MEMORY
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
FLASH_FIRMWARE (rx) : ORIGIN = 0x08001000, LENGTH = 1024K-128K-4K /* For now, limit to 1MB so that bank switching is still possible. */
FLASH_FS (rw) : ORIGIN = 0x080e0000, LENGTH = 128K
FLASH_FS (rw) : ORIGIN = 0x08100000, LENGTH = 1024K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K
}

11
ports/stm/supervisor/internal_flash.c
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@ -95,12 +95,8 @@ STATIC const flash_layout_t flash_layout[] = {
STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4)));
#elif defined(STM32L4)
// todo - the L4 devices can have different flash sizes and different page sizes
// depending upon the dual bank configuration
// This is hardcoded for the Swan R5. When support for other devices is needed more conditionals will be required
// to differentiate.
STATIC const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x1000, 256 },
{ 0x08100000, 0x1000, 256 },
};
STATIC uint8_t _flash_cache[0x1000] __attribute__((aligned(4)));
@ -174,6 +170,9 @@ uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *si
}
void supervisor_flash_init(void) {
#ifdef STM32L4
// todo - check that the device is in dual bank mode
#endif
}
uint32_t supervisor_flash_get_block_size(void) {
@ -202,7 +201,7 @@ void port_internal_flash_flush(void) {
FLASH_EraseInitTypeDef EraseInitStruct = {};
#if CPY_STM32L4
EraseInitStruct.TypeErase = TYPEERASE_PAGES;
EraseInitStruct.Banks = FLASH_BANK_1;
EraseInitStruct.Banks = FLASH_BANK_2; // filesystem stored in upper 1MB of flash in dual bank mode
#else
EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V

6
ports/stm/supervisor/internal_flash.h
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@ -97,9 +97,9 @@
#endif
#ifdef STM32L4R5xx
#define STM32_FLASH_SIZE 0x100000 // 1MB // for now just use the first bank
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x20000 // 128KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x080e0000
#define STM32_FLASH_SIZE 0x200000 // 2MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x100000 // 1024KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08100000
#endif
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)