From 59cb8e91b2696f81256069f59fbd216de071e8b0 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Fri, 12 Nov 2021 19:30:24 -0600 Subject: [PATCH] mimxrt1011: enable -Werror=missing-prototypes --- ports/mimxrt10xx/Makefile | 4 ++-- ports/mimxrt10xx/common-hal/analogio/AnalogIn.c | 1 + ports/mimxrt10xx/common-hal/busio/I2C.h | 2 ++ ports/mimxrt10xx/common-hal/busio/UART.c | 2 +- ports/mimxrt10xx/common-hal/busio/UART.h | 1 + ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c | 2 +- ports/mimxrt10xx/common-hal/microcontroller/Processor.c | 1 + ports/mimxrt10xx/common-hal/os/__init__.c | 4 +++- ports/mimxrt10xx/common-hal/rtc/RTC.c | 2 ++ ports/mimxrt10xx/mphalport.c | 1 + .../mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c | 2 ++ ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c | 5 +++-- ports/mimxrt10xx/supervisor/internal_flash.c | 4 ---- ports/mimxrt10xx/supervisor/internal_flash.h | 6 ++++++ ports/mimxrt10xx/supervisor/port.c | 7 +++++++ ports/mimxrt10xx/supervisor/usb.c | 1 + 16 files changed, 34 insertions(+), 11 deletions(-) diff --git a/ports/mimxrt10xx/Makefile b/ports/mimxrt10xx/Makefile index 5a8ac51fcf..8e83fb53b8 100644 --- a/ports/mimxrt10xx/Makefile +++ b/ports/mimxrt10xx/Makefile @@ -92,7 +92,7 @@ else #CFLAGS += -flto -flto-partition=none endif -CFLAGS += $(INC) -ggdb -Wall -Werror -std=gnu11 -nostdlib -fshort-enums $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) +CFLAGS += $(INC) -ggdb -Wall -Werror -std=gnu11 -nostdlib -fshort-enums $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) -Werror=missing-prototypes # TODO: add these when -Werror is applied # Disable some warnings, as do most ports. NXP SDK causes undef, tinyusb causes cast-align @@ -148,7 +148,7 @@ SRC_SDK := \ system_$(CHIP_FAMILY).c \ SRC_SDK := $(addprefix sdk/devices/$(CHIP_FAMILY)/, $(SRC_SDK)) -$(addprefix $(BUILD)/, $(SRC_SDK:.c=.o)): CFLAGS += -Wno-undef +$(addprefix $(BUILD)/, $(SRC_SDK:.c=.o)): CFLAGS += -Wno-undef -Wno-missing-prototypes SRC_C += \ background.c \ diff --git a/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c b/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c index 5e7bb82c77..2d809c258c 100644 --- a/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c +++ b/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c @@ -26,6 +26,7 @@ */ #include "common-hal/analogio/AnalogIn.h" +#include "shared-bindings/analogio/AnalogIn.h" #include "shared-bindings/microcontroller/Pin.h" #include diff --git a/ports/mimxrt10xx/common-hal/busio/I2C.h b/ports/mimxrt10xx/common-hal/busio/I2C.h index 789f01a5f5..6b37255fe3 100644 --- a/ports/mimxrt10xx/common-hal/busio/I2C.h +++ b/ports/mimxrt10xx/common-hal/busio/I2C.h @@ -41,4 +41,6 @@ typedef struct { const mcu_periph_obj_t *sda; } busio_i2c_obj_t; +void i2c_reset(void); + #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_BUSIO_I2C_H diff --git a/ports/mimxrt10xx/common-hal/busio/UART.c b/ports/mimxrt10xx/common-hal/busio/UART.c index 16c4ba77e4..7933975322 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.c +++ b/ports/mimxrt10xx/common-hal/busio/UART.c @@ -65,7 +65,7 @@ static void config_periph_pin(const mcu_periph_obj_t *periph) { | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } -void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *user_data) { +STATIC void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *user_data) { busio_uart_obj_t *self = (busio_uart_obj_t *)user_data; if (status == kStatus_LPUART_RxIdle) { diff --git a/ports/mimxrt10xx/common-hal/busio/UART.h b/ports/mimxrt10xx/common-hal/busio/UART.h index 604fef2cf3..78c91173a3 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.h +++ b/ports/mimxrt10xx/common-hal/busio/UART.h @@ -51,4 +51,5 @@ typedef struct { const mcu_periph_obj_t *rts; } busio_uart_obj_t; +void uart_reset(void); #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_BUSIO_UART_H diff --git a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c index 445ffa91c5..27753f47dc 100644 --- a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c +++ b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c @@ -40,7 +40,7 @@ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5 5U -void pin_config(const mcu_pin_obj_t *pin, bool open_drain, digitalio_pull_t pull) { +STATIC void pin_config(const mcu_pin_obj_t *pin, bool open_drain, digitalio_pull_t pull) { IOMUXC_SetPinConfig(0, 0, 0, 0, pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(1) | IOMUXC_SW_PAD_CTL_PAD_PUS((pull == PULL_UP) ? 2 : 0) diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c index b097133d57..697d97ca43 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c @@ -28,6 +28,7 @@ #include #include "common-hal/microcontroller/Processor.h" +#include "shared-bindings/microcontroller/Processor.h" #include "shared-bindings/microcontroller/ResetReason.h" #include "fsl_tempmon.h" diff --git a/ports/mimxrt10xx/common-hal/os/__init__.c b/ports/mimxrt10xx/common-hal/os/__init__.c index dd1d186f1c..e2c43e43fa 100644 --- a/ports/mimxrt10xx/common-hal/os/__init__.c +++ b/ports/mimxrt10xx/common-hal/os/__init__.c @@ -31,6 +31,8 @@ #include "py/objtuple.h" #include "py/qstr.h" +#include "shared-bindings/os/__init__.h" + #include "fsl_trng.h" STATIC const qstr os_uname_info_fields[] = { @@ -58,7 +60,7 @@ mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; } -bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { +bool common_hal_os_urandom(uint8_t *buffer, mp_uint_t length) { trng_config_t trngConfig; TRNG_GetDefaultConfig(&trngConfig); diff --git a/ports/mimxrt10xx/common-hal/rtc/RTC.c b/ports/mimxrt10xx/common-hal/rtc/RTC.c index 8619a7eaec..04aa799ce5 100644 --- a/ports/mimxrt10xx/common-hal/rtc/RTC.c +++ b/ports/mimxrt10xx/common-hal/rtc/RTC.c @@ -31,6 +31,8 @@ #include "py/runtime.h" #include "shared/timeutils/timeutils.h" #include "shared-bindings/rtc/__init__.h" +#include "shared-bindings/rtc/RTC.h" +#include "common-hal/rtc/RTC.h" #include "supervisor/shared/translate.h" #include "fsl_snvs_hp.h" diff --git a/ports/mimxrt10xx/mphalport.c b/ports/mimxrt10xx/mphalport.c index ff7a880ab7..ad0fb4d9ba 100644 --- a/ports/mimxrt10xx/mphalport.c +++ b/ports/mimxrt10xx/mphalport.c @@ -25,6 +25,7 @@ * THE SOFTWARE. */ +#include "py/mphal.h" #include "py/mpstate.h" #include "py/smallint.h" diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c index e6354386a9..e96b55f3e9 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c @@ -35,6 +35,8 @@ #include "fsl_clock.h" #include "fsl_iomuxc.h" +#include "clocks.h" + #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ diff --git a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c index 251e6f9acd..950e9aa403 100644 --- a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c +++ b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c @@ -10,9 +10,10 @@ #include "fsl_flexspi.h" #include "internal_flash.h" #include "boards/flash_config.h" +#include "supervisor/internal_flash.h" #include "supervisor/linker.h" -status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type * base, uint32_t baseAddr) +STATIC status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type * base, uint32_t baseAddr) { flexspi_transfer_t flashXfer; status_t status; @@ -29,7 +30,7 @@ status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type * base, uint32_t b return status; } -status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type * base) +STATIC status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type * base) { /* Wait status ready. */ bool isBusy; diff --git a/ports/mimxrt10xx/supervisor/internal_flash.c b/ports/mimxrt10xx/supervisor/internal_flash.c index 84c478bcfb..72d57d1dd4 100644 --- a/ports/mimxrt10xx/supervisor/internal_flash.c +++ b/ports/mimxrt10xx/supervisor/internal_flash.c @@ -52,10 +52,6 @@ extern uint32_t __fatfs_flash_length[]; uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4))); uint32_t _flash_page_addr = NO_CACHE; -extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); -extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src); -extern status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base); - void PLACE_IN_ITCM(supervisor_flash_init)(void) { // Update the LUT to make sure all entries are available. FLEXSPI_UpdateLUT(FLEXSPI, 0, (const uint32_t *)&qspiflash_config.memConfig.lookupTable, 64); diff --git a/ports/mimxrt10xx/supervisor/internal_flash.h b/ports/mimxrt10xx/supervisor/internal_flash.h index ae33fd134f..66d3f73db1 100644 --- a/ports/mimxrt10xx/supervisor/internal_flash.h +++ b/ports/mimxrt10xx/supervisor/internal_flash.h @@ -30,6 +30,7 @@ #include #include "py/mpconfig.h" +#include "fsl_common.h" #define INTERNAL_FLASH_SYSTICK_MASK (0x1ff) // 512ms #define INTERNAL_FLASH_IDLE_TICK(tick) (((tick) & INTERNAL_FLASH_SYSTICK_MASK) == 2) @@ -41,4 +42,9 @@ #define ROM_INDEX_PAGEPROGRAM 9 #define ROM_INDEX_READSTATUSREG 1 +extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); +extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src); +extern status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base); + + #endif // MICROPY_INCLUDED_MIMXRT10XX_INTERNAL_FLASH_H diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c index 88a4ce5bb7..0b25bb6d2a 100644 --- a/ports/mimxrt10xx/supervisor/port.c +++ b/ports/mimxrt10xx/supervisor/port.c @@ -104,6 +104,7 @@ extern uint32_t _ld_itcm_flash_copy; extern void main(void); // This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c. +void Reset_Handler(void); __attribute__((used, naked)) void Reset_Handler(void) { __disable_irq(); SCB->VTOR = (uint32_t)&__isr_vector; @@ -358,6 +359,8 @@ uint64_t port_get_raw_ticks(uint8_t *subticks) { return ticks / 32; } +void SNVS_HP_WRAPPER_IRQHandler(void); +__attribute__((used)) void SNVS_HP_WRAPPER_IRQHandler(void) { if ((SNVS->HPSR & SNVS_HPSR_PI_MASK) != 0) { supervisor_tick(); @@ -415,6 +418,7 @@ void port_idle_until_interrupt(void) { /** * \brief Default interrupt handler for unused IRQs. */ +void MemManage_Handler(void); __attribute__((used)) void MemManage_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { @@ -425,6 +429,7 @@ __attribute__((used)) void MemManage_Handler(void) { /** * \brief Default interrupt handler for unused IRQs. */ +void BusFault_Handler(void); __attribute__((used)) void BusFault_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { @@ -435,6 +440,7 @@ __attribute__((used)) void BusFault_Handler(void) { /** * \brief Default interrupt handler for unused IRQs. */ +void UsageFault_Handler(void); __attribute__((used)) void UsageFault_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { @@ -445,6 +451,7 @@ __attribute__((used)) void UsageFault_Handler(void) { /** * \brief Default interrupt handler for unused IRQs. */ +void HardFault_Handler(void); __attribute__((used)) void HardFault_Handler(void) { reset_into_safe_mode(HARD_CRASH); while (true) { diff --git a/ports/mimxrt10xx/supervisor/usb.c b/ports/mimxrt10xx/supervisor/usb.c index 57f0387990..c00ff44acd 100644 --- a/ports/mimxrt10xx/supervisor/usb.c +++ b/ports/mimxrt10xx/supervisor/usb.c @@ -52,6 +52,7 @@ void init_usb_hardware(void) { usb_phy->TX = phytx; } +void USB_OTG1_IRQHandler(void); void USB_OTG1_IRQHandler(void) { usb_irq_handler(); }