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Merge pull request #2132 from hierophect/stm32-f412-tinyusb 

STM32: Add USB support to F412 Discovery
This commit is contained in:
Dan Halbert 2019-09-09 17:41:21 -04:00 committed by GitHub
parent 6ad860a963 c438468a82
commit 53b0b35e34
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 166 additions and 247 deletions
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2
lib/tinyusb

@ -1 +1 @@
Subproject commit 00c440cb26fbea7fd367623454d8b67855f1372f Subproject commit f8081536310e5ac7a1e8c8ba9295890429a2cb6f

248
ports/stm32f4/boards/STM32F412ZGTx_FLASH.ld
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@ -1,189 +1,105 @@
/* /*
****************************************************************************** GNU linker script for STM32F412
**
** File : LinkerScript.ld
**
** Author : Auto-generated by Ac6 System Workbench
**
** Abstract : Linker script for STM32F412ZGTx series
** 1024Kbytes FLASH and 256Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of Ac6 nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/ */
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20040000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */ /* Specify the memory areas */
MEMORY MEMORY
{ {
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */
FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 960K /* sector 4 is 64K, sectors 5,6,7 are 128K */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K
} }
/* Define output sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_start = _ebss; /* heap starts just after statically allocated memory */
_heap_end = 0x20020000; /* tunable */
ENTRY(Reset_Handler)
/* define output sections */
SECTIONS SECTIONS
{ {
/* The startup code goes first into FLASH */ /* The startup code goes first into FLASH */
.isr_vector : .isr_vector :
{ {
. = ALIGN(4); . = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */ KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */ /* This first flash block is 16K annd the isr vectors only take up
.text : about 400 bytes. Micropython pads this with files, but this didn't
{ work with the size of Circuitpython's ff object. */
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init)) . = ALIGN(4);
KEEP (*(.fini)) } >FLASH_ISR
. = ALIGN(4); /* The program code and other data goes into FLASH */
_etext = .; /* define a global symbols at end of code */ .text :
} >FLASH {
. = ALIGN(4);
*(.text*) /* .text* sections (code) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
/* Constant data goes into FLASH */ . = ALIGN(4);
.rodata : _etext = .; /* define a global symbol at end of code */
{ } >FLASH_TEXT
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH /* used by the startup to initialize data */
.ARM : { _sidata = LOADADDR(.data);
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array : /* This is the initialized data section
{ The program executes knowing that the data is in the RAM
PROVIDE_HIDDEN (__preinit_array_start = .); but the loader puts the initial values in the FLASH (inidata).
KEEP (*(.preinit_array*)) It is one task of the startup to copy the initial values from FLASH to RAM. */
PROVIDE_HIDDEN (__preinit_array_end = .); .data :
} >FLASH {
.init_array : . = ALIGN(4);
{ _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
PROVIDE_HIDDEN (__init_array_start = .); *(.data*) /* .data* sections */
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */ . = ALIGN(4);
_sidata = LOADADDR(.data); _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
} >RAM AT> FLASH_TEXT
/* Initialized data sections goes into RAM, load LMA copy after code */ /* Uninitialized data section */
.data : .bss :
{ {
. = ALIGN(4); . = ALIGN(4);
_sdata = .; /* create a global symbol at data start */ _sbss = .; /* define a global symbol at bss start; used by startup code */
*(.data) /* .data sections */ *(.bss*)
*(.data*) /* .data* sections */ *(COMMON)
. = ALIGN(4); . = ALIGN(4);
_edata = .; /* define a global symbol at data end */ _ebss = .; /* define a global symbol at bss end; used by startup code and GC */
} >RAM AT> FLASH } >RAM
/* this is to define the start of the heap, and make sure we have a minimum size */
/* Uninitialized data section */ .heap :
. = ALIGN(4); {
.bss : . = ALIGN(4);
{ . = . + _minimum_heap_size;
/* This is used by the startup in order to initialize the .bss secion */ . = ALIGN(4);
_sbss = .; /* define a global symbol at bss start */ } >RAM
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4); /* this just checks there is enough RAM for the stack */
_ebss = .; /* define a global symbol at bss end */ .stack :
__bss_end__ = _ebss; {
} >RAM . = ALIGN(4);
. = . + _minimum_stack_size;
. = ALIGN(4);
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */ .ARM.attributes 0 : { *(.ARM.attributes) }
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
} }

7
ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.mk
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@ -1,9 +1,10 @@
USB_VID = 0x483 USB_VID = 0x239A
USB_PID = 0x572B USB_PID = 0x8056
USB_PRODUCT = "STM32F412ZG Discovery Board - CPy" USB_PRODUCT = "STM32F412ZG Discovery Board - CPy"
USB_MANUFACTURER = "STMicroelectronics" USB_MANUFACTURER = "STMicroelectronics"
DISABLE_FILESYSTEM = 1 INTERNAL_FLASH_FILESYSTEM = 1
LONGINT_IMPL = NONE
MCU_SERIES = m4 MCU_SERIES = m4
MCU_VARIANT = stm32f4 MCU_VARIANT = stm32f4

83
ports/stm32f4/peripherals/stm32f4/stm32f412zx/clocks.c
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@ -28,48 +28,47 @@
void stm32f4_peripherals_clocks_init(void) { void stm32f4_peripherals_clocks_init(void) {
//System clock init //System clock init
RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 72;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 3;
RCC_OscInitStruct.PLL.PLLR = 2;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1|RCC_PERIPHCLK_SDIO /* Enable Power Control clock */
|RCC_PERIPHCLK_CLK48; __HAL_RCC_PWR_CLK_ENABLE();
PeriphClkInitStruct.PLLI2S.PLLI2SN = 50;
PeriphClkInitStruct.PLLI2S.PLLI2SM = 4;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 2;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48;
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
PeriphClkInitStruct.I2sApb1ClockSelection = RCC_I2SAPB1CLKSOURCE_PLLI2S;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); /* The voltage scaling allows optimizing the power consumption when the
* device is clocked below the maximum system frequency, to update the
* voltage scaling value regarding system frequency refer to product
* datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
RCC_OscInitStruct.PLL.PLLR = 2;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Select PLLSAI output as USB clock source */
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
* clocks dividers */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
} }

4
ports/stm32f4/supervisor/internal_flash.h
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@ -34,12 +34,12 @@
#ifdef STM32F411xE #ifdef STM32F411xE
#define STM32_FLASH_SIZE 0x80000 //512KiB #define STM32_FLASH_SIZE 0x80000 //512KiB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //112KiB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#endif #endif
#ifdef STM32F412Zx #ifdef STM32F412Zx
#define STM32_FLASH_SIZE 0x100000 //1MB #define STM32_FLASH_SIZE 0x100000 //1MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //112KiB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#endif #endif
#define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location #define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location

69
ports/stm32f4/supervisor/usb.c
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@ -33,43 +33,46 @@
#include "stm32f4xx_hal.h" #include "stm32f4xx_hal.h"
void init_usb_hardware(void) { void init_usb_hardware(void) {
// HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, GPIO_PIN_RESET); //LED 2 //TODO: if future chips overload this with options, move to peripherals management.
GPIO_InitTypeDef GPIO_InitStruct = {0};
/**USB_OTG_FS GPIO Configuration
PA10 ------> USB_OTG_FS_ID
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
__HAL_RCC_GPIOA_CLK_ENABLE();
/* Configure DM DP Pins */ GPIO_InitTypeDef GPIO_InitStruct = {0};
GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; /**USB_OTG_FS GPIO Configuration
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; PA10 ------> USB_OTG_FS_ID
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; PA11 ------> USB_OTG_FS_DM
GPIO_InitStruct.Pull = GPIO_NOPULL; PA12 ------> USB_OTG_FS_DP
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; */
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); __HAL_RCC_GPIOA_CLK_ENABLE();
/* Configure VBUS Pin */ /* Configure DM DP Pins */
GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* This for ID line debug */ /* Configure VBUS Pin */
GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* Peripheral clock enable */ /* This for ID line debug */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE(); GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
// /* Peripheral interrupt init */ #ifdef STM32F412Zx
// HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); /* Configure POWER_SWITCH IO pin (F412 ONLY)*/
// HAL_NVIC_EnableIRQ(OTG_FS_IRQn); GPIO_InitStruct.Pin = GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
#endif
//HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_RESET); //LED 3 /* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
} }